74LVT16374A; 74LVTH16374A 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state Rev. 11 -- 5 February 2019 Product data sheet 1. General description The 74LVT16374A; 74LVTH16374A are high performance BiCMOS products designed for VCC operation at 3.3 V. This device is a 16-bit edge-triggered D-type flip-flop featuring non-inverting 3-state outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (nCP), the nQn outputs of the flip-flop take on the logic levels set up at the nDn inputs. 2. Features and benefits * * * * * * * * * * * * 16-bit edge-triggered flip-flop 3-state buffers Output capability: +64 mA and -32 mA TTL input and output switching levels Input and output interface capability to systems at 5 V supply Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs. (74LVTH16374A only) Live insertion and extraction permitted Power-up reset Power-up 3-state No bus current loading when output is tied to 5 V bus Latch-up protection: * JESD78B Class II exceeds 500 mA ESD protection: * HBM JESD22-A114F exceeds 2000 V * MM JESD22-A115-A exceeds 200 V 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVT16374ADL -40 C to +85 C SSOP48 plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 74LVT16374ADGG -40 C to +85 C TSSOP48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 74LVTH16374ADGG 74LVT16374A; 74LVTH16374A Nexperia 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state 4. Functional diagram 47 46 44 43 41 40 38 37 1 1OE 48 1CP 24 2OE 25 2CP 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 48 1CP 1 1OE 1D0 1D1 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2 36 3 5 35 33 6 32 8 30 9 11 29 27 1D2 1D3 12 1D4 1D5 26 1D6 1D7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 25 2CP 24 2OE 2D0 2D1 2D2 2D3 2D4 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2D5 2D6 13 14 16 17 19 20 22 23 2D7 EN1 C3 EN2 C4 47 3D 46 5 43 6 41 8 40 9 38 11 37 12 36 4D 35 Fig. 2. nD1 D CP nD2 D Q CP nD3 D Q CP 13 2 14 33 16 32 17 30 19 29 20 27 22 26 23 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 001aaa254 Logic symbol nD0 3 44 001aac369 Fig. 1. 2 1 nD4 D Q IEC logic symbol CP nD5 D Q CP nD6 D Q CP nD7 D Q CP D Q CP Q nCP nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 001aac371 Fig. 3. Logic diagram 74LVT_LVTH16374A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 -- 5 February 2019 (c) Nexperia B.V. 2019. All rights reserved 2 / 14 74LVT16374A; 74LVTH16374A Nexperia 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state 5. Pinning information 5.1. Pinning 74LVT16374A 74LVTH16374A 1OE 1 48 1CP 1Q0 2 47 1D0 1Q1 3 46 1D1 GND 4 45 GND 1Q2 5 44 1D2 1Q3 6 43 1D3 VCC 7 42 VCC 1Q4 8 41 1D4 1Q5 9 40 1D5 GND 10 39 GND 1Q6 11 38 1D6 1Q7 12 37 1D7 2Q0 13 36 2D0 2Q1 14 35 2D1 GND 15 34 GND 2Q2 16 33 2D2 2Q3 17 32 2D3 VCC 18 31 VCC 2Q4 19 30 2D4 2Q5 20 29 2D5 GND 21 28 GND 2Q6 22 27 2D6 2Q7 23 26 2D7 2OE 24 25 2CP 001aak263 Fig. 4. Pin configuration SOT370-1 (SSOP48) and SOT362-1 (TSSOP48) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1OE, 2OE 1, 24 output enable input (active LOW) 1CP, 2CP 48, 25 clock input 1Q0, 1Q1, 1Q2, 1Q3, 1Q4, 1Q5, 1Q6, 1Q7 2, 3, 5, 6, 8, 9, 11, 12 data output 2Q0, 2Q1, 2Q2, 2Q3, 2Q4, 2Q5, 2Q6, 2Q7 13, 14, 16, 17, 19, 20, 22, 23 data output GND 4, 10, 15, 21, 28, 34, 39, 45 ground (0 V) VCC 7, 18, 31, 42 supply voltage 1D0, 1D1, 1D2, 1D3, 1D4, 1D5, 1D6, 1D7 47, 46, 44, 43, 41, 40, 38, 37 data input 2D0, 2D1, 2D2, 2D3, 2D4, 2D5, 2D6, 2D7 36, 35, 33, 32, 30, 29, 27, 26 data input 74LVT_LVTH16374A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 -- 5 February 2019 (c) Nexperia B.V. 2019. All rights reserved 3 / 14 74LVT16374A; 74LVTH16374A Nexperia 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state 6. Functional description Table 3. Function table H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW clock transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW clock transition; NC = no change; X = don't care; Z = high-impedance OFF-state; = LOW-to-HIGH clock transition. Operating mode Input Output Internal register nOE nCP nDn L l L L L h H H Hold L NC X NC NC Disable outputs H NC X NC Z H nDn nDn Z Load and read register nQ0 to nQ7 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC supply voltage VI input voltage VO output voltage output in OFF-state or HIGH-state IIK input clamping current IOK IO Unit -0.5 +4.6 V -0.5 +7.0 V [1] -0.5 +7.0 V VI < 0 V -50 - mA output clamping current VO < 0 V -50 - mA output current output in LOW-state - 128 mA output in HIGH-state -64 - mA -65 +150 C [2] - 150 C [3] - 500 mW storage temperature Tj junction temperature Ptot total power dissipation [3] Max [1] Tstg [1] [2] Min Tamb = -40 C to +85 C The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. Above 60 C the value of Ptot derates linearly with 5.5 mW/K. 74LVT_LVTH16374A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 -- 5 February 2019 (c) Nexperia B.V. 2019. All rights reserved 4 / 14 74LVT16374A; 74LVTH16374A Nexperia 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VCC supply voltage 2.7 - 3.6 V VI input voltage 0 - 5.5 V VIH HIGH-level input voltage 2.0 - - V VIL LOW-level input voltage V IOH HIGH-level output current IOL LOW-level output current - - 0.8 -32 - - mA none - - 32 mA current duty cycle 50 %; fi 1 kHz - - 64 mA -40 - +85 C - - 10 ns/V Tamb ambient temperature in free-air t/V input transition rise and fall rate outputs enabled 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Tamb = -40 C to +85 C Min Typ [1] Max VIK input clamping voltage VCC = 2.7 V; IIK = -18 mA -1.2 -0.85 - V VOH HIGH-level output voltage IOH = -100 A; VCC = 2.7 V to 3.6 V VCC - 0.2 VCC - V IOH = -8 mA; VCC = 2.7 V 2.4 2.5 - V IOH = -32 mA; VCC = 3.0 V 2.0 2.3 - V IOL = 100 A - 0.07 0.2 V IOL = 24 mA - 0.3 0.5 V IOL = 16 mA - 0.25 0.4 V IOL = 32 mA - 0.3 0.5 V IOL = 64 mA - 0.4 0.55 V - 0.1 0.55 V VCC = 3.6 V; VI = VCC or GND - 0.1 1 A VCC = 0 V or 3.6 V; VI = 5.5 V - 0.4 10 A VCC = 0 V or 3.6 V; VI = 5.5 V - 0.4 10 A VCC = 3.6 V; VI = VCC - 0.1 1 A VCC = 3.6 V; VI = 0 V -5 -0.4 - A - 0.1 100 A VOL LOW-level output voltage Unit VCC = 2.7 V VCC = 3.0 V VOL(pu) power-up LOW-level output voltage VCC = 3.6 V; IO = 1 mA; VI = VCC or GND II input leakage current control pins input data pins [2] [3] IOFF power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V IBHL bus hold LOW current VCC = 3 V; VI = 0.8 V 75 135 - A IBHH bus hold HIGH current VCC = 3 V; VI = 2.0 V - -135 -75 A IBHLO bus hold LOW overdrive current input data pins; VI = 0 V to 3.6 V; VCC = 3.6 V 500 - - A 74LVT_LVTH16374A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 -- 5 February 2019 [4] (c) Nexperia B.V. 2019. All rights reserved 5 / 14 74LVT16374A; 74LVTH16374A Nexperia 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state Symbol Parameter Conditions Typ [1] Max - - -500 A - 50 125 A - 1 100 A output HIGH: VO = 3.0 V - 0.5 5 A output LOW: VO = 0.5 V -5 0.5 - A outputs HIGH - 0.07 0.12 mA outputs LOW - 4.0 6.0 mA [6] - 0.07 0.12 mA [7] - 0.1 0.2 mA bus hold HIGH overdrive current input data pins; VI = 0 V to 3.6 V; VCC = 3.6 V ILO output leakage current output in HIGH-state when VO > VCC; VO = 5.5 V; VCC = 3.0 V IO(pu/pd) power-up/power-down output VCC 1.2 V; VO = 0.5 V to VCC; current VI = GND or VCC; nOE = don't care OFF-state output current ICC supply current Unit Min IBHHO IOZ Tamb = -40 C to +85 C [4] [5] VCC = 3.6 V; VI = VIH or VIL VCC = 3.6 V; VI = GND or VCC; IO = 0 A outputs disabled ICC additional supply current per input pin; VCC = 3.0 V to 3.6 V; one input at VCC - 0.6 V, other inputs at VCC or GND CI input capacitance input pins; VI = 0 V or 3.0 V - 3 - pF CO output capacitance output pins nQn; outputs disabled; VO = 0 V or VCC - 9 - pF [1] [2] [3] [4] [5] [6] [7] Typical values are measured at VCC = 3.3 V and at Tamb = 25 C. For valid test results, data must not be loaded into the flips-flops (or latches) after applying power. Unused pins at VCC or GND. This is the bus hold overdrive current required to force the input to the opposite logic state. This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V 0.3 V a transition time of 100 s is permitted. This parameter is valid for Tamb = 25 C only. ICC is measured with outputs pulled to VCC or GND. This is the increase in supply current for each input at the specified voltage level other than VCC or GND. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 8. Symbol Parameter Conditions fmax maximum frequency nCP; VCC = 3.3 V 0.3 V; see Fig. 5 tPLH LOW to HIGH propagation delay nCP to nQn; see Fig. 5 VCC = 3.3 V 0.3 V VCC = 2.7 V tPHL HIGH to LOW propagation delay OFF-state to HIGH propagation delay VCC = 3.3 V 0.3 V OFF-state to LOW propagation delay VCC = 3.3 V 0.3 V Product data sheet Typ [1] Max 150 - - 1.5 2.9 5.0 ns - - 5.6 ns 1.5 3.0 5.0 ns - - 5.6 ns 1.5 3.2 4.8 ns - - 6.0 ns 1.5 3.0 4.6 ns - - 5.2 ns MHz nOE to nQn; see Fig. 6 VCC = 3.3 V 0.3 V VCC = 2.7 V 74LVT_LVTH16374A Min nOE to nQn; see Fig. 6 VCC = 2.7 V tPZL Unit nCP to nQn; see Fig. 5 VCC = 2.7 V tPZH Tamb = -40 C to +85 C All information provided in this document is subject to legal disclaimers. Rev. 11 -- 5 February 2019 (c) Nexperia B.V. 2019. All rights reserved 6 / 14 74LVT16374A; 74LVTH16374A Nexperia 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state Symbol Parameter tPHZ Conditions HIGH to OFF-state propagation delay Tamb = -40 C to +85 C Min Typ [1] Max 1.5 3.9 5.4 ns - - 6.0 ns 1.5 3.4 4.6 ns - - 5.0 ns VCC = 3.3 V 0.3 V 2.0 0.7 - ns VCC = 2.7 V 2.0 - - ns VCC = 3.3 V 0.3 V 0.8 0 - ns VCC = 2.7 V 0.1 - - ns VCC = 3.3 V 0.3 V 1.5 0.6 - ns VCC = 2.7 V 1.5 - - ns VCC = 3.3 V 0.3 V 3.0 1.6 - ns VCC = 2.7 V 3.0 - - ns nOE to nQn; see Fig. 6 VCC = 3.3 V 0.3 V VCC = 2.7 V tPLZ LOW to OFF-state propagation delay nOE to nQn; see Fig. 6 VCC = 3.3 V 0.3 V VCC = 2.7 V tsu set-up time th hold time tW pulse width Unit nDn to nCP; HIGH or LOW; see Fig. 7 nDn to nCP; HIGH or LOW; see Fig. 7 nCP HIGH; see Fig. 5 nCP LOW; see Fig. 5 [1] All typical values are measured at VCC = 3.3 V and Tamb = 25 C. 10.1. Waveforms and test circuit 1/fmax VI nCP input VM VM GND tW t PHL t PLH VOH VM nQn output VOL 001aaa256 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 5. Propagation delay clock input to output, clock pulse width and maximum clock frequency 74LVT_LVTH16374A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 -- 5 February 2019 (c) Nexperia B.V. 2019. All rights reserved 7 / 14 74LVT16374A; 74LVTH16374A Nexperia 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state VI nOE input VM GND tPZL tPLZ 3.0 V VM nYn output VOL VX t PZH t PHZ VOH nYn output VY VM 0V 001aae464 Measurements points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 6. Enable and disable times VI VM nCP input GND t su t su th th VI VM nDn input GND VOH VM nQn output VOL 001aaa257 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig. 7. Data set-up and hold times Table 8. Measurement points Input Output VM VM VX VY 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 74LVT_LVTH16374A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 -- 5 February 2019 (c) Nexperia B.V. 2019. All rights reserved 8 / 14 74LVT16374A; 74LVTH16374A Nexperia 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state VI negative pulse tW 90 % VM 0V VI tf tr tr tf 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC PULSE GENERATOR VI RL VO DUT RT CL RL 001aae235 Test data is given in Table 9. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig. 8. Test circuit for measuring switching times Table 9. Test data Input Load VEXT VI fi tW tr, tf CL RL tPHZ, tPZH tPLZ, tPZL tPLH, tPHL 2.7 V 10 MHz 500 ns 2.5 ns 50 pF 500 GND 6V open 74LVT_LVTH16374A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 -- 5 February 2019 (c) Nexperia B.V. 2019. All rights reserved 9 / 14 74LVT16374A; 74LVTH16374A Nexperia 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state 11. Package outline SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 D E A X c y HE v M A Z 25 48 Q A2 A1 A (A 3 ) pin 1 index Lp L 24 1 detail X w M bp e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2.8 0.4 0.2 2.35 2.20 0.25 0.3 0.2 0.22 0.13 16.00 15.75 7.6 7.4 0.635 10.4 10.1 1.4 1.0 0.6 1.2 1.0 0.25 0.18 0.1 0.85 0.40 8o 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT370-1 Fig. 9. REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-118 Package outline SOT370-1 (SSOP48) 74LVT_LVTH16374A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 -- 5 February 2019 (c) Nexperia B.V. 2019. All rights reserved 10 / 14 74LVT16374A; 74LVTH16374A Nexperia 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 D E A X c v HE y A Z 48 25 Q A2 A1 (A3) pin 1 index A Lp 1 L 24 bp e detail X w 0 5 mm 2.5 scale Dimensions (mm are the original dimensions) Unit mm max nom min A 1.2 A1 A2 0.15 1.05 0.05 0.85 A3 0.25 bp c D(1) E(2) 0.28 0.2 12.6 6.2 0.17 0.1 12.4 6.0 e HE 0.5 8.3 7.9 L 1 Lp Q 0.8 0.50 0.4 0.35 v w 0.25 0.08 y 0.1 Z 0.8 8 0.4 0 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. Outline version SOT362-1 References IEC JEDEC JEITA sot362-1_po European projection Issue date 03-02-19 13-08-05 MO-153 Fig. 10. Package outline SOT362-1 (TSSOP48) 74LVT_LVTH16374A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 -- 5 February 2019 (c) Nexperia B.V. 2019. All rights reserved 11 / 14 74LVT16374A; 74LVTH16374A Nexperia 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state 12. Abbreviations Table 10. Abbreviations Acronym Description BiCMOS Bipolar Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVT_LVTH16374A v.11 20190205 Product data sheet - Modifications: * * * * 74LVT_LVTH16374A v.10 The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type numbers 74LVT16374AEV (SOT702-1) and 74LVTH16374ABX (SOT1134-2) removed. Package outline drawing SOT362-1 (TSSOP48) updated. 74LVT_LVTH16374A v.10 20120402 Modifications: * 74LVT_LVTH16374A v.9 20111122 Modifications: * 74LVT_LVTH16374A v.8 20110620 74LVT_LVTH16374A v.7 Product data sheet - 74LVT_LVTH16374A v.9 For type number 74LVTH16374ABX the sot code has changed to SOT1134-2. - 74LVT_LVTH16374A v.8 Product data sheet - 74LVT_LVTH16374A v.7 20100322 Product data sheet - 74LVT_LVTH16374A v.6 74LVT_LVTH16374A v.6 20100118 product data sheet - 74LVT16374A v.5 74LVT16374A v.5 20040916 product data sheet - 74LVT16374A v.4 74LVT16374A v.4 20021101 product specification - 74LVT16374A v.3 74LVT16374A v.3 19991018 product specification - 74LVT16374A v.2 74LVT16374A v.2 19980219 product specification - - 74LVT_LVTH16374A Product data sheet Product data sheet Legal pages updated. All information provided in this document is subject to legal disclaimers. Rev. 11 -- 5 February 2019 (c) Nexperia B.V. 2019. All rights reserved 12 / 14 74LVT16374A; 74LVTH16374A Nexperia 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state 14. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Data sheet status Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. 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Suitability for use -- Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal 74LVT_LVTH16374A Product data sheet Applications -- Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. 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Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. 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Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia's warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia's specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia's standard warranty and Nexperia's product specifications. Translations -- A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 11 -- 5 February 2019 (c) Nexperia B.V. 2019. All rights reserved 13 / 14 74LVT16374A; 74LVTH16374A Nexperia 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................3 5.1. Pinning.........................................................................3 5.2. Pin description............................................................. 3 6. Functional description................................................. 4 7. Limiting values............................................................. 4 8. Recommended operating conditions..........................5 9. Static characteristics....................................................5 10. Dynamic characteristics............................................ 6 10.1. Waveforms and test circuit........................................ 7 11. Package outline........................................................ 10 12. Abbreviations............................................................ 12 13. Revision history........................................................12 14. Legal information......................................................13 (c) Nexperia B.V. 2019. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 5 February 2019 74LVT_LVTH16374A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 -- 5 February 2019 (c) Nexperia B.V. 2019. All rights reserved 14 / 14