T4-LDS-0249, Rev. 2 (4/25/13) ©2013 Microsemi Corporation Page 1 of 6
2N682, 2N683, and 2N685 – 2N692
Availa ble on
commercial
versions
PNPN Silicon, Reverse-Blocking,
Power Triode Thyristors
Qualified per MIL-PRF-19500/108
Qualified Levels:
JAN and JANTX
DESCRIPTION
This silicon controlled rectifier device is military qualified up to a JANTX level for high-reliability
applications.
TO-208 / TO-48
Package
Important: For the latest i nformation, vis it our website http://www.microsemi.com.
FEATURES
• JEDEC registered 2N682, 2N683, 2N685, and 2N687 – 2N692.
• JAN and JANTX qualifications are avail abl e per MIL-PRF-19500/108.
• RoHS compliant versions available (commercial grade only).
APPLICATIONS / BENEFITS
• A general purpose, reverse-blocking thy rist or.
MAXIMUM RATINGS
MSC – Lawrence
6 Lake Street,
Lawrence, MA 01841
Tel: 1-800-446-1158 or
(978) 620-2600
Fax: (978) 689-0803
MSC – Ireland
Gort Road Business Park,
Ennis, Co. Clare, Ireland
Tel: +353 (0) 65 6840044
Fax: +353 (0) 65 6822298
Website:
www.microsemi.com
Parameters/Test Conditions
Symbol
Value
Unit
Junction Temperature
TJ
-65 to +125
oC
Storage Temperature
TSTG
-65 to +150
oC
Gate Voltage (Peak Total Value)
VGM
5
V(pk)
Maximum Average DC Output Current (1)
IO
16
A
Non-repetitive Peak On-State Current (2) @ t = 7 ms
ITSM
150
A
Notes: 1. This average forward current is for a maxim um case temperature of +65 °C, and 180 electrical degrees
of conduction.
2. Surge rating is non-recurrent and applies only with device in the conducting state. The peak rate of surge
current must not exceed 100 amperes during the first 10 μs after switching from the off (blocking) state
to the on (conducting) state. This tim e is measured from the point where the thyristor voltage has
decayed to 90 percent of its initial blocking value.
T4-LDS-0249, Rev. 2 (4/25/13) ©2013 Microsemi Corporation Page 2 of 6
2N682, 2N683, and 2N685 – 2N692
• CASE: Nickel plated copper.
• TERMINALS: Nickel plated steel, solder dipped or RoHS compli ant matt e-tin plating (on commercial and CDS grade onl y ) .
• MARKING: Manufacturer’s ID, part number, date code, polarity.
• POLARITY: Terminal 1: gate, termi nal 2: cathode, terminal 3 (stud): anode.
• WEIGHT: Approximately 12.36 grams.
• See Package Dimensions on last page.
JAN 2N682 (e3)
Reliability Level
JAN = Jan level
JANTX = JANTX level
CDS (reference JANS)
Blank = Commercial
JEDEC type number
(See Electrical Characteristics
table)
RoHS Compli ance
e3 = RoHS compliant (available
on commercial grade only)
Blank = non-RoHS compliant
SYMBOLS & DEFINITIONS
Symbol
Definition
C
Capacitance
di/dt
Critical rate of rise of on-st ate current
dv/dt
Critical rate of rise of off-state v oltage
f
frequency
IF
Forward current
IT
On-state current
ITM
On-state current (peak total value)
R
Resistance
Re
Responsivity, radiant
RL
Resistor load
t
time
tp
Pulse variation
VAA
Anode power supply voltage (dc)
T4-LDS-0249, Rev. 2 (4/25/13) ©2013 Microsemi Corporation Page 3 of 6
2N682, 2N683, and 2N685 – 2N692
Parameters / Test Conditions
Symbol
Min.
Max.
Unit
Repetitive Peak Reverse Voltage
and
Repetitive Peak Off-State Voltage
2N682
2N683
2N685
2N686
2N687
2N688
2N689
2N690
2N691
2N692
VRRM
(1)
and
VDRM
50
100
200
250
300
400
500
600
700
800
V (pk)
(1) Values applicable to zero or negative gate voltage (VGM).
Parameters / Test Conditions
Symbol
Min.
Max.
Unit
Holding current:
Bias condition D; VAA = 24 V m axim um ;
ITM = IF1 = 1 A
IT = IF2 = 100 mA
trigger volta ge sour c e = 10 V
trigger PW = 100 μs (minimum)
R2 = 20 Ω
IH 50 mA
Reverse blocking current
AC method, bias condition D;
f = 60 Hz, VRRM = rated
IRRM1 2 mA (pk)
Forward blocking current
AC method, bias condition D;
f = 60 Hz; VDRM = rated IDRM1 2 mA (pk)
Gate trigger voltage and current
V2 = VD = 6 V; RL = 50 Ω;
Re = 20 Ω maximum
VGT1
IGT1
3
35
V
mA
Forward on voltage
ITM = 50 A(pk) (pulse);
pulse width = 8.5 ms; maximum;
duty cycle = 2 percent maximum VTM 2 V (pk)
Reverse gate current
VG = 5 V
IG 250 mA
T4-LDS-0249, Rev. 2 (4/25/13) ©2013 Microsemi Corporation Page 4 of 6
2N682, 2N683, and 2N685 – 2N692
Parameters / Test Conditions
Symbol
Min.
Max.
Unit
Reverse blocking current (TC = +120 ºC)
AC method, bias condition D;
f = 60 Hz; VRRM = rated
IRRM2 5 mA (pk)
Forward blocking current (TC = +12 0 ºC)
AC method, bias condition D;
f = 60 Hz; V
DRM
= rated IDRM2 5 mA (pk)
Gate trigger voltage (TC = +120 ºC; Re = 20 Ω max)
V
2
= V
DM
= 50 V; R
L
= 140 Ω
V2 = VDM = 100 V; RL = 140 Ω
V2 = VDM = 200 V; RL = 140 Ω
V2 = VDM = 250 V; RL = 650 Ω
V2 = VDM = 300 V; RL = 650 Ω
V2 = VDM = 400 V; RL = 3 k Ω
V2 = VDM = 500 V; RL = 3 k Ω
V2 = VDM = 600 V; RL = 3 k Ω
V2 = VDM = 700 V; RL = 3 k Ω
V2 = VDM = 800 V; RL = 3 k Ω
2N682
2N683
2N685
2N686
2N687
2N688
2N689
2N690
2N691
2N692
VGT2 .25 V
Reverse blocking current (T
C
= -65 ºC)
AC method, bias condition D;
f = 60 Hz; V
RRM
= rated IRRM3 2 mA (pk)
Forward blocking current (
TC
= -65 ºC
)
AC method, bias condition D;
f = 60 Hz; V
DRM
= rated IDRM3 2 mA (pk)
Gate trigger voltage and current (T
C
= -65 ºC)
V2 = VD = 6 V; RL = 50 Ω;
R
e
= 20 Ω maximum VGT3
IGT2 3
80 V
mA
Exponential rate of voltage rise
Bias condition D; TC = +120°C minimum,
dv/dt = 25 v/μs; repetition rate = 60 pps;
test duration = 15 s;
C = 1.0 μF; RL = 50 Ω
VAA = 50 V
VAA = 100 V
VAA = 200 V
VAA = 250 V
VAA = 300 V
VAA = 400 V
VAA = 500 V
VAA = 600 V
VAA = 700 V
VAA = 800 V
2N682
2N683
2N685
2N686
2N687
2N688
2N689
2N690
2N691
2N692
VD
47
95
190
240
285
380
475
570
665
760
V
T4-LDS-0249, Rev. 2 (4/25/13) ©2013 Microsemi Corporation Page 5 of 6
2N682, 2N683, and 2N685 – 2N692
Parameters / Test Conditions Symbol Min. Max. Unit
Circuit-commutated turn-off time
TC = +120°C minimum; ITM = 10 A;
ton = 100 ±50 μs; di/dt = 5 A/μs minimum;
di/dt = 8 A/μs maximum; reverse voltage at t1 = 15 V minimum;
repetition rate = 60 pps maximum; di/dt = 20 V/μs;
gate bias conditions; gate source voltage = 0 V;
gate source resistance = 100 Ω
V
DM
= V
DRM
= 50 V (pk); V
RRM
= 50 V maximum
VDM = VDRM = 100 V (pk); VRRM = 100 V m ax im um
VDM = VDRM = 200 V (pk); VRRM = 200 V m ax im um
VDM = VDRM = 250 V (pk); VRRM = 250 V m ax im um
VDM = VDRM = 300 V (pk); VRRM = 300 V m ax im um
VDM = VDRM = 400 V (pk); VRRM = 400 V m ax im um
VDM = VDRM = 500 V (pk); VRRM = 500 V m ax im um
VDM = VDRM = 600 V (pk); VRRM = 600 V m ax im um
VDM = VDRM = 700 V (pk); VRRM = 700 V m ax im um
VDM = VDRM = 800 V (pk); VRRM = 800 V m ax im um
2N682
2N683
2N685
2N686
2N687
2N688
2N689
2N690
2N691
2N692
t
off
30
30
30
30
30
30
40
40
60
60
µs
Gate controlled turn-on time
VAA = 50 V for 2N682
VAA = 100 V for 2N683, 2N685 through 2N692
ITM = 10 A; VGG = 10 V; Re = 25 Ω
tp1 = 15 ±5 μs; 4 A/μs ≤ di/dt ≤ 200 A/μs.
2N682,
2N683,
2N685
through
2N692
ton
5
µs
T4-LDS-0249, Rev. 2 (4/25/13) ©2013 Microsemi Corporation Page 6 of 6
2N682, 2N683, and 2N685 – 2N692
NOTES:
1. Dimensions are in inches. Millimeters are given for information only.
2. Device contour, except on hex head and noted terminal dimensions, is
optional within zone defined by CD and OAH, CD not to exceed actual
HF.
3. Contour and angular orientation of terminals 1 and 2 with respect to
hex portion and to each other are optional.
4. Chamfer or undercut on one or both ends of the hexagonal portion are
optional.
5. Square or radi us on end of termi nal is opti ona l.
6. Minimum difference in terminal lengths to establish datum line for
numbering terminals.
7. Dimension SD is pitch diameter of coated thre ads.
8. In accordance with ASME Y14.5M, diameters are equivalent to Φx
symbology.
Dimensions
Ltr
Inches
Millimeters
Notes
Min
Max
Min
Max
b
0.115
0.139
2.92
3.53
3
b1
0.210
0.300
5.33
7.62
3
CD
-
0.543
-
13.8
2
CH
-
0.550
-
14.00
e2
0.125
-
3.17
-
6
HF
0.544
0.563
13.8
14.3
HT
0.075
0.200
1.9
5.08
4
OAH
-
1.193
-
30.3
2
S
0.120
-
3.05
-
3
SD
¼ - 28 UNF 2A
SL
0.422
0.453
10.7
11.5
SU
-
0.090
-
2.29
ΦT
0.125
0.165
3.17
4.19
ΦT1
0.060
0.075
1.52
1.9
UD
0.220
0.249
5.59
6.32
Terminal 1
Gate
Terminal 2
Cathode
5
Terminal 3
Anode (Stud)
7