2Kx8 Dual-Port Static RAM
fax id: 5201
CY7C132/CY7C136
CY7C142/CY7C146
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 9 5 1 3 4 • 408-943-260 0
December 1989 – Revised March 27, 1997
1CY7C132/CY7C1 36
Features
• Tru e Dual-Ported memory cel ls whic h allow simulta-
neous reads of the same memory location
• 2K x 8 organization
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 1 5 ns
• Low operating power: ICC = 90 mA (max.)
• Fully asynchronous op eration
• Automatic power-down
• Master CY7C132/CY7C136 easily expands data bus
width to 16 or more bits us ing slave CY7C142/CY7C146
• BUSY output flag on CY7C132/CY7C136; BUSY input
on CY7C142/CY7C146
• INT flag for port-to-port communication (52-pin
PLCC/PQFP versions)
• Available in 48-pin DIP (CY7C132/142), 52-pin PLCC and
52-pin TQFP (CY7C136/146)
• Pin-compatible and functionally equivalent to
IDT7132/IDT7142
Functional Description
The CY7C132/CY7C136/CY7C142 and CY7C146 are
high-speed CMOS 2K by 8 dual-port static R AMs. Two ports
are provided to permit independent a ccess t o any location in
memory. The CY7C132/ CY7C136 can be utilized as either a
standalone 8-bit dual-port static RAM or as a MASTER du-
al-port RAM in conjunction with the CY7C142/CY7C146
SLAVE dual-port device in systems requiring 16-bit or greater
word width s. I t is the solution to applications requiring shared
or buffered data such as cache memory for DSP, bit-sli ce, or
multiprocessor designs.
Each port has independent control pins; chip enable (CE),
write enable (R /W), and output enable (OE). BUSY flags are
provided on each port. In addition, an interrupt flag (INT) is
provided on each port of the 52-pin PLCC version. BUSY sig-
nals that the port is trying to access the same location currently
being accessed by the other port. O n the PLCC version, INT
is an interrupt flag indicating that data has been placed in a
unique location (7FF for the left po rt and 7FE for the right port).
An automatic power-down feature is controll ed independently
on each port by the chip enable ( CE) pi n s.
The CY7C132/CY7C142 are available in 48-pin DIP. The
CY7C136/CY7C146 are available in 52-pin PLCC and PQFP.
Notes:
1. CY7 C132/CY 7C136 (Maste r): B USY is open d ra in o utput and requires pull-u p resisto r.
CY7 C142/CY 7C146 (Slave): BUSY i s i nput.
2. Open drain outputs; pull-up resistor required.
LogicBlock Diagram Pin Configuration
C132-1 C132-2
13
14
15
16
17
18
19
20
21
22
23 26
27
28
32
31
30
29
33
36
35
34
24 25
GND
R/WL
BUSYL[1]
CEL
OEL
A10L
A0L A0R
A10R
R/WR
CER
OER
CER
OER
CEL
OEL
R/WLR/WR
I/O7L
I/O0L
I/O7R
I/O0R
BUSYR[1]
INTL[2] INTR[2]
ARBITRATION
LOGIC
(7C132/7C136 ONLY)
AND
INTERRUPTLOGIC
(7C136/7C146 ONLY)
CONTROL
I/O CONTROL
I/O
MEMORY
ARRAY ADDRESS
DECODER
ADDRESS
DECODER
1
2
3
4
5
6
7
8
9
10
11 38
39
40
44
43
42
41
45
48
47
46
12 37
R/WL
CEL
BUSYL
A10L
OEL
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
CER
R/WR
BUSYR
A10R
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/O7R
I/O6R
I/O5R
I/O4R
I/O3R
I/O2R
I/O1R
I/O0R
VCC
DIP
Top View
7C132
7C142
CY7C132/CY7C136
CY7C142/CY7C146
2
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ..................................... −65°C to +150°C
Ambient Temper ature with
Power Applied..................................................−55°C to +125°C
Supply Volta ge to Gro und Potential
(Pin 48 to Pin 24).................................................−0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State.....................................................−0.5V to +7.0V
DC Input Voltage.................................................−3.5V to +7.0V
Output Current into Outputs (LOW)........................ .....20 mA
Static Discharge Voltage.......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up C urrent.................................................. .. >200 mA
]
Pin Configurations (continued)
1
Top View
PLCC
OER
A0R
8
9
10
11
12
13
14
15
16
17
18
19
20
46
45
44
43
42
41
40
39
38
37
36
35
34
2122 23 24 25 26 27 28 29 30 31 32 33
7 6 5 4 3 2 52 51 50 49 48 47
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
NC
I/O7R
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
C132-3
7C136
7C146
46
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
1415 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 45 44 43 42 41 40
Top View
PQFP
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
NC
I/O7R
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
C132-4
7C136
7C146
Selectio n G uide
7C136-15[3,4]
7C146-15
7C132-25[3]
7C136-25
7C142-25
7C146-25
7C132-30
7C136-30
7C142-30
7C146-30
7C132-35
7C136-35
7C142-35
7C146-35
7C132-45
7C136-45
7C142-45
7C146-45
7C132-55
7C136-55
7C142-55
7C146-55
Maximum Access Time (ns) 15 25 30 35 45 55
Maximum Operating
Current (mA) Com’l/Ind 190 170 170 120 90 90
Maximum Operating
Current (mA) Military 170 120 120
Maximum Standby
Current (mA) Com’l/Ind 75 65 65 45 35 35
Military 65 45 45
Notes:
3. 15 and 25-ns version available in PQFP and PLCC pac kages only.
4. Shaded area contains preliminary information.
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C 5V ± 10%
Industrial −40°C to +85°C 5V ± 10%
Military[5] −55°C to +125°C 5V ± 10%
Note:
5. TA is the “instant on” case temperature.
CY7C132/CY7C136
CY7C142/CY7C146
3
]
Electrical Characteristics Over the Operating Range[6]
Parameter Description Test Conditions
7C136-15[3,4]
7C146-15
7C132-30[3]
7C136-25,30
7C142-30
7C146-25,30
7C132-35
7C136-35
7C142-35
7C146-35
7C132-45,55
7C136-45,55
7C142-45,55
7C146-45,55
UnitMin. Max. Min. Max. Min. Max. Min. Max.
VOH Outpu t HIGH V oltage VCC = Min., IOH = -4.0 mA 2.4 2.4 2.4 2.4 V
VOL Output LOW Voltage IOL = 4.0 mA 0.4 0.4 0.4 0.4 V
IOL = 16.0 mA [7] 0.5 0.5 0.5 0.5
VIH Input HIGH Voltage 2.2 2.2 2.2 2.2 V
VIL Input LOW Voltage 0.8 0.8 0.8 0.8 V
IIX Input Load Curr ent GND < VI < VCC -5 +5 −5 +5 −5 +5 −5 +5 µA
IOZ Output Leakage
Current GND < V O < VCC,
Output Disabled -5 +5 −5 +5 −5 +5 −5 +5 µA
IOS Output Short
Circuit Current[8] VCC = Max.,
VOUT = GND -350 −350 −350 −350 mA
ICC VCC Operating
Supply Current CE = VIL,
Outputs Open,
f = fMAX[9]
Com’l 190 170 120 90 mA
Mil 170 120
ISB1 Standby Current
Both Port s,
TTL Inputs
CEL and CER > VIH,
f = fMAX[9] Com’l 75 65 45 35 mA
Mil 65 45
ISB2 Standby Current
One Port,
TTL Inputs
CEL or CE R > VIH,
Active Port Outputs
Open,
f = fMAX[9]
Com’l 135 115 90 75 mA
Mil 115 90
ISB3 Standby Current
Both Port s,
CMOS Inputs
Both Ports CEL and
CER > VCC – 0.2V,
VIN > V CC – 0.2V or
VIN < 0.2 V, f = 0
Com’l 15 15 15 15 mA
Mil 15 15
ISB4 Standby Current
One Port,
CMOS Inputs
On e Port CEL or
CER > VCC – 0.2V,
VIN > V CC – 0.2V or
VIN < 0.2V,
Acti ve P ort Outp uts
Open,
f = fMAX[9]
Com’l 125 105 85 70 mA
Mil 105 85
Capacitance[10]
Parameter Description Test C onditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MH z,
VCC = 5.0V 15 pF
COUT Out put Capacitance 10 pF
Notes:
6. See the last page of this specification for Group A subgroup testing information.
7. BUSY and INT pins only.
8. Duration of the short circuit should not exceed 30 seconds.
9. At f=fMAX, add ress and data inp uts are cycli ng at the maximum fr equency of r ead cycle of 1/trc and using A C Test W avefor ms i nput le vels of GND to 3V.
10. This parameter is guaranteed but not tested.
CY7C132/CY7C136
CY7C142/CY7C146
4
]
AC Test Loads and Waveforms
3.0V
5V
OUTPUT
R1893Ω
R2
347Ω
30 pF
INCLUDING
JIGAND
SCOPE
GND
90% 90%
10%
<5ns <5ns
5V
OUTPUT
C132-5
R1893Ω
R2
347Ω
5pF
INCLUDING
JIGAND
SCOPE C132-6
(a) (b)
OUTPUT 1.4V
Equivalent to: TH VÉNIN EQUIVALENT
5V
281Ω
30pF
BUSY
OR
INT
BUSYOutput Load
(CY7C132/CY7C136 ONLY)
10%
ALL INPUT PUL SES
250Ω
Switching Characteristics Over the Oper ating Range[6, 11]
Parameter Description
7C136-15[3,4]
7C146-15
7C132-25[3]
7C136-25
7C142-25
7C146-25
7C132-30
7C136-30
7C142-30
7C146-30
UnitMin. Max. Min. Max. Min. Max.
READ CYCLE
tRC Read Cycle Time 15 25 30 ns
tAA Address to Data Val id[12] 15 25 30 ns
tOHA Data Hold from Address Change 0 0 0 ns
tACE CE LOW to Data Valid[12] 15 25 30 ns
tDOE OE LOW to Data Vali d[12] 10 15 20 ns
tLZOE OE LOW to Low Z[10, 13] 3 3 3 ns
tHZOE OE HIGH to Hi gh Z[10, 13, 14] 10 15 15 ns
tLZCE CE LOW to Low Z[10, 13] 3 5 5 ns
tHZCE CE HIGH to High Z[10, 13, 14] 10 15 15 ns
tPU CE LOW to Power-Up[10] 0 0 0 ns
tPD CE HIGH to Power-Down[10] 15 25 25 ns
WRITE CYCLE[15]
tWC Write Cy cl e Tim e 15 25 30 ns
tSCE CE LOW to Write End 12 20 25 ns
tAW Address Set-Up to Write End 12 20 25 ns
tHA Address Hold from Write End 2 2 2 ns
tSA Address Set-Up to Write Start 0 0 0 ns
tPWE R/W Pulse Width 12 15 25 ns
tSD Data Set-Up to Write End 10 15 15 ns
tHD Data H old from Write End 0 0 0 ns
tHZWE R/W LOW to High Z [10] 10 15 15 ns
tLZWE R/W HIGH to Low Z [10] 0 0 0 ns
CY7C132/CY7C136
CY7C142/CY7C146
5
BUSY/INTERRUPT TIMING
tBLA BUSY LOW from Address Match 15 20 20 ns
tBHA BUSY HIGH from Address Mismatch[16] 15 20 20 ns
tBLC BUSY LOW from CE LOW 15 20 20 ns
tBHC BUSY HIGH from CE HIGH[16] 15 20 20 ns
tPS Port Set Up for Priority 5 5 5 ns
tWB R/W LOW after BUSY LOW[17] 0 0 0 ns
tWH R/W H IGH afte r BUSY HIGH 13 20 30 ns
tBDD BUSY HIGH to Valid Data 15 25 30 ns
tDDD Write Data Valid to Read Data Valid Note
18 Note
18 Note
18 ns
tWDD Write Pulse to Data Delay Note
18 Note
18 Note
18 ns
INTERRUPT TIMIN G[19]
tWINS R/W to IN TERRUPT Se t T ime 15 25 25 ns
tEINS CE to INT ERRUPT Set Time 15 25 25 ns
tINS Address to INTERRUPT Set T im e 15 25 25 ns
tOINR OE to IN TERR U PT Reset Time[16] 15 25 25 ns
tEINR CE to INTERRUPT Reset Time[16] 15 25 25 ns
tINR Address to INTERRUPT Rese t Tim e [16] 15 25 25 ns
Switching Characteristics Over the Oper ating Range[6, 11] (co ntinue d )
Parameter Description
7C136-15[3,4]
7C146-15
7C132-25[3]
7C136-25
7C142-25
7C146-25
7C132-30
7C136-30
7C142-30
7C146-30
UnitMin. Max. Min. Max. Min. Max.
Switching Characteristics Over the Oper ating Range[6, 11]
7C132-35
7C136-35
7C142-35
7C146-35
7C132-45
7C136-45
7C142-45
7C146-45
7C132-55
7C136-55
7C142-55
7C146-55
Parameter Description Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time 35 45 55 ns
tAA Address to Data Valid[12] 35 45 55 ns
tOHA Data Hold from Address Change 0 0 0 ns
tACE CE LOW to Data Valid[12] 35 45 55 ns
tDOE OE LOW to Data Valid[12] 20 25 25 ns
tLZOE OE LOW to Low Z[10, 13] 333ns
t
HZOE OE HIGH to Hi gh Z[10, 13, 14] 20 20 25 ns
tLZCE CE LOW to Low Z[10, 13] 555ns
t
HZCE CE HIGH to High Z[10, 13, 14] 20 20 25 ns
tPU CE LOW to Power-Up[10] 000ns
t
PD CE HIGH to Power-Down[10] 35 35 35 ns
CY7C132/CY7C136
CY7C142/CY7C146
6
WRITE CYCLE[15]
tWC Write Cycl e Time 35 4 5 55 ns
tSCE CE LOW to Write End 30 35 40 n s
tAW Address Set-Up to Write End 30 3 5 4 0 ns
tHA Address Hold from Write End 2 2 2 ns
tSA Address Set-Up to Write Start 0 0 0 ns
tPWE R/W Pulse Width 25 30 30 ns
tSD Data Set-Up to Write En d 15 20 20 ns
tHD Data Hold from Write End 0 0 0 ns
tHZWE R/W LOW to High Z [10] 20 20 25 ns
tLZWE R/W HIG H to Low Z [10] 000ns
BUSY/INT ERRUPT TIMING
tBLA BUSY LOW from Address Match 20 25 30 ns
tBHA BUSY HIGH from Address Mismatch[16] 20 25 30 ns
tBLC BUSY LOW from CE LOW 20 25 30 ns
tBHC BUSY HIGH from CE HIGH[16] 20 25 30 ns
tPS Port Set Up for Priority 5 5 5 ns
tWB R/W LOW after BUSY LOW[17] 000ns
t
WH R/W H IGH af ter BUSY HIGH 30 35 35 ns
tBDD BUSY HIGH to Valid Data 35 45 45 n s
tDDD Write Data Valid to Read Data Valid Note
18 Note
18 Note
18 ns
tWDD Write Pulse to Data Delay Note
18 Note
18 Note
18 ns
INTERRUPT TIMING[19]
tWINS R/W to INTERRUPT S e t T i m e 2 5 35 45 ns
tEINS CE to INTERRUPT Set Time 25 35 45 ns
tINS Address to INTERRUPT Set Time 25 35 45 ns
tOINR OE to INTER R UPT Reset Time[16] 25 35 45 ns
tEINR CE to INT ERRUPT Reset Time[16] 25 35 45 ns
tINR Address to INTERRUPT Rese t Tim e [16] 25 35 45 ns
Notes:
11. Test conditions assume signal transition times of 5 ns or les s, timing reference l evels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
IOL/IOH, and 30-pF load capac itance.
12. AC test conditions use VOH = 1.6V a nd VOL = 1.4V.
13. At any given temperature and voltage condition for any given device, tHZCE is l ess than tLZCE and tHZOE is l ess than tLZOE.
14. tLZCE, tLZWE, tHZOE, tLZOE, tHZCE, an d tHZWE are tes ted with CL = 5pF as in par t ( b) of AC Test Loads
.
T ran sition i s measured ±500 mV from s teady- state vol tag e.
15. The internal write time of the memory is defined by the overlap of CE LOW and R /W LO W. Both s ignals must be LOW to i nitiat e a write a nd ei t her sig nal can ter minate
a write by going H IGH. The da ta i nput se tup an d hold t iming should be r efe renced to th e rising e dge of the si gnal t hat te rminates the write.
16. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
17. CY7 C142/CY 7C146 only.
18. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undis t urbed until one access time after one of the following:
BUSY on Port B goes H IGH.
Port B’s addre ss toggl ed.
CE for Port B is toggled.
R/W for P ort B is toggled dur ing valid read.
19. 52-pin PLCC and PQ FP versions only.
Switching Characteristics Over the Oper ating Range[6, 11] (co ntinue d )
7C132-35
7C136-35
7C142-35
7C146-35
7C132-45
7C136-45
7C142-45
7C146-45
7C132-55
7C136-55
7C142-55
7C146-55
CY7C132/CY7C136
CY7C142/CY7C146
7
Switching Waveforms
Read Cycle No. 1 (Either Port-Address Access)[20, 21]
Read Cycle No. 2 (Eit her Port-CE/OE)[20, 22]
Read Cycle No. 3 (Read with BUSY Master: CY7C132 and CY7C136)
n
Notes:
20. R/W is HIG H for rea d cycle.
21. Device is continuously selected, CE = V IL and OE = VIL.
22. Address valid prior to or coincident with CE trans ition LO W.
tRC
tAA
tOHA
DATA VALIDPREVIOUS DATA VALID
DATA OUT
ADDRESS
C132-7
tACE
tLZOE tDOE tHZOE
tHZCE
DATA VALID
DATA OUT
CE
OE
tLZCE
tPU
ICC
ISB
tPD
C132-8
tBHA
tBDD
VALID
tDDD
tWDD
ADDRESS MATCH
ADDRESS MATCH
R/WR
ADDRESS
R
DINR
ADDRESS
L
BUSYL
DOUTL
C132-9
tPS
tBLA
tRC
tPWE
VALID
CY7C132/CY7C136
CY7C142/CY7C146
8
Write Cycle No.1 (OE Three-States Data I/Os-Either Port)[15, 23]
Write Cycle No. 2 (R/W Three–States Data I/Os-Either Port)[ 15, 24 ]
Notes:
23. If OE is LOW during a R/W contr olled w rite c ycle, the write pulse width mus t be the larger of tPWE or tHZWE + tSD to allow the dat a I /O pins to enter high impe dance and for data
to be pl aced o n the bus for the requi red tSD.
24. If the CE LOW tran sition occurs s imul taneously with or after th e R/W L OW transiti on, the ou tputs remai n in a high- impedanc e stat e.
Switching Waveforms (continued)
tAW
tWC
DATA VALID
HIGH IMPEDAN CE
tSCE
tSA tPWE
tHD
tSD
tHA
tHZOE
CE
R/W
ADDRESS
OE
DOUT
DATAIN
C132-10
tAW
tWC
tSCE
tSA tPWE
tHD
tSD
tHZWE
tHA
HIGH IMPEDANCE
CE
R/W
ADDRESS
DOUT
DATAIN
tLZWE
DATA VALID
C132-11
CY7C132/CY7C136
CY7C142/CY7C146
9
Busy Timing Diagram No. 1 (CE Arbitration)
Busy Timing Diagram No. 2 (Address Arbitration)
Switching Waveforms (continued)
ADDRESS MATCH
tPS
CELValidFirst:
tBLC tBHC
ADDRESS MATCH
tPS
tBLC tBHC
CERValidFirst:
C132-12
C132-13
BUSYL
CER
CEL
ADDRESS L,R
BUSYR
CEL
CER
ADDRESSL,R
Left AddressValidFirst:
ADDRESS MATCH
tPS
ADDRESSL
BUSY R
ADDRESS MI SMATCH
tRCor tWC
tBLA tBHA
ADDRESSR
ADDRESS MATCH ADDRESS MI SMATCH
tPS
ADDRESSL
BUSYL
tRCor tWC
tBLA tBHA
ADDRESS R
RightAddressValidFirst:
C132-14
C132-15
CY7C132/CY7C136
CY7C142/CY7C146
10
Busy Timing Diagram No. 3 (Write with BUSY, Slave: CY7C142/CY7C146)
Interrupt Timing Diagra ms[19]
Left Side Sets INTR:
Right Side Clears INTR:
Switching Waveforms (continued)
tPWE
tWB tWH
BUSY
C132-16
R/W
CE
WRITE 7FF
tINS
ADDRESS L
R/WL
tWC
tEINS
CELtHA
tSA tWINS
INTRC132-17
READ 7FF
tRC
tEINR
tHA tINR
tOINR
ADDRESS
R
CER
R/WR
INTR
OER
C132-18
CY7C132/CY7C136
CY7C142/CY7C146
11
Right Side Sets INTL:
Right Side Clears INTL:
Interrupt Timing Diagra ms[19] (continue d )
WRITE 7FE
tINS
ADDRESSR
R/W
R
tWC
tEINS
CERtHA
tSA tWINS
INTL
C132-19
READ 7FE
tEINR
tHA tINR
tOINR
ADDRESSL
CEL
R/WL
INTL
OEL
tRC
C132-20
CY7C132/CY7C136
CY7C142/CY7C146
12
Ty pical DC and AC Characteristics
1.4
1.0
0.4
4.0 4.5 5.0 5.5 6.0 -55 25 125
1.2
1.0
120
100
80
60
40
20
0 1.0 2.0 3.0 4.0
SUPPLYVOLTAGE(V)
NORMAL IZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
AMBIENTTEMPERATURE(°C) OUTPUTVOLTAGE(V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
0.0
0.8 0.8
0.6
0.6
VCC =5.0V
VIN =5.0V VCC =5.0V
TA=25°C
0
ICC
ICC
1.6
1.4
1.2
1.0
0.8
-55 125
NORMAL IZED ACCES S TIME
vs. AMBIENT TEMPERATURE
AMBIENTTEMPERATURE(°C)
1.4
1.3
1.2
1.0
0.9
4.0 4.5 5.0 5.5 6.0
SUPPLYVOLTAGE(V)
NORMAL IZED ACCESS TIME
vs. SUPPLY VOLTAGE
120
140
100
60
40
20
0.0 1.0 2.0 3.0 4.0
0
80
OUTPUTVOLTAGE(V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
VCC =5.0V
TA=25°C
0.6
0.8
VCC =5.0V
TA=25°C
1.25
1.0
0.75
10 40
0.50
NORMAL IZED I CC vs. CYCLE TIME
CYCLE FREQUENCY (MHz )
3.0
2.5
2.0
1.5
0.5
0 1.0 2.0 3.0 5.0
25.0
30.0
20.0
10.0
5.0
0 200 400 600 800
0
15.0
0.0
SUPPLYVOLTAGE(V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
CAPACITANCE(pF)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
4.0 1000
1.0
20 30
0.2
0.6
1.2
ISB3 0.2
0.4
ISB3
25
1.1
VCC =4.5V
TA=25°C
VCC =5.0V
TA=25°C
VIN =0.5V
CY7C132/CY7C136
CY7C142/CY7C146
13
Shaded area contains preliminary information.
Orde rin g Inf orm a tio n
Speed
(ns) O rderi n g Code Package
Name Package Type Operating
Range
30 CY7C132-30PC P25 48-Lead (600-Mil) Molded DIP Commercial
CY7C132-30PI P25 48-Lead (600-Mil) Molded DIP Industrial
35 CY7C132-35PC P25 48-Lead (600-Mil) Molded DIP Commercial
CY7C132-35PI P25 48-Lead (600-Mil) Molded DIP Industrial
CY7C132-35DMB D26 48-L ead (6 00-Mil) Sidebraze DIP Military
45 CY7C132-45PC P25 48-Lead (600-Mil) Molded DIP Commercial
CY7C132-45PI P25 48-Lead (600-Mil) Molded DIP Industrial
CY7C132-45DMB D26 48-L ead (6 00-Mil) Sidebraze DIP Military
55 CY7C132-55PC P25 48-Lead (600-Mil) Molded DIP Commercial
CY7C132-55PI P25 48-Lead (600-Mil) Molded DIP Industrial
CY7C132-55DMB D26 48-L ead (6 00-Mil) Sidebraze DIP Military
Speed
(ns) O rderi n g Code Package
Name Package Type Operating
Range
15 CY7C136-15JC J69 52-Lead Pla stic Leaded Chip Carrier Commercial
CY7C136-15NC N52 52-Pin Plastic Quad Flatpack
25 CY7C136-25JC J69 52-Lead Pla stic Leaded Chip Carrier Commercial
CY7C136-25NC N52 52-Pin Plastic Quad Flatpack
30 CY7C136-30JC J69 52-Lead Pla stic Leaded Chip Carrier Commercial
CY7C136-30NC N52 52-Pin Plastic Quad Flatpack
CY7C136-30JI J69 52-L ead Pl astic Leaded C hip Carrier Industrial
35 CY7C136-35JC J69 52-Lead Pla stic Leaded Chip Carrier Commercial
CY7C136-35NC N52 52-Pin Plastic Quad Flatpack
CY7C136-35JI J69 52-L ead Pl astic Leaded C hip Carrier Industrial
CY7C136-35LMB L69 52-Square Le adless Chip Carrier Military
45 CY7C136-45JC J69 52-Lead Pla stic Leaded Chip Carrier Commercial
CY7C136-45NC N52 52-Pin Plastic Quad Flatpack
CY7C136-45JI J69 52-L ead Pl astic Leaded C hip Carrier Industrial
CY7C136-45LMB L69 52-Square Le adless Chip Carrier Military
55 CY7C136-55JC J69 52-Lead Pla stic Leaded Chip Carrier Commercial
CY7C136-55NC N52 52-Pin Plastic Quad Flatpack
CY7C136-55JI J69 52-L ead Pl astic Leaded C hip Carrier Industrial
CY7C136-55LMB L69 52-Square Le adless Chip Carrier Military
CY7C132/CY7C136
CY7C142/CY7C146
14
Orde rin g Inf orm a tio n (continued)
Shaded area contains preliminary information.
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
30 CY7C142-30PC P25 48-Lead (600-Mil) Molded DIP Commercial
CY7C142-30PI P25 48-Lead (600-Mil) Molded DIP Industrial
35 CY7C142-35PC P25 48-Lead (600-Mil) Molded DIP Commercial
CY7C142-35PI P25 48-Lead (600-Mil) Molded DIP Industrial
CY7C142-35DMB D26 48-L ead (6 00-Mil) Sidebraze DIP Military
45 CY7C142-45PC P25 48-Lead (600-Mil) Molded DIP Commercial
CY7C142-45PI P25 48-Lead (600-Mil) Molded DIP Industrial
CY7C142-45DMB D26 48-L ead (6 00-Mil) Sidebraze DIP Military
55 CY7C142-55PC P25 48-Lead (600-Mil) Molded DIP Commercial
CY7C142-55PI P25 48-Lead (600-Mil) Molded DIP Industrial
CY7C142-55DMB D26 48-L ead (6 00-Mil) Sidebraze DIP Military
Speed
(ns) O rderi n g Code Package
Name Package Type Operating
Range
15 CY7C136-15JC J69 52-Lead Plastic Leaded Chip Carrier Commercial
CY7C136-15NC N52 52-Pin Plastic Quad Flatpack
25 CY7C146-25JC J69 52-Lead Plastic Leaded Chip Carrier Commercial
CY7C146-25NC N52 52-Pin Plastic Quad Flatpack
30 CY7C146-30JC J69 52-Lead Plastic Leaded Chip Carrier Commercial
CY7C146-30NC N52 52-Pin Plastic Quad Flatpack
CY7C146-30JI J69 52-Lead Plastic Leaded Chip Carrier Industrial
35 CY7C146-35JC J69 52-Lead Plastic Leaded Chip Carrier Commercial
CY7C146-35NC N52 52-Pin Plastic Quad Flatpack
CY7C146-35JI J69 52-Lead Plastic Leaded Chip Carrier Industrial
CY7C146-35LMB L69 52-Sq uare Leadless Chip Carrier Military
45 CY7C146-45JC J69 52-Lead Plastic Leaded Chip Carrier Commercial
CY7C146-45NC N52 52-Pin Plastic Quad Flatpack
CY7C146-45JI J69 52-Lead Plastic Leaded Chip Carrier Industrial
CY7C146-45LMB L69 52-Sq uare Leadless Chip Carrier Military
55 CY7C146-55JC J69 52-Lead Plastic Leaded Chip Carrier Commercial
CY7C146-55NC N52 52-Pin Plastic Quad Flatpack
CY7C146-55JI J69 52-Lead Plastic Leaded Chip Carrier Industrial
CY7C146-55LMB L69 52-Sq uare Leadless Chip Carrier Military
CY7C132/CY7C136
CY7C142/CY7C146
15
MIL ITARY SPECIFICAT IONS
Group A Subgroup Testing
DC Characteristics Switching Characteristics
Parameter Subgroups
VOH 1, 2, 3
VOL 1, 2, 3
VIH 1, 2, 3
VIL Max. 1, 2, 3
IIX 1, 2, 3
IOZ 1, 2, 3
ICC 1, 2, 3
ISB1 1, 2, 3
ISB2 1, 2, 3
ISB3 1, 2, 3
ISB4 1, 2, 3
Parameter Subgroups
READ CYCLE
tRC 7, 8, 9, 10, 11
tAA 7, 8, 9, 10, 11
tACE 7, 8, 9, 10, 11
tDOE 7, 8, 9, 10, 11
WRITE CYCLE
tWC 7, 8, 9, 10, 11
tSCE 7, 8, 9, 10, 11
tAW 7, 8, 9, 10, 11
tHA 7, 8, 9, 10, 11
tSA 7, 8, 9, 10, 11
tPWE 7, 8, 9, 10, 11
tSD 7, 8, 9, 10, 11
tHD 7, 8, 9, 10, 11
BUSY/INTERRUPT TIMIN G
tBLA 7, 8, 9, 10, 11
tBHA 7, 8, 9, 10, 11
tBLC 7, 8, 9, 10, 11
tBHC 7, 8, 9, 10, 11
tPS 7, 8, 9, 10, 11
tWINS 7, 8, 9, 10, 11
tEINS 7, 8, 9, 10, 11
tINS 7, 8, 9, 10, 11
tOINR 7, 8, 9, 10, 11
tEINR 7, 8, 9, 10, 11
tINR 7, 8, 9, 10, 11
BUSY TIMING
tWB[25] 7, 8, 9, 10, 11
tWH 7, 8, 9, 10, 11
tBDD 7, 8, 9, 10, 11
Note:
25. CY7C142/CY7C146 only.
Document #: 38-00061-K
CY7C132/CY7C136
CY7C142/CY7C146
16
Package Diagrams
48-Lead (600-Mil ) Sidebraze DIP D26
52-Le ad Plastic Leaded Chi p Carrier J69
CY7C132/CY7C136
CY7C142/CY7C146
17
52-Square Leadless Chip Carrier L6 9
52-Lead Plastic Quad Flatpack N52
Package Diagrams (continued)
CY7C132/CY7C136
CY7C142/CY7C146
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no r esponsibility for the use
of any circuitry othe r than circui try embodi ed in a Cypress Semi conductor prod uct. Nor do es it convey or im ply an y li cens e under p atent or other rights . Cy press Semi conductor does not authori ze
its product s for use as critic al components in life-support systems where a malfunct ion or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes a ll risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
48-Lead (600-Mil ) Molded DIP P25
Package Diagrams (continued)
