MF1129-02 CMOS 4-BIT SINGLE CHIP MICROCOMPUTER S1C60N07 Technical Manual S1C60N07 Technical Hardware NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. (c) SEIKO EPSON CORPORATION 2001 All rights reserved. The information of the product number change Starting April 1, 2001, the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales representative. Configuration of product number Devices S1 C 60N01 F 0A01 00 Packing specification Specification Package (D: die form; F: QFP) Model number Model name (C: microcomputer, digital products) Product classification (S1: semiconductor) Development tools C 60R08 S5U1 D1 1 00 Packing specification Version (1: Version 1 2) Tool type (D1: Development Tool 1) Corresponding model number (60R08: for S1C60R08) Tool classification (C: microcomputer use) Product classification (S5U1: development tool for semiconductor products) 1: For details about tool types, see the tables below. (In some manuals, tool types are represented by one digit.) 2: Actual versions are not written in the manuals. Comparison table between new and previous number S1C60 Family processors Previous No. E0C6001 E0C6002 E0C6003 E0C6004 E0C6005 E0C6006 E0C6007 E0C6008 E0C6009 E0C6011 E0C6013 E0C6014 E0C60R08 New No. S1C60N01 S1C60N02 S1C60N03 S1C60N04 S1C60N05 S1C60N06 S1C60N07 S1C60N08 S1C60N09 S1C60N11 S1C60N13 S1C60140 S1C60R08 S1C62 Family processors Previous No. E0C621A E0C6215 E0C621C E0C6S27 E0C6S37 E0C623A E0C623E E0C6S32 E0C6233 E0C6235 E0C623B E0C6244 E0C624A E0C6S46 New No. S1C621A0 S1C62150 S1C621C0 S1C6S2N7 S1C6S3N7 S1C6N3A0 S1C6N3E0 S1C6S3N2 S1C62N33 S1C62N35 S1C6N3B0 S1C62440 S1C624A0 S1C6S460 Previous No. E0C6247 E0C6248 E0C6S48 E0C624C E0C6251 E0C6256 E0C6292 E0C6262 E0C6266 E0C6274 E0C6281 E0C6282 E0C62M2 E0C62T3 New No. S1C62470 S1C62480 S1C6S480 S1C624C0 S1C62N51 S1C62560 S1C62920 S1C62N62 S1C62660 S1C62740 S1C62N81 S1C62N82 S1C62M20 S1C62T30 Comparison table between new and previous number of development tools Development tools for the S1C60/62 Family Previous No. ASM62 DEV6001 DEV6002 DEV6003 DEV6004 DEV6005 DEV6006 DEV6007 DEV6008 DEV6009 DEV6011 DEV60R08 DEV621A DEV621C DEV623B DEV6244 DEV624A DEV624C DEV6248 DEV6247 New No. S5U1C62000A S5U1C60N01D S5U1C60N02D S5U1C60N03D S5U1C60N04D S5U1C60N05D S5U1C60N06D S5U1C60N07D S5U1C60N08D S5U1C60N09D S5U1C60N11D S5U1C60R08D S5U1C621A0D S5U1C621C0D S5U1C623B0D S5U1C62440D S5U1C624A0D S5U1C624C0D S5U1C62480D S5U1C62470D Previous No. DEV6262 DEV6266 DEV6274 DEV6292 DEV62M2 DEV6233 DEV6235 DEV6251 DEV6256 DEV6281 DEV6282 DEV6S27 DEV6S32 DEV6S37 EVA6008 EVA6011 EVA621AR EVA621C EVA6237 EVA623A New No. S5U1C62620D S5U1C62660D S5U1C62740D S5U1C62920D S5U1C62M20D S5U1C62N33D S5U1C62N35D S5U1C62N51D S5U1C62560D S5U1C62N81D S5U1C62N82D S5U1C6S2N7D S5U1C6S3N2D S5U1C6S3N7D S5U1C60N08E S5U1C60N11E S5U1C621A0E2 S5U1C621C0E S5U1C62N37E S5U1C623A0E Previous No. EVA623B EVA623E EVA6247 EVA6248 EVA6251R EVA6256 EVA6262 EVA6266 EVA6274 EVA6281 EVA6282 EVA62M1 EVA62T3 EVA6S27 EVA6S32R ICE62R KIT6003 KIT6004 KIT6007 New No. S5U1C623B0E S5U1C623E0E S5U1C62470E S5U1C62480E S5U1C62N51E1 S5U1C62N56E S5U1C62620E S5U1C62660E S5U1C62740E S5U1C62N81E S5U1C62N82E S5U1C62M10E S5U1C62T30E S5U1C6S2N7E S5U1C6S3N2E2 S5U1C62000H S5U1C60N03K S5U1C60N04K S5U1C60N07K CONTENTS CONTENTS CHAPTER 1 OUTLINE .....................................................................................................1 1.1 Features.....................................................................................................................................................................1 1.2 Block Diagram .........................................................................................................................................................2 1.3 Pin Layout Diagram...............................................................................................................................................3 1.4 Pin Description ........................................................................................................................................................3 CHAPTER 2 CPU AND BUILT-IN MEMORY......................................................................4 2.1 CPU and Instruction Set ......................................................................................................................................4 2.2 Program Memory (ROM) .....................................................................................................................................9 2.3 Data Memory (RAM) .............................................................................................................................................9 CHAPTER 3 POWER SOURCE...................................................................................... 14 3.1 Power Supply System........................................................................................................................................14 3.2 Heavy Load Protection Mode .........................................................................................................................15 3.2.1 Control of heavy load protection mode ....................................................................................15 3.2.2 Programming notes ..........................................................................................................................15 3.3 CPU Operating Voltage Change....................................................................................................................16 CHAPTER 4 INITIAL RESET .......................................................................................... 17 4.1 Initial Reset Factors ............................................................................................................................................17 4.1.1 Power-on reset circuit......................................................................................................................17 4.1.2 External initial reset by the #RESET terminal........................................................................17 4.1.3 External initial reset by simultaneous low level input of K00-K03 terminals.............18 4.1.4 Initial reset by watchdog timer......................................................................................................18 4.1.5 Internal register at initial resetting...............................................................................................18 4.2 Watchdog Timer...................................................................................................................................................19 4.2.1 Configuration of watchdog timer..................................................................................................19 4.2.2 Control of watchdog timer..............................................................................................................19 4.2.3 Programming notes ..........................................................................................................................19 CHAPTER 5 OSCILLATION CIRCUIT............................................................................. 20 5.1 Configuration of Oscillation Circuit................................................................................................................20 5.2 OSC1 Oscillation Circuit....................................................................................................................................20 5.3 OSC3 Oscillation Circuit....................................................................................................................................21 5.4 Operating Voltage Change ..............................................................................................................................22 5.5 Clock Frequency and Instruction Execution Time...................................................................................22 5.6 Control of Oscillation Circuit............................................................................................................................23 5.7 Programming Notes............................................................................................................................................25 CHAPTER 6 INPUT/OUTPUT PORTS............................................................................. 26 6.1 Input Port (Kxx) ....................................................................................................................................................26 6.1.1 Configuration of input ports ...........................................................................................................26 6.1.2 Mask option.........................................................................................................................................26 6.1.3 Interrupt function ...............................................................................................................................26 6.1.4 Control of input ports .......................................................................................................................27 6.1.5 Programming notes ..........................................................................................................................28 S1C60N07 TECHNICAL MANUAL EPSON i CONTENTS 6.2 Output Port (Rxx).................................................................................................................................................29 6.2.1 Configuration of output ports ........................................................................................................29 6.2.2 Mask option.........................................................................................................................................29 6.2.3 High impedance control..................................................................................................................31 6.2.4 Control of output ports ....................................................................................................................31 6.2.5 Programming notes ..........................................................................................................................32 6.3 I/O Port (Pxx) ........................................................................................................................................................33 6.3.1 Configuration of I/O ports...............................................................................................................33 6.3.2 Mask option.........................................................................................................................................33 6.3.3 I/O control register and input/output mode .............................................................................33 6.3.4 Pull up resistor...................................................................................................................................33 6.3.5 Control of I/O ports...........................................................................................................................34 6.3.6 Programming notes ..........................................................................................................................35 CHAPTER 7 LCD DRIVER ............................................................................................. 36 7.1 Drive Duty...............................................................................................................................................................36 7.2 Mask Option ..........................................................................................................................................................39 7.3 Display Data Memory.........................................................................................................................................39 7.4 Control of LCD Driver.........................................................................................................................................40 7.5 Programming Note ..............................................................................................................................................41 CHAPTER 8 TIMERS ..................................................................................................... 42 8.1 Clock Timer............................................................................................................................................................42 8.1.1 Configuration of clock timer...........................................................................................................42 8.1.2 Interrupt function ...............................................................................................................................42 8.1.3 Control of clock timer.......................................................................................................................43 8.1.4 Programming notes ..........................................................................................................................44 8.2 Stopwatch Timer..................................................................................................................................................45 8.2.1 Configuration of stopwatch timer ................................................................................................45 8.2.2 Count-up pattern ...............................................................................................................................45 8.2.3 Interrupt function ...............................................................................................................................46 8.2.4 Control of stopwatch timer.............................................................................................................47 8.2.5 Programming notes ..........................................................................................................................48 8.3 Programmable Timer..........................................................................................................................................49 8.3.1 Configuration of programmable timer ........................................................................................49 8.3.2 Interrupt function ...............................................................................................................................50 8.3.3 Control of programmable timer....................................................................................................51 8.3.4 Programming notes ..........................................................................................................................53 CHAPTER 9 SOUND GENERATOR ............................................................................... 54 9.1 Configuration of Sound Generator................................................................................................................54 9.2 Mask Option ..........................................................................................................................................................54 9.3 Frequency Setting ...............................................................................................................................................55 9.4 Digital Envelope ...................................................................................................................................................55 9.5 1-shot Output ........................................................................................................................................................56 9.6 Control of Sound Generator............................................................................................................................57 9.7 Programming Notes............................................................................................................................................59 CHAPTER 10 INTERRUPT AND HALT........................................................................... 60 10.1 Interrupt Factor Flag and Interrupt Mask..................................................................................................61 10.2 Interrupt Vector ..................................................................................................................................................62 10.3 Programming Notes .........................................................................................................................................62 ii EPSON S1C60N07 TECHNICAL MANUAL CONTENTS CHAPTER 11 SUMMARY OF NOTES............................................................................. 64 11.1 Notes for Low Current Consumption..........................................................................................................64 11.2 Summary of Notes by Function....................................................................................................................65 11.3 Precautions on Mounting ...............................................................................................................................69 CHAPTER 12 BASIC EXTERNAL CONNECTION DIAGRAM........................................... 71 CHAPTER 13 ELECTRICAL CHARACTERISTICS ..........................................................72 13.1 Absolute Maximum Rating.............................................................................................................................72 13.2 Recommended Operating Conditions.......................................................................................................72 13.3 DC Characteristics............................................................................................................................................72 13.4 Analog Circuit Characteristics and Consumed Current......................................................................73 13.5 AC Characteristics............................................................................................................................................74 13.6 Oscillation Characteristics..............................................................................................................................75 CHAPTER 14 PACKAGE ............................................................................................... 77 14.1 Plastic Package .................................................................................................................................................77 14.2 Ceramic Package for Test Samples ..........................................................................................................78 CHAPTER 15 PAD LAYOUT .......................................................................................... 79 15.1 Diagram of Pad Layout ...................................................................................................................................79 15.2 Pad Coordinates ...............................................................................................................................................80 S1C60N07 TECHNICAL MANUAL EPSON iii CHAPTER 1: OUTLINE CHAPTER 1 OUTLINE The S1C60N07 is a microcomputer with a C-MOS 4-bit core CPU S1C6200C as main component, and ROM, RAM, dot matrix LCD driver, time base counter and other circuits built-in. 1.1 Features Oscillation circuit ........................OSC1: 32.768 kHz (Typ.) Crystal or CR oscillation circuit (1) OSC3: 2 MHz (Max.) CR or ceramic oscillation circuit (1) Instruction set................................108 types Instruction execution time.......32.768 kHz: 152.6 sec 213.6 sec 366.2 sec 1 MHz: 5.0 sec 7.0 sec 12.0 sec 2 MHz: 2.5 sec 3.5 sec 6.0 sec ROM capacity ...............................4,096 words x 12 bits RAM capacity................................Data memory: 512 words x 4 bits Display memory: 160 words x 4 bits Input port.........................................4 bits (Pull-up resistors may be supplemented 1) Output port.....................................6 bits (Buzzer and clock outputs are possible 1) I/O port.............................................4 bits Dot matrix type LCD driver ..40 segments x 16 or 8 commons (2) Time base counter .......................Clock timer, stopwatch timer Programmable timer..................8-bit timer x 1 ch., with event counter and clock output functions Watchdog timer............................Built-in Sound generator...........................8 programmable sounds (8 types of frequency) with envelope and 1-shot output functions External interrupt.......................Input port interrupt: 1 system Internal interrupt.........................Clock timer interrupt: 1 system Stopwatch timer interrupt: 1 system Programmable timer interrupt: 1 system Power supply voltage.................2.2 V to 5.5 V (Min. 1.8 V when the OSC3 oscillation circuit is not used) Current consumption (Typ.)...During HALT: 32.768 kHz (crystal oscillation), 3.0 V 2.5 A During operation: 32.768 kHz (crystal oscillation), 3.0 V 6.5 A 2 MHz (CR oscillation), 3.0 V 1 mA Package.............................................QFP15-100pin (plastic) or chip 1: Can be selected with mask option 2: Can be selected with software S1C60N07 TECHNICAL MANUAL EPSON 1 CHAPTER 1: OUTLINE 1.2 Block Diagram ROM 4,096 words x 12 bits System Reset Control #RESET Core CPU S1C6200C OSC1 OSC2 OSC3 OSC4 OSC Interrupt Generator RAM Clock Timer 512 words x 4 bits COM0-15 SEG0-39 VDD VL1-VL5 CA-CF VREF VS1 VSS LCD Driver Watchdog Timer 40 SEG x 16 COM Stopwatch Timer Power Controller Programmable Timer/Counter Sound Generator R32 R33(PTCLK) R40(#FOUT) R41 R42(#BZ/FOUT) R43(BZ) Input Port K00-K03 #TEST I/O Port P00-P03 Output Port Fig. 1.2.1 Block diagram 2 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 1: OUTLINE 1.3 Pin Layout Diagram QFP15-100pin 75 51 50 76 INDEX 26 100 1 25 No. Pin name No. Pin name No. Pin name No. Pin name 1 VL4 26 N.C. 51 N.C. 76 N.C. 2 27 SEG39 52 SEG15 77 N.C. VL5 CF 3 28 SEG38 53 SEG14 78 N.C. CE 4 29 SEG37 54 SEG13 79 R43 CD 5 30 SEG36 55 SEG12 80 R42 CC 6 31 SEG35 56 SEG11 81 R41 CB 7 32 SEG34 57 SEG10 82 R40 CA 8 33 SEG33 58 SEG9 83 R33 COM0 9 34 SEG32 59 SEG8 84 R32 10 COM1 35 SEG31 60 SEG7 85 #RESET 11 COM2 36 SEG30 61 SEG6 86 #TEST 12 COM3 37 SEG29 62 SEG5 87 VSS 13 COM4 38 SEG28 63 SEG4 88 OSC4 14 COM5 39 SEG27 64 SEG3 89 OSC3 15 COM6 40 SEG26 65 SEG2 90 VS1 16 COM7 41 SEG25 66 SEG1 91 OSC2 17 COM8 42 SEG24 67 SEG0 92 OSC1 18 COM9 43 SEG23 68 K03 93 VDD 19 COM10 44 SEG22 69 K02 94 VREF 20 COM11 45 SEG21 70 K01 95 VL1 21 COM12 46 SEG20 71 K00 96 VL2 22 COM13 47 SEG19 72 P03 97 VL3 23 COM14 48 SEG18 73 P02 98 N.C. 24 COM15 49 SEG17 74 P01 99 N.C. 25 N.C. 50 SEG16 75 P00 100 N.C. N.C.: No Connection Fig. 1.3.1 Pin layout diagram 1.4 Pin Description Table 1.4.1 Pin description Pin name VDD VSS VS1 VL1-VL5 VREF CA-CF OSC1 OSC2 OSC3 OSC4 COM0-COM15 SEG0-SEG39 K00-K03 P00-P03 R32 R33 R40 R41 R42 R43 #RESET #TEST Pin No. 93 87 90 95-97, 1, 2 I/O - - - - 94 8-3 92 91 89 88 9-24 67-52, 50-27 71-68 75-72 84 83 82 81 80 79 85 86 O - I O I O O O I I/O O O O O O O I I Function Power supply (+) Power supply (-) Internal logic system/oscillation system regulated voltage output LCD system power supply 1/4 bias generated internally, 1/5 bias generated externally 1 LCD system power test pin 2 LCD system voltage booster condenser connecting pin Crystal or CR oscillator input 1 Crystal or CR oscillator output 1, CD buiil-in CR or ceramic oscillator input 1 CR or ceramic oscillator output 1 LCD common output (1/8 duty or 1/16 duty is selected on software) LCD segment output Input port (pull up resistor is available by mask option) 1 Complementary output I/O port or Nch open drain Output port output 1 Output port or PTCLK output Output port or #FOUT output 1 Output port Output port, #BZ output or FOUT output 1 Output port or BZ output 1 Initial reset input terminal Testing input terminal 3 1 Selected by mask option 2 Leave the VREF pin unconnected (N.C.). 3 The #TEST pin is used when the IC load is being detected. During ordinary operation be certain to connect this pin to VDD. S1C60N07 TECHNICAL MANUAL EPSON 3 CHAPTER 2: CPU AND BUILT-IN MEMORY CHAPTER 2 CPU AND BUILT-IN MEMORY 2.1 CPU and Instruction Set The S1C60N07 uses the 4-bit core CPU S1C6200C for its CPU. It has almost the same register configurations, instructions, and other features as the other family devices which use the S1C6200/6200A/6200B, allowing full use of software assets. The instruction set of the S1C60N07 has 108 types of instructions, all consisting of one word (12 bits). For detailed information on the CPU and the instruction set, refer to the "S1C6200/6200A Core CPU Manual". Note, however, that because S1C60N07 does not assume SLEEP operation, the SLP instruction is not available in the S1C6200 instruction set. The instruction list is shown in Tables 2.1.1(a)-(c). The following lists the symbols used in the instruction list: Symbols associated with registers and memory A B X Y XH XL YH YL XP YP SP SPH SPL MX, M(X) MY, M(Y) Mn, M(n) M(SP) r, q A register B register XHL register (low order eight bits of index register IX) YHL register (low order eight bits of index register IY) XH register (high order four bits of XHL register) XL register (low order four bits of XHL register) YH register (high order four bits of YHL register) YL register (low order four bits of YHL register) XP register (high order four bits of index register IX) YP register (high order four bits of index register IY) Stack pointer SP High-order four bits of stack pointer SP Low-order four bits of stack pointer SP Data memory whose address is specified with index register IX Data memory whose address is specified with index register IY Data memory address 000H-00FH (address specified with immediate data n of 00H-0FH) Data memory whose address is specified with stack pointer SP Two-bit register code r, q is two-bit immediate data; according to the contents of these bits, they indicate registers A, B, and MX and MY (data memory whose addresses are specified with index registers IX and IY) r r1 0 0 1 1 q r0 0 1 0 1 q1 0 0 1 1 q0 0 1 0 1 Register specified A B MX MY Symbols associated with program counter NBP NPP PCB PCP PCS PCSH PCSL 4 New bank pointer New page pointer Program counter bank Program counter page Program counter step Four high order bits of PCS Four low order bits of PCS EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 2: CPU AND BUILT-IN MEMORY Symbols associated with flags F C Z D I Flag register (I, D, Z, C) Carry flag Zero flag Decimal flag Interrupt flag Flag reset Flag set Flag set or reset Associated with immediate data p s l i Five-bit immediate data or label 00H-1FH Eight-bit immediate data or label 00H-0FFH Eight-bit immediate data 00H-0FFH Four-bit immediate data 00H-0FH Associated with arithmetic and other operations + Add Subtract Logical AND Logical OR Exclusive-OR Add-subtract instruction for decimal operation when the D flag is set S1C60N07 TECHNICAL MANUAL EPSON 5 CHAPTER 2: CPU AND BUILT-IN MEMORY Table 2.1.1(a) Instruction sets (1) Classification Mnemonic Operation Code Operand Flag B A 9 8 7 6 5 4 3 2 1 0 I D Z C Clock Operation p 1 1 1 0 0 1 0 p4 p3 p2 p1 p0 5 NBP p4, NPP p3~p0 s 0 0 0 0 s7 s6 s5 s4 s3 s2 s1 s0 5 PCB NBP, PCP NPP, PCS s7~s0 C, s 0 0 1 0 s7 s6 s5 s4 s3 s2 s1 s0 5 PCB NBP, PCP NPP, PCS s7~s0 if C=1 NC, s 0 0 1 1 s7 s6 s5 s4 s3 s2 s1 s0 5 PCB NBP, PCP NPP, PCS s7~s0 if C=0 Z, s 0 1 1 0 s7 s6 s5 s4 s3 s2 s1 s0 5 PCB NBP, PCP NPP, PCS s7~s0 if Z=1 NZ, s 0 1 1 1 s7 s6 s5 s4 s3 s2 s1 s0 5 PCB NBP, PCP NPP, PCS s7~s0 if Z=0 JPBA 1 1 1 1 1 1 1 0 1 0 0 0 5 PCB NBP, PCP NPP, PCSH B, PCSL A CALL s 0 1 0 0 s7 s6 s5 s4 s3 s2 s1 s0 7 M(SP-1) PCP, M(SP-2) PCSH, M(SP-3) PCSL+1 CALZ s 0 1 0 1 s7 s6 s5 s4 s3 s2 s1 s0 7 RET 1 1 1 1 1 1 0 1 1 1 1 1 7 RETS 1 1 1 1 1 1 0 1 1 1 1 0 12 RETD l 0 0 0 1 l7 l6 l5 l4 l3 l2 l1 l0 12 System NOP5 1 1 1 1 1 1 1 1 1 0 1 1 5 No operation (5 clock cycles) control NOP7 1 1 1 1 1 1 1 1 1 1 1 1 7 No operation (7 clock cycles) instructions HALT 1 1 1 1 1 1 1 1 1 0 0 0 5 Halt (stop clock) X 1 1 1 0 1 1 1 0 0 0 0 0 5 X X+1 operation Y 1 1 1 0 1 1 1 1 0 0 0 0 5 Y Y+1 instructions LD X, x 1 0 1 1 x7 x6 x5 x4 x3 x2 x1 x0 5 XH x7~x4, XL x3~x0 Y, y 1 0 0 0 y7 y6 y5 y4 y3 y2 y1 y0 5 YH y7~y4, YL y3~y0 XP, r 1 1 1 0 1 0 0 0 0 0 r1 r0 5 XP r XH, r 1 1 1 0 1 0 0 0 0 1 r1 r0 5 XH r XL, r 1 1 1 0 1 0 0 0 1 0 r1 r0 5 XL r YP, r 1 1 1 0 1 0 0 1 0 0 r1 r0 5 YP r YH, r 1 1 1 0 1 0 0 1 0 1 r1 r0 5 YH r YL, r 1 1 1 0 1 0 0 1 1 0 r1 r0 5 YL r r, XP 1 1 1 0 1 0 1 0 0 0 r1 r0 5 r XP r, XH 1 1 1 0 1 0 1 0 0 1 r1 r0 5 r XH r, XL 1 1 1 0 1 0 1 0 1 0 r1 r0 5 r XL r, YP 1 1 1 0 1 0 1 1 0 0 r1 r0 5 r YP r, YH 1 1 1 0 1 0 1 1 0 1 r1 r0 5 r YH r, YL 1 1 1 0 1 0 1 1 1 0 r1 r0 5 r YL XH, i 1 0 1 0 0 0 0 0 i3 i2 i1 i0 7 XH XH+i3~i0+C XL, i 1 0 1 0 0 0 0 1 i3 i2 i1 i0 7 XL XL+i3~i0+C YH, i 1 0 1 0 0 0 1 0 i3 i2 i1 i0 7 YH YH+i3~i0+C YL, i 1 0 1 0 0 0 1 1 i3 i2 i1 i0 7 YL YL+i3~i0+C Branch PSET instructions JP SP SP-3, PCP NPP, PCS s7~s0 M(SP-1) PCP, M(SP-2) PCSH, M(SP-3) PCSL+1 SP SP-3, PCP 0, PCS s7~s0 PCSL M(SP), PCSH M(SP+1), PCP M(SP+2) SP SP+3 PCSL M(SP), PCSH M(SP+1), PCP M(SP+2) SP SP+3, PC PC+1 PCSL M(SP), PCSH M(SP+1), PCP M(SP+2) SP SP+3, M(X) l 3~ l 0, M(X+1) l 7~ l 4, X X+2 Index INC ADC 6 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 2: CPU AND BUILT-IN MEMORY Table 2.1.1(b) Instruction sets (2) Classification Mnemonic Operation Code Operand Flag B A 9 8 7 6 5 4 3 2 1 0 I D Z C Clock Operation XH, i 1 0 1 0 0 1 0 0 i3 i2 i1 i0 7 XH-i3~i0 operation XL, i 1 0 1 0 0 1 0 1 i3 i2 i1 i0 7 XL-i3~i0 instructions YH, i 1 0 1 0 0 1 1 0 i3 i2 i1 i0 7 YH-i3~i0 YL, i 1 0 1 0 0 1 1 1 i3 i2 i1 i0 7 YL-i3~i0 r, i 1 1 1 0 0 0 r1 r0 i3 i2 i1 i0 5 r i3~i0 transfer r, q 1 1 1 0 1 1 0 0 r1 r0 q1 q0 5 r q instructions A, Mn 1 1 1 1 1 0 1 0 n3 n2 n1 n0 5 A M(n3~n0) B, Mn 1 1 1 1 1 0 1 1 n3 n2 n1 n0 5 B M(n3~n0) Mn, A 1 1 1 1 1 0 0 0 n3 n2 n1 n0 5 M(n3~n0) A Mn, B 1 1 1 1 1 0 0 1 n3 n2 n1 n0 5 M(n3~n0) B LDPX MX, i 1 1 1 0 0 1 1 0 i3 i2 i1 i0 5 M(X) i3~i0, X X+1 1 1 1 0 1 1 1 0 r1 r0 q1 q0 5 r q, X X+1 LDPY MY, i 1 1 1 0 0 1 1 1 i3 i2 i1 i0 5 M(Y) i3~i0, Y Y+1 1 1 1 0 1 1 1 1 r1 r0 q1 q0 5 r q, Y Y+1 1 0 0 1 l7 l6 l5 l4 l3 l2 l1 l0 5 M(X) l 3~ l 0, M(X+1) l 7~ l 4, X X+2 Index Data CP LD r, q r, q LBPX MX, l Flag SET F, i 1 1 1 1 0 1 0 0 i3 i2 i1 i0 7 F F i3~i0 operation RST F, i 1 1 1 1 0 1 0 1 i3 i2 i1 i0 7 F F i3~i0 instructions SCF 1 1 1 1 0 1 0 0 0 0 0 1 7 C 1 RCF 1 1 1 1 0 1 0 1 1 1 1 0 7 C 0 SZF 1 1 1 1 0 1 0 0 0 0 1 0 7 Z 1 RZF 1 1 1 1 0 1 0 1 1 1 0 1 7 Z 0 SDF 1 1 1 1 0 1 0 0 0 1 0 0 7 D 1 (Decimal Adjuster ON) RDF 1 1 1 1 0 1 0 1 1 0 1 1 7 D 0 (Decimal Adjuster OFF) EI 1 1 1 1 0 1 0 0 1 0 0 0 7 I 1 (Enables Interrupt) DI 1 1 1 1 0 1 0 1 0 1 1 1 7 I 0 (Disables Interrupt) Stack INC SP 1 1 1 1 1 1 0 1 1 0 1 1 5 SP SP+1 operation DEC SP 1 1 1 1 1 1 0 0 1 0 1 1 5 SP SP-1 1 1 1 1 1 1 0 0 0 0 r1 r0 5 SP SP-1, M(SP) r XP 1 1 1 1 1 1 0 0 0 1 0 0 5 SP SP-1, M(SP) XP XH 1 1 1 1 1 1 0 0 0 1 0 1 5 SP SP-1, M(SP) XH XL 1 1 1 1 1 1 0 0 0 1 1 0 5 SP SP-1, M(SP) XL YP 1 1 1 1 1 1 0 0 0 1 1 1 5 SP SP-1, M(SP) YP YH 1 1 1 1 1 1 0 0 1 0 0 0 5 SP SP-1, M(SP) YH YL 1 1 1 1 1 1 0 0 1 0 0 1 5 SP SP-1, M(SP) YL F 1 1 1 1 1 1 0 0 1 0 1 0 5 SP SP-1, M(SP) F r 1 1 1 1 1 1 0 1 0 0 r1 r0 5 r M(SP), SP SP+1 XP 1 1 1 1 1 1 0 1 0 1 0 0 5 XP M(SP), SP SP+1 XH 1 1 1 1 1 1 0 1 0 1 0 1 5 XH M(SP), SP SP+1 XL 1 1 1 1 1 1 0 1 0 1 1 0 5 XL M(SP), SP SP+1 YP 1 1 1 1 1 1 0 1 0 1 1 1 5 YP M(SP), SP SP+1 instructions PUSH r POP S1C60N07 TECHNICAL MANUAL EPSON 7 CHAPTER 2: CPU AND BUILT-IN MEMORY Table 2.1.1(c) Instruction sets (3) Classification Mnemonic Operand Flag B A 9 8 7 6 5 4 3 2 1 0 I D Z C Clock Operation YH 1 1 1 1 1 1 0 1 1 0 0 0 5 YH M(SP), SP SP+1 operation YL 1 1 1 1 1 1 0 1 1 0 0 1 5 YL M(SP), SP SP+1 instructions F 1 1 1 1 1 1 0 1 1 0 1 0 5 F M(SP), SP SP+1 SPH, r 1 1 1 1 1 1 1 0 0 0 r1 r0 5 SPH r SPL, r 1 1 1 1 1 1 1 1 0 0 r1 r0 5 SPL r r, SPH 1 1 1 1 1 1 1 0 0 1 r1 r0 5 r SPH r, SPL 1 1 1 1 1 1 1 1 0 1 r1 r0 5 r SPL Stack POP LD Arithmetic r, i 1 1 0 0 0 0 r1 r0 i3 i2 i1 i0 7 r r+i3~i0 r, q 1 0 1 0 1 0 0 0 r1 r0 q1 q0 7 r r+q r, i 1 1 0 0 0 1 r1 r0 i3 i2 i1 i0 7 r r+i3~i0+C r, q 1 0 1 0 1 0 0 1 r1 r0 q1 q0 7 r r+q+C SUB r, q 1 0 1 0 1 0 1 0 r1 r0 q1 q0 7 r r-q SBC r, i 1 1 0 1 0 1 r1 r0 i3 i2 i1 i0 7 r r-i3~i0-C r, q 1 0 1 0 1 0 1 1 r1 r0 q1 q0 7 r r-q-C r, i 1 1 0 0 1 0 r1 r0 i3 i2 i1 i0 7 r r i3~i0 r, q 1 0 1 0 1 1 0 0 r1 r0 q1 q0 7 r r q r, i 1 1 0 0 1 1 r1 r0 i3 i2 i1 i0 7 r r i3~i0 r, q 1 0 1 0 1 1 0 1 r1 r0 q1 q0 7 r r q r, i 1 1 0 1 0 0 r1 r0 i3 i2 i1 i0 7 r r i3~i0 r, q 1 0 1 0 1 1 1 0 r1 r0 q1 q0 7 r r q r, i 1 1 0 1 1 1 r1 r0 i3 i2 i1 i0 7 r-i3~i0 r, q 1 1 1 1 0 0 0 0 r1 r0 q1 q0 7 r-q r, i 1 1 0 1 1 0 r1 r0 i3 i2 i1 i0 7 r i3~i0 r, q 1 1 1 1 0 0 0 1 r1 r0 q1 q0 7 r q RLC r 1 0 1 0 1 1 1 1 r1 r0 r1 r0 7 d3 d2, d2 d1, d1 d0, d0 C, C d3 RRC r 1 1 1 0 1 0 0 0 1 1 r1 r0 5 d3 C, d2 d3, d1 d2, d0 d1, C d0 INC Mn 1 1 1 1 0 1 1 0 n3 n2 n1 n0 7 M(n3~n0) M(n3~n0)+1 DEC Mn 1 1 1 1 0 1 1 1 n3 n2 n1 n0 7 M(n3~n0) M(n3~n0)-1 ACPX MX, r 1 1 1 1 0 0 1 0 1 0 r1 r0 7 M(X) M(X)+r+C, X X+1 ACPY MY, r 1 1 1 1 0 0 1 0 1 1 r1 r0 7 M(Y) M(Y)+r+C, Y Y+1 SCPX MX, r 1 1 1 1 0 0 1 1 1 0 r1 r0 7 M(X) M(X)-r-C, X X+1 SCPY MY, r 1 1 1 1 0 0 1 1 1 1 r1 r0 7 M(Y) M(Y)-r-C, Y Y+1 7 r r ADD instructions ADC AND OR XOR CP FAN NOT 8 Operation Code r 1 1 0 1 0 0 r1 r0 1 1 1 1 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 2: CPU AND BUILT-IN MEMORY 2.2 Program Memory (ROM) The built-in ROM, a mask ROM for loading the program, has a capacity of 4,096 steps x 12 bits. The program area consists of 16 (0-15) pages x 256 (00H-FFH) steps. After initial reset, the program beginning address is set to bank 0, page 1, step 00H. The interrupt vector is allocated to page 1, steps 02H-0CH. Bank 0 Page 0 Page 1 Page 2 Page 3 Page 4 Page 5 Page 6 Page 7 Page 8 Page 9 Page 10 Page 11 Page 12 Page 13 Page 14 Page 15 Step 00H Step 02H Program start address Interrupt vector Step 0CH Step 0DH Step FFH 12 bits Fig. 2.2.1 Configuration of the built-in ROM 2.3 Data Memory (RAM) The S1C60N07 built-in data memories are configured a general-purpose RAM, display data memory of the LCD, and I/O data memory which controls the peripheral circuit. General-purpose RAM: 512 words x 4 bits (000H-1FFH) Display data memory: 160 words x 4 bits (E00H-E4FH, E80H-ECFH) I/O memory: 33 words x 4 bits (F00H-F7FH) During programming, take note of the following: (1) Since the stack area is taken from the RAM area, take care that destruction of stack data due to data writing does not occur. Sub-routine calls or interrupts consume 3 words of the stack area. (2) RAM address 000H-00FH are memory register areas that are addressed with register pointer RP. The memory map of the built-in data memory (RAM) and details of the I/O data memory map are shown in Figure 2.3.1 and Tables 2.3.1(a)-(c), respectively. Note: Memory is not mounted in unused area within the memory map and in memory area not indicated in this chapter. For this reason, normal operation cannot be assured for programs that have been prepared with access to these areas. S1C60N07 TECHNICAL MANUAL EPSON 9 CHAPTER 2: CPU AND BUILT-IN MEMORY Address Low Address 0 Page High 0 1 2 3 4 5 6 7 0 8 9 A B C D E F 0 1 2 3 4 5 6 7 1 8 9 A B C D E F 1 2 3 4 5 6 7 8 9 A B C D E M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF RAM (256 words x 4 bits) R/W RAM (256 words x 4 bits) R/W Low F 0 Page High 0 1 2 3 4 5 6 7 E 8 9 A B C D E F 0 1 2 3 F 4 5 6 7 1 2 3 4 5 6 7 8 9 A B C D E F Display data memory (80 words x 4 bits) R/W Display data memory (80 words x 4 bits) R/W I/O memory Unused area Fig. 2.3.1 Memory map 10 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 2: CPU AND BUILT-IN MEMORY Table 2.3.1(a) I/O data memory map (1) Address Register D2 D1 D3 IT1 IT2 D0 IT8 IT32 ISW1 ISW0 F00H R 0 0 F01H R 0 0 IPT 0 F02H R 0 0 0 IK0 F04H R EIT1 EIT8 EIT32 EISW1 EISW0 EIT2 F10H R/W 0 0 F11H R 0 R/W 0 0 EIPT F12H R/W R EIK03 EIK02 EIK01 EIK00 F14H R/W TM3 TM2 TM1 TM0 TM5 TM4 SWL1 SWL0 F20H R TM7 TM6 F21H R SWL3 SWL2 F22H R SWH3 SWH2 SWH1 SWH0 F23H R PT3 PT2 PT1 PT0 F24H R PT7 PT6 PT5 PT4 F25H R 1 3 5 Initial value following initial reset Reset (0) immediately after being read Undefined S1C60N07 TECHNICAL MANUAL Name IT1 *3 IT2 *3 IT8 *3 IT32 *3 0 *4 0 *4 ISW1 *3 ISW0 *3 0 *4 0 *4 0 *4 IPT *3 0 *4 0 *4 0 *4 IK0 *3 EIT1 EIT2 EIT8 EIT32 0 *4 0 *4 EISW1 EISW0 0 *4 0 *4 0 *4 EIPT EIK03 EIK02 EIK01 EIK00 TM3 TM2 TM1 TM0 TM7 TM6 TM5 TM4 SWL3 SWL2 SWL1 SWL0 SWH3 SWH2 SWH1 SWH0 PT3 PT2 PT1 PT0 PT7 PT6 PT5 PT4 2 4 Init *1 0 0 0 0 - *2 - *2 0 0 - *2 - *2 - *2 0 - *2 - *2 - *2 0 0 0 0 0 - *2 - *2 0 0 - *2 - *2 - *2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X *5 X *5 X *5 X *5 X *5 X *5 X *5 X *5 Comment 1 Yes Yes Yes Yes 0 No No No No Interrupt factor flag (clock timer 1 Hz) Interrupt factor flag (clock timer 2 Hz) Interrupt factor flag (clock timer 8 Hz) Interrupt factor flag (clock timer 32 Hz) Yes Yes No No Interrupt factor flag (stopwatch 1 Hz) Interrupt factor flag (stopwatch 10 Hz) Yes No Interrupt factor flag (programmable timer) Yes Enable Enable Enable Enable No Mask Mask Mask Mask Interrupt factor flag (K00-K03) Interrupt mask register (clock timer 1 Hz) Interrupt mask register (clock timer 2 Hz) Interrupt mask register (clock timer 8 Hz) Interrupt mask register (clock timer 32 Hz) Enable Enable Mask Mask Interrupt mask register (stopwatch 1 Hz) Interrupt mask register (stopwatch 10 Hz) Enable Enable Enable Enable Enable Mask Mask Mask Mask Mask Interrupt mask register (programmble timer) Interrupt mask register (K03) Interrupt mask register (K02) Interrupt mask register (K01) Interrupt mask register (K00) Clock timer data (16 Hz) Clock timer data (32 Hz) Clock timer data (64 Hz) Clock timer data (128 Hz) Clock timer data (1 Hz) Clock timer data (2 Hz) Clock timer data (4 Hz) Clock timer data (8 Hz) MSB Stopwatch timer 1/100 sec data (BCD) LSB MSB Stopwatch timer 1/10 sec data (BCD) LSB MSB Programmable timer data (low-order) LSB MSB Programmable timer data (high-order) LSB Not set in the circuit Always "0" when being read EPSON 11 CHAPTER 2: CPU AND BUILT-IN MEMORY Table 2.3.1(b) I/O data memory map (2) Address D3 Register D2 D1 D0 RD3 RD2 RD0 RD1 F26H R/W RD7 RD6 RD5 RD4 K01 K00 F27H R/W K03 K02 F40H R R33 F53H R32 0 0 R/W R43 R R42 R41 R40 R/W Name RD3 RD2 RD1 RD0 RD7 RD6 RD5 RD4 K03 K02 K01 K00 R33 Init *1 X *5 X *5 X *5 X *5 X *5 X *5 X *5 X *5 - *2 - *2 - *2 - *2 X *5 R32 0 *4 0 *4 R43 X *5 - *2 - *2 1 R42 1 R41 R40 1 1 F54H P03 P02 F60H R/W CLKCHG OSCC VSC1 F70H R/W ALOFF ALON LDUTY F71H R/W LC3 LC2 LC1 F72H R/W SHOTPW BZFQ2 BZFQ1 F74H R/W BZSHOT ENVRST F75H W W R 0 0 F76H R 0 0 F77H R 1 3 6 12 P03 P02 P01 P00 CLKCHG VSC0 OSCC VSC1 VSC0 ALOFF HLMOD ALON LDUTY HLMOD LC3 LC0 LC2 LC1 LC0 SHOTPW BZFQ0 BZFQ2 BZFQ1 BZFQ0 X X X X 0 0 0 0 1 0 0 0 X X X X 0 0 0 0 ENVON BZSHOT 0 P00 P01 ENVRT *5 *5 *5 *5 Comment 0 MSB Programmable timer reload data (low-order) LSB MSB Programmable timer reload data (high-order) LSB High High High High High Off High Low Low Low Low Low On Low High Off High Off *6 High High Off High High High High OSC3 On Low On Low On *6 Low Low On Low Low Low Low OSC1 Off Output port (R43) Buzzer output (BZ) Output port (R42) Clock output (FOUT) [Buzzer inverted output (#BZ)] Output port (R41) Output port (R40) Clock inverted output (#FOUT) All off All on 1/8 HLMOD Normal Normal 1/16 Normal All LCD dots fade out control All LCD dots displayed control LCD drive duty switch Heavy load protection mode Input port (K00-K03) Output port (R33) PTCLK output Output port (R32) I/O port (P00-P03) CPU system clock switch OSC3 oscillation On/Off CPU operating voltage switch *5 LCD contrast adjustment LC3-LC0 = 0 light : LC3-LC0 = 15 dark *5 *5 *5 ENVRST RESET ENVRT 0 ENVON 0 0 *4 - *2 TMRST WDRST 0 *4 - *2 *4 TMRST Reset W WDRST Reset 0 *4 - *2 SWRST SWRUN 0 *4 - *2 *4 SWRST Reset R/W W SWRUN 0 R/W 1 62.5 ms 31.25 ms 1-shot buzzer pulse width Buzzer frequency selection Trigger BUSY Reset 1.0 sec On - READY - 0.5 sec Off Reset Reset - - Reset Run - Stop 1-shot buzzer trigger (W) Status (R) Envelope reset Envelope cycle selection Envelope On/Off Clock timer reset Watchdog timer reset Stopwatch timer reset Stopwatch timer Run/Stop Initial value following initial reset 2 Not set in the circuit Reset (0) immediately after being read 4 Always "0" when being read 5 Undefined When selecting options enclosed in brackets [ ] as output option, the output register will function as register only and will not affect the individual outputs. EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 2: CPU AND BUILT-IN MEMORY Table 2.3.1(c) I/O data memory map (3) Address Register D2 D1 D3 0 0 PTRST F78H W R PTCOUT PTC2 PTC1 F79H R/W HZR3 0 0 F7BH R/W 0 R 0 0 F7DH R 0 0 0 F7EH R 0 0 F7FH R 1 3 5 0 D0 Name 0 *4 PTRUN 0 *4 *4 PTRST R/W PTRUN PTCOUT PTC0 PTC2 PTC1 PTC0 HZR3 0 0 *4 0 *4 0 *4 0 *4 IOC0 0 *4 0 *4 R/W IOC0 0 *4 PUP0 0 *4 0 *4 R/W PUP0 0 *4 LCDOFF 0 *4 0 *4 R/W LCDOFF Initial value following initial reset Reset (0) immediately after being read Undefined S1C60N07 TECHNICAL MANUAL 2 4 Init *1 1 - *2 - *2 Reset Reset Run 0 On 0 0 0 0 Output 0 - *2 - *2 - *2 - *2 - *2 - *2 Output 0 - *2 - *2 - *2 Off 0 - *2 - *2 - *2 Normal 1 Comment 0 - Stop Off Programmable timer reset Programmable timer Run/Stop Programmable timer clock output Programmable timer input clock selection High-Z Input R32-R33 output high-impedance control I/O control (P00-P03) On I/O pull up resistor On/Off (P00-P03) Off LCD display control Not set in the circuit Always "0" when being read EPSON 13 CHAPTER 3: POWER SOURCE CHAPTER 3 POWER SOURCE 3.1 Power Supply System The S1C60N07 operating power voltage is as follows: 2.2-5.5 V (Min. 1.8 V, when OSC3 oscillation circuit is not used) The S1C60N07 operates when a single power supply within the above range is applied between VDD and VSS. Even if the voltage is not within the above range necessary for the internal circuits, the IC itself can generate the following built-in power circuits. Table 3.1.1 Power supply circuits Circuit Power supply circuit Oscillation circuit and internal circuits Regulated voltage circuit LCD driver LCD system voltage circuit Output voltage VS1 VL1 -VL5 Notes: * VL3 is used only when the driving voltage of the LCD system will be supplied externally (1/5 bias); when using the internal LCD system voltage circuit (1/4 bias), it should be shorted with VL2. * See "13 Electrical Characteristics" for voltage values. V DD Internal circuit VS1 V S1 Regulated voltage circuit Oscillation circuit OSC1-4 V L1 V L2 V L3 V L4 V L5 External power supply CA CB CC V L1 -V L5 LCD system voltage circuit LCD driver COM0-15 SEG0-39 CD CE CF VSS Fig. 3.1.1 Configuration of power supply 14 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 3: POWER SOURCE 3.2 Heavy Load Protection Mode Because the load of the battery in the S1C60N07 becomes heavy due to the buzzer, lamp, and other features, it has been equipped with heavy load protection function in case of power voltage drop. This functions works in the heavy load protection mode. Based on the workings of the heavy load protection function, the S1C60N07 realizes operation at 2.2 V (Min. 1.8 V, when OSC3 oscillation circuit is not used) source voltage. When driving heavy loads, set the IC to heavy load protection mode. At the normal mode, the LCD system regulated voltage is created with VL2; VL1 is 1/2 reduced VL2 voltage while VL4 and VL5 are created by boosting to 1.5 and 2 times voltages, respectively. On the other hand, at the heavy load protection mode, the regulated voltage is VL1; VL2, VL4, and VL5 are created by boosting to 2, 3 and 4 times voltages. Because of this, the consumed current becomes greater than that in the normal mode, be careful not to set the heavy load protection unless necessary. The LCD system voltage modes are shown in Table 3.2.1. Terminal VL1 VL2 VL4 VL5 Table 3.2.1 LCD system voltage mode Normal mode Heavy load protection mode 1/2 VL2 VL1 regulated voltage VL2 regulated voltage 2 VL1 3/2 VL2 3 VL1 4/2 VL2 4 VL1 3.2.1 Control of heavy load protection mode The control register for the heavy load protection mode are explained below. Table 3.2.1.1 Control register for heavy load protection mode Address D3 ALOFF Register D2 D1 ALON LDUTY F71H R/W D0 HLMOD Name ALOFF ALON LDUTY HLMOD Init 1 0 0 0 1 All off All on 1/8 HLMOD 0 Normal Normal 1/16 Normal Comment All LCD dots fade out control All LCD dots displayed control LCD drive duty switch Heavy load protection mode HLMOD (F71H [D0], R/W) Controls the heavy load protection mode. When "1" is written: Heavy load protection mode is set When "0" is written: Heavy load protection mode is released Reading: Valid Conversion to heavy load protection mode is done by writing "1" to HLMOD while cancellation of this mode is done by writing "0". At initial reset, the mode is set to "0" (heavy load protection mode cancellation). 3.2.2 Programming notes (1) When driving heavy loads, set it to heavy load protection mode. Unless it is necessary, be careful not to set the heavy load protection mode with the software. (2) Perform heavy load driving only after setting up at least 1 ms wait time through the software, after switching to the heavy load protection mode. (See Figure 3.2.2.1.) (3) When the heavy load protection mode is to canceled after completion of heavy load driving, set up at least 2 seconds wait time through the software. (See Figure 3.2.2.1.) S1C60N07 TECHNICAL MANUAL EPSON 15 CHAPTER 3: POWER SOURCE Heavy load ON OFF Heavy load protection mode ON OFF 1 ms or more 2 sec or more Fig. 3.2.2.1 Control timing for heavy load protection mode 3.3 CPU Operating Voltage Change During operation, S1C60N07 can change OSC1 and OSC3 system clocks through the software, and operation at clock mode or high-speed mode is then possible. In this case, to obtain stable operating, operating voltage VS1 of the internal circuit is changed through the software. For details, see Chapter 5, "Oscillation Circuit". 16 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 4: INITIAL RESET CHAPTER 4 INITIAL RESET 4.1 Initial Reset Factors The S1C60N07 requires initial reset function to initialize the circuits. There are three types of initial reset factors: (1) Initial reset by power-on reset (2) External reset through low level input to the #RESET terminal (3) External initial reset by simultaneous low level input of K00-K03 terminals (mask option) (4) Initial reset by watchdog timer Note: The S1C60N07 must be reset after turning power on using the initial reset factor (1) or (2). Figure 4.1.1 shows the configuration of the initial reset circuit. OSC1 OSC2 OSC1 oscillation circuit Power-on reset circuit Mask option VDD Watchdog timer K00 K01 Time authorize circuit K02 Noise rejector Internal initial reset K03 VDD #RESET Fig. 4.1.1 Configuration of initial reset circuit 4.1.1 Power-on reset circuit The power-on reset circuit outputs the initial reset signal at power-on until the oscillation circuit starts oscillating. Note: The power-on reset circuit may not work properly due to unstable or lower voltage input. The following two initial reset method are recommended to generate the initial reset signal. 4.1.2 External initial reset by the #RESET terminal An initial reset can be executed externally by setting the reset terminal to low level. This low level must be maintained for at least 2 ms (in case oscillation frequency fOSC1 = 32.768 kHz), because the initial reset circuit contains a noise rejector. When the reset terminal goes high, the CPU will start operating. S1C60N07 TECHNICAL MANUAL EPSON 17 CHAPTER 4: INITIAL RESET 4.1.3 External initial reset by simultaneous low level input of K00-K03 terminals Initial reset may be done by simultaneously providing low level input externally to the input port (K00- K03) selected by mask option. Because the initial reset circuit has time authorize circuit built-in, keep the specified input port terminal at Low level for at least 2 seconds (in case oscillation frequency fOSC1 = 32.768 kHz). The input port combination which can be selected from the mask option are as follows: * Not use * K00K01 * K00K01K02 * K00K01K02K03 4.1.4 Initial reset by watchdog timer If the CPU runs away for some reason, the watchdog timer will detect this situation and output an initial reset signal. See "4.2 Watchdog Timer" for details. 4.1.5 Internal register at initial resetting The CPU is initialized by initial resetting as follows: Table 4.1.5.1 Initial values CPU Core Name Symbol Bit size Program counter step PCS 8 Program counter page PCP 4 Program counter bank PCB 1 New page pointer NPP 4 New bank pointer NBP 1 Stack pointer SP 8 Index register X X 12 Index register Y Y 12 Register pointer RP 4 General-purpose register A A 4 General-purpose register B B 4 Interrupt flag I 1 Decimal flag D 1 Zero flag Z 1 Carry flag C 1 Initial value 00H 1H 0 1H 0 Undefined Undefined Undefined Undefined Undefined Undefined 0 0 Undefined Undefined Peripheral Circuits Bit size Initial value RAM 512 x 4 Undefined Display memory 160 x 4 Undefined Other peripheral circuits - See Tables 2.3.1(a)-(c). Name 18 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 4: INITIAL RESET 4.2 Watchdog Timer 4.2.1 Configuration of watchdog timer S1C60N07 has a built-in watchdog timer with OSC1 (clock timer 1 Hz signal) basic oscillation. The watchdog timer needs to be reset periodically through the software, and if not reset within 3-4 seconds, it automatically generates an initial reset signal to the CPU. Figure 4.2.1.1 shows the configuration of the watchdog timer. Clock timer TM0-TM7 OSC1 demultiplier (256 Hz) 1 Hz Watchdog timer Initial reset signal Watchdog timer reset signal Fig. 4.2.1.1 Configuration of watchdog timer By resetting the watchdog timer during the program's main routine, program runaways which do not pass the watchdog timer processing during main routine can be detected. Note, however, that the watchdog timer operates even during HALT such that if the HALT condition continues for 3-4 seconds, it is re-initiated through initial resetting. 4.2.2 Control of watchdog timer The control register of the watchdog timer is explained below. Table 4.2.2.1 Control register of watchdog timer Address Register D2 D1 D3 0 0 D0 TMRST WDRST F76H R W Name 0 0 TMRST WDRST Init - - Reset Reset 1 0 Reset Reset - - Comment Clock timer reset Watchdog timer reset WDRST (F76H [D0], W) This bit resets the watchdog timer. When "1" is written: Watchdog timer reset When "0" is written: No operation Reading: Always "0" By writing "1" on WDRST, the watchdog timer is reset, after which it is immediately restarted. Writing "0" will mean no operation. Because this bit is only for writing, it is always set to "0" during reading. 4.2.3 Programming notes (1) The watchdog timer must reset within 3-second cycles by the software. (2) When the clock timer is reset (TMRST "1"), the watchdog timer is counted up; reset the watchdog immediately after if necessary. S1C60N07 TECHNICAL MANUAL EPSON 19 CHAPTER 5: OSCILLATION CIRCUIT CHAPTER 5 OSCILLATION CIRCUIT 5.1 Configuration of Oscillation Circuit The S1C60N07 has two oscillation circuits (OSC1 and OSC3). OSC1 is either a crystal or a CR oscillation circuit that supplies the operating clock to the CPU and peripheral circuits. OSC3 is either a CR or a ceramic oscillation circuit. When processing with the S1C60N07 requires high-speed operation, the CPU operating clock can be switched from OSC1 to OSC3 by the software. To stabilize operation of the internal circuits, the operating voltage VS1 must be switched according to the oscillation circuit to be used. Figure 5.1.1 is the block diagram of this oscillation system. OSC1 oscillation circuit Divider To peripheral circuits Clock switch OSC3 oscillation circuit To CPU CPU clock selection signal Oscillation circuit control signal V S1 Oscillation system voltage regulator Operating voltage selection signal Fig. 5.1.1 Oscillation system block diagram 5.2 OSC1 Oscillation Circuit The OSC1 oscillation circuit generates the main clock for the CPU and the peripheral circuits. Either the crystal oscillation circuit or the CR oscillation circuit can be selected as the circuit type by mask option. Figure 5.2.1 shows the configuration of the OSC1 oscillation circuit. VDD Rfx CGX RDX OSC1 X'tal To CPU and peripheral circuit CDX VDD OSC2 (1) Crystal oscillation circuit OSC1 RCR1 To CPU and peripheral circuit CCR OSC2 (2) CR oscillation circuit Fig. 5.2.1 OSC1 oscillation circuit As shown in Figure 5.2.1, the crystal oscillation circuit can be configured simply by connecting the crystal oscillator (X'tal) of 32.768 kHz (Typ.) and the feedback resistor Rfx (10 M) between the OSC1 and OSC2 terminals and the trimmer capacitor (CGX) between the OSC1 and VDD terminals when crystal oscillation is selected. When CR oscillation is selected by mask option, connect the resistor R CR1 between the OSC1 and OSC2 terminals. See "13 Electrical Characteristics" for resistance value of R CR1. Notes: * The current consumption of CR oscillation is larger than crystal oscillation. * Be aware that the CR oscillation frequency changes slightly. Pay special attention to the circuits that use f OSC1 as the source clock, such as the timer (time lag), the LCD frame frequency (display quality, flicker in low frequency) and the sound generator (sound quality). 20 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 5: OSCILLATION CIRCUIT 5.3 OSC3 Oscillation Circuit The S1C60N07 has built-in the OSC3 oscillation circuit that generates the CPU's sub-clock (Max. 2 MHz) for high speed operation. The mask option enables selection of either the CR or ceramic oscillation circuit. When CR oscillation is selected, only a resistance is required as an external element. When ceramic oscillation is selected, a ceramic oscillator and two capacitors (gate and drain capacitance) are required. Figure 5.3.1 shows the configuration of the OSC3 oscillation circuit. CCR OSC3 RCR2 To CPU and SIO OSC4 Oscillation circuit control signal (1) CR oscillation circuit CDC To CPU and SIO RDC Ceramic OSC3 Rfc VDD CGC OSC4 Oscillation circuit control signal (2) Ceramic oscillation circuit Fig. 5.3.1 OSC3 oscillation circuit As shown in Figure 5.3.1, the CR oscillation circuit can be configured simply by connecting the resistor R CR2 between the OSC3 and OSC4 terminals when CR oscillation is selected. See "13 Electrical Characteristics" for resistance value of R CR2. When ceramic oscillation is selected, the ceramic oscillation circuit can be configured by connecting the ceramic oscillator (Max. 2 MHz) and feedback resistor Rfc (about 1 M) between the OSC3 and OSC4 terminals, capacitor C GC between the OSC3 and OSC4 terminals, and capacitor C DC between the OSC4 and VDD terminals. For both C GC and C DC, connect capacitors that are about 100 pF. To reduce current consumption of the OSC3 oscillation circuit, oscillation can be stopped by the software (OSCC register). When the OSC3 oscillation circuit is not used, connect the OSC3 terminal to VS1. VDD VS1 OSC3 Fig. 5.3.2 Connection diagram when the OSC3 oscillation circuit is unused S1C60N07 TECHNICAL MANUAL EPSON 21 CHAPTER 5: OSCILLATION CIRCUIT 5.4 Operating Voltage Change S1C60N07 can change OSC1 and OSC3 system clocks through the software. In this case, to obtain stable operation, operating voltage VS1 of the internal circuit is changed through the software. Likewise, when selecting OSC1 as the system clock, there is need to change operating voltage VS1 according to the value of the power voltage (V DD-VSS). Oscillation frequency and the corresponding operating voltage VS1 are shown in Table 5.4.1. Table 5.4.1 Oscillation frequency and operating voltage Oscillation frequency Oscillation circuit Operating voltage VS1 32.768 kHz OSC1 -1.2 V or -2.1 V 1 MHz OSC3 -2.1 V 2 MHz OSC3 -3.0 V The VDD reference voltage is used as the operating voltage VS1. When OSC3 is to be used as the CPU system clock, change the operating voltage VS1 accordingly through the software and then turn the OSC3 oscillation ON and switch the clock frequency. If the OSC3 oscillation frequency is to be fixed around 1 MHz, set the operating voltage to -2.1 V; at 2 MHz, set the operating voltage to -3.0 V. Moreover, when the CPU is to be operated with OSC1, set the operating voltage to -1.2 V if the power voltage is less than 3.1 V (V DD-VSS < 3.1 V); set the operating voltage to -2.1 V if the voltage is 3.1 V or more (V DD-VSS 3.1 V). However, it can be used fixed at -1.2 V (at OSC1 operation) for power whose initial value is 3.6 V or less as in lithium batteries. Note: Switching VS1 when the power source voltage is lower than the set voltage may cause misoperation. 5.5 Clock Frequency and Instruction Execution Time Table 5.5.1 shows the instruction execution time according to each frequency of the system clock. Table 5.5.1 Clock frequency and instruction execution time Clock frequency Instruction execution time (s) 5-clock instruction 7-clock instruction 12-clock instruction 32.768 kHz 152.6 213.6 366.2 1 MHz 5.0 7.0 12.0 2 MHz 2.5 3.5 6.0 22 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 5: OSCILLATION CIRCUIT 5.6 Control of Oscillation Circuit The control registers for the oscillation circuit are explained below. Table 5.6.1 Control registers of oscillation circuit Address D3 CLKCHG Register D2 D1 OSCC VSC1 F70H R/W D0 VSC0 Name CLKCHG OSCC VSC1 VSC0 Init 0 0 0 0 1 OSC3 On 0 OSC1 Off Comment CPU system clock switch OSC3 oscillation On/Off CPU operating voltage switch VSC0 and VSC1 (F70H [D0 and D1], R/W) Switches the operating voltage of the internal circuit in accordance to the oscillation frequency and power source voltage. The corresponding setting description is shown in Table 5.6.2. Table 5.6.2 Corresponding between oscillation frequency, power source voltage, and operating voltage (VS1) VSC1 VSC0 VS1 Oscillation circuit Oscillation frequency Power source voltage (VDD -VSS) 0 0 -1.2 V OSC1 32.768 kHz Under 3.1 V 0 1 -2.1 V OSC1 32.768 kHz 3.1 V or more () 0 1 -2.1 V OSC3 1 MHz 2.2 V or more 1 x -3.0 V OSC3 2 MHz 3.1 V or more The VDD reference voltage is used as the operating voltage VS1. There is no need to set the () state with regards to power whose initial value is 3.6 V or less as in lithium batteries. VSC1 and VSC0 are set to "0" at initial reset. Notes: * When switching VS1 from -1.2 V (for OSC1 crystal oscillation circuit) to -3.0 V (for OSC3 oscillation circuit), or vice versa, be sure to hold the -2.1 V setting for more than 5 ms first for power voltage stabilization. (VSC1, VSC0) = (0, 0) (0, 1) 5 ms WAIT (1, x) = (1, x) (0, 1) 5 ms WAIT (0, 0) = (0, 0) (1, x) is prohibited = (1, x) (0, 0) is prohibited * When CR oscillation has been selected by the mask option as OSC1, VS1 becomes -2.1 V even when VSC1 = VSC0 = 0 and will never become -1.2 V. In addition, since the current consumption is great for CR oscillation compared with the quartz crystal oscillation, when low power consumption is required, you should select quartz crystal oscillation as OSC1. OSCC (F70H [D2], R/W) Controls the oscillation of the OSC3 oscillation circuit. When "1" is written: OSC3 oscillation ON When "0" is written: OSC3 oscillation OFF Reading: Valid When high-speed operation of the CPU is required, OSCC is set to "1"; otherwise, set it to "0" to minimize power current consumption. At initial reset, OSCC is set to "0". Note: It takes 5 ms for the OSC3 oscillation circuit to stabilize after oscillation turns ON. Since oscillation stabilization time differs according to external oscillation terminal and usage conditions, set the stand-by time with enough allowance when switching the clock frequency. S1C60N07 TECHNICAL MANUAL EPSON 23 CHAPTER 5: OSCILLATION CIRCUIT CLKCHG (F70H [D3], R/W) Selects the CPU operating clock. When "1" is written: OSC3 clock is selected When "0" is written: OSC1 clock is selected Reading: Valid When assigning OSC3 as the CPU operating clock, set CLKCHG to "1"; when assigning OSC1, set it to "0". At initial reset, CLKCHG is set to "0". Note: When switching the CPU operating clock from OSC1 to OSC3, follow the flow chart shown in Figure 5.6.1 and then proceed with software processing. Condition: VDD - VSS < -3.1 V VS1 = -1.2 V Condition: VS1 = -2.1 V, OSC3 = 1 MHz (stabilized) VS1 = -3.0 V, OSC3 = 2 MHz (stabilized) CLK CHG CLK CHG Set VS1 to -2.1 V OSC3 oscillation ON OSC3>500 kHz N 5 ms WAIT Y CLK OSC1OSC3 5 ms WAIT Set VS1 to -3.0 V OSC3 oscillation ON 5 ms WAIT CLK OSC1OSC3 Fig. 5.6.1 CPU operating clock control flow 24 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 5: OSCILLATION CIRCUIT 5.7 Programming Notes (1) When high-speed operation of the CPU is not required, observe the following reminders to minimize power current consumption. Set the CPU operating clock to OSC1. Turn the OSC3 oscillation OFF. Set the internal operating voltage (V S1) to -1.2 V or -2.1 V. (2) When the CPU is to be operated with OSC1, set the operating voltage to -1.2 V if the power voltage is less than 3.1 V (V DD-VSS < 3.1 V); set the operating voltage to -2.1 V if the voltage is 3.1 V or more (V DD-VSS 3.1 V). Moreover, because -1.2 V will be set during initial reset, be sure to execute the previous process at the beginning of the initial routine. Note, however, that it can be used fixed at 1.2 V (at OSC1 operation) for power whose initial value is 3.6 V or less as in lithium batteries. (3) When switching VS1 from -1.2 V (for OSC1 crystal oscillation circuit) to -3.0 V (for OSC3 oscillation circuit), or vice versa, be sure to hold the -2.1 V setting for more than 5 ms first for power voltage stabilization. (VSC1, VSC0) = (0, 0) (0, 1) 5 ms WAIT (1, x) = (1, x) (0, 1) 5 ms WAIT (0, 0) = (0, 0) (1, x) is prohibited = (1, x) (0, 0) is prohibited (4) When switching the CPU operating clock from OSC1 to OSC3, follow the flow chart shown in Figure 5.6.1 and then proceed with software processing. (5) Use separate instructions to switch the clock from OSC3 to OSC1 and turn the OSC3 oscillation OFF. Simultaneous processing with a single instruction may cause malfunction of the CPU. S1C60N07 TECHNICAL MANUAL EPSON 25 CHAPTER 6: INPUT/OUTPUT PORTS CHAPTER 6 INPUT/OUTPUT PORTS 6.1 Input Port (Kxx) 6.1.1 Configuration of input ports The S1C60N07 has 4 bits of general input ports (K00-K03) built-in. Figure 6.1.1.1 shows the configuration of the input port. VDD Interrupt request Data bus Mask option K Address VSS Fig. 6.1.1.1 Configuration of input port The input port pin K03 is used as the clock input pins for the programmable timer. See "8.3 Programmable Timer" for details. 6.1.2 Mask option The input ports (K00-K03) are provided with built-in pull up resistor the use of which may be selected for every bit with the mask option. Selection of "Pull up resistor enable" with the mask option suits input from the push switch, key matrix, and so forth. When changing the input port from low level to high level with a pull up resistor, a delay in the waveform rise time will occur depending on the time constant of the pull up resistor and input gate capacity. Hence, when reading data from the input port, set an appropriate waiting time. Care is particularly required for key matrix configuration scanning. For reference, approximately 500 s waiting time is required. When "Pull up resistor disabled" is selected, the port can be used for slide switch input and interfacing with other LSIs. In this case, take care that floating state does not occur. 6.1.3 Interrupt function All four bits of the input ports K00-K03 provide the interrupt function. Whether to mask the interrupt function can be selected individually for all four bits by the software. Figure 6.1.3.1 shows the configuration of the input (K00-K03) interrupt circuit. Data bus K Address Interrupt mask register (EIK) Address Noise rejector Interrupt factor flag (IK0) Mask option (K00-K03) Interrupt request Address Fig. 6.1.3.1 Configuration of input (K00-K03) interrupt circuit The interrupt mask registers (EIK00-EIK03) enable or mask the interrupt generation of the corresponding input port K00-K03. When an input signal which is not masked goes low, the interrupt factor flag (IK0) is set to "1" and an interrupt occurs at the falling edge of the input signal. 26 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 6: INPUT/OUTPUT PORTS 6.1.4 Control of input ports The control registers for the input ports are explained below. Table 6.1.4.1 Control registers of input ports Address Register D2 D1 D3 0 0 0 D0 IK0 F04H R EIK03 EIK02 EIK01 EIK00 F14H R/W K03 K01 K02 K00 F40H R Name 0 0 0 IK0 EIK03 EIK02 EIK01 EIK00 K03 K02 K01 K00 Init - - - 0 0 0 0 0 - - - - 1 0 Yes Enable Enable Enable Enable High High High High No Mask Mask Mask Mask Low Low Low Low Comment Interrupt factor flag (K00-K03) Interrupt mask register (K03) Interrupt mask register (K02) Interrupt mask register (K01) Interrupt mask register (K00) Input port (K00-K03) K00-K03 (F40H, R) Input data of the input port terminal may be read out with these registers. When "1" is read: High level When "0" is read: Low level Writing: Invalid The terminal voltage of 4 bits input ports (K00-K03) are each reading as "1" and "0" at high (V DD) level and low (V SS) level, respectively. When these bits are used for reading only, writing operation becomes invalid. EIK00-EIK03 (F14H, R/W) This is the interrupt mask register of the input ports. When "1" is written: Enable When "0" is written: Mask Reading: Valid EIK0x corresponds to input port K0x. Whether to mask the interrupt function can be set in units of 1 bit. Be sure that writing to the interrupt mask register is done with the interrupt in the DISABLE state (DI). Writing to the interrupt mask register while in the ENABLE state (EI) may cause malfunction. At initial reset, this register is set to "0" (mask). IK0 (F04H [D0], R) This is the interrupt factor flag of the input ports. When "1" is read: Interrupt has occurred When "0" is read: Interrupt has not occurred Writing: Invalid The interrupt factor flags IK0 is associated with K00-K03. From the status of this flag, the software can decide whether an input interrupt has occurred. The flag will not be set even if an input port status changes when the interrupt mask register (EIK0x) is set to "0". Be sure that the interrupt factor flag reading is done with the interrupt in the DISABLE state (DI). Reading the interrupt factor flag while in the ENABLE state (EI) may cause malfunction. At initial reset, this flag is set to "0". S1C60N07 TECHNICAL MANUAL EPSON 27 CHAPTER 6: INPUT/OUTPUT PORTS 6.1.5 Programming notes (1) When changing the input port from low level to high level with a pull up resistor, a delay in the waveform rise time will occur depending on the time constant of the pull up resistor and input gate capacity. Hence, when reading data from the input port, set an appropriate waiting time. Care is particularly required for key matrix configuration scanning. For reference, approximately 500 s waiting time is required. (2) Input interrupt programming related precautions Port K input Active status Mask register Factor flag set Not set When the content of the mask register is rewritten, while the port K input is in the active status, the input interrupt factor flag is set at . Fig. 6.1.5.1 Input interrupt timing When using an input interrupt, if you rewrite the content of the mask register, when the value of the input terminal which becomes the interrupt input is in the active status (input terminal = low status), the factor flag for input interrupt may be set. For example, a factor flag is set with the timing of shown in Figure 6.1.5.1. However, when clearing the content of the mask register with the input terminal kept in the low status and then setting it, the factor flag of the input interrupt is again set at the timing that has been set. Consequently, when the input terminal is in the active status (low status), do not rewrite the mask register (clearing, then setting the mask register), so that a factor flag will only set at the rising edge in this case. When clearing, then setting the mask register, set the mask register, when the input terminal is not in the active status (high status). (3) Be sure that writing to the interrupt mask register is done with the interrupt in the DISABLE state (DI). Writing to the interrupt mask register while in the ENABLE state (EI) may cause malfunction. (4) Be sure that the interrupt factor flag reading is done with the interrupt in the DISABLE state (DI). Reading the interrupt factor flag while in the ENABLE state (EI) may cause malfunction. 28 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 6: INPUT/OUTPUT PORTS 6.2 Output Port (Rxx) 6.2.1 Configuration of output ports The S1C60N07 has 6 bits (R32, R33, and R40-R43) of general output ports built-in. Figure 6.2.1.1 shows the configuration of the output port. Address VDD Data bus High impedance control register Mask option Data register R Address VSS Fig. 6.2.1.1 Configuration of output port 6.2.2 Mask option The output ports may be selected for the following by mask option. (1) Output specification of output ports The output specification of each output port may be selected (in 1-bit units). Two types of output specification may be selected: complementary output and N channel (Nch) open drain output. However, even if Nch open drain is selected, application on the terminal of voltage exceeding the power current voltage is not permitted. (2) Special output Output ports R33, R40, R42 and R43 may be selected, in addition to DC output, as special output port as follows: R33: R40: R42: R43: Programmable timer operating clock output (PTCLK) Clock inverted output (#FOUT) Buzzer inverted output (#BZ) or clock output (FOUT) Buzzer output (BZ) S1C60N07 TECHNICAL MANUAL EPSON 29 CHAPTER 6: INPUT/OUTPUT PORTS Buzzer outputs BZ (R43) and #BZ (R42) Through mask option selection, R43 and R42 may be assigned as buzzer outputs. BZ and #BZ are buzzer signal outputs for driving piezo-electric buzzers, the buzzer signal being created by the division of fOSC1. Moreover, digital envelope may be added to the buzzer signal. See Chapter 9, "Sound Generator" for details. Buzzer output BZ and #BZ can be controlled simultaneously by register R43. Note, however, that register R42 at #BZ output selection may be used as a 1-bit general register in which Read/Write operation is possible, and the data of said register will not affect #BZ (output from the R42 terminal). Notes: * The BZ and #BZ output signals could generate hazards during ON/OFF switching. * When output port R43 is set to DC output, output port R42 may not be set to #BZ output. Figure 6.2.2.1 shows the output waveform of BZ and #BZ. R43 register 1 0 1 BZ output (R43 terminal) #BZ output (R42 terminal) Fig. 6.2.2.1 Output waveform of BZ and #BZ PTCLK (R33) The operating clock for the programmable timer is output externally from this port. In this case, the clock output ON or OFF may be controlled from the R33 register by setting PTCOUT (F79H [D3]) to "1". The clock frequency is selected by the 3-bit register PTC0-PTC2. Moreover, when PTCOUT is set to "0", output port R33 becomes DC output. Because of the above functions, PTCLK output and DC output belong to a common option selection item. Refer to "8.3 Programmable Timer" regarding selection of clock frequency. Clock outputs FOUT (R42), #FOUT (R40) When R40 and R42 are selected to clock output, it outputs the clock of fOSC3, fOSC1 or the demultiplied fOSC1. R40 (#FOUT) output generates an antiphase clock in relation to R42 (FOUT). Figure 6.2.2.2 shows the output waveform of FOUT and #FOUT. The clock frequency is selectable with the mask options, from the frequencies listed in Table 6.2.2.1. R42/R40 register 1 0 1 FOUT output (R42 terminal) #FOUT output (R40 terminal) Fig. 6.2.2.2 Output waveform of FOUT and #FOUT Note: Clock output signal could generate hazards during ON/OFF switching. Table 6.2.2.1 FOUT clock frequency Setting Clock frequency (Hz) fOSC3 OSC3 oscillation frequency fOSC1/1 32,768 fOSC1/2 16,384 fOSC1/4 8,192 fOSC1/8 4,096 fOSC1/16 2,048 fOSC1/32 1,024 fOSC1/64 512 fOSC1/128 256 30 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 6: INPUT/OUTPUT PORTS 6.2.3 High impedance control The terminal output state of output ports R32 and R33 may be selected for high impedance state using the high impedance control register HZR3. 6.2.4 Control of output ports The control registers for the output ports are explained below. Table 6.2.4.1 Control registers of output ports Address D3 Register D2 D1 R33 R32 F53H 0 0 R/W R43 D0 Name R33 Init X R32 0 0 R43 X - - 1 R42 1 R41 R40 1 1 HZR3 0 0 0 0 - - - R R42 R41 R40 R/W F54H HZR3 0 0 0 F7BH R/W R 1 High Off High 0 Low On Low High Off High Off Low On Low On High High Off Output Low Low On High-Z Comment Output port (R33) PTCLK output Output port (R32) Output port (R43) Buzzer output (BZ) Output port (R42) Clock output (FOUT) [Buzzer inverted output (#BZ)] Output port (R41) Output port (R40) Clock inverted output (#FOUT) R32-R33 output high-impedance control HZR3 (F7BH [D3], R/W) Controls high impedance loading to output ports R32 and R33. When "1" is written: Data output When "0" is written: High impedance Reading: Valid By writing "1" in the control register HZR3, the output register data (R32 and R33) is generated in the terminal; writing "0" will generate high impedance state. During initial reset, this register is set to "0" and the ports acquire high impedance state. When DC output is selected R32, R33, R40-R43 (F53H [D2] and [D3], F54H, R/W) Sets the output data for the output ports. When "1" is written: High level When "0" is written: Low level Reading: Valid Output port terminals will generate the data written into the corresponding registers (R32, R33, R40-R43) as it is. The output port terminal goes high (V DD) when "1" is written to the register, and goes low (V SS) when "0" is written. At initial reset, only R40-R43 are set to "1" and the other output registers become undefined. S1C60N07 TECHNICAL MANUAL EPSON 31 CHAPTER 6: INPUT/OUTPUT PORTS When special output is selected R43 (F54H [D3], R/W) when BZ and #BZ output is selected Performs the output control of buzzer signal (BZ, #BZ). When "0" is written: Buzzer signal output When "1" is written: Low level (DC) Reading: Valid When "0" is set on R43, BZ signal is generated from R43 terminal; at the same time, #BZ signal (BZ inverted signal) is generated from R42 terminal if R42 is set to #BZ output. When "1" is set on R43, R43 terminal (and R42 terminal too, when #BZ output is selected) output goes low (V SS). Note, however, that R42 at #BZ output selection may be used as a 1-bit general register in which Read/Write operation is possible, and the data of said register will not affect #BZ (R42 terminal output). At initial reset, R43 and R42 are set to "1". R33 (F53H [D3], R/W) when PTCLK (DC) output is selected Controls the output of the programmable timer operating clock (PTCLK). When "0" is written: Clock output When "1" is written: High level (DC) Reading: Valid With "1" written on PTCOUT (F79H [D3]), the operating clock of the programmable timer may be generated externally by writing "0" on R33 register. Moreover, the output will go high (V DD) by writing "1". However, when PTCOUT is "0", the output becomes regular DC output. R40, R42 (F54H [D0, D2], R/W) when FOUT and #FOUT output is selected Controls the #FOUT and FOUT (clock) output. When "0" is written: Clock output When "1" is written: High level (DC) Reading: Valid When R42 is set to FOUT output, clock with the specified frequency is generated from R42 terminal by writing "0" on R42 register. By writing "1", the R42 terminal will go high (V DD). The same applies to R40. The clock phase when #FOUT signal is output from R40 is antiphase to that of R42. At initial reset, R40 and R42 are set to "1". 6.2.5 Programming notes (1) When BZ, #BZ, FOUT, #FOUT, and PTCLK (DC) are selected by mask option, a hazard may be observed in the output waveform when the data of the output register changes. (2) Because the R32 and R33 ports gain high impedance during initial reset, be careful when using them as interface with external devices and the like. 32 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 6: INPUT/OUTPUT PORTS 6.3 I/O Port (Pxx) 6.3.1 Configuration of I/O ports The S1C60N07 has 4 bits of general I/O ports (P00-P03) built-in. Figure 6.3.1.1 shows the configuration of the I/O port. VDD Data bus Address Pull up control register Address Address Address Data register P I/O control register Fig. 6.3.1.1 Configuration of I/O port 6.3.2 Mask option Output specification (during output) for the I/O port may be selected by mask option (selected with the 4 bits group). Two types of output specification may be selected: complementary output and N channel (Nch) open drain output. However, even if Nch open drain is selected, application on the terminal of voltage exceeding the power current voltage is not permitted. 6.3.3 I/O control register and input/output mode Input or output mode can be set for the four bits of I/O port P00-P03 by writing data to the I/O control register IOC0. To set the input mode, "0" is written to the I/O control register. When an I/O port is set to input mode, it becomes high impedance state and works as an input port. The output mode is set when "1" is written to the I/O control register. When an I/O port set to output mode works as an output port, it outputs a high level (V DD) when the data of output register is "1", and a low level (V SS) when the data of output register is "0". 6.3.4 Pull up resistor Pull up resistors can be added to four bits of I/O ports by writing data to the pull up control register PUP0. When "0" is written to the pull up control register, the I/O port terminals are pulled up. When "1" is written, the pull up resistors are disconnected. S1C60N07 TECHNICAL MANUAL EPSON 33 CHAPTER 6: INPUT/OUTPUT PORTS 6.3.5 Control of I/O ports The control registers for the I/O ports are explained below. Table 6.3.5.1 Control register of I/O ports Address D3 Register D2 D1 D0 P03 P02 P00 P01 F60H R/W 0 0 0 IOC0 F7DH R 0 0 R/W 0 PUP0 F7EH R R/W Name P03 P02 P01 P00 0 0 0 IOC0 0 0 0 PUP0 Init X X X X - - - 0 - - - 0 1 High High High High 0 Low Low Low Low Output Input Off On Comment I/O port (P00-P03) I/O control (P00-P03) I/O pull up resistor On/Off (P00-P03) IOC0 (F7DH [D0], R/W) Input/output direction of I/O ports are set in units of 4 bits. When "1" is written: Output mode When "0" is written: Input mode Reading: Valid By writing "1" to IOC0, the I/O ports enter the output mode, while writing "0" they enter the input mode. At initial reset, IOC0 is set to "0" and the I/O ports are all in the input mode. PUP0 (F7EH [D0], R/W) Whether the I/O ports will be pulled up or not is set in units of 4 bits. When "0" is written: Pull up ON When "1" is written: Pull up OFF Reading: Valid By writing "0" to PUP0, the I/O ports are pulled up, while writing "1" turns the pull up function OFF. At initial reset, PUP0 is set at "0", and all I/O ports are pulled up. P00-P03 (F60H, R/W) * During writing operation When "1" is written: High level When "0" is written: Low level When the I/O port is set at output port, the data written is generated on the I/O port terminal as it is. When "1" is written as port data, the port terminal goes high (V DD) and goes low (V SS) when "0" is written. Note, however, that even at input mode, port data writing is also possible. * During reading operation When "1" is read: High level When "0" is read: Low level Reading the I/O port terminal voltage level. When the I/O port is at input mode, voltage level input of the port terminal is read; when set at output mode, output voltage level is read. When the terminal voltage is at high (V DD) level, port data reading is "1"; at low (V SS) level, it is "0". 34 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 6: INPUT/OUTPUT PORTS 6.3.6 Programming notes (1) When the I/O port is set at output mode, and low impedance load is connected to the port terminal, the data written and read may differ. (2) If the state of the I/O port meets all of the following 4 conditions, the reading data will be undefined: * The input/output mode is set at output mode * Output specification is set at Nch open drain * The content of the data register is "1" * The pull up resistor turned is OFF S1C60N07 TECHNICAL MANUAL EPSON 35 CHAPTER 7: LCD DRIVER CHAPTER 7 LCD DRIVER The S1C60N07 has 16 common terminals and 40 segment terminals and can drive a maximum of 640 (40 x 16) dots (8 characters x 2 lines) LCD. This LCD driver performs the following control through the software. * Drive duty can be set to 1/16 or 1/8 duty. * LCD contrast can be adjusted through a 16 steps range. * All dots of the LCD panel can be switched ON and OFF. 7.1 Drive Duty Because the power for LCD driving is generated by the internal circuit of the CPU, there is no need to provide for it externally. Driving is done by 1/16 duty or 1/8 duty dynamic drive through 4 electric potentials (1/4 bias) : VL1, VL2, VL4, and VL5. The 5 electric potentials are entered in VL1, VL2, VL3, VL4 and VL5 terminals and 1/5 bias driving may then be set. Drive duty may be selected from the software. Dot number differences due to the selected duty are shown in Table 7.1.1. Table 7.1.1 Differences due to selected duty Duty Common terminal in use Maximum dot number Frame frequency 1/16 COM0-15 640 dots 32 Hz 1/8 COM0-7 320 dots 32 Hz Frame frequency = fOSC1/1,024 Figure 7.1.1 shows the drive waveform for 1/16 duty (1/5 bias), and Figure 7.1.2 shows the drive waveform for 1/8 duty (1/4 bias). 36 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 7: LCD DRIVER 0 1 2 3 15 0 1 2 3 15 VDD VSS FR VDD VL1 VL2 COM0 VL3 VL4 COM0 1 VL5 2 VDD 3 VL1 VL2 4 VL3 5 VL4 COM1 VL5 6 VDD 7 VL1 VL2 VL3 VL4 COM2 8 VL5 9 VDD VL1 10 VL2 11 VL3 SEG0 VL4 12 VL5 13 VDD VL1 14 VL2 15 VL3 SEG1 4 3 2 1 SEG0 VL4 VL5 -VL5 -VL4 -VL3 -VL2 SEG0~COM0 -VL1 VDD (GND) VL1 VL2 VL3 VL4 VL5 -VL5 -VL4 -VL3 -VL2 SEG1~COM0 -VL1 VDD (GND) VL1 VL2 VL3 VL4 VL5 Fig. 7.1.1 Drive waveform for 1/16 duty (1/5 bias) Note: 1/5 bias may only be utilized when power for LCD driving is supplied externally; when internal power circuit is used, 1/4 bias is utilized. S1C60N07 TECHNICAL MANUAL EPSON 37 CHAPTER 7: LCD DRIVER 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 V DD V SS FR V DD V L1 V L2 (V L3) COM0 V L4 V L5 COM0 V DD 1 2 V L1 V L2 (V L3) COM1 V L4 3 V L5 4 V DD 5 V L1 V L2 (V L3) COM2 6 V L4 V L5 4 3 2 1 SEG0 7 V DD V L1 V L2 (V L3) SEG0 V L4 V L5 V DD V L1 V L2 (V L3) SEG1 V L4 V L5 -V L5 -V L4 -V L2 (-VL3) -V L1 SEG0~COM0 V DD (GND) V L1 V L2 (V L3) V L4 V L5 -V L5 -V L4 -V L2 (-VL3) -V L1 SEG1~COM0 V DD (GND) V L1 V L2 (V L3) V L4 V L5 Fig. 7.1.2 Drive waveform for 1/8 duty (1/4 bias) 38 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 7: LCD DRIVER 7.2 Mask Option Disconnecting the internal power for LCD driving will enable electric potentials to be supplied externally. In such case, the 5 electric potentials are entered in VL1, VL2, VL3, VL4 and VL5 terminals and 1/5 bias driving may then be set. Since 1/5 bias driving provides better display quality, when low power current consumption is not required (i.e., when power is supplied from AC outlet), select external power mode. However, note that in order to maintain a stable display, power source must be one which will remain stable even when heavy load such as buzzer, etc. is driven. Moreover, in the external power mode, the contrast adjustment function cannot be used. Accommodate this limitation by utilizing the external circuit as necessary. A sample circuit of external power for LCD driving when power is supplied externally is shown in Figure 7.2.1. V DD VDD V L1 V L2 V L3 S1C60N07 V L4 Power save circuit V L5 V SS VSS Rxx Fig. 7.2.1 Sample circuit of external power for LCD driving when power is supplied externally 7.3 Display Data Memory The display data memory of the S1C60N07 is allocated to the built-in RAM addresses E00H-E4FH and E80H-ECFH. Figure 7.3.1 shows the correspondence between the display data memory and the LCD dot matrix. COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 SEG0 SEG1 SEG2 SEG3 SEG39 D0 D0 D0 D0 D0 D1 D1 D1 D1 D1 E00H E02H E04H E06H * * * E4EH D2 D2 D2 D2 D2 D3 D3 D3 D3 D3 D0 D0 D0 D0 D0 D1 D1 D1 D1 D1 E01H E03H E05H E07H * * * E4FH D2 D2 D2 D2 D2 D3 D3 D3 D3 D3 D0 D0 D0 D0 D1 D1 D1 D1 E80H E82H E84H E86H * * * D2 D2 D2 D2 D3 D3 D3 D3 D0 D0 D0 D0 D1 D1 D1 D1 E81H E83H E85H E87H * * * D2 D2 D2 D2 D3 D3 D3 D3 D0 D1 ECEH D2 D3 D0 D1 ECFH D2 D3 Memory address Data bit Fig. 7.3.1 LCD dot matrix and segment memory correspondence When the segment memory bit is assigned as "1", the corresponding LCD dot lights up, and when assigned as "0", the dot dies out. At 1/16 duty drive and 1/8 duty drive, COM0 to COM15 lines and COM0 to COM7 lines light up, respectively. At initial reset, the display data memory content becomes undefined and hence, there is need to initialize by software. S1C60N07 TECHNICAL MANUAL EPSON 39 CHAPTER 7: LCD DRIVER 7.4 Control of LCD Driver The control registers for the LCD driver are explained below. Table 7.4.1 Control registers of LCD driver Address D3 ALOFF Register D2 D1 ALON LDUTY F71H R/W LC3 LC2 LC1 F72H R/W 0 0 0 F7FH R D0 Name ALOFF HLMOD ALON LDUTY HLMOD LC3 LC0 LC2 LC1 LC0 0 *4 LCDOFF 0 *4 0 *4 R/W LCDOFF Init 1 All off 1 All on 0 1/8 0 HLMOD 0 X X X X - *2 - *2 - *2 Normal 1 0 Normal Normal 1/16 Normal Comment All LCD dots fade out control All LCD dots displayed control LCD drive duty switch Heavy load protection mode LCD contrast adjustment LC3-LC0 = 0 light : LC3-LC0 = 15 dark Off LCD display control LDUTY (F71H [D1], R/W) Sets the LCD drive duty. When "1" is written: 1/8 duty When "0" is written: 1/16 duty Reading: Valid Writing "1" or "0" on LDUTY will set is to 1/8 duty or 1/16 duty, respectively. At initial reset, LDUTY is set at "0". ALON (F71H [D2], R/W) Displays the all LCD dots on. When "1" is written: All LCD dots displayed When "0" is written: Normal operation Reading: Valid Writing "1" to ALON will display all the LCD dots on; writing "0" will set the LCD display back to normal. LCD panel testing may be conducted with this function. Total LCD displaying at ALON = "1" is a static operation and does not affect the content of the display data memory. ALON precedes ALOFF. At initial reset, ALON is set at "0". ALOFF (F71H [D3], R/W) Fade outs the all LCD dots. When "1" is written: All LCD dots fade out When "0" is written: Normal operation Reading: Valid When "1" is written on ALOFF, all LCD dots will fade out; writing "0" will set it back to normal. All fading out of LCD at ALOFF = "1" is due to light out signals and does not affect the content of the display data memory. Flashing of the entire LCD panel is performed by this function. At initial reset, ALOFF is set to "1". 40 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 7: LCD DRIVER LC0, LC1, LC2, LC3 (F72H, R/W) Will adjust the LCD contrast. Contrast may be adjusted to 16 levels as shown in Table 7.4.2. 0 1 2 3 4 5 6 7 8 9 A B C D E F LC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Table 7.4.2 LCD contrast LC2 LC1 LC0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Contrast light dark At room temperature, use setting number 7 or 8 as standard. The voltage of the LCD system power terminals VL1, VL2, VL4 and VL5 changes through this function. Because at initial reset, the contents of LC0-LC3 are undefined, initialize it by the software. LCDOFF (F7FH [D0], R/W) Control the LCD system voltage circuit ON and OFF. When "1" is written: Normal operation When "0" is written: Display OFF Reading: Valid When "1" is written to LCDOFF, the LCD system voltage circuit turns ON and generate the LCD drive volatges. When "0" is written, all the drive voltages go to VSS level and the display turns OFF. At initial reset, this register is set to "1". 7.5 Programming Note Because at initial reset, the contents of display data memory and LC0-LC3 are undefined, there is need to initialize by software. S1C60N07 TECHNICAL MANUAL EPSON 41 CHAPTER 8: TIMERS CHAPTER 8 TIMERS 8.1 Clock Timer 8.1.1 Configuration of clock timer The S1C60N07 has a clock timer with OSC1 (crystal oscillation) as basic oscillation built-in. The clock timer is configured with an 8 bits binary counter with 256 Hz signal divided from OSC1 as input clock, allowing 128 Hz-1 Hz of data to be read by the software. Figure 8.1.1.1 shows the configuration of the clock timer. Data bus 256 Hz OSC1 oscillation circuit Divider 128 Hz-16 Hz 8 Hz-1 Hz 32 Hz, 8 Hz, 2 Hz, 1 Hz Clock timer reset signal Interrupt control Interrupt request Fig. 8.1.1.1 Configuration of clock timer 8.1.2 Interrupt function The clock timer has interrupt capability, and interrupt is generated by the falling edge of 32 Hz, 8 Hz, 2 Hz, and 1 Hz signals. Figure 8.1.2.1 shows the timing chart of the clock timer. Address Register Frequency D0 128 Hz D1 64 Hz D2 32 Hz D3 16 Hz D0 8 Hz D1 4 Hz D2 2 Hz D3 1 Hz Clock timer timing chart F20H F21H 32 Hz interrupt request 8 Hz interrupt request 2 Hz interrupt request 1 Hz interrupt request Fig. 8.1.2.1 Timing chart of clock timer The clock timer interrupt is generated at the falling edge of the frequencies (32 Hz, 8 Hz, 2 Hz, and 1 Hz). At this time, the corresponding interrupt factor flag (IT32, IT8, IT2, and IT1) is set to "1". Selection of whether to mask the separate interrupts can be made with the interrupt mask registers (EIT32, EIT8, EIT2, and EIT1). However, regardless of the interrupt mask register setting, the interrupt factor flag is set to "1" at the falling edge of the corresponding signal. 42 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 8: TIMERS 8.1.3 Control of clock timer The control registers for the clock timer are explained below. Table 8.1.3.1 Control registers of clock timer Address Register D2 D1 D3 IT1 D0 IT8 IT32 EIT8 EIT32 TM1 TM0 TM5 TM4 TMRST WDRST IT2 F00H R EIT1 EIT2 F10H R/W TM3 TM2 F20H R TM7 TM6 F21H R 0 0 F76H R W Name IT1 IT2 IT8 IT32 EIT1 EIT2 EIT8 EIT32 TM3 TM2 TM1 TM0 TM7 TM6 TM5 TM4 0 0 TMRST WDRST Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - - Reset Reset 1 Yes Yes Yes Yes Enable Enable Enable Enable 0 No No No No Mask Mask Mask Mask Reset Reset - - Comment Interrupt factor flag (clock timer 1 Hz) Interrupt factor flag (clock timer 2 Hz) Interrupt factor flag (clock timer 8 Hz) Interrupt factor flag (clock timer 32 Hz) Interrupt mask register (clock timer 1 Hz) Interrupt mask register (clock timer 2 Hz) Interrupt mask register (clock timer 8 Hz) Interrupt mask register (clock timer 32 Hz) Clock timer data (16 Hz) Clock timer data (32 Hz) Clock timer data (64 Hz) Clock timer data (128 Hz) Clock timer data (1 Hz) Clock timer data (2 Hz) Clock timer data (4 Hz) Clock timer data (8 Hz) Clock timer reset Watchdog timer reset TMRST (F76H [D1], W) This bit resets the clock timer. When "1" is written: Clock timer reset When "0" is written: No operation Reading: Always "0" By writing "1" on TMRST, the clock timer is reset and all timer data are set to "0". Because this bit is only for writing, it is always "0" during reading. TM0-TM7 (F20H, F21H, R) Will read the data of the clock timer. TMx (x = 0-7) and frequency correspondence are as follows: F20H TM0: 128 Hz TM1: 64 Hz TM2: 32 Hz TM3: 16 Hz F21H TM4: 8 TM5: 4 TM6: 2 TM7: 1 Hz Hz Hz Hz The above 8 bits are only for reading and render writing operation invalid. At initial reset, timer data is initialized to "0". EIT32, EIT8, EIT2, EIT1 (F10H, R/W) These are the interrupt mask registers of the clock timer. When "1" is written: Enabled When "0" is written: Masked Reading: Valid EIT32, EIT8, EIT2, and EIT1 correspond to 32 Hz, 8 Hz, 2 Hz, and 1 Hz timer interrupts, respectively. Be sure that writing to the interrupt mask register is done with the interrupt in the DISABLE state (DI). Writing to the interrupt mask register while in the ENABLE state (EI) may cause malfunction. At initial reset, these registers are all set to "0" (mask). S1C60N07 TECHNICAL MANUAL EPSON 43 CHAPTER 8: TIMERS IT32, IT8, IT2, IT1 (F00H, R) These are the interrupt factor flags of the clock timer. When "1" is read: Interrupt has occurred When "0" is read: Interrupt has not occurred Writing: Invalid IT32, IT8, IT2, and IT1 correspond to 32 Hz, 8 Hz, 2 Hz, and 1 Hz timer interrupts, respectively. The occurrence of clock timer interrupt can be determined by the software through these flags. However, regardless of interrupt masking, these flags are set to "1" due to the falling edge of the corresponding signal. Be sure that the interrupt factor flag reading is done with the interrupt in the DISABLE state (DI). Reading the interrupt factor flag while in the ENABLE state (EI) may cause malfunction. At initial reset, these flags are set to "0". 8.1.4 Programming notes (1) When the clock timer has been reset, the interrupt factor flag (IT) may sometimes be set to "1". Consequently, perform flag read (reset the flag) as necessary at reset. (2) Because the watchdog timer counts up during reset as in the above (1), reset the watchdog timer as necessary. (3) When the low-order digits (TM0-TM3) and high-order digits (TM4-TM7) are consecutively read, proper reading may not be obtained due to the carry from the low-order digits into the high-order digits (when the reading of the low-order digits and high-order digits span the timing of the carry). For this reason, perform multiple reading of timer data, make comparisons and use matching data as result. (4) Be sure that writing to the interrupt mask register is done with the interrupt in the DISABLE state (DI). Writing to the interrupt mask register while in the ENABLE state (EI) may cause malfunction. (5) Be sure that the interrupt factor flag reading is done with the interrupt in the DISABLE state (DI). Reading the interrupt factor flag while in the ENABLE state (EI) may cause malfunction. 44 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 8: TIMERS 8.2 Stopwatch Timer 8.2.1 Configuration of stopwatch timer The S1C60N07 has 1/100 sec unit (SWL) and 1/10 sec unit (SWH) stopwatch timer built-in. The stopwatch timer is configured with a 2 levels 4 bits BCD counter which has an input clock approximating 100 Hz signal (signal divided from OSC1 to the closest 100 Hz) and data can be read in units of 4 bits by software. Figure 8.2.1.1 shows the configuration of the stopwatch timer. Data bus 256 Hz OSC1 oscillation circuit Divider SWL counter 10 Hz SWH counter 10 Hz, 1 Hz Stopwatch timer reset signal Stopwatch timer RUN/STOP signal Interrupt control Interrupt request Fig. 8.2.1.1 Configuration of stopwatch timer The stopwatch timer can be used as a separate timer from the clock timer. In particular, digital watch stopwatch functions can be realized easily with software. 8.2.2 Count-up pattern The stopwatch timer is configured of 4 bits BCD counters SWL and SWH. The counter SWL, at the stage preceding the stopwatch timer, has an approximated 100 Hz signal for the input clock. It counts up every 1/100 sec, and generates an approximated 10 Hz signal. The counter SWH has an approximated 10 Hz signal generated by the counter SWL for the input clock. In count-up every 1/10 sec, and generated 1 Hz signal. Figure 8.2.2.1 shows the count-up pattern of the stopwatch timer. SWH count-up pattern SWH count value 0 Count time (sec) 1 26 256 SWL count-up pattern 1 SWL count value Count time (sec) SWL count-up pattern 2 SWL count value Count time (sec) 2 3 4 5 6 7 8 9 0 26 25 25 26 26 25 25 26 26 256 256 256 256 256 256 256 256 256 26 x 6 + 25 x 4 = 1 (sec) 256 256 0 1 3 256 0 2 3 4 5 6 7 8 9 0 2 3 2 3 2 3 2 3 2 256 256 256 256 256 256 256 256 256 25 256 (sec) 1 2 3 4 5 6 7 8 9 0 3 3 3 2 3 2 3 2 3 2 256 256 256 256 256 256 256 256 256 256 26 (sec) 256 1 Hz signal generation Approximate 10 Hz signal generation Approximate 10 Hz signal generation Fig. 8.2.2.1 Count-up pattern of stopwatch timer SWL generates an approximated 10 Hz signal from the basic 256 Hz signal. The count-up intervals are 2/256 sec and 3/256 sec, so that finally two patterns are generated: 25/256 sec and 26/256 sec intervals. Consequently, these patterns do not amount to an accurate 1/100 sec. SWH counts the approximated 10 Hz signals generated by the 25/256 sec and 26/256 sec intervals in the ratio of 4 : 6, to generate a 1 Hz signal. The count-up intervals are 25/256 sec and 26/256 sec, which do not amount to an accurate 1/10 sec. S1C60N07 TECHNICAL MANUAL EPSON 45 CHAPTER 8: TIMERS 8.2.3 Interrupt function Stopwatch timers SWL and SWH, through their respective overflows, can generate 10 Hz (approximate 10 Hz) and 1 Hz interrupts. Figure 8.2.3.1 shows the timing chart for the stopwatch timer. Address Register F22H D0 1/100sec (BCD) D1 Stopwatch timer (SWL) timing chart D2 D3 10 Hz interrupt request Address Register F23H D0 1/10sec (BCD) D1 Stopwatch timer (SWH) timing chart D2 D3 1 Hz interrupt request Fig. 8.2.3.1 Timing chart for stopwatch timer The stopwatch interrupts are generated by the overflow of their respective counters SWL and SWH (changing "9" to "0"). At this time, the corresponding interrupt factor flags (ISW0 and ISW1) are set to "1". The respective interrupts can be masked separately through the interrupt mask registers (EISW0 and EISW1). However, regardless of the setting of the interrupt mask registers, the interrupt factor flags are set to "1" by the overflow of their corresponding counters. 46 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 8: TIMERS 8.2.4 Control of stopwatch timer The control registers for the stopwatch timer are explained below. Table 8.2.4.1 Control registers of stopwatch timer Address Register D2 D1 D3 0 0 D0 ISW1 ISW0 F01H R 0 0 EISW1 EISW0 F11H R SWL3 R/W SWL2 SWL1 SWL0 F22H R SWH3 SWH2 SWH1 SWH0 F23H R 0 0 SWRST SWRUN F77H R W R/W Name 0 0 ISW1 ISW0 0 0 EISW1 EISW0 SWL3 SWL2 SWL1 SWL0 SWH3 SWH2 SWH1 SWH0 0 0 SWRST SWRUN Init - - 0 0 - - 0 0 0 0 0 0 0 0 0 0 - - Reset 0 1 No No Enable Enable Comment 0 Mask Mask Interrupt factor flag (stopwatch 1 Hz) Interrupt factor flag (stopwatch 10 Hz) Interrupt mask register (stopwatch 1 Hz) Interrupt mask register (stopwatch 10 Hz) MSB Stopwatch timer 1/100 sec data (BCD) LSB MSB Stopwatch timer 1/10 sec data (BCD) LSB Reset Run - Stop Stopwatch timer reset Stopwatch timer Run/Stop SWRST (F77H [D1], W) This bit resets the stopwatch timer. When "1" is written: Stopwatch timer reset When "0" is written: No operation Reading: Always "0" By writing "1" on SWRST, the stopwatch timer is reset. All timer data is set to "0". When the stopwatch timer is reset in the RUN mode, it will re-start counting immediately after the reset and at STOP mode, the reset data is maintained. Because this bit is for writing only, it is always "0" during reading. SWRUN (F77H [D0], R/W) This register controls RUN/STOP of the stopwatch timer. When "1" is written: RUN When "0" is written: STOP Reading: Valid By writing "1" on SWRUN, the stopwatch timer performs counting operation. Writing "0" will make the stopwatch stop counting. Even if the stopwatch is stopped, the timer data at that point is kept. When data of the counter is read at run mode, proper reading may not be obtained due to the carry from low-order digits (SWL) into high-order digits (SWH) (i.e., in case SWL and SWH reading span the timing of the carry). To avoid this occurrence, perform the reading after suspending the counter once and then set the SWRUN to "1" again. Moreover, it is required that the suspension period not exceed 976 s (1/4 cycle of 256 Hz). At initial reset, SWRUN is set to "0". SWL0-SWL3 (F22H, R) Will read the stopwatch timer data to the 1/100 sec digits (BCD). Since these bits are for reading only, writing operation is invalidated. At initial reset, timer data is set to "0". S1C60N07 TECHNICAL MANUAL EPSON 47 CHAPTER 8: TIMERS SWH0-SWH3 (F23H, R) Will read the stopwatch timer data to the 1/10 sec digits (BCD). Since these bits are for reading only, writing operation is invalidated. At initial reset, timer data is set to "0". EISW0, EISW1 (F11H [D0, D1], R/W) These are the interrupt mask registers of the stopwatch timer. When "1" is written: Enabled When "0" is written: Masked Reading: Valid EISW0 and EISW1 correspond to 10 Hz and 1 Hz stopwatch timer interrupts, respectively. Be sure that writing to the interrupt mask register is done with the interrupt in the DISABLE state (DI). Writing to the interrupt mask register while in the ENABLE state (EI) may cause malfunction. At initial reset, these registers are all set to "0" (mask). ISW0, ISW1 (F01H [D0, D1], R) These are the interrupt factor flags of the stopwatch timer. When "1" is read: Interrupt has occurred When "0" is read: Interrupt has not occurred Writing: Invalid ISW0 and ISW1 correspond to 10 Hz and 1 Hz stopwatch timer interrupts, respectively. The occurrence of stopwatch timer interrupt can be determined by the software through these flags. However, regardless of interrupt masking, these flags are set to "1" by the overflow of the corresponding counters. Be sure that the interrupt factor flag reading is done with the interrupt in the DISABLE state (DI). Reading the interrupt factor flag while in the ENABLE state (EI) may cause malfunction. At initial reset, these flags are set to "0". 8.2.5 Programming notes (1) When data of the counter is read at run mode, perform the reading after suspending the counter once and then set SWRUN to "1" again. Moreover, it is required that the suspension period not exceed 976 s (1/4 cycle of 256 Hz). (2) Be sure that writing to the interrupt mask register is done with the interrupt in the DISABLE state (DI). Writing to the interrupt mask register while in the ENABLE state (EI) may cause malfunction. (3) Be sure that the interrupt factor flag reading is done with the interrupt in the DISABLE state (DI). Reading the interrupt factor flag while in the ENABLE state (EI) may cause malfunction. 48 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 8: TIMERS 8.3 Programmable Timer 8.3.1 Configuration of programmable timer The S1C60N07 has a programmable timer with OSC1 (crystal oscillation) as basic oscillation built-in. The programmable timer is configured with an 8 bits pre-settable down counter and it has been downcount at initial value by 256 Hz-8,192 Hz signal or by the input signal of input port K03. The initial value of count data can be set by software to the reload register; at the point where the downcounter value is "0", the programmable timer reloads the initial value and continues to down-count. The down-counter data may be read through the software. Moreover, the input clock being selected may be generated to output port R33. Figure 8.3.1.1 shows the configuration of the programmable timer. R33 256 Hz-8,192 Hz Reload register Divider Data bus OSC1 oscillation circuit Selector K03 Noise reject circuit 8-bit down counter Programmable timer reset signal Interrupt control Programmable timer RUN/STOP signal Fig. 8.3.1.1 Configuration of programmable timer Interrupt request One input clock may be selected by software from any of the following 8 types: (1) K03 input (with noise rejector) (2) K03 input (direct) (3) 256 Hz (4) 512 Hz (5) 1,024 Hz (6) 2,048 Hz (7) 4,096 Hz (8) 8,192 Hz Note, however, that down-count is done at falling edges of the input signal as shown in Figure 8.3.1.2. Input clock Down count Down count Fig. 8.3.1.2 Timing of down-counts Type (1) K03 input (with noise rejector) is for counting by key entry, the input signal from which passes the 256 Hz sampling noise reject circuit. With this, no more than 2 ms of chattering is purged, and at least 4 ms signal is received. S1C60N07 TECHNICAL MANUAL EPSON 49 CHAPTER 8: TIMERS 8.3.2 Interrupt function The programmable timer generates interrupt after the down-count from the initial setting is completed and the content of the down-counter indicates 00H. After interrupt generation, the programmable timer reloads the initial count value into the down-counter and resumes counting. Figure 8.3.2.1 shows the timing chart of the programmable timer. PTRST PTRUN Input clock D3 Timer data D2 high-order D1 address (F25H) D0 Timer data low-order address (F24H) D3 D2 D1 D0 Note: When "A6H" is set into reload register Interrupt request Fig. 8.3.2.1 Timing chart of programmable timer When the down-counter values PT0-PT7 have become 00H the interrupt factor flag IPT is set to "1" and an interrupt is generated. The interrupt can be masked through the interrupt mask register EIPT. However, regardless of the setting of the interrupt mask register, the interrupt factor flag is set to "1" when the down-counter equals 00H. 50 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 8: TIMERS 8.3.3 Control of programmable timer The control registers for the programmable timer are explained below. Table 8.3.3.1 Control registers of programmable timer Address Register D2 D1 D3 0 0 0 F02H R 0 0 0 F12H R PT3 PT2 PT1 F24H R PT7 PT6 PT5 F25H R RD3 RD2 RD1 F26H R/W RD7 RD6 RD5 F27H R/W 0 0 PTRST F78H W R PTCOUT PTC2 PTC1 F79H R/W D0 Name 0 IPT 0 0 IPT 0 EIPT 0 0 R/W EIPT PT3 PT0 PT2 PT1 PT0 PT7 PT4 PT6 PT5 PT4 RD3 RD0 RD2 RD1 RD0 RD7 RD4 RD6 RD5 RD4 0 PTRUN 0 PTRST R/W PTRUN PTCOUT PTC0 PTC2 PTC1 PTC0 Init - - - 0 - - - 0 X X X X X X X X X X X X X X X X - - Reset 0 0 0 0 0 1 0 Yes No Enable Mask Comment Interrupt factor flag (programmable timer) Interrupt mask register (programmble timer) MSB Programmable timer data (low-order) LSB MSB Programmable timer data (high-order) LSB MSB Programmable timer reload data (low-order) LSB MSB Programmable timer reload data (high-order) LSB Reset Run On - Stop Off Programmable timer reset Programmable timer Run/Stop Programmable timer clock output Programmable timer input clock selection PTC0, PTC1, PTC2 (F79H [D0-D2], R/W) Selects the input clock. The PTC0-PTC2 setting and input clock correspondence is shown in Table 8.3.3.2. PTC2 0 0 0 0 1 1 1 1 Table 8.3.3.2 Input clock setting PTC1 PTC0 Input clock 0 0 K03 input (with noise rejector) 0 1 K03 input (direct) 1 0 256 Hz 1 1 512 Hz 0 0 1,024 Hz 0 1 2,048 Hz 1 0 4,096 Hz 1 1 8,192 Hz PTCOUT (F79H [D3], R/W) Generates the input clock being selected to output port R33. Refer to Section 6.2, "Output Port" regarding control methods. S1C60N07 TECHNICAL MANUAL EPSON 51 CHAPTER 8: TIMERS RD0-RD3, RD4-RD7 (F26H, F27H, R/W) These are reload registers for setting the initial value of the timer. Sets the low-order 4 bits of the 8 bits timer data to RD0-RD3, and the high-order 4 bits to RD4-RD7. The set timer data is loaded to the down-counter when the programmable timer is reset or when the content of the down-counter is 00H. When data of reload registers is set at "00H", the down-counter becomes a 256-value counter. At initial reset, this register will be undefined. PTRST (F78H [D1], W) This bit resets the programmable timer. When "1" is written: Programmable timer reset When "0" is written: No operation Reading: Always "0" By writing "1" on PTRST, the programmable timer is reset. The contents set in RD0-RD7 are loaded into the down-counter. When the programmable timer is reset in the RUN mode, it will re-start counting immediately after loading and at STOP mode, the load data is maintained. Because this bit is only for writing, it is always "0" during reading. PTRUN (F78H [D0], R/W) This register controls RUN/STOP of the programmable timer. When "1" is written: RUN When "0" is written: STOP Reading: Valid By writing "1" on PTRUN, the programmable timer performs counting operation. Writing "0" will make the programmable timer stop counting. Even if the programmable timer is stopped, the timer data at that point is kept. When data of the counter is read at the RUN mode, proper reading may not be obtained due to the carry from the low-order digits (PT0-PT3) into the high-order digits (PT4-PT7) (when the reading of the low-order digits and high-order digits span the timing of the carry). To avoid this occurrence, perform the reading after suspending the programmable timer once, and set the PTRUN to "1" again. Moreover, it is required that the suspension period be within 1/4 cycle of the input clock (in case of 1/2 duty). At initial reset, PTRUN is set to "0". PT0-PT3, PT4-PT7 (F24H, F25H, R) Will read the data from the down-counter of the programmable timer. Will read the low-order 4 bits of the 8 bits counter data PT0-PT3, and the high-order 4 bits PT4-PT7. Because these 8 bits are only for reading, writing operation is rendered invalid. At initial reset, timer data will be undefined. EIPT (F12H [D0], R/W) This is the interrupt mask register of the programmable timer. When "1" is written: Enabled When "0" is written: Masked Reading: Valid Be sure that writing to the interrupt mask register is done with the interrupt in the DISABLE state (DI). Writing to the interrupt mask register while in the ENABLE state (EI) may cause malfunction. At initial reset, this register is set to "0" (mask). 52 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 8: TIMERS IPT (F02H [D0], R) This is the interrupt factor flag of the programmable timer. When "1" is read: Interrupt has occurred When "0" is read: Interrupt has not occurred Writing: Invalid From the status of this flag, the software can decide whether the programmable timer interrupt. Note, however, that even if the interrupt is masked, this flag will be set to "1" by the counter value will become "00H". Be sure that the interrupt factor flag reading is done with the interrupt in the DISABLE state (DI). Reading the interrupt factor flag while in the ENABLE state (EI) may cause malfunction. At initial reset, this flag is set to "0". 8.3.4 Programming notes (1) When initiating programmable timer count, perform programming by the following steps: 1. Set the initial data to RD0-RD7. 2. Reset the programmable timer by writing "1" to PTRST. 3. Start the down-count by writing "1" to PTRUN. (2) When the reload register (RD0-RD7) value is set at "00H", the down-counter becomes a 256-value counter. (3) When data of the timer is read consecutively in 8 bits in the RUN mode, perform the reading after suspending the timer once and then set the PTRUN to "1" again. Moreover, it is required that the suspension period be within 1/4 cycle of the input clock (in case of 1/2 duty). Accordingly, when the input clock is a fast clock faster than a 256 Hz, high speed processing by OSC3 is required. (4) Be sure that writing to the interrupt mask register is done with the interrupt in the DISABLE state (DI). Writing to the interrupt mask register while in the ENABLE state (EI) may cause malfunction. (5) Be sure that the interrupt factor flag reading is done with the interrupt in the DISABLE state (DI). Reading the interrupt factor flag while in the ENABLE state (EI) may cause malfunction. S1C60N07 TECHNICAL MANUAL EPSON 53 CHAPTER 9: SOUND GENERATOR CHAPTER 9 SOUND GENERATOR 9.1 Configuration of Sound Generator The S1C60N07 is capable of generating buzzer signals (BZ and #BZ) to drive a piezo-electric buzzer. The buzzer signal frequency may be selected by software from 8 types of signal divided from fOSC1 (32.768 kHz). Also, digital envelope which is duty ratio controlled may be added to the buzzer signal. In addition, 1-shot output circuit is built-in to output key operation check sound, and the like. Figure 9.1.1 shows the sound generator configuration. Figure 9.1.2 shows the sound generator timing chart. [ENVRST] 256 Hz [ENVRT] Envelope generation circuit [BZFQ0-BZFQ2] 32.768 kHz Envelope addition circuit Programmable dividing circuit [ENVON] [R43] 1-shot output circuit R43 (BZ) Output port R42 (#BZ) [R42] [BZSHOT] [SHOTPW] [ ]: Register Fig. 9.1.1 Configuration of sound generator BZFQ0-2 ENVON ENVON R43 (register) BZ (R43 terminal) #BZ (R42 terminal) Fig. 9.1.2 Timing chart of sound generator 9.2 Mask Option (1) Selection can be made whether to output the BZ signal from the R43 terminal. (2) Selection can be made whether to output the #BZ signal from the R42 terminal. However, if the BZ signal is not output the #BZ signal cannot be output. See Section 6.2, "Output Port" for details of the above mask option. 54 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 9: SOUND GENERATOR 9.3 Frequency Setting The frequencies of the buzzer signals (BZ, #BZ) are set by writing data to registers BZFQ0-BZFQ2. Table 9.3.1 lists the register setting values and the frequencies that can be set. Table 9.3.1 Setting of frequencies of buzzer signals BZFQ2 BZFQ1 BZFQ0 Buzzer frequency (Hz) 0 0 0 4,096.0 0 0 1 3,276.8 0 1 0 2,730.7 0 1 1 2,340.6 1 0 0 2,048.0 1 0 1 1,638.4 1 1 0 1,365.3 1 1 1 1,170.3 Note: A hazard may be observed in the output waveform of the BZ and #BZ signals when switches the buzzer frequency while the BZ and #BZ signals being output. 9.4 Digital Envelope A duty ratio control data envelope (with duty ratio change in 8 steps) can be added to the buzzer signal (BZ, #BZ). Duty ratio refers to the ratio of pulse width to the pulse cycle; given that high level output time is TH, and low level output time is TL, BZ output becomes TH/(TH+TL). #BZ output becomes TL/(TH+TL) owing to the inverted output of the BZ output. Moreover, care is necessary as the duty ratio differs according to the buzzer frequency. Envelope addition is performed by writing "1" to ENVON; when "0" is written, the duty ratio is fixed at the maximum (1/2 duty). Moreover, when envelope is added, writing "1" to ENVRST will cause the BZ signal duty ratio to be returned to maximum. The decay time of the envelope (time for the duty ratio to change) can be selected with the register ENVRT. This time is 62.5 ms (16 Hz) when "0" is written, and 125 ms (8 Hz) when "1" is written. However, a maximum difference of 4 ms is taken from envelope-ON until the first change. Table 9.4.1 lists the duty ratio and buzzer frequencies. Figure 9.4.1 shows the digital envelope timing chart. Duty Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Level 8 S1C60N07 TECHNICAL MANUAL Table 9.4.1 Duty ratio and buzzer frequencies Buzzer frequencies ratio 4,096.6 3,276.8 2,730.7 2,340.6 2,048.0 1,638.4 1,365.3 1,170.3 (max.) 8/16 8/20 12/24 12/28 7/16 7/20 11/24 11/28 6/16 6/20 10/24 10/28 5/16 5/20 9/24 9/28 4/16 4/20 8/24 8/28 3/16 3/20 7/24 7/28 2/16 2/20 6/24 6/28 (min.) 1/16 1/20 5/24 5/28 EPSON 55 CHAPTER 9: SOUND GENERATOR No change of duty level BZFQ0-2 ENON ENVRST ENVRT R43 (register) BZ signal duty ratio Level 1 (MAX) 2 3 4 5 6 7 8 (MIN) t01 t02 t03 t04 t05 t06 t07 t01 +0 62.5 -4 t11 t12 t13 t14 t15 t16 t17 +0 125 -4 t01 = msec t11 = msec t02-07 = 62.5 msec t12-17 = 125 msec Fig. 9.4.1 Digital envelope timing chart 9.5 1-shot Output In order to cause the buzzer to ring in a short period of time as in the case of key operation check sound, 1-shot output function is built-in. The time duration for buzzer signal to be output (BZ and #BZ) may be selected by SHOTPW; when "0" is written on SHOTPW, it is set to 31.25 ms and to 62.5 ms when "1" written. Actual output operation is performed by writing "1" on BZSHOT; after performing the previously described writing operation, it synchronizes with the internal 256 Hz signal and buzzer signal is output in output port R43 (R42). Moreover, after the set time has lapsed, it synchronizes with the same 256 Hz previously described and the buzzer signal is automatically turned off. Also, by reading BZSHOT, whether the 1-shot circuit is in operation or not may be determined with the software. Figure 9.5.1 shows the timing chart of the 1-shot output. 256 Hz SHOTPW BZSHOT * W (trigger) BZSHOT * R (status) BZ (R43 terminal) #BZ (R42 terminal) Fig. 9.5.1 Timing chart of 1-shot output 56 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 9: SOUND GENERATOR 9.6 Control of Sound Generator The control registers for the sound generator are explained below. Table 9.6.1 Control registers of sound generator Address D3 Register D2 D1 D0 R43 R42 R40 Name R43 Init 1 R42 1 R41 R40 1 1 SHOTPW BZFQ2 BZFQ1 BZFQ0 0 0 0 0 ENVON BZSHOT 0 R41 R/W F54H SHOTPW BZFQ2 BZFQ1 BZFQ0 F74H R/W BZSHOT ENVRST F75H W ENVRT W R/W R ENVRST ENVRT ENVON RESET 0 0 1 High Off High Off Comment 0 Low On Low On Output port (R43) Buzzer output (BZ) Output port (R42) Clock output (FOUT) [Buzzer inverted output (#BZ)] Output port (R41) High Low Output port (R40) High Low Clock inverted output (#FOUT) Off On 62.5 ms 31.25 ms 1-shot buzzer pulse width Buzzer frequency selection Trigger BUSY Reset 1.0 sec On - READY - 0.5 sec Off 1-shot buzzer trigger (W) Status (R) Envelope reset Envelope cycle selection Envelope On/Off BZFQ0-BZFQ2 (F74H [D0-D2], R/W) Will select the buzzer signal frequency. Table 9.6.2 Setting of frequencies of buzzer signals BZFQ2 BZFQ1 BZFQ0 Buzzer frequency (Hz) 0 0 0 4,096.0 0 0 1 3,276.8 0 1 0 2,730.7 0 1 1 2,340.6 1 0 0 2,048.0 1 0 1 1,638.4 1 1 0 1,365.3 1 1 1 1,170.3 At initial reset, 4,096 Hz is selected. ENVRST (F75H [D2], W) This is the reset input to make the duty ratio of the buzzer signal the maximum. When "1" is written: Reset input When "0" is written: No operation Reading: Always "0" When envelope is added to the buzzer signal, by writing "1" on ENVRST, the envelope is reset and duty ratio becomes maximum. When envelope is not added, or when buzzer signal is not being output, reset operation is ineffective. ENVON (F75H [D0], R/W) This controls adding the envelope to the buzzer signal. When "1" is written: Envelope added (ON) When "0" is written: No envelope (OFF) Reading: Valid By writing "1" on ENVON, envelope is added to the buzzer signal. Writing "0" means envelope will not be added. At initial reset, ENVON is set to "0" and envelope OFF will be selected. S1C60N07 TECHNICAL MANUAL EPSON 57 CHAPTER 9: SOUND GENERATOR ENVRT (F75H [D1], R/W) Selects the attenuation time of the envelope added to the buzzer signal. When "1" is written: 1.0 sec (125 ms x 7 = 875 ms) When "0" is written: 0.5 sec (62.5 ms x 7 = 437.5 ms) Reading: Valid The attenuation time of digital envelopes is determined by the time change for duty ratio. When "1" is written on ENVRT, attenuation time is set in 125 ms (8 Hz) units (125 ms x 7 = 875 ms), and in 62.5 ms (16 Hz) unit (62.5 ms x 7 = 437.5 ms) when "0" is written. However, there is a maximum error of 4 ms from envelope ON to the first change in both cases. At initial reset, ENVRT is set to "0". R43, R42 (F54H [D3, D2], R/W) Controls the output of the buzzer signals (BZ, #BZ). When "0" is written: Buzzer signal output When "1" is written: Low level (DC) Reading: Valid When "0" is set on R43, BZ signal is generated from R43 terminal, and if R42 is set to #BZ output, #BZ signal (inverted signal of BZ) is generated at the same time. When "1" is set on R43, R43 terminal (R42 too, if #BZ output is selected) becomes of low (V SS) level output. However, R42 with #BZ output selected, may be used as a 1-bit general register capable of read/write function, the data of which register does not affect #BZ (R42 terminal output). At initial reset, both R43 and R42 are set to "1". Note: BZ and #BZ output signals may produce hazards during ON/OFF switching. SHOTPW (F74H [D3], R/W) Sets the output time duration of the 1-shot buzzer. When "1" is written: 62.5 ms When "0" is written: 31.25 ms Reading: Valid Output time duration is set to 62.5 ms or 31.25 ms by writing "1" or "0", respectively, on SHOTPW. At initial reset, SHOTPW is set to "0". BZSHOT (F75H [D3], W, R) Controls the output of the 1-shot buzzer. * During writing operation When "1" is written: Trigger When "0" is written: No operation When "1" is written on BZSHOT, the 1-shot circuit operates and the buzzer signal (BZ and #BZ) is output. The 1-shot buzzer operates only when the regular buzzer output is in the OFF (R43 = "1") state and writing to BZSHOT becomes invalid in the ON (R43 = "0") state. * During reading operation When "1" is read: Busy When "0" is read: Ready The BZSHOT reads "1" when the 1-shot buzzer is ringing and "0" when it is not ringing. The period of "1" is from the time of the trigger until the buzzer output is turned OFF. At initial reset, "0" is read. 58 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 9: SOUND GENERATOR 9.7 Programming Notes (1) The BZ and #BZ signals may generate hazards in the following cases: * When the content of R43 register is changed, BZ and #BZ signals are switched ON or OFF. * When the contents of buzzer frequency selection registers (BZFQ0-BZFQ2) while the buzzer signal (BZ and #BZ) is being output. (2) The 1-shot buzzer operates only when the regular buzzer output is in the OFF (R43 = "1") state and writing to BZSHOT becomes invalid in the ON (R43 = "0") state. S1C60N07 TECHNICAL MANUAL EPSON 59 CHAPTER 10: INTERRUPT AND HALT CHAPTER 10 INTERRUPT AND HALT The S1C60N07 has the following interrupt functions built-in, and masking is possible for each one. External interrupt Internal interrupt * Input interrupt (1 system) * Clock timer interrupt (3 systems) * Stopwatch timer interrupt (2 systems) * Programmable timer interrupt (1 system) To allow the interrupt to function, it is necessary that the interrupt mask register of the required system be set to "1" (enable) and, at the same time, the interrupt flag be set to "1" (EI). When interrupt occurs, the interrupt flag is automatically reset to "0" (DI), prohibiting the any consequent interrupts. The CPU stops the operating clock when a HALT instruction is executed and then enters the HALT state. Re-running the CPU from the HALT state requires issuance of interrupt request. If return through interrupt request is not effective, return is effected from initial reset by the watchdog timer. Figure 10.1 shows the configuration of the interrupt circuit. See the explanations of the relevant circuits for interrupt details. IPT EIPT ISW1 EISW1 ISW0 EISW0 IT1 EIT1 Interrupt vector generation circuit IT2 EIT2 Program counter (low-order 4 bits) IT8 EIT8 IT32 EIT32 INT (interrupt request) Interrupt flag K00 EIK00 K01 EIK01 IK0 K02 Interrupt factor flag Interrupt mask register EIK02 K03 EIK03 Fig. 10.1 Configuration of interrupt circuit 60 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 10: INTERRUPT AND HALT 10.1 Interrupt Factor Flag and Interrupt Mask The corresponding interrupt factor flag is set to "1" with the individual interrupt element. If the following conditions exist, interrupt for the CPU occurs when the interrupt factor flag is set to "1". * The corresponding interrupt mask register is set at "1" (enable). * The interrupt flag is set at "1" (EI). The interrupt factor flag is reset to "0" at the read-only register by reading the data. Be sure that the interrupt factor flag reading is done with the interrupt in the DISABLE state (DI). Reading the interrupt factor flag while in the ENABLE state (EI) may cause malfunction. At initial reset, the interrupt factor flag is reset to "0". The interrupt can be masked by the corresponding interrupt mask register. The interrupt mask register is a register capable of read/write operation; by writing "1", it is enabled (interrupt is allowed) and by writing "0", it is masked (interrupt is prohibited). Be sure that writing to the interrupt mask register is done with the interrupt in the DISABLE state (DI). Writing to the interrupt mask register while in the ENABLE state (EI) may cause malfunction. At initial reset, the interrupt mask register is set to "0". The interrupt factor flag is set to "1" by interrupt factor even if the interrupt is masked. (The input interrupt factor flag IK0 will be eliminated.) Table 10.1.1 shows the correspondence between interrupt factor flags and interrupt mask registers. Table 10.1.1 Interrupt factor flags and interrupt mask registers Interrupt factor Interrupt factor flag Interrupt mask register Falling edge of clock timer (1 Hz) IT1 (F00H [D3]) EIT1 (F10H [D3]) Falling edge of clock timer (2 Hz) IT2 (F00H [D2]) EIT2 (F10H [D2]) Falling edge of clock timer (8 Hz) IT8 (F00H [D1]) EIT8 (F10H [D1]) Falling edge of clock timer (32 Hz) IT32 (F00H [D0]) EIT32 (F10H [D0]) Overflow of stopwatch timer (SWH) (1 Hz) ISW1 (F01H [D1]) EISW1 ( F11H [D1]) Overflow of stopwatch timer (SWL) (10 Hz) ISW0 (F01H [D0]) EISW0 ( F11H [D0]) Changing of input (K00-K03) status IK0 (F04H [D0]) EIK03 (F14H [D3]) EIK02 (F14H [D2]) EIK01 (F14H [D1]) EIK00 (F14H [D0]) Counter value of programmable timer = 00H IPT (F02H [D0]) EIPT (F12H [D0]) S1C60N07 TECHNICAL MANUAL EPSON 61 CHAPTER 10: INTERRUPT AND HALT 10.2 Interrupt Vector When an interrupt request is issued to the CPU, the CPU starts interrupt processing. Interrupt processing is accomplished by the following steps after the instruction being executed is completed. 1. The address (value of the program counter) of the program which should be run next is saved in the stack area (RAM). 2. The vector address (1 page 02H-0CH) for each interrupt request is set to the program counter. 3. Branch instruction written to the vector is effected (branch to software interrupt processing routine). Note: Time equivalent to 12 cycles of CPU system clock is required for steps 1 and 2. The interrupt request and interrupt vector correspondence is shown in Table 10.2.1. Table 10.2.1 Interrupt vector (PCP and PCS) 102H 104H 106H 10CH Interrupt request and interrupt vectors Interrupt request Priority Clock timer interrupt Stopwatch timer interrupt Input (K00-K03) interrupt Programmable timer interrupt Low High When multiple interrupts simultaneously occur, the high priority vector address is set to the program counter. 10.3 Programming Notes (1) The interrupt factor flag is set when the interrupt conditions are established, regardless of the setting of the interrupt mask register. Note, however, that the input interrupt factor flag (IK0) will be eliminated. (2) When an interrupt occurs, the interrupt flag will be reset by the hardware and it will become DI status. After completion of the interrupt processing, set to the EI status through the software as needed. Moreover, the nesting level may be set to be programmable by setting to the EI state at the beginning of the interrupt processing routine. (3) The interrupt factor flags must always be reset before setting the EI status. When the interrupt mask register has been set to "1", the same interrupt will occur again if the EI status is set unless of resetting the interrupt factor flag. (4) The interrupt factor flag will be reset by reading through the software. Because of this, when multiple interrupt factor flags are to be assigned to the same address, perform the flag check after the contents of the address has been stored in the RAM. Direct checking with the FAN instruction will cause all the interrupt factor flag to be reset. (5) Be sure that the interrupt factor flag reading is done with the interrupt in the DISABLE state (DI). Reading the interrupt factor flag while in the ENABLE state (EI) may cause malfunction. (6) Be sure that writing to the interrupt mask register is done with the interrupt in the DISABLE state (DI). Writing to the interrupt mask register while in the ENABLE state (EI) may cause malfunction. (7) When multiple interrupts simultaneously occur, the high priority vector address is set to the program counter. 62 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 10: INTERRUPT AND HALT (8) If an interrupt occurs while the CPU is processing some other interrupt request of which the priority is lower than the new one but the CPU has not fetched the interrupt vector, the CPU may shift to a vector address (one of among 102H, 104H, 106H and 10CH) that is different from the new interrupt. Therefore, make sure the interrupt factor flag has been set immediately after the branch instruction stored in the vector address is executed and quit the interrupt processing if it has not been set. Furthermore, place a branch instruction for executing the interrupt processing routine in the vector address 10CH because the CPU may shift to that address. By setting the start address of the programmable timer interrupt processing routine as the branch destination, the priority level by hardware can be maintained. If the program does not have the individual processing routine for each interrupt (for example, in the case of all interrupts using the same processing routine in which the type of interrupt is judged by reading the interrupt flags, or in the case of the main routine checking all the interrupt flags by branching the flow the RET instruction stored in all the vector address), place the instruction the same as the other interrupt vectors in address 10CH. When the interrupt function is not used, it is not necessary to pay attention to the above mentioned precautions. S1C60N07 TECHNICAL MANUAL EPSON 63 CHAPTER 11: SUMMARY OF NOTES CHAPTER 11 SUMMARY OF NOTES 11.1 Notes for Low Current Consumption The S1C60N07 contains control registers for each of the circuits so that current consumption can be lowered. These control registers lower the current consumption through programs that operate the circuits at the minimum levels. The following text explains the circuits that can control operation and their control registers. Refer to these when putting programs together. Table 11.1.1 Circuits and control registers Control registers Order of consumed current CPU HALT instruction See electrical characteristics (Chapter 13) CPU operation frequency CLKCHG, OSCC See electrical characteristics (Chapter 13) Internal regulated voltage VSC0, VSC1 See electrical characteristics (Chapter 13) Heavy load protection mode HLMOD See electrical characteristics (Chapter 13) Circuits (and Items) Below are the circuit status at initial reset. CPU: CPU operating frequency: Operating OSC1 side (CLKCHG = "0"), OSC3 oscillation circuit is stopped (OSCC = "0") Internal regulated voltage: -1.2 V (VSC0, VSC1 = "0") When CR oscillation is selected by mask option, the internal regulated voltage becomes -2.1 V. Heavy load protection mode: Normal operating mode (HLMOD = "0") Also, be careful about panel selection because the current consumption can differ by the order of several A on account of the LCD panel characteristics. 64 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 11: SUMMARY OF NOTES 11.2 Summary of Notes by Function Here, the cautionary notes are summed up by function category. Keep these notes well in mined when programming. Memory Memory is not mounted in unused area within the memory map and in memory area not indicated in this manual. For this reason, normal operation cannot be assured for programs that have been prepared with access to these areas. Heavy load protection mode (1) When driving heavy loads, set it to heavy load protection mode. Unless it is necessary, be careful not to set the heavy load protection mode with the software. (2) Perform heavy load driving only after setting up at least 1 ms wait time through the software, after switching to the heavy load protection mode. (See Figure 3.2.2.1.) (3) When the heavy load protection mode is to canceled after completion of heavy load driving, set up at least 2 seconds wait time through the software. (See Figure 3.2.2.1.) Watchdog timer (1) The watchdog timer must reset within 3-second cycles by the software. (2) When the clock timer is reset (TMRST "1"), the watchdog timer is counted up; reset the watchdog immediately after if necessary. Oscillation circuit (1) When high-speed operation of the CPU is not required, observe the following reminders to minimize power current consumption. Set the CPU operating clock to OSC1. Turn the OSC3 oscillation OFF. Set the internal operating voltage (V S1) to -1.2 V or -2.1 V. (2) When the CPU is to be operated with OSC1, set the operating voltage to -1.2 V if the power voltage is less than 3.1 V (V DD-VSS < 3.1 V); set the operating voltage to -2.1 V if the voltage is 3.1 V or more (V DD-VSS 3.1 V). Moreover, because -1.2 V will be set during initial reset, be sure to execute the previous process at the beginning of the initial routine. Note, however, that it can be used fixed at 1.2 V (at OSC1 operation) for power whose initial value is 3.6 V or less as in lithium batteries. (3) When switching VS1 from -1.2 V (for OSC1 crystal oscillation circuit) to -3.0 V (for OSC3 oscillation circuit), or vice versa, be sure to hold the -2.1 V setting for more than 5 ms first for power voltage stabilization. (VSC1, VSC0) = (0, 0) (0, 1) 5 ms WAIT (1, x) = (1, x) (0, 1) 5 ms WAIT (0, 0) = (0, 0) (1, x) is prohibited = (1, x) (0, 0) is prohibited (4) When switching the CPU operating clock from OSC1 to OSC3, follow the flow chart shown in Figure 5.6.1 and then proceed with software processing. (5) Use separate instructions to switch the clock from OSC3 to OSC1 and turn the OSC3 oscillation OFF. Simultaneous processing with a single instruction may cause malfunction of the CPU. (6) When CR oscillation has been selected by the mask option, internal regulated voltage becomes -2.1 V and will never become -1.2 V. S1C60N07 TECHNICAL MANUAL EPSON 65 CHAPTER 11: SUMMARY OF NOTES Input port (Kxx) (1) When changing the input port from low level to high level with a pull up resistor, a delay in the waveform rise time will occur depending on the time constant of the pull up resistor and input gate capacity. Hence, when reading data from the input port, set an appropriate waiting time. Care is particularly required for key matrix configuration scanning. For reference, approximately 500 s waiting time is required. (2) Input interrupt programming related precautions Port K input Active status Mask register Factor flag set Not set When the content of the mask register is rewritten, while the port K input is in the active status, the input interrupt factor flag is set at . Fig. 11.2.1 Input interrupt timing When using an input interrupt, if you rewrite the content of the mask register, when the value of the input terminal which becomes the interrupt input is in the active status (input terminal = low status), the factor flag for input interrupt may be set. For example, a factor flag is set with the timing of shown in Figure 11.2.1. However, when clearing the content of the mask register with the input terminal kept in the low status and then setting it, the factor flag of the input interrupt is again set at the timing that has been set. Consequently, when the input terminal is in the active status (low status), do not rewrite the mask register (clearing, then setting the mask register), so that a factor flag will only set at the rising edge in this case. When clearing, then setting the mask register, set the mask register, when the input terminal is not in the active status (high status). Output port (Rxx) (1) When BZ, #BZ, FOUT, #FOUT, and PTCLK (DC) are selected by mask option, a hazard may be observed in the output waveform when the data of the output register changes. (2) Because the R32 and R33 ports gain high impedance during initial reset, be careful when using them as interface with external devices and the like. I/O port (Pxx) (1) When the I/O port is set at output mode, and low impedance load is connected to the port terminal, the data written and read may differ. (2) If the state of the I/O port meets all of the following 4 conditions, the reading data will be undefined: * The input/output mode is set at output mode * Output specification is set at Nch open drain * The content of the data register is "1" * The pull up resistor turned is OFF LCD driver Because at initial reset, the contents of segment data memory and LC0-LC3 are undefined, there is need to initialize by software. Clock timer (1) When the clock timer has been reset, the interrupt factor flag (IT) may sometimes be set to "1". Consequently, perform flag read (reset the flag) as necessary at reset. (2) Because the watchdog timer counts up during reset as in the above (1), reset the watchdog timer as necessary. 66 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 11: SUMMARY OF NOTES (3) When the low-order digits (TM0-TM3) and high-order digits (TM4-TM7) are consecutively read, proper reading may not be obtained due to the carry from the low-order digits into the high-order digits (when the reading of the low-order digits and high-order digits span the timing of the carry). For this reason, perform multiple reading of timer data, make comparisons and use matching data as result. Stopwatch timer When data of the counter is read at run mode, perform the reading after suspending the counter once and then set SWRUN to "1" again. Moreover, it is required that the suspension period not exceed 976 s (1/4 cycle of 256 Hz). Programmable timer (1) When initiating programmable timer count, perform programming by the following steps: 1. Set the initial data to RD0-RD7. 2. Reset the programmable timer by writing "1" to PTRST. 3. Start the down-count by writing "1" to PTRUN. (2) When the reload register (RD0-RD7) value is set at "00H", the down-counter becomes a 256-value counter. (3) When data of the timer is read consecutively in 8 bits in the RUN mode, perform the reading after suspending the timer once and then set the PTRUN to "1" again. Moreover, it is required that the suspension period be within 1/4 cycle of the input clock (in case of 1/2 duty). Accordingly, when the input clock is a fast clock faster than 256 Hz, high speed processing by OSC3 is required. Sound generator (1) The BZ and #BZ signals may generate hazards in the following cases: * When the content of R43 register is changed, BZ and #BZ signals are switched ON or OFF. * When the contents of buzzer frequency selection registers (BZFQ0-BZFQ2) while the buzzer signal (BZ and #BZ) is being output. (2) The 1-shot buzzer operates only when the regular buzzer output is in the OFF (R43 = "1") state and writing to BZSHOT becomes invalid in the ON (R43 = "0") state. Interrupt (1) The interrupt factor flag is set when the interrupt conditions are established, regardless of the setting of the interrupt mask register. Note, however, that the input interrupt factor flag (IK0) will be eliminated. (2) When an interrupt occurs, the interrupt flag will be reset by the hardware and it will become DI status. After completion of the interrupt processing, set to the EI status through the software as needed. Moreover, the nesting level may be set to be programmable by setting to the EI state at the beginning of the interrupt processing routine. (3) The interrupt factor flags must always be reset before setting the EI status. When the interrupt mask register has been set to "1", the same interrupt will occur again if the EI status is set unless of resetting the interrupt factor flag. (4) The interrupt factor flag will be reset by reading through the software. Because of this, when multiple interrupt factor flags are to be assigned to the same address, perform the flag check after the contents of the address has been stored in the RAM. Direct checking with the FAN instruction will cause all the interrupt factor flag to be reset. (5) Be sure that the interrupt factor flag reading is done with the interrupt in the DISABLE state (DI). Reading the interrupt factor flag while in the ENABLE state (EI) may cause malfunction. (6) Be sure that writing to the interrupt mask register is done with the interrupt in the DISABLE state (DI). Writing to the interrupt mask register while in the ENABLE state (EI) may cause malfunction. S1C60N07 TECHNICAL MANUAL EPSON 67 CHAPTER 11: SUMMARY OF NOTES (7) When multiple interrupts simultaneously occur, the high priority vector address is set to the program counter. (8) If an interrupt occurs while the CPU is processing some other interrupt request of which the priority is lower than the new one but the CPU has not fetched the interrupt vector, the CPU may shift to a vector address (one of among 102H, 104H, 106H and 10CH) that is different from the new interrupt. Therefore, make sure the interrupt factor flag has been set immediately after the branch instruction stored in the vector address is executed and quit the interrupt processing if it has not been set. Furthermore, place a branch instruction for executing the interrupt processing routine in the vector address 10CH because the CPU may shift to that address. By setting the start address of the programmable timer interrupt processing routine as the branch destination, the priority level by hardware can be maintained. If the program does not have the individual processing routine for each interrupt (for example, in the case of all interrupts using the same processing routine in which the type of interrupt is judged by reading the interrupt flags, or in the case of the main routine checking all the interrupt flags by branching the flow the RET instruction stored in all the vector address), place the instruction the same as the other interrupt vectors in address 10CH. When the interrupt function is not used, it is not necessary to pay attention to the above mentioned precautions. 68 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 11: SUMMARY OF NOTES 11.3 Precautions on Mounting Oscillation Circuit * Oscillation characteristics change depending on conditions (board pattern, components used, etc.). In particular, when a ceramic oscillator or crystal oscillator is used, use the oscillator manufacturer's recommended values for constants such as capacitance and resistance. * Disturbances of the oscillation clock due to noise may cause a malfunction. Consider the following points to prevent this: (1) Components which are connected to the OSC1 (OSC3) and OSC2 (OSC4) terminals, such as oscillators, resistors and capacitors, should be connected in the shortest line. (2) As shown in the figure, make a VDD pattern as large as possible at circumscription of the OSC1 (OSC3) and OSC2 (OSC4) terminals and the components connected to these terminals. Furthermore, do not use this VDD pattern for any purpose other than the oscillation system. Sample VDD pattern (OSC3) OSC4 OSC3 VDD * In order to prevent unstable operation of the oscillation circuit due to current leak between OSC1 (OSC3) and VSS, please keep enough distance between OSC3 and VSS or other signals on the board pattern. Reset Circuit * The power-on reset signal which is input to the #RESET terminal changes depending on conditions (power rise time, components used, board pattern, etc.). Decide the time constant of the capacitor and resistor after enough tests have been completed with the application product. When using the built-in pull-up resistor of the #RESET terminal, take into consideration dispersion of the resistance for setting the constant. * In order to prevent any occurrences of unnecessary resetting caused by noise during operating, components such as capacitors and resistors should be connected to the #RESET terminal in the shortest line. Power Supply Circuit * Sudden power supply variation due to noise may cause malfunction. Consider the following points to prevent this: (1) The power supply should be connected to the VDD and VSS terminal with patterns as short and large as possible. Furthermore, similar consideration is necessary when VL1-VL5 are supplied from outside the IC. S1C60N07 TECHNICAL MANUAL EPSON 69 CHAPTER 11: SUMMARY OF NOTES (2) When connecting between the VDD and VSS terminals with a bypass capacitor, the terminals should be connected as short as possible. Bypass capacitor connection example VDD VDD VSS VSS (3) Components which are connected to the VS1, VL1-VL5 terminals, such as capacitors and resistors, should be connected in the shortest line. In particular, the VL1-VL5 voltages affect the display quality. * Do not connect anything to the VL1-VL5 terminals when the LCD driver is not used. Arrangement of Signal Lines * In order to prevent generation of electromagnetic induction noise caused by mutual inductance, do not arrange a large current signal line near the circuits that are sensitive to noise such as the oscillation unit. * When a signal line is parallel with a high-speed line in long distance or intersects a high-speed line, noise may generated by mutual interference between the signals and it may cause a malfunction. Do not arrange a high-speed signal line especially near circuits that are sensitive to noise such as the oscillation unit. Prohibited pattern OSC4 OSC3 VDD Large current signal line High-speed signal line Precautions for Visible Radiation (when bare chip is mounted) * Visible radiation causes semiconductor devices to change the electrical characteristics. It may cause this IC to malfunction. When developing products which use this IC, consider the following precautions to prevent malfunctions caused by visible radiation. (1) Design the product and implement the IC on the board so that it is shielded from visible radiation in actual use. (2) The inspection process of the product needs an environment that shields the IC from visible radiation. (3) As well as the face of the IC, shield the back and side too. 70 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 12: BASIC EXTERNAL CONNECTION DIAGRAM CHAPTER 12 BASIC EXTERNAL CONNECTION DIAGRAM I/O DATA COM0 | COM15 SEG0 | SEG39 LCD PANEL 40 x 16 R32 R33 R40 R41 R42 P00-P03 S1C60N07 R43 VREF VSS [The potential of the substrate (back of the chip) is VDD.] INPUT DATA OUTPUT DATA FOUT Buzzer N.C. #RESET K00-K03 + C3 C2 C1 C7 C6 C5 C4 C8 OSC1 OCS3 OSC2 OSC4 VL5 VL4 VL3 VL2 VL1 VS1 CF AE AD CC CB CA #TEST VDD Rfc Rfx Ceramic X'tal CDC CGC CGX POWER 3-5 V RCR2 RCR1 Mask option X'tal Rfx CGX (RCR1) Crystal oscillator Feedback resistor Trimmer capacitor Resistor for OSC1 CR oscillation Ceramic Ceramic oscillator Rfc Feedback resistor CGC Gate capacitor CDC Drain capacitor (RCR2) Resistor for OSC3 CR oscillation 32.768 kHz, CI(Max)=35 k 10 M 5-25 pF 1.6 M (32 kHz Typ.) 500 kHz-2 MHz 1 M 100 pF 100 pF 20 k-100 k (VSC=2) 40 k-100 k (VSC=1) C1 C2 C3 C4 C5 C6 C7 C8 Booster capacitor (1) Booster capacitor (2) Booster capacitor (3) Capacitor between VDD and VL1 Capacitor between VDD and VL2 Capacitor between VDD and VL4 Capacitor between VDD and VL5 Capacitor between VDD and VS1 0.1F 1 0.1F 1 0.1F 1 0.1F 1 0.1F 1 0.1F 1 0.1F 1 0.1F 1 When the load on the liquid crystal system is large, increase the capacitance of the voltage booster capacitors (C1 -C 3 ) and the capacitors between VDD and liquid crystal system power (C4 -C 7 ). Note: The above table is simply an example. Refer to Chapter 13, "Electrical Characteristics", for detailed characteristics. S1C60N07 TECHNICAL MANUAL EPSON 71 CHAPTER 13: ELECTRICAL CHARACTERISTICS CHAPTER 13 ELECTRICAL CHARACTERISTICS 13.1 Absolute Maximum Rating (VDD=0V) Item Symbol Rated value Unit Supply voltage VSS -7.0 to 0.5 V VI Input voltage (1) VSS - 0.3 to 0.5 V VIOSC VS1 - 0.3 to 0.5 Input voltage (2) V Permissible total output current 1 IVSS 10 mA Topr Operating temperature -20 to 70 C Tstg Storage temperature -65 to 150 C Tsol Soldering temperature / time 260C, 10sec (lead section) - PD Permissible dissipation 2 250 mW 1 The permissible total output current is the sum total of the current (average current) that simultaneously flows from the output pin (or is drawn in). 2 In case of plastic package. 13.2 Recommended Operating Conditions Item Supply voltage Symbol VSS VDD=0V Oscillation frequency (1) Oscillation frequency (2) Oscillation frequency (3) Voltage booster capacitor (1) Voltage booster capacitor (2) Voltage booster capacitor (3) Capacitor between VDD and VL1 Capacitor between VDD and VL2 Capacitor between VDD and VL4 Capacitor between VDD and VL5 Capacitor between VDD and VS1 fOSC1 fOSC3 fOSC3 C1 C2 C3 C4 C5 C6 C7 C8 Condition VSC="0" VSC="1" VSC="2" VSC="1" VSC="2" Min. -3.8 -5.5 -5.5 20 50 50 (Ta=-20 to 70C) Typ. Max. Unit -3.0 -1.8 V -3.0 -2.2 V -5.0 -3.5 V 32.768 50 kHz 1,000 1,200 kHz 2,000 2,300 kHz 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 13.3 DC Characteristics Conditions unless otherwise specified: VDD=0V, VSS=-3.0V, VL1=-1.0V, VL2=-2.0V, VL4=-3.0V, VL5=-4.0V, fOSC1=32.768kHz, fOSC3=1MHz, Ta=25C, C1-C8=0.047F Item Symbol Condition Min. Typ. Max. Unit VSS=-2.2 to -5.5V K00-03, P00-03 High-level input voltage (1) VIH1 0.2*VSS 0 V Ta=25C VSS Low-level input voltage (1) VIL1 0.8*VSS V VSS=-2.2 to -5.5V #RESET High-level input voltage (2) VIH2 -0.2 0 V Ta=25C Low-level input voltage (2) VIL2 VSS VSS+0.2 V K00-03, P00-03, #RESET VSS=-3.0V, VIH=0V High-level input current IIH 0 0.5 A VSS=-3.0V, VIL1=VSS Low-level input current (1) -45 -15 A IIL1 With Pull-up resistor VSS=-3.0V, VIL2=VSS Low-level input current (2) IIL2 -0.5 0 A No Pull-up resistor VSS=-2.2V P00-03, R32, R33, R40, R41 High-level output current (1) IOH1 -1.0 mA VOH1=-0.5V VSS=-2.2V, 4.0 Low-level output current (1) IOL1 mA VOL1=VSS+0.5V R42, R43 VSS=-2.2V High-level output current (2) IOH2 -2.0 mA VOH2=-0.5V VSS=-2.2V, 8.0 Low-level output current (2) IOL2 mA VOL2=VSS+0.5V COM0-15 VOH3=-0.05V Common output current IOH3 -30 A VOL3=VL5+0.05V IOL3 30 A VOH4=-0.05V SEG0-39 Segment output current IOH4 -10 A VOL4=VL5+0.05V IOL4 10 A 72 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 13: ELECTRICAL CHARACTERISTICS 13.4 Analog Circuit Characteristics and Consumed Current Conditions unless otherwise specified: VDD=0V, VSS=-3.0V, VL1=-1.0V, VL2=-2.0V, VL4=-3.0V, VL5=-4.0V, fOSC1=32.768kHz, fOSC3=1MHz, Ta=25C, C1~C8=0.047F Item Symbol Condition Min. Typ. Max. Unit LCD drive voltage VL1 Connects a 1M load resistance between VDD and 1/2*VL2 1/2*VL2 V (Normal mode) VL1 (No panel load) -0.1 x0.95 -2.06 Connects a 1M load resistance LC="0" VL2 -2.11 between VDD and VL2 (No panel load) LC="1" -2.17 LC="2" -2.22 LC="3" -2.27 LC="4" -2.32 LC="5" -2.38 LC="6" -2.43 LC="7" Typ. Typ. V -2.48 LC="8" x1.12 x0.88 -2.53 LC="9" -2.59 LC="10" -2.64 LC="11" -2.69 LC="12" -2.74 LC="13" -2.80 LC="14" -2.85 LC="15" Connects a 1M load resistance between VDD and 3/2*VL2 3/2*VL2 V VL4 VL4 (No panel load) x0.95 V Connects a 1M load resistance between VDD and VL5 2*VL2 2*VL2 VL5 (No panel load) x0.95 LCD drive voltage -1.05 Connects a 1M load resistance LC="0" VL1 (Heavy load protection mode) -1.08 between VDD and VL1 (No panel load) LC="1" -1.11 LC="2" -1.13 LC="3" -1.16 LC="4" -1.19 LC="5" -1.21 LC="6" -1.24 LC="7" Typ. Typ. V -1.26 LC="8" x0.88 x1.12 -1.29 LC="9" -1.32 LC="10" -1.34 LC="11" -1.37 LC="12" -1.40 LC="13" -1.42 LC="14" -1.45 LC="15" V Connects a 1M load resistance between VDD and 2*VL1 2*VL1 VL2 VL2 (No panel load) x0.90 V Connects a 1M load resistance between VDD and 3*VL1 VL4 3*VL1 x0.90 VL4 (No panel load) V Connects a 1M load resistance between VDD and 4*VL1 VL5 4*VL1 VL5 (No panel load) x0.90 Current consumption 1 2.5 A During HALT (VSC="0", OSCC="0") 5.0 Ihlt 6.5 A (OSC1/crystal oscillation) IEX1 During operation at 32kHz (VSC="0", OSCC="0") 9.0 400 A During operation at 1MHz (VSC="1") 600 IEX2 1,000 1,500 A During operation at 2MHz (VSC="2", VSS=-5.0V) IEX3 20 A Current consumption 1 70 Ihlt During HALT (VSC="0"or"1", OSCC="0") 25 A 80 (OSC1/CR oscillation) IEX1 During operation at fOSC1 (VSC="0"or"1", OSCC="0") 420 A 600 During operation at 1MHz (VSC="1") IEX2 1,000 1,500 A During operation at 2MHz (VSC="2", VSS=-5.0V) IEX3 1 No panel loard. S1C60N07 TECHNICAL MANUAL EPSON 73 CHAPTER 13: ELECTRICAL CHARACTERISTICS 13.5 AC Characteristics #RESET input Condition: VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25C, VIH=0.5VSS, VIL=0.9VSS Item Symbol Min. Typ. #RESET input time 2.0 tsr Max. Unit ms tsr #RESET 74 VIH VIL EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 13: ELECTRICAL CHARACTERISTICS 13.6 Oscillation Characteristics The oscillation characteristics change depending on the conditions (components used, board pattern, etc.). Use the following characteristics as reference values. OSC1 crystal oscillation characteristics Conditions unless otherwise specified: VDD=0V, VSS=-3.0V, Crystal: Q13MC146, CGX=25pF, CDX=built-in, Rfx=10M, Ta=25C, VSC="0" Item Symbol Condition Min. tsta Oscillation start time VSS=-2.2 to -5.5V CD Package as assembled Built-in drain capacitance Bare chip Frequency/voltage deviation f/V VSS=-2.2 to -5.5V Frequency/IC deviation -10 f/IC Frequency adjustable range 35 f/CG CG=5 to 25pF Harmonic oscillation start voltage Vhho CG=5pF (VSS) Permitted leak resistance 200 Between OSC1 and VDD, VS1 Rleak Typ. Max. 5 22 21 5 +10 45 -5.5 Unit s pF pF ppm ppm ppm V M OSC1 CR oscillation characteristics Conditions unless otherwise specified: VDD=0V, VSS=-3.0V, Ta=25C, VSC="0" or "1" Item Symbol Oscillation frequency fOSC1 RCR1=1.6M Oscillation start time Frequency/voltage deviation tsta f/V Condition VSS=-2.2 to -5.5V VSS=-2.2 to -5.5V Min. Typ. x70% Typ. 32 Max. Unit Typ. kHz x130% 3 ms +5 % Typ. 860 Max. Unit Typ. kHz x130% 3 ms +5 % Typ. 1.7 Max. Unit Typ. MHz x130% 3 ms +5 % -5 OSC3 CR oscillation characteristics 1 Conditions unless otherwise specified: VDD=0V, VSS=-3.0V, Ta=25C, VSC="1" Item Symbol Oscillation frequency fOSC3 RCR2=40k Oscillation start time Frequency/voltage deviation tsta f/V Condition VSS=-2.2 to -5.5V VSS=-2.2 to -5.5V Min. Typ. x70% -5 OSC3 CR oscillation characteristics 2 Conditions unless otherwise specified: VDD=0V, VSS=-5.0V, Ta=25C, VSC="2" Item Symbol Oscillation frequency fOSC3 RCR2=20k Oscillation start time Frequency/voltage deviation tsta f/V Condition VSS=-3.5 to -5.5V VSS=-3.5 to -5.5V Min. Typ. x70% -5 OSC3 ceramic oscillation characteristics 1 Conditions unless otherwise specified: VDD=0V, VSS=-3.0V, Ta=25C, VSC="1", Ceramic oscillator: CSB 1000J 1 (1MHz), CGC=CDC=100pF, Rfc=1M Item Symbol Condition Min. Typ. Max. tsta Oscillation start time VSS=-2.2 to -5.5V 3 Frequency/voltage deviation f/V VSS=-2.2 to -5.5V -3 +3 1 Made by Murata Mfg. Co. Unit ms % OSC3 ceramic oscillation characteristics 2 Conditions unless otherwise specified: VDD=0V, VSS=-5.0V, Ta=25C, VSC="2", Ceramic oscillator: CSA 2.00MG 1 (2MHz), CGC=CDC=100pF, Rfc=1M Item Symbol Condition Min. Typ. Max. tsta Oscillation start time VSS=-3.5 to -5.5V 3 Frequency/voltage deviation f/V VSS=-3.5 to -5.5V -3 +3 1 Made by Murata Mfg. Co. S1C60N07 TECHNICAL MANUAL EPSON Unit ms % 75 CHAPTER 13: ELECTRICAL CHARACTERISTICS OSC3 CR oscillation frequency - resistance characteristic Reference 5M CR oscillation frequency fOSC3 [Hz] VDD = 0V VSS = -3.0V VSC = "1" Ta = 25C Typ. value 2M 1M 500k 200k 100k 10k 20k 30k 40k 50k 100k 200k 500k Resistance for CR oscillation RCR2 [] Reference 5M CR oscillation frequency fOSC3 [Hz] VDD = 0V VSS = -5.0V VSC = "2" Ta = 25C Typ. value 2M 1M 500k 200k 100k 10k 20k 30k 40k 50k 100k 200k 500k Resistance for CR oscillation RCR2 [] 76 EPSON S1C60N07 TECHNICAL MANUAL CHAPTER 14: PACKAGE CHAPTER 14 PACKAGE 14.1 Plastic Package QFP15-100pin (Unit: mm) 160.4 140.1 75 51 160.4 50 140.1 76 INDEX 100 26 1.40.1 25 0.5 +0.1 0.18 -0.05 +0.05 0.125 -0.025 0 10 0.50.2 0.1 1.7max 1 1 S1C60N07 TECHNICAL MANUAL EPSON 77 CHAPTER 14: PACKAGE 14.2 Ceramic Package for Test Samples QFP15-100pin (Unit: mm) 17.00 0.30 12.00Typ. 100 76 75 25 51 13.97 0.15 1 26 50 0.50Typ. GLASS 78 0.20 0.38 0.08 0.95 0.08 2.54Max. 0.76 0.13 0.50 EPSON CERAMIC 0.82 0.30 S1C60N07 TECHNICAL MANUAL CHAPTER 15: PAD LAYOUT CHAPTER 15 PAD LAYOUT Die No. 15.1 Diagram of Pad Layout 20 15 10 5 1 91 90 25 85 30 35 80 X (0, 0) 3.87 mm Y 75 40 70 45 50 55 60 65 3.87 mm S1C60N07 TECHNICAL MANUAL EPSON 79 CHAPTER 15: PAD LAYOUT 15.2 Pad Coordinates Pad No. Name 1 SEG39 2 SEG38 3 SEG37 4 SEG36 5 SEG35 6 SEG34 7 SEG33 8 SEG32 9 SEG31 10 SEG30 11 SEG29 12 SEG28 13 SEG27 14 SEG26 15 SEG25 16 SEG24 17 SEG23 18 SEG22 19 SEG21 20 SEG20 21 SEG19 22 SEG18 23 SEG17 24 SEG16 25 SEG15 26 SEG14 27 SEG13 28 SEG12 29 SEG11 30 SEG10 31 SEG9 80 Coordinate Pad X Y No. Name 1,402 1,768 32 SEG8 1,272 1,768 33 SEG7 1,142 1,768 34 SEG6 1,012 1,768 35 SEG5 882 1,768 36 SEG4 752 1,768 37 SEG3 622 1,768 38 SEG2 492 1,768 39 SEG1 362 1,768 40 SEG0 232 1,768 41 K03 102 1,768 42 K02 -28 1,768 43 K01 -158 1,768 44 K00 -288 1,768 45 P03 -418 1,768 46 P02 -548 1,768 47 P01 -678 1,768 48 P00 -808 1,768 49 R43 -938 1,768 50 R42 -1,068 1,768 51 R41 -1,198 1,768 52 R40 -1,328 1,768 53 R33 -1,458 1,768 54 R32 -1,588 1,768 55 #RESET -1,768 1,337 56 #TEST -1,768 1,207 57 VSS -1,768 1,077 58 OSC4 -1,768 947 59 OSC3 -1,768 817 60 VS1 -1,768 687 61 OSC2 -1,768 557 62 OSC1 Coordinate Pad X Y No. Name -1,768 427 63 VDD -1,768 297 64 VREF -1,768 167 65 VL1 -1,768 37 66 VL2 -1,768 -93 67 VL3 -1,768 -223 68 VL4 -1,768 -353 69 VL5 -1,768 -483 70 CF -1,768 -613 71 CE -1,768 -773 72 CD -1,768 -903 73 CC -1,768 -1,033 74 CB -1,768 -1,163 75 CA -1,768 -1,307 76 COM0 -1,768 -1,437 77 COM1 -1,768 -1,568 78 COM2 -1,768 -1,698 79 COM3 -1,283 -1,768 80 COM4 -1,153 -1,768 81 COM5 -927 -1,768 82 COM6 -797 -1,768 83 COM7 -658 -1,768 84 COM8 -528 -1,768 85 COM9 -383 -1,768 86 COM10 -253 -1,768 87 COM11 -39 -1,768 88 COM12 91 -1,768 89 COM13 221 -1,768 90 COM14 351 -1,768 91 COM15 481 -1,768 - - 611 -1,768 - - EPSON (unit: m) Coordinate X Y 741 -1,768 871 -1,768 1,034 -1,768 1,164 -1,768 1,294 -1,768 1,768 -1,476 1,768 -1,346 1,768 -1,216 1,768 -1,086 1,768 -956 1,768 -826 1,768 -696 1,768 -566 1,768 -436 1,768 -306 1,768 -176 1,768 -46 1,768 84 1,768 214 1,768 344 1,768 474 1,768 604 1,768 734 1,768 864 1,768 994 1,768 1,124 1,768 1,254 1,768 1,384 1,768 1,545 - - - - S1C60N07 TECHNICAL MANUAL International Sales Operations AMERICA ASIA EPSON ELECTRONICS AMERICA, INC. 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Phone: +1-781-246-3600 Fax: +1-781-246-5443 EPSON HONG KONG LTD. 20/F., Harbour Centre, 25 Harbour Road Wanchai, Hong Kong Phone: +852-2585-4600 Fax: +852-2827-4346 Telex: 65542 EPSCO HX EPSON TAIWAN TECHNOLOGY & TRADING LTD. 10F, No. 287, Nanking East Road, Sec. 3 Taipei Phone: 02-2717-7360 Fax: 02-2712-9164 Telex: 24444 EPSONTB HSINCHU OFFICE Southeast 3010 Royal Blvd. South, Suite 170 Alpharetta, GA 30005, U.S.A. Phone: +1-877-EEA-0020 Fax: +1-770-777-2637 13F-3, No. 295, Kuang-Fu Road, Sec. 2 HsinChu 300 Phone: 03-573-9900 Fax: 03-573-9169 EPSON SINGAPORE PTE., LTD. No. 1 Temasek Avenue, #36-00 Millenia Tower, SINGAPORE 039192 Phone: +65-337-7911 Fax: +65-334-2716 EUROPE EPSON EUROPE ELECTRONICS GmbH SEIKO EPSON CORPORATION KOREA OFFICE - HEADQUARTERS Riesstrasse 15 80992 Munich, GERMANY Phone: +49-(0)89-14005-0 Fax: +49-(0)89-14005-110 SALES OFFICE Altstadtstrasse 176 51379 Leverkusen, GERMANY Phone: +49-(0)2171-5045-0 Fax: +49-(0)2171-5045-10 UK BRANCH OFFICE Unit 2.4, Doncastle House, Doncastle Road Bracknell, Berkshire RG12 8PE, ENGLAND Phone: +44-(0)1344-381700 Fax: +44-(0)1344-381701 50F, KLI 63 Bldg., 60 Yoido-dong Youngdeungpo-Ku, Seoul, 150-763, KOREA Phone: 02-784-6027 Fax: 02-767-3677 SEIKO EPSON CORPORATION ELECTRONIC DEVICES MARKETING DIVISION Electronic Device Marketing Department IC Marketing & Engineering Group 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5816 Fax: +81-(0)42-587-5624 ED International Marketing Department Europe & U.S.A. FRENCH BRANCH OFFICE 1 Avenue de l' Atlantique, LP 915 Les Conquerants Z.A. de Courtaboeuf 2, F-91976 Les Ulis Cedex, FRANCE Phone: +33-(0)1-64862350 Fax: +33-(0)1-64862355 BARCELONA BRANCH OFFICE Barcelona Design Center Edificio Prima Sant Cugat Avda. Alcalde Barrils num. 64-68 E-08190 Sant Cugat del Valles, SPAIN Phone: +34-93-544-2490 Fax: +34-93-544-2491 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5812 Fax: +81-(0)42-587-5564 ED International Marketing Department Asia 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5814 Fax: +81-(0)42-587-5110 In pursuit of "Saving" Technology, Epson electronic devices. Our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers' dreams. Epson IS energy savings. S1C60N07 Technical Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/ First issue September, 1998 Printed March, 2001 in Japan M A