S1C60N07 - Epson Company - Datasheet.Directory

MF1129-02

Technical Manual

CMOS 4-BIT SINGLE CHIP MICROCOMPUTER

S1C60N07 Technical Hardware

S1C60N07

NOTICE

No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko

Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any

liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or

circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such

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products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from

the Ministry of International Trade and Industry or other approval from another government agency.

The information of the product number change

Configuration of product number

Devices

Comparison table between new and previous number

S1C60 Family processors

Starting April 1, 2001, the product number will be changed as listed below. To order from April 1,

2001 please use the new product number. For further information, please contact Epson sales

representative.

S1 C60N01 F0A01 Packing specification

Specification

Package (D: die form; F: QFP)

Model number

Model name (C: microcomputer, digital products)

Product classification (S1: semiconductor)

Development tools

S5U1 C60R08 D1 1Packing specification

Version (1: Version 1 ∗2)

Tool type (D1: Development Tool ∗1)

Corresponding model number (60R08: for S1C60R08)

Tool classification (C: microcomputer use)

Product classification

(S5U1: development tool for semiconductor products)

∗1: For details about tool types, see the tables below. (In some manuals, tool types are represented by one digit.)

∗2: Actual versions are not written in the manuals.

Previous No.

E0C6001

E0C6002

E0C6003

E0C6004

E0C6005

E0C6006

E0C6007

E0C6008

E0C6009

E0C6011

E0C6013

E0C6014

E0C60R08

New No.

S1C60N01

S1C60N02

S1C60N03

S1C60N04

S1C60N05

S1C60N06

S1C60N07

S1C60N08

S1C60N09

S1C60N11

S1C60N13

S1C60140

S1C60R08

S1C62 Family processors

Previous No.

E0C621A

E0C6215

E0C621C

E0C6S27

E0C6S37

E0C623A

E0C623E

E0C6S32

E0C6233

E0C6235

E0C623B

E0C6244

E0C624A

E0C6S46

New No.

S1C621A0

S1C62150

S1C621C0

S1C6S2N7

S1C6S3N7

S1C6N3A0

S1C6N3E0

S1C6S3N2

S1C62N33

S1C62N35

S1C6N3B0

S1C62440

S1C624A0

S1C6S460

Previous No.

E0C6247

E0C6248

E0C6S48

E0C624C

E0C6251

E0C6256

E0C6292

E0C6262

E0C6266

E0C6274

E0C6281

E0C6282

E0C62M2

E0C62T3

New No.

S1C62470

S1C62480

S1C6S480

S1C624C0

S1C62N51

S1C62560

S1C62920

S1C62N62

S1C62660

S1C62740

S1C62N81

S1C62N82

S1C62M20

S1C62T30

Comparison table between new and previous number of development tools

Development tools for the S1C60/62 Family

Previous No.

ASM62

DEV6001

DEV6002

DEV6003

DEV6004

DEV6005

DEV6006

DEV6007

DEV6008

DEV6009

DEV6011

DEV60R08

DEV621A

DEV621C

DEV623B

DEV6244

DEV624A

DEV624C

DEV6248

DEV6247

New No.

S5U1C62000A

S5U1C60N01D

S5U1C60N02D

S5U1C60N03D

S5U1C60N04D

S5U1C60N05D

S5U1C60N06D

S5U1C60N07D

S5U1C60N08D

S5U1C60N09D

S5U1C60N11D

S5U1C60R08D

S5U1C621A0D

S5U1C621C0D

S5U1C623B0D

S5U1C62440D

S5U1C624A0D

S5U1C624C0D

S5U1C62480D

S5U1C62470D

Previous No.

DEV6262

DEV6266

DEV6274

DEV6292

DEV62M2

DEV6233

DEV6235

DEV6251

DEV6256

DEV6281

DEV6282

DEV6S27

DEV6S32

DEV6S37

EVA6008

EVA6011

EVA621AR

EVA621C

EVA6237

EVA623A

New No.

S5U1C62620D

S5U1C62660D

S5U1C62740D

S5U1C62920D

S5U1C62M20D

S5U1C62N33D

S5U1C62N35D

S5U1C62N51D

S5U1C62560D

S5U1C62N81D

S5U1C62N82D

S5U1C6S2N7D

S5U1C6S3N2D

S5U1C6S3N7D

S5U1C60N08E

S5U1C60N11E

S5U1C621A0E2

S5U1C621C0E

S5U1C62N37E

S5U1C623A0E

Previous No.

EVA623B

EVA623E

EVA6247

EVA6248

EVA6251R

EVA6256

EVA6262

EVA6266

EVA6274

EVA6281

EVA6282

EVA62M1

EVA62T3

EVA6S27

EVA6S32R

ICE62R

KIT6003

KIT6004

KIT6007

New No.

S5U1C623B0E

S5U1C623E0E

S5U1C62470E

S5U1C62480E

S5U1C62N51E1

S5U1C62N56E

S5U1C62620E

S5U1C62660E

S5U1C62740E

S5U1C62N81E

S5U1C62N82E

S5U1C62M10E

S5U1C62T30E

S5U1C6S2N7E

S5U1C6S3N2E2

S5U1C62000H

S5U1C60N03K

S5U1C60N04K

S5U1C60N07K

CONTENTS

S1C60N07 TECHNICAL MANUAL EPSON i

CONTENTS

CHAPTER 1 OUTLINE .....................................................................................................1

1.1 Features.....................................................................................................................................................................1

1.2 Block Diagram.........................................................................................................................................................2

1.3 Pin Layout Diagram...............................................................................................................................................3

1.4 Pin Description........................................................................................................................................................3

CHAPTER 2 CPU AND BUILT-IN MEMORY......................................................................4

2.1 CPU and Instruction Set......................................................................................................................................4

2.2 Program Memory (ROM).....................................................................................................................................9

2.3 Data Memory (RAM).............................................................................................................................................9

CHAPTER 3 POWER SOURCE......................................................................................14

3.1 Power Supply System........................................................................................................................................14

3.2 Heavy Load Protection Mode.........................................................................................................................15

3.2.1 Control of heavy load protection mode....................................................................................15

3.2.2 Programming notes..........................................................................................................................15

3.3 CPU Operating Voltage Change....................................................................................................................16

CHAPTER 4 INITIAL RESET..........................................................................................17

4.1 Initial Reset Factors............................................................................................................................................17

4.1.1 Power-on reset circuit......................................................................................................................17

4.1.2 External initial reset by the #RESET terminal........................................................................17

4.1.3 External initial reset by simultaneous low level input of K00–K03 terminals.............18

4.1.4 Initial reset by watchdog timer......................................................................................................18

4.1.5 Internal register at initial resetting ...............................................................................................18

4.2 Watchdog Timer...................................................................................................................................................19

4.2.1 Configuration of watchdog timer..................................................................................................19

4.2.2 Control of watchdog timer..............................................................................................................19

4.2.3 Programming notes..........................................................................................................................19

CHAPTER 5 OSCILLATION CIRCUIT.............................................................................20

5.1 Configuration of Oscillation Circuit................................................................................................................20

5.2 OSC1 Oscillation Circuit....................................................................................................................................20

5.3 OSC3 Oscillation Circuit....................................................................................................................................21

5.4 Operating Voltage Change..............................................................................................................................22

5.5 Clock Frequency and Instruction Execution Time...................................................................................22

5.6 Control of Oscillation Circuit............................................................................................................................23

5.7 Programming Notes............................................................................................................................................25

CHAPTER 6 INPUT/OUTPUT PORTS.............................................................................26

6.1 Input Port (Kxx)....................................................................................................................................................26

6.1.1 Configuration of input ports...........................................................................................................26

6.1.2 Mask option .........................................................................................................................................26

6.1.3 Interrupt function...............................................................................................................................26

6.1.4 Control of input ports.......................................................................................................................27

6.1.5 Programming notes..........................................................................................................................28

CONTENTS

ii EPSON S1C60N07 TECHNICAL MANUAL

6.2 Output Port (Rxx) .................................................................................................................................................29

6.2.1 Configuration of output ports........................................................................................................29

6.2.2 Mask option .........................................................................................................................................29

6.2.3 High impedance control..................................................................................................................31

6.2.4 Control of output ports....................................................................................................................31

6.2.5 Programming notes..........................................................................................................................32

6.3 I/O Port (Pxx)........................................................................................................................................................33

6.3.1 Configuration of I/O ports...............................................................................................................33

6.3.2 Mask option .........................................................................................................................................33

6.3.3 I/O control register and input/output mode.............................................................................33

6.3.4 Pull up resistor ...................................................................................................................................33

6.3.5 Control of I/O ports...........................................................................................................................34

6.3.6 Programming notes..........................................................................................................................35

CHAPTER 7 LCD DRIVER.............................................................................................36

7.1 Drive Duty...............................................................................................................................................................36

7.2 Mask Option..........................................................................................................................................................39

7.3 Display Data Memory.........................................................................................................................................39

7.4 Control of LCD Driver.........................................................................................................................................40

7.5 Programming Note..............................................................................................................................................41

CHAPTER 8 TIMERS..................................................................................................... 42

8.1 Clock Timer............................................................................................................................................................42

8.1.1 Configuration of clock timer...........................................................................................................42

8.1.2 Interrupt function...............................................................................................................................42

8.1.3 Control of clock timer.......................................................................................................................43

8.1.4 Programming notes..........................................................................................................................44

8.2 Stopwatch Timer..................................................................................................................................................45

8.2.1 Configuration of stopwa tch timer................................................................................................45

8.2.2 Count-up pattern...............................................................................................................................45

8.2.3 Interrupt function...............................................................................................................................46

8.2.4 Control of stopwatch timer.............................................................................................................47

8.2.5 Programming notes..........................................................................................................................48

8.3 Programmable Timer..........................................................................................................................................49

8.3.1 Configuration of programmable timer........................................................................................49

8.3.2 Interrupt function...............................................................................................................................50

8.3.3 Control of programmable timer ....................................................................................................51

8.3.4 Programming notes..........................................................................................................................53

CHAPTER 9 SOUND GENERATOR ...............................................................................54

9.1 Configuration of Sound Generator................................................................................................................54

9.2 Mask Option..........................................................................................................................................................54

9.3 Frequency Setting...............................................................................................................................................55

9.4 Digital Envelope...................................................................................................................................................55

9.5 1-shot Output........................................................................................................................................................56

9.6 Control of Sound Generator............................................................................................................................57

9.7 Programming Notes............................................................................................................................................59

CHAPTER 10 INTERRUPT AND HALT...........................................................................60

10.1 Interrupt Factor Flag and Interrupt Mask..................................................................................................61

10.2 Interrupt Vector..................................................................................................................................................62

10.3 Programming Notes.........................................................................................................................................62

CONTENTS

S1C60N07 TECHNICAL MANUAL EPSON iii

CHAPTER 11 SUMMARY OF NOTES.............................................................................64

11.1 Notes for Low Current Consumption..........................................................................................................64

11.2 Summary of Notes by Function....................................................................................................................65

11.3 Precautions on Mounting...............................................................................................................................69

CHAPTER 12 BASIC EX TERNAL CONNECTION DIAGRAM...........................................71

CHAPTER 13 ELECTRICAL CHARACTERISTICS..........................................................72

13.1 Absolute Maximum Rating.............................................................................................................................72

13.2 Recommended Operating Conditions.......................................................................................................72

13.3 DC Characteristics............................................................................................................................................72

13.4 Analog Circuit Characteristics and Consumed Current......................................................................73

13.5 AC Characteristics............................................................................................................................................74

13.6 Oscillation Characteristics..............................................................................................................................75

CHAPTER 14 PACKAGE ...............................................................................................77

14.1 Plastic Package.................................................................................................................................................77

14.2 Ceramic Package for Test Samples..........................................................................................................78

CHAPTER 15 PAD LAYOUT ..........................................................................................79

15.1 Diagram of Pad Layout...................................................................................................................................79

15.2 Pad Coordinates...............................................................................................................................................80

CHAPTER 1: OUTLINE

S1C60N07 TECHNICAL MANUAL EPSON 1

CHAPTER 1 OUTLINE

The S1C60N07 is a microcomputer with a C-MOS 4-bit core CPU S1C6200C as main

component, and ROM, RAM, dot matrix LCD driver, time base counter and other circuits built-in.

1.1 Features

Oscillation circuit........................OSC1: 32.768 kHz (Typ.) Crystal or CR oscillation circuit (∗1)

OSC3: 2 MHz (Max.) CR or ceramic oscillation circuit (∗1)

Instruction set................................108 types

Instruction execution time.......32.768 kHz: 152.6 µsec 213.6 µsec 366.2 µsec

1 MHz: 5.0 µsec 7.0 µsec 12.0 µsec

2 MHz: 2.5 µsec 3.5 µsec 6.0 µsec

ROM capacity...............................4,096 words × 12 bits

RAM capacity................................Data memory: 512 words × 4 bits

Display memory: 160 words × 4 bits

Input port .........................................4 b i t s ( P u ll-up resistors may be supplemented ∗1)

Output port.....................................6 b i t s ( Buzzer and clock outputs are possible ∗1)

I/O port.............................................4 b i t s

Dot matrix type LCD driver..40 segments × 16 or 8 commons (∗2)

Time base counter.......................Clock timer, stopwatch timer

Programmable timer..................8-bit timer × 1 ch., with event counter and clock output functions

Watchdog timer............................Built-in

Sound generator ...........................8 p r o g r ammable sounds (8 types of frequency)

with envelope and 1-shot output functions

External interrupt.......................Input port interrupt: 1 system

Internal interrupt .........................Clock timer interrupt: 1 system

Stopwatch timer interrupt: 1 system

Programmable timer interrupt: 1 system

Power supply voltage .................2.2 V to 5.5 V (Min. 1.8 V when the OSC3 oscillation circuit is not used)

Current consumption (Typ.) ...During HAL T: 32.768 kHz (crystal oscillation), 3.0 V 2.5 µA

During operation: 32.768 kHz (crystal oscillation), 3.0 V 6.5 µA

2 MHz (CR oscillation), 3.0 V 1 mA

Package.............................................QFP15-100pin (plastic) or chip

∗1: Can be selected with mask option ∗2: Can be selected with software

CHAPTER 1: OUTLINE

2EPSON S1C60N07 TECHNICAL MANUAL

1.2 Block Diagram

OSC1

OSC2

OSC3

OSC4

COM0–15

SEG0–39

VDD

VL1–VL5

CA–CF

VREF

VS1

VSS

R32

R33(PTCLK)

R40(#FOUT)

R41

R42(#BZ/FOUT)

R43(BZ)

K00–K03

#TEST

#RESET

P00–P03

Core CPU S1C6200C

ROM

4,096 words × 12 bits System Reset

Control

Interrupt

Generator

RAM

512 words × 4 bits

OSC

LCD Driver

40 SEG × 16 COM

Power

Controller

Sound

Generator

Output Port

Clock Timer

Watchdog Timer

Stopwatch

Timer

Programmable

Timer/Counter

Input Port

I/O Port

Fig. 1.2.1 Block diagram

CHAPTER 1: OUTLINE

S1C60N07 TECHNICAL MANUAL EPSON 3

1.3 Pin Layout Diagram

No.

Pin name

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM9

COM10

COM11

COM12

COM13

COM14

COM15

N.C.

No.

Pin name

N.C.

SEG39

SEG38

SEG37

SEG36

SEG35

SEG34

SEG33

SEG32

SEG31

SEG30

SEG29

SEG28

SEG27

SEG26

SEG25

SEG24

SEG23

SEG22

SEG21

SEG20

SEG19

SEG18

SEG17

SEG16

No.

Pin name

N.C.

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9

SEG8

SEG7

SEG6

SEG5

SEG4

SEG3

SEG2

SEG1

SEG0

K03

K02

K01

K00

P03

P02

P01

P00

No.

100

Pin name

N.C.

R43

R42

R41

R40

R33

R32

#RESET

#TEST

OSC4

OSC3

OSC2

OSC1

REF

N.C.

QFP15-100pin

N.C.: No Connection

5175

INDEX

251

100

Fig. 1.3.1 Pin layout diagram

1.4 Pin Description

Table 1.4.1 Pin description

Pin name

–V

REF

CA–CF

OSC1

OSC2

OSC3

OSC4

COM0–COM15

SEG0–SEG39

K00–K03

P00–P03

R32

R33

R40

R41

R42

R43

#RESET

#TEST

Function

Power supply (+)

Power supply (-)

Internal logic system/oscillation system regulated voltage output

LCD system power supply

1/4 bias generated internally, 1/5 bias generated externally ∗1

LCD system power test pin ∗2

LCD system voltage booster condenser connecting pin

Crystal or CR oscillator input ∗1

Crystal or CR oscillator output ∗1, C

buiil-in

CR or ceramic oscillator input ∗1

CR or ceramic oscillator output ∗1

LCD common output (1/8 duty or 1/16 duty is selected on software)

LCD segment output

Input port (pull up resistor is available by mask option) ∗1

I/O port

Output port

Output port or PTCLK output

Output port or #FOUT output ∗1

Output port

Output port, #BZ output or FOUT output ∗1

Output port or BZ output ∗1

Initial reset input terminal

Testing input terminal ∗3

Pin No.

95–97, 1, 2

8–3

9–24

67–52, 50–27

71–68

75–72

I/O

–

I/O

Complementary output

or Nch open drain

output ∗1

∗1

∗2

∗3

Selected by mask option

Leave the V

REF

pin unconnected (N.C.).

The #TEST pin is used when the IC load is being detected.

During ordinary operation be certain to connect this pin to V

CHAPTER 2: CPU AND BUILT-IN MEMORY

4EPSON S1C60N07 TECHNICAL MANUAL

CHAPTER 2 CPU AND BUILT-IN MEMORY

2.1 CPU and Instruction Set

The S1C60N07 uses the 4-bit core CPU S1C6200C for its CPU. It has almost the same register

configurations, instructions, and other features as the other family devices which use the

S1C6200/6200A/6200B, allowing full use of software assets. The instruction set of the S1C60N07 has

108 types of instructions, all consisting of one word (12 bits).

For detailed information on the CPU and the instruction set, refer to the "S1C6200/6200A Core CPU

Manual".

Note, however, that because S1C60N07 does not assume SLEEP operation, the SLP instruction is not

available in the S1C6200 instruction set.

The instruction list is shown in Tables 2.1.1(a) –(c).

The following lists the symbols used in the instruction list:

Symbols associated with registers and memory

AA register

BB register

XXHL register (low order eight bits of index r egister IX)

YYHL register (low order eight bits of index register IY)

XH XH register (high order four bits of XHL register)

XL XL register (low order four bits of XHL register)

YH YH register (high order four bits of YHL register)

YL YL register (low order four bits of YHL register)

XP XP register (high order four bits of index register IX)

YP YP register (high order four bits of index register IY)

SP Stack pointer SP

SPH High-order four bits of stack pointer SP

SPL Low-order four bits of stack pointer SP

MX, M(X) Data memory whose address is specified with index register IX

MY, M(Y) Data memory whose address is specified with index register IY

Mn, M(n) Data memory address 000H–00FH (address specified with immediate data n of 00H– 0FH)

M(SP) Data memory whose address is specified with stack pointer SP

r, q Two-bit register code

r, q is two-bit immediate data; according to the contents of these bits, they indicate registers A, B, and MX

and MY (data memory whose addresses are specified with index registers IX and IY)

r q Register

r1 r0 q1 q0 specified

0000 A

0101 B

1010 MX

1111 MY

Symbols associated with program counter

NBP New bank pointer

NPP New page pointer

PCB Program counter bank

PCP Program counter page

PCS Program counter step

PCSH Four high order bits of PCS

PCSL Four low order bits of PCS

CHAPTER 2: CPU AND BUILT-IN MEMORY

S1C60N07 TECHNICAL MANUAL EPSON 5

Symbols associated with flags

FFlag register (I, D, Z, C)

C Carry flag

ZZero flag

DDecimal flag

IInterrupt flag

↓Flag reset

↑Flag set

↕Flag set or reset

Associated with immediate data

pFive-bit immediate data or label 00H–1FH

sEight-bit immediate data or label 00H –0FFH

lEight-bit immediate data 00H –0FFH

iFour-bit immediate data 00H –0FH

Associated with arithmetic and other operations

+Add

-Subtract

∧Logical AND

∨Logical OR

∀Exclusive-OR

★Add-subtract instruction for decimal operation when the D flag is set

CHAPTER 2: CPU AND BUILT-IN MEMORY

6EPSON S1C60N07 TECHNICAL MANUAL

Table 2.1.1(a) Instruction sets (1)

C, s

NC, s

Z, s

NZ, s

X, x

Y, y

XP, r

XH, r

XL, r

YP, r

YH, r

YL, r

r, XP

r, XH

r, XL

r, YP

r, YH

r, YL

XH, i

XL, i

YH, i

YL, i

PSET

JPBA

CALL

CALZ

RET

RETS

RETD

NOP5

NOP7

HALT

INC

ADC

Branch

instructions

System

control

instructions

Index

operation

instructions

Classification Operand IDZC

↑

Clock

Operation Code Flag

NBP p4, NPP p3~p0

PCB NBP, PCP NPP, PCS s7~s0

PCB NBP, PCP NPP, PCS s7~s0 if C=1

PCB NBP, PCP NPP, PCS s7~s0 if C=0

PCB NBP, PCP NPP, PCS s7~s0 if Z=1

PCB NBP, PCP NPP, PCS s7~s0 if Z=0

←

←←

←

PCB NBP, PCP NPP, PCSH B, PCSL A

M(SP-1) PCP, M(SP-2) PCSH, M(SP-3) PCSL+1

SP SP-3, PCP NPP, PCS s7~s0

M(SP-1) PCP, M(SP-2) PCSH, M(SP-3) PCSL+1

SP SP-3, PCP 0, PCS s7~s0

PCSL M(SP), PCSH M(SP+1), PCP M(SP+2)

SP SP+3

PCSL M(SP), PCSH M(SP+1), PCP M(SP+2)

SP SP+3, PC PC+1

PCSL M(SP), PCSH M(SP+1), PCP M(SP+2)

SP SP+3, M(X) 3~ 0, M(X+1) 7~ 4, X X+2

No operation (5 clock cycles)

No operation (7 clock cycles)

Halt (stop clock)

X X+1

Y Y+1

XH x7~x4, XL x3~x0

YH y7~y4, YL y3~y0

r XP

r XH

r XL

r YP

r YH

r YL

←←

←←←

←←← ←←←

←←←

←←← ←

←← ←← ←

←←←←

←

←←

←

←←

←

Mne-

monic Operation

XH+i3~i0+C

XL+i3~i0+C

YH+i3~i0+C

YL+i3~i0+C

↓

l llllllll

ll ll

CHAPTER 2: CPU AND BUILT-IN MEMORY

S1C60N07 TECHNICAL MANUAL EPSON 7

Table 2.1.1(b) Instruction sets (2)

XH, i

XL, i

YH, i

YL, i

r, i

r, q

A, Mn

B, Mn

Mn, A

Mn, B

MX, i

r, q

MY, i

r, q

MX,

F, i

LDPX

LDPY

LBPX

SET

RST

SCF

RCF

SZF

RZF

SDF

RDF

INC

DEC

PUSH

POP

Index

operation

instructions

Data

transfer

instructions

Flag

operation

instructions

Stack

operation

instructions

Classification Operand IDZC

↑

↓

↑

↓

↑

↓

↑

↓

↑

↓

↑

↓

Clock

Operation Code Flag

XH-i3~i0

XL-i3~i0

YH-i3~i0

YL-i3~i0

r i3~i0

r q

M(n3~n0) A

M(n3~n0) B

M(X) i3~i0, X X+1

r q, X X+1

M(Y) i3~i0, Y Y+1

r q, Y Y+1

M(X) 3~ 0, M(X+1) 7~ 4, X X+2

←

←←

←

←← ←←

Mne-

monic Operation

↓

↑

↓

↑

↓

SP SP+1

SP SP-1

SP SP-1, M(SP) r

SP SP-1, M(SP) XP

SP SP-1, M(SP) XH

SP SP-1, M(SP) XL

SP SP-1, M(SP) YP

SP SP-1, M(SP) YH

SP SP-1, M(SP) YL

SP SP-1, M(SP) F

r M(SP), SP SP+1

←

M(n3~n0)

←

←←

←

F i3~i0

1 (Decimal Adjuster ON)

0 (Decimal Adjuster OFF)

1 (Enables Interrupt)

0 (Disables Interrupt)

←

←←

←

M(SP), SP SP+1

←

l llllllll l l l l

CHAPTER 2: CPU AND BUILT-IN MEMORY

8EPSON S1C60N07 TECHNICAL MANUAL

Table 2.1.1(c) Instruction sets (3)

d3 d2, d2 d1, d1 d0, d0 C, C d3

d3 C, d2 d3, d1 d2, d0 d1, C d0

M(n3~n0) M(n3~n0)+1

M(n3~n0) M(n3~n0)-1

↓

SPH, r

SPL, r

r, SPH

r, SPL

r, i

r, q

r, i

r, q

r, i

r, q

r, i

r, q

r, i

r, q

r, i

r, q

r, i

r, q

r, i

r, q

MX, r

MY, r

MX, r

MY, r

POP

ADD

ADC

SUB

SBC

AND

XOR

FAN

RLC

RRC

INC

DEC

ACPX

ACPY

SCPX

SCPY

NOT

Stack

operation

instructions

Arithmetic

instructions

Classification Operand IDZC

↑↑

↑

Clock

Operation Code Flag

F M(SP), SP SP+1

SPH

SPL

r SPH

r SPL

←

Mne-

monic Operation

↓

↑

←

↓↓

★

r r+i3~i0

r r+q

r r+i3~i0+C

r r+q+C

r r-q

r r-i3~i0-C

r r-q-C

r r i3~i0

r r q

r r i3~i0

r r q

r r i3~i0

r r q

r-i3~i0

r-q

r i3~i0

r q

M(X) M(X)+r+C, X X+1

M(Y) M(Y)+r+C, Y Y+1

M(X) M(X)-r-C, X X+1

M(Y) M(Y)-r-C, Y Y+1

r r

M(SP), SP SP+1

←

←←

←

←←← ←

←← ← ←←

←

CHAPTER 2: CPU AND BUILT-IN MEMORY

S1C60N07 TECHNICAL MANUAL EPSON 9

2.2 Program Memory (ROM)

The built-in ROM, a mask ROM for loading the program, has a capacity of 4,096 steps × 12 bits. The

program area consists of 16 (0–15) pages × 256 (00H –FFH) steps. After initial reset, the program

beginning address is set to bank 0, page 1, step 00H. The interrupt vector is allocated to page 1, steps

02H–0CH.

Bank 0

Step 00H

Step 02H

Step 0CH

Step 0DH

Step FFH

12 bits

Program start address

Interrupt vector

Page 0

Page 1

Page 2

Page 3

Page 4

Page 5

Page 6

Page 7

Page 8

Page 9

Page 10

Page 11

Page 12

Page 13

Page 14

Page 15

Fig. 2.2.1 Configuration of the built-in ROM

2.3 Data Memory (RAM)

The S1C60N07 built-in data memories are configured a general-purpose RAM, display data memory of

the LCD, and I/O data memory which controls the peripheral circuit.

General-purpose RAM:512 words × 4 bits (000H –1FFH)

Display data memory: 160 words × 4 bits (E00H–E4FH, E80H–ECFH)

I/O memory: 33 words × 4 bits (F00H–F7FH)

During programming, take note of the following:

(1) Since the stack area is taken from the RAM area, take care that destruction of stack data due to data

writing does not occur. Sub-routine calls or interrupts consume 3 words of the stack area.

(2) RAM address 000H –00FH are memory register areas that are addressed with register pointer RP.

The memory map of the built-in data memory (RAM) and details of the I/O data memory map are shown

in Figure 2.3.1 and Tables 2.3.1(a)–(c), respectively.

Note: Memory is not mounted in unused area within the memory map and in memory area not indicated in

this chapter. For this reason, normal operation cannot be assured for programs that have been

prepared with access to these areas.

CHAPTER 2: CPU AND BUILT-IN MEMORY

10 EPSON S1C60N07 TECHNICAL MANUAL

0 RAM (256 words × 4 bits)

R/W

Low

High

Address

Page 0 1 2 3 4 5 6 7 8 9 A B C D E F

M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF

1 RAM (256 words × 4 bits)

R/W

Display data memory (80 words × 4 bits)

R/W

Display data memory (80 words × 4 bits)

R/W

Low

High

Address

Page 0 1 2 3 4 5 6 7 8 9 A B C D E F

I/O memory

Unused area

Fig. 2.3.1 Memory map

CHAPTER 2: CPU AND BUILT-IN MEMORY

S1C60N07 TECHNICAL MANUAL EPSON 11

Table 2.3.1(a) I/O data memory map (1)

Address Comment

D3 D2 D1 D0 Name Init 1 0

F00H

IT32

IT1

IT2

IT8

IT32

Interrupt factor flag (clock timer 1 Hz)

Interrupt factor flag (clock timer 2 Hz)

Interrupt factor flag (clock timer 8 Hz)

Interrupt factor flag (clock timer 32 Hz)

Yes

IT8IT2IT1

F01H

ISW0

ISW1

ISW0

–

Interrupt factor flag (stopwatch 1 Hz)

Interrupt factor flag (stopwatch 10 Hz)

Yes

Yes No

ISW100

F02H

IPT

–

0Yes No

000

F04H

IK0

–

Interrupt factor flag (K00–K03)

Yes No

000

F10H

EIT32

R/W

EIT1

EIT2

EIT8

EIT32

Interrupt mask register (clock timer 1 Hz)

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

Enable

Mask

EIT8EIT2EIT1

F11H

EISW0

R/W

EISW1

EISW0

–

Interrupt mask register (stopwatch 1 Hz)

Interrupt mask register (stopwatch 10 Hz)

Enable

Enable Mask

Mask

EISW100

F12H

EIPT

R/W

EIPT

–

0Enable Mask

F14H

EIK00

R/W

EIK03

EIK02

EIK01

EIK00

Interrupt mask register (K03)

Interrupt mask register (K02)

Interrupt mask register (K01)

Interrupt mask register (K00)

Enable

Mask

EIK01EIK02EIK03

Interrupt factor flag (programmable timer)

Interrupt mask register (programmble timer)

F20H

TM0

TM3

TM2

TM1

TM0

Clock timer data (16 Hz)

Clock timer data (32 Hz)

Clock timer data (64 Hz)

Clock timer data (128 Hz)

TM1TM2TM3

F21H

TM7

TM6

TM5

TM4

Clock timer data (1 Hz)

Clock timer data (2 Hz)

Clock timer data (4 Hz)

Clock timer data (8 Hz)

TM4TM5TM6TM7

F22H

SWL3

SWL2

SWL1

SWL0

F23H

SWH0

SWH3

SWH2

SWH1

SWH0

SWH1SWH2SWH3

F24H

PT0

PT3

PT2

PT1

PT0

PT1PT2PT3

F25H

PT4

PT7

PT6

PT5

PT4

PT5PT6PT7

SWL0SWL1SWL2SWL3

Stopwatch timer

1/100 sec data (BCD)

MSB

LSB

Stopwatch timer

1/10 sec data (BCD)

MSB

LSB

Programmable timer data (low-order)

MSB

LSB

Programmable timer data (high-order)

MSB

LSB

∗1 Initial value following initial reset ∗2 Not set in the circuit

∗3 Reset (0) immediately after being read ∗4 Always "0" when being read

∗5 Undefined

CHAPTER 2: CPU AND BUILT-IN MEMORY

12 EPSON S1C60N07 TECHNICAL MANUAL

Table 2.3.1(b) I/O data memory map (2)

Address Comment

D3 D2 D1 D0 Name Init 1 0

F26H

RD0

R/W

RD3

RD2

RD1

RD0

RD1RD2RD3

F27H

RD4

R/W

RD7

RD6

RD5

RD4

RD5RD6RD7

F40H

K00

K03

K02

K01

K00

–

High

Low

K01

K02

K03

Programmable timer

reload data (low-order)

MSB

LSB

Programmable timer

reload data (high-order)

MSB

LSB

Input port (K00–K03)

F60H

P00

R/W

P03

P02

P01

P00

I/O port (P00–P03)

High

Low

P01P02P03

F70H

VSC0 CLKCHG

OSCC

VSC1

VSC0

CPU system clock switch

OSC3 oscillation On/Off

OSC3

VSC1OSCCCLKCHG

F71H

HLMOD

R/W

ALOFF

ALON

LDUTY

HLMOD

All LCD dots fade out control

All LCD dots displayed control

LCD drive duty switch

Heavy load protection mode

All off

All on

1/8

HLMOD

Normal

1/16

Normal

LDUTYALONALOFF

F72H

LC0 LC3

LC2

LC1

LC0

LC1LC2LC3

F74H

BZFQ0

R/W

SHOTPW

BZFQ2

BZFQ1

BZFQ0

1-shot buzzer pulse width

62.5 ms 31.25 ms

BZFQ1BZFQ2SHOTPW

F75H

ENVON

BZSHOT

RESET

1-shot buzzer trigger (W)

Status (R)

Envelope reset

Envelope cycle selection

Envelope On/Off

Trigger

BUSY

Reset

1.0 sec

–

READY

–

0.5 sec

Off

ENVRTENVRSTBZSHOT

F76H

WDRST 0

TMRST

WDRST

–

Reset

Clock timer reset

Watchdog timer reset

Reset

Reset –

–

TMRST00

F77H

SWRST

SWRUN

–

Reset

Stopwatch timer reset

Stopwatch timer Run/Stop

Reset

Run –

Stop

WR/W

ENVRST

ENVRT

ENVON

SWRUN

R/W

SWRST

CPU operating voltage switch

OSC1

Off

LCD contrast adjustment

LC3–LC0 = 0 light

LC3–LC0 = 15 dark

Buzzer frequency selection

R/W

F53H

R/W R

–

Output port (R33)

PTCLK output

Output port (R32)

High

Off

High

Low

0R32R33

F54H

R40

R/W

R43

R42

R41

R40

Output port (R43)

Buzzer output (BZ)

Output port (R42)

Clock output (FOUT)

[Buzzer inverted output (#BZ)]

Output port (R41)

Output port (R40)

Clock inverted output (#FOUT)

High

Off

High

Off

High

Off

Low

R41R42R43

R33

R32

∗1 Initial value following initial reset ∗2 Not set in the circuit

∗3 Reset (0) immediately after being read ∗4 Always "0" when being read ∗5 Undefined

∗6 When selecting options enclosed in brackets [ ] as output option, the output register will function as register only

and will not affect the individual outputs.

CHAPTER 2: CPU AND BUILT-IN MEMORY

S1C60N07 TECHNICAL MANUAL EPSON 13

Table 2.3.1(c) I/O data memory map (3)

Address Comment

D3 D2 D1 D0 Name Init 1 0

F78H

PTRST

PTRUN

–

Reset

Programmable timer reset

Programmable timer Run/Stop

Reset

Run –

Stop

F79H

PTC0

R/W

PTCOUT

PTC2

PTC1

PTC0

Programmable timer clock output

On Off

PTC1PTC2PTCOUT

Programmable timer input clock selection

PTRUN

R/W

PTRST

F7DH

IOC0

RR/W

IOC0

–

I/O control (P00–P03)

Output Input

000

F7EH

PUP0 0

PUP0

–

I/O pull up resistor On/Off (P00–P03)

Off On

000

F7BH

R/W R

HZR3

–

R32–R33 output high-impedance control

Output High-Z

00HZR3

RR/W

F7FH

LCDOFF 0

LCDOFF

–

LCD display control

Normal Off

000

∗1 Initial value following initial reset ∗2 Not set in the circuit

∗3 Reset (0) immediately after being read ∗4 Always "0" when being read

∗5 Undefined

CHAPTER 3: POWER SOURCE

14 EPSON S1C60N07 TECHNICAL MANUAL

CHAPTER 3 POWER SOURCE

3.1 Power Supply System

The S1C60N07 operating power voltage is as follows:

2.2– 5.5 V (Min. 1.8 V, when OSC3 oscillation circuit is not used)

The S1C60N07 operates when a single power supply within the above range is applied between VDD and

VSS. Even if the voltage is not within the above range necessary for the internal circuits, the IC itself can

generate the following built-in power circuits.

Table 3.1.1 Power supply circuits

Circuit Power supply circuit Output voltage

Oscillation circuit and internal circuits Regulated voltage circuit V S1

LCD driver LCD system voltage circuit VL1–VL5

Notes: • VL3 is used only when the driving voltage of the LCD system will be supplied externally (1/5

bias); when using the internal LCD system voltage circuit (1/4 bias), it should be shorted with

VL2.

• See "13 Electrical Characteristics" for voltage values.

External

power

supply

Internal

circuit

Oscillation

circuit

LCD

driver

LCD system

voltage

circuit

Regulated voltage

circuit

VDD

VL1

VL3

VL4

VSS

–VL5

OSC1–4

COM0–15

SEG0–39

S1 S1

VL5

VL1

VL2

Fig. 3.1.1 Configuration of power supply

CHAPTER 3: POWER SOURCE

S1C60N07 TECHNICAL MANUAL EPSON 15

3.2 Heavy Load Protection Mode

Because the load of the battery in the S1C60N07 becomes heavy due to the buzzer, lamp, and other

features, it has been equipped with heavy load protection function in case of power voltage drop. This

functions works in the heavy load protection mode.

Based on the workings of the heavy load protection function, the S1C60N07 realizes operation at 2.2 V

(Min. 1.8 V, when OSC3 oscillation circuit is not used) source voltage.

When driving heavy loads, set the IC to heavy load protection mode.

At the normal mode, the LCD system regulated voltage is created with VL2; VL1 is 1/2 reduced VL2

voltage while VL4 and VL5 are created by boosting to 1.5 and 2 times voltages, respectively. On the other

hand, at the heavy load protection mode, the regulated voltage is VL1; VL2, VL4, and VL5 are created by

boosting to 2, 3 and 4 times voltages. Because of this, the consumed current becomes greater than that in

the normal mode, be careful not to set t he heavy load protection unless necessary.

The LCD system voltage modes are shown in Table 3.2.1.

Table 3.2.1 LCD system voltage mode

Terminal Normal mode Heavy load protection mode

VL1 1/2 V L2 VL1 regulated voltage

VL2 VL2 regulated voltage 2 V L1

VL4 3/2 V L2 3 VL1

VL5 4/2 V L2 4 VL1

3.2.1 Control of heavy load protection mode

The control register for the heavy load protection mode are explained below.

Table 3.2.1.1 Control register for heavy load protection mode

Address Comment

D3 D2 D1 D0 Name Init 1 0

F71H

HLMOD

R/W

ALOFF

ALON

LDUTY

HLMOD

All LCD dots fade out control

All LCD dots displayed control

LCD drive duty switch

Heavy load protection mode

All off

All on

1/8

HLMOD

Normal

1/16

Normal

LDUTYALONALOFF

HLMOD (F71H [D0], R/W)

Controls the heavy load protection mode.

When "1" is written: Heavy load protection mode is set

When "0" is written: Heavy load protection mode is released

Reading: Valid

Conversion to heavy load protection mode is done by writing "1" to HLMOD while cancellation of this

mode is done by writing "0".

At initial reset, the mode is set to "0" (heavy load protection mode cancellation).

3.2.2 Programming notes

(1) When driving heavy loads, set it to heavy load protection mode. Unless it is necessary, be careful not

to set the heavy load protection mode with the software.

(2) Perform heavy load driving only after setting up at least 1 ms wait time through the software, after

switching to the heavy load protection mode. (See Figure 3.2.2.1.)

(3) When the heavy load protection mode is to canceled after completion of heavy load driving, set up at

least 2 seconds wait time through the software. (See Figure 3.2.2.1.)

CHAPTER 3: POWER SOURCE

16 EPSON S1C60N07 TECHNICAL MANUAL

OFF

1 ms or more 2 sec or more

Heavy load

protection mode

Fig. 3.2.2.1 Control timing for heavy load protection mode

3.3 CPU Operating Voltage Change

During operation, S1C60N07 can change OSC1 and OSC3 system clocks through the software, and

operation at clock mode or high-speed mode is then possible. In this case, to obtain stable operating,

operating voltage VS1 of the internal circuit is changed through the software. For details, see Chapter 5,

"Oscillation Circuit".

CHAPTER 4: INITIAL RESET

S1C60N07 TECHNICAL MANUAL EPSON 17

CHAPTER 4 INITIAL RESET

4.1 Initial Reset Factors

The S1C60N07 requires initial reset function to initialize the circuits.

There are three types of initial reset factors:

(1) Initial reset by power-on reset

(2) External reset through low level input to the #RESET terminal

(3) External initial reset by simultaneous low level input of K00–K03 terminals (mask option)

(4) Initial reset by watchdog timer

Note: The S1C60N07 must be reset after turning power on using the initial reset factor (1) or (2).

Figure 4.1.1 shows the configuration of the initial reset circuit.

#RESET

K00

K01

K02

K03

OSC2

OSC1 OSC1

oscillation

circuit

Time

authorize

circuit

Noise

rejector Internal

initial

reset

VDD

Watchdog

timer

VDD

Mask option

Power-on

reset circuit

Fig. 4.1.1 Configuration of initial reset circuit

4.1.1 Power-on reset circuit

The power-on reset circuit outputs the initial reset signal at power-on until the oscillation circuit starts

oscillating.

Note: The power-on reset circuit may not work properly due to unstable or lower voltage input.

The following two initial reset method are recommended to generate the initial reset signal.

4.1.2 External initial reset by the #RESET terminal

An initial reset can be executed externally by setting the reset terminal to low level. This low level must

be maintained for at least 2 ms (in case oscillation frequency fOSC1 = 32.768 kHz), because the initial reset

circuit contains a noise rejector. When the reset terminal goes high, the CPU will start operating.

CHAPTER 4: INITIAL RESET

18 EPSON S1C60N07 TECHNICAL MANUAL

4.1.3 External initial reset by simultaneous low level input of K00–K03 terminals

Initial reset may be done by simultaneously providing low level input externally to the input port (K00–

K03) selected by mask option. Because the initial reset circuit has time authorize circuit built-in, keep the

specified input port terminal at Low level for at least 2 seconds (in case oscillation frequency fOSC1 =

32.768 kHz). The input port combination which can be selected from the mask option are as follows:

• Not use

• K00∗K01

• K00∗K01∗K02

• K00∗K01∗K02∗K03

4.1.4 Initial reset by watchdog timer

If the CPU runs away for some reason, the watchdog timer will detect this situation and output an initial

reset signal. See "4.2 Watchdog Timer" for details.

4.1.5 Internal register at initial resetting

The CPU is initialized by initial resetting as follows:

Table 4.1.5.1 Initial values

Name

Program counter step

Program counter page

Program counter bank

New page pointer

New bank pointer

Stack pointer

Index register X

Index register Y

General-purpose register A

General-purpose register B

Interrupt flag

Decimal flag

Zero flag

Carry flag

CPU Core

Symbol

PCS

PCP

PCB

NPP

NBP

Bit size

Initial value

00H

Undefined

Name

RAM

Display memory

Other peripheral circuits

Peripheral Circuits

Bit size

512 × 4

160 × 4

–

Initial value

Undefined

∗

∗ See Tables 2.3.1(a)– (c).

CHAPTER 4: INITIAL RESET

S1C60N07 TECHNICAL MANUAL EPSON 19

4.2 Watchdog Timer

4.2.1 Configuration of watchdog timer

S1C60N07 has a built-in watchdog timer with OSC1 (clock timer 1 Hz signal) basic oscillation. The

watchdog timer needs to be reset periodically through the software, and if not reset within 3–4 seconds, it

automatically generates an initial reset signal to the CPU.

Figure 4.2.1.1 shows the configuration of the watchdog timer.

Clock timer

TM0–TM7

1 Hz Watchdog timer Initial reset signal

OSC1 demultiplier

(256 Hz)

Watchdog timer

reset signal

Fig. 4.2.1.1 Configuration of watchdog timer

By resetting the watchdog timer during the program's main routine, program runaways which do not pass

the watchdog timer processing during main routine can be detected.

Note, however, that the watchdog timer operates even during HALT such that if the HALT condition

continues for 3–4 seconds, it is re-initiated through initial resetting.

4.2.2 Control of watchdog timer

The control register of the watchdog timer is explained below.

Table 4.2.2.1 Control register of watchdog timer

Address Comment

D3 D2 D1 D0 Name Init 1 0

F76H

WDRST 0

TMRST

WDRST

–

Reset

Clock timer reset

Watchdog timer reset

Reset

Reset –

–

TMRST00

WDRST (F7 6H [D0], W)

This bit resets the watchdog timer.

When "1" is written: Watchdog timer reset

When "0" is written: No operation

Reading: Always "0"

By writing "1" on WDRST, the watchdog timer is reset, after which it is immediately restarted. Writing

"0" will mean no operation.

Because this bit is only for writing, it is always set to "0" during reading.

4.2.3 Programming notes

(1) The watchdog timer must reset within 3-second cycles by the software.

(2) When the clock timer is reset (TMRST ← "1"), the watchdog timer is counted up; reset the watchdog

immediately after if necessary.

CHAPTER 5: OSCILLATION CIRCUIT

20 EPSON S1C60N07 TECHNICAL MANUAL

CHAPTER 5 OSCILLATION CIRCUIT

5.1 Configuration of Oscillation Circuit

The S1C60N07 has two oscillation circuits (OSC1 and OSC3). OSC1 is either a crystal or a CR

oscillation circuit that supplies the operating clock to the CPU and peripheral circuits. OSC3 is either a

CR or a ceramic oscillation circuit. When processing with the S1C60N07 requires high-speed operation,

the CPU operating clock can be switched from OSC1 to OSC3 by the software. To stabilize operation of

the internal circuits, the operating voltage VS1 must be switched according to the oscillation circuit to be

used. Figure 5.1.1 is the block diagram of this oscillation system.

Oscillation circuit control signal

CPU clock selection signal

To CPU

To peripheral

circuits

Clock

switch

OSC1

oscillation circuit

OSC3

oscillation circuit

Oscillation system

voltage regulator Operating voltage selection signal

VS1

Divider

Fig. 5.1.1 Oscillation system block diagram

5.2 OSC1 Oscillation Circuit

The OSC1 oscillation circuit generates the main clock for the CPU and the peripheral circuits. Either the

crystal oscillation circuit or the CR oscillation circuit can be selected as the circuit type by mask option.

Figure 5.2.1 shows the configuration of the OSC1 oscillation circuit.

OSC2

OSC1

X'tal

To CPU and

peripheral circuit

Rfx

(1) Crystal oscillation circuit

OSC2

OSC1 To CPU and

peripheral circuit

CR1

(2) CR oscillation circuit

Fig. 5.2.1 OSC1 oscillation circuit

As shown in Figure 5.2.1, the c rystal oscillation circuit can be configured simply by connecting the crystal

oscillator (X'tal) of 32.768 kHz (Typ.) and the feedback resistor Rfx (10 MΩ) between the OSC1 and

OSC2 terminals and the trimmer capacitor (CGX) between the OSC1 and VDD termina ls when crystal

oscillation is selected.

When CR oscillation is selected by mask option, connect the resistor RCR1 between the OSC1 and OSC2

terminals. See "13 Electrical Characteristics" for resistance value of RCR1.

Notes: • The current consumption of CR oscillation is larger than crystal oscillation.

• Be aware that the CR oscillation frequency changes slightly.

Pay special attention to the circuits that use fOSC1 as the source clock, such as the timer (time

lag), the LCD frame frequency (display quality, flicker in low frequency) and the sound

generator (sound quality).

CHAPTER 5: OSCILLATION CIRCUIT

S1C60N07 TECHNICAL MANUAL EPSON 21

5.3 OSC3 Oscillation Circuit

The S1C60N07 has built-in the OSC3 oscillation circuit that generates the CPU's sub-clock (Max. 2

MHz) for high speed operation. The mask option enables selection of either the CR or ceramic oscillation

circuit. When CR oscillation is selected, only a resistance is required as an external element. When

ceramic oscillation is selected, a ceramic oscillator and two capacitors (gate and drain capacitance) are

required.

Figure 5.3.1 shows the configuration of the OSC3 oscillation circuit.

OSC4

OSC3

CR2

Oscillation circuit control signal

To CPU

and SIO

(1) CR oscillation circuit

OSC4

OSC3

Ceramic

Rfc

Oscillation circuit control signal

To CPU

and SIO

(2) Ceramic oscillation circuit

Fig. 5.3.1 OSC3 oscillation circuit

As shown in Figure 5.3.1, the CR oscillation circuit can be configu red simply by connecting the resistor

RCR2 between the OSC3 and OSC4 terminals when CR oscillation is selected. See "13 Electrical

Characteristics" for resistance value of RCR2.

When ceramic oscillation is selected, the ceramic oscillation circuit can be configured by connecting the

ceramic oscillator (Max. 2 MHz) and feedback resistor Rfc (about 1 MΩ) between the OSC3 and OSC4

terminals, capacitor CGC between the OSC3 and OSC4 terminals, and capacitor CDC between the OSC4

and VDD terminals. For both C GC and C DC, connect capacitors that are about 100 pF. To reduce current

consumption of the OSC3 oscillation circuit, oscillation can be stopped by the software (OSCC register).

When the OSC3 oscillation circuit is not used, connect the OSC3 terminal to VS1.

VDD

OSC3

VS1

Fig. 5.3.2 Connection diagram when the OSC3 oscillation circuit is unused

CHAPTER 5: OSCILLATION CIRCUIT

22 EPSON S1C60N07 TECHNICAL MANUAL

5.4 Operating Voltage Change

S1C60N07 can change OSC1 and OSC3 system clocks through the software. In this case, to obtain stable

operation, operating voltage VS1 of the internal circuit is changed through the software.

Likewise, when selecting OSC1 as the system clock, there is need to change operating voltage VS1

according to the value of the power voltage (V DD–VSS).

Oscillation frequency and the corresponding operating voltage VS1 are shown in Table 5.4.1.

Table 5.4.1 Oscillation frequency and operating voltage

Oscillation frequency Oscillation circuit Operating voltage VS1

32.768 kHz OSC1 -1.2 V or -2.1 V

1 MHz OSC3 -2.1 V

2 MHz OSC3 -3.0 V

The VDD reference voltage is used as the operating voltage VS1.

When OSC3 is to be used as the CPU system clock, change the operating voltage V S1 accordingly through

the software and then turn the OSC3 oscillation ON and switch the clock frequency.

If the OSC3 oscillation frequency is to be fixed around 1 MHz, set the operating voltage to -2.1 V; at 2

MHz, set the operating voltage to -3.0 V.

Moreover, when the CPU is to be operated with OSC1, set the operating voltage to -1.2 V if the power

voltage is less than 3.1 V (VDD–VSS < 3.1 V) ; set the operating voltage to -2.1 V if the voltage is 3.1 V or

more (VDD–VSS ≥ 3.1 V). However, it can be used fixed at -1.2 V (at OSC1 operation) for power whose

initial value is 3.6 V or less as in lithium batteries.

Note: Switching VS1 when the power source voltage is lower than the set voltage may cause

misoperation.

5.5 Clock Frequency and Instruction Execution Time

Table 5.5.1 shows the instruction execution time according to each frequency of the system clock.

Table 5.5.1 Clock frequency and instruction execution time

Clock frequency Instruction execution time (µs)

5-clock instruction 7-clock instruction 12-clock instruction

32.768 kHz 152.6 213.6 366.2

1 MHz 5.0 7.0 12.0

2 MHz 2.5 3.5 6.0

CHAPTER 5: OSCILLATION CIRCUIT

S1C60N07 TECHNICAL MANUAL EPSON 23

5.6 Control of Oscillation Circuit

The control registers for the oscillation circuit are explained below.

Table 5.6.1 Control registers of oscillation circuit

Address Comment

D3 D2 D1 D0 Name Init 1 0

F70H

VSC0 CLKCHG

OSCC

VSC1

VSC0

CPU system clock switch

OSC3 oscillation On/Off

OSC3

VSC1OSCCCLKCHG

CPU operating voltage switch

OSC1

Off

R/W

VSC0 and VSC1 (F70H [D0 and D1], R/W)

Switches the operating voltage of the internal circuit in accordance to the oscillation frequency and power

source voltage.

The corresponding setting description is shown in Table 5.6.2.

Table 5.6.2 Corresponding between oscillation frequency, power source voltage, and operating voltage (VS1)

VSC1 VSC0 VS1 Oscillation circuit Oscillation frequency Power source voltage (VDD–VSS)

0 0 -1.2 V OSC1 32.768 kHz Under 3.1 V

0 1 -2.1 V OSC1 32.768 kHz 3.1 V or more (∗)

0 1 -2.1 V OSC3 1 MHz 2.2 V or more

1×-3.0 V OSC3 2 MHz 3.1 V or more

The VDD reference voltage is used as the operating voltage VS1.

There is no need to set the (∗) state with regards to power whose initial value is 3.6 V or less as in lithium

batteries.

VSC1 and VSC0 are set to "0" at initial reset.

Notes: •When switching VS1 from -1.2 V (for OSC1 crystal oscillation circuit) to -3.0 V (for OSC3

oscillation circuit), or vice versa, be sure to hold the -2.1 V setting for more than 5 ms first for

power voltage stabilization.

(VSC1, VSC0)= (0, 0)→ (0, 1) → 5 ms WAIT → (1, ×)

= (1, ×)→ (0, 1) → 5 ms WAIT → (0, 0)

= (0, 0)→ (1, ×) is prohibited

= (1, ×)→ (0, 0) is prohibited

•When CR oscillation has been selected by the mask option as OSC1, VS1 becomes -2.1 V

even when VSC1 = VSC0 = 0 and will never become -1.2 V. In addition, since the current

consumption is great for CR oscillation compared with the quartz crystal oscillation, when low

power consumption is required, you should select quartz crystal oscillation as OSC1.

OSCC (F70H [D2], R/W)

Controls the oscillation of the OSC3 oscillation circuit.

When "1" is written: OSC3 oscillation ON

When "0" is written: OSC3 oscillation OFF

Reading: Valid

When high-speed operation of the CPU is required, OSCC is set to "1"; otherwise, set it to "0" to

minimize power current consumption.

At initial reset, OSCC is set to "0".

Note: It takes 5 ms for the OSC3 oscillation circuit to stabilize after oscillation turns ON. Since oscillation

stabilization time differs according to external oscillation terminal and usage conditions, set the

stand-by time with enough allowance when switching the clock frequency.

CHAPTER 5: OSCILLATION CIRCUIT

24 EPSON S1C60N07 TECHNICAL MANUAL

CLKCHG (F70H [D3], R/W)

Selects the CPU operating clock.

When "1" is written: OSC3 clock is selected

When "0" is written: OSC1 clock is selected

Reading: Valid

When assigning OSC3 as the CPU operating clock, set CLKCHG to "1"; when assigning OSC1, set it to

"0".

At initial reset, CLKCHG is set to "0".

Note: When switching the CPU operating clock from OSC1 to OSC3, follow the flow chart shown in

Figure 5.6.1 and then proceed with software processing.

CLK CHG

to -2.1 V

CLK CHG

OSC3

oscillation ON

5 ms WAIT

CLK

OSC1→OSC3

OSC3>500 kHz

5 ms WAIT

CLK

OSC1→OSC3

= -2.1 V, OSC3 = 1 MHz (stabilized)

= -3.0 V, OSC3 = 2 MHz (stabilized)

S1V

S1Set V

S1VS1V

OSC3

oscillation ON

= -1.2 V

to -3.0 VS1Set V

Condition:

DD < -3.1 V Condition:

– VSS

Fig. 5.6.1 CPU operating clock control flow

CHAPTER 5: OSCILLATION CIRCUIT

S1C60N07 TECHNICAL MANUAL EPSON 25

5.7 Programming Notes

(1) When high-speed operation of the CPU is not required, observe the following reminders to minimize

power current consumption.

Set the CPU operating clock to OSC1.

Turn the OSC3 oscillation OFF.

Set the internal operating voltage (VS1) to -1.2 V or -2.1 V.

(2) When the CPU is to be operated with OSC1, set the operating voltage to -1.2 V if the power voltage is

less than 3.1 V (VDD–VSS < 3.1 V); set the operating voltage to -2.1 V if the voltage is 3.1 V or more

(VDD–VSS ≥ 3.1 V). Moreover, because -1.2 V will be set during initial reset, be sure to execute the

previous process at the beginning of the initial routine. Note, however, that it can be used fixed at 1.2

V (at OSC1 operation) for power whose initial value is 3.6 V or less as in lithium batteries.

(3) When switching VS1 from -1.2 V (for OSC1 crystal oscillation circuit) to -3.0 V (for OSC3 oscillation

circuit), or vice versa, be sure to hold the -2.1 V setting for more than 5 ms first for power voltage

stabilization.

(VSC1, VSC0) = (0, 0) → (0, 1) → 5 ms WAIT → (1, ×)

= (1, ×)→ (0, 1) → 5 ms WAIT → (0, 0)

= (0, 0) → (1, ×) is prohibited

= (1, ×)→ (0, 0) is prohibited

(4) When switching the CPU operating clock from OSC1 to OSC3 , follow the flow chart shown in Figure

5.6.1 and then proceed with software processing.

(5) Use separate instructions to switch the clock from OSC3 to OSC1 and turn the OSC3 oscillation OFF.

Simultaneous processing with a single instruction may cause malfunction of the CPU.

CHAPTER 6: INPUT/OUTPUT PORTS

26 EPSON S1C60N07 TECHNICAL MANUAL

CHAPTER 6 INPUT/OUTPUT PORTS

6.1 Input Port (Kxx)

6.1.1 Configuration of input ports

The S1C60N07 has 4 bits of general input ports (K00–K03) built-in.

Figure 6.1.1.1 shows the configuration of the input port.

VDD

VSS

Interrupt

request

Data bus

Address

Mask option

Fig. 6.1.1.1 Configuration of input port

The input port pin K03 is used as the clock input pins for the programmable timer. See "8.3

Programmable Timer" for details.

6.1.2 Mask option

The input ports (K00–K03) are provided with built-in pull up resistor the use of which may be selected for

every bit with the mask option.

Selection of "Pull up resistor enable" with the mask option suits input from the push switch, key matrix,

and so forth. When changing the input port from low level to high level with a pull up resistor, a delay in

the waveform rise time will occur depending on the time constant of the pull up resistor and input gate

capacity. Hence, when reading data from the input port, set an appropriate waiting time. Care is

particularly required for key matrix configuration scanning. For reference, approximately 500 µs waiting

time is required.

When "Pull up resistor disabled" is selected, the port can be used for slide switch input and interfacing

with other LSIs. In this case, take care that floating state does not occur.

6.1.3 Interrupt function

All four bits of the input ports K00–K03 provide the interrupt function.

Whether to mask the interrupt function can be selected individually for all four bits by the software.

Figure 6.1.3.1 shows the configuration of the input (K00 –K03) interrupt circuit.

Data bus

Address

Interrupt factor

flag (IK0)

Noise

rejector

Address

Interrupt mask

Interrupt request

Mask

option

(K00–K03)

Fig. 6.1.3.1 Configuration of input (K00–K03) interrupt circuit

The interrupt mask registers (EIK00–EIK03) enable or mask the interrupt generation of the corresponding

input port K00–K03. When an input signal which is not masked goes low, the interrupt factor flag (IK0) is

set to "1" and an interrupt occurs at the falling edge of the input signal.

CHAPTER 6: INPUT/OUTPUT PORTS

S1C60N07 TECHNICAL MANUAL EPSON 27

6.1.4 Control of input ports

The control registers for the input ports are explained below.

Table 6.1.4.1 Control registers of input ports

Address Comment

D3 D2 D1 D0 Name Init 1 0

F04H

IK0

–

Interrupt factor flag (K00–K03)

Yes No

000

F14H

EIK00

R/W

EIK03

EIK02

EIK01

EIK00

Interrupt mask register (K03)

Interrupt mask register (K02)

Interrupt mask register (K01)

Interrupt mask register (K00)

Enable

Mask

EIK01EIK02EIK03

F40H

K00

K03

K02

K01

K00

–

High

Low

K01

K02

K03

Input port (K00–K03)

K00–K03 (F40H, R)

Input data of the input port terminal may be read out with these registers.

When "1" is read: High level

When "0" is read: Low level

Writing: Invalid

The terminal voltage of 4 bits input ports (K00–K03) are each reading as "1" and "0" at high (V DD) level

and low (VSS) level, respectively.

When these bits are used for reading only, writing operation becomes invalid.

EIK00–EIK03 (F14H, R/W)

This is the interrupt mask register of the input ports.

When "1" is written: Enable

When "0" is written: Mask

Reading: Valid

EIK0x corresponds to input port K0x. Whether to mask the interrupt function can be set in units of 1 bit.

Be sure that writing to the interrupt mask register is done with the interrupt in the DISABLE state (DI).

Writing to the interrupt mask register while in the ENABLE state (EI) may cause malfunction.

At initial reset, this register is set to "0" (mask).

IK0 (F04H [D0], R)

This is the interrupt factor flag of the input ports.

When "1" is read: Interrupt has occurred

When "0" is read: Interrupt has not occurred

Writing: Invalid

The interrupt factor flags IK0 is associated with K00–K03. From the status of this flag, the software can

decide whether an input interrupt has occurred.

The flag will not be set even if an input port status changes when the interrupt mask register (EIK0x) is set

to "0".

Be sure that the interrupt factor flag reading is done with the interrupt in the DISABLE state (DI). Reading

the interrupt factor flag while in the ENABLE state (EI) may cause malfunction.

At initial reset, this flag is set to "0".

CHAPTER 6: INPUT/OUTPUT PORTS

28 EPSON S1C60N07 TECHNICAL MANUAL

6.1.5 Programming notes

(1) When changing the input port from low level to high level with a pull up resistor, a delay in the

waveform rise time will occur depending on the time constant of the pull up resistor and input gate

capacity. Hence, when reading data from the input port, set an appropriate waiting time. Care is

particularly required for key matrix configuration scanning. For reference, approximately 500 µs

waiting time is required.

(2) Input interrupt programming related precautions

Port K input

Factor flag set Not set

Mask register

Active status

➀

When the content of the mask register is rewritten, while the port K input is in

the active status, the input interrupt factor flag is set at ➀.

Fig. 6.1.5.1 Input interrupt timing

When using an input interrupt, if you rewrite the content of the mask register, when the value of the

input terminal which becomes the interrupt input is in the active status (input terminal = low status),

the factor flag for input interrupt may be set.

For example, a factor flag is set with the timing of ➀ shown in Figure 6.1.5.1. However, when clearing

the content of the mask register with the input ter minal kept in the low status and then setting it, the

factor flag of the input interrupt is again set at the timing that has been set.

Consequently, when the input terminal is in the active status (low status), do not rewrite the mask

this case. When clearing, then setting the mask register, set the mask register, when the input terminal

is not in the active status (high status).

(3) Be sure that writing to the interrupt mask register is done with the interrupt in the DISABLE state (DI).

Writing to the interrupt mask register while in the ENABLE state (EI) may cause malfunction.

(4) Be sure that the interrupt factor flag reading is done with the interrupt in the DISABLE state (DI).

Reading the interrupt factor flag while in the ENABLE state (EI) may cause malfunction.

CHAPTER 6: INPUT/OUTPUT PORTS

S1C60N07 TECHNICAL MANUAL EPSON 29

6.2 Output Port (Rxx)

6.2.1 Configuration of output ports

The S1C60N07 has 6 bits (R32, R33, and R40–R43) of general output ports built-in.

Figure 6.2.1.1 shows the configuration of the output port.

VDD

VSS

Data bus

Address

High impedance

control register Mask

option

Data register

Address

Fig. 6.2.1.1 Configuration of output port

6.2.2 Mask option

The output ports may be selected for the following by mask option.

(1) Output specification of output ports

The output specification of each output port may be selected (in 1-bit units). Two types of output

specification may be selected: complementary output and N channel (Nch) open drain output.

However, even if Nch open drain is selected, application on the terminal of voltage exceeding the

power current voltage is not permitted.

(2) Special output

Output ports R33, R40, R42 and R43 may be selected, in addition to DC output, as special output port

as follows:

R33: Programmable timer operating clock output (PTCLK)

R40: Clock inverted output (#FOUT)

R42: Buzzer inverted output (#BZ) or clock output (FOUT)

R43: Buzzer output (BZ)

CHAPTER 6: INPUT/OUTPUT PORTS

30 EPSON S1C60N07 TECHNICAL MANUAL

Buzzer outputs BZ (R43) and #BZ (R42)

Through mask option selection, R43 and R42 may be assigned as buzzer outputs. BZ and #BZ are

buzzer signal outputs for driving piezo-electric buzzers, the buzzer signal being created by the

division of fOSC1. Moreover, digital envelope may be added to the buzzer signal.

See Chapter 9, "Sound Generator" for details.

Buzzer output BZ and #BZ can be controlled simultaneously by register R43. Note, however, that

operation is possible, and the data of said register will not affect #BZ (output from the R42 term inal).

Notes: • The BZ and #BZ output signals could generate hazards during ON/OFF switching.

• When output port R43 is set to DC output, output port R42 may not be set to #BZ output.

Figure 6.2.2.1 shows the output waveform of BZ and #BZ.

R43 register

BZ output (R43 terminal)

#BZ output (R42 terminal)

10 1

Fig. 6. 2.2.1 Output waveform of BZ and #BZ

PTCLK (R33)

The operating clock for the programmable timer is output externally from this port. In this case, the

clock output ON or OFF may be controlled from the R33 register by setting PTCOUT (F79H [D3]) to

"1". The clock frequency is selected by the 3-bit register PTC0–PTC2.

Moreover, when PTCOUT is set to "0", output port R33 becomes DC output.

Because of the above functions, PTCLK output and DC output belong to a common option selection

item. Refer to "8.3 Programmable Timer" regarding selection of clock frequency.

Clock outputs FOUT (R42), #FOUT (R40)

When R40 and R42 are selected to clock output, it outputs the clock of fOSC3, fOSC1 or the demultiplied

fOSC1. R40 (#FOUT) output generates an antiphase clock in relation to R42 (FOUT). Figure 6.2.2.2

shows the output waveform of FOUT and #FOUT. The clock frequency is selectable with the mask

options, from the frequencies listed in Table 6.2.2.1.

R42/R40 register

FOUT output (R42 terminal)

#FOUT output (R40 terminal)

10 1

Fig. 6.2.2.2 Output waveform of FOUT and #FOUT

Note: Clock output signal could generate hazards during ON/OFF switching.

Table 6.2.2.1 FOUT clock frequency

Setting Clock frequency (Hz)

fOSC3 OSC3 oscillation frequency

fOSC1/1 32,768

fOSC1/2 16,384

fOSC1/4 8,192

fOSC1/8 4,096

fOSC1/16 2,048

fOSC1/32 1,024

fOSC1/64 512

fOSC1/128 256

CHAPTER 6: INPUT/OUTPUT PORTS

S1C60N07 TECHNICAL MANUAL EPSON 31

6.2.3 High impedance control

The terminal output state of output ports R32 and R33 may be selected for high impedance state using the

high impedance control register HZR3.

6.2.4 Control of output ports

The control registers for the output ports are explained below.

Table 6.2.4.1 Control registers of output ports

Address Comment

D3 D2 D1 D0 Name Init 1 0

F53H

R/W R

–

Output port (R33)

PTCLK output

Output port (R32)

High

Off

High

Low

0R32R33

F54H

R40

R/W

R43

R42

R41

R40

Output port (R43)

Buzzer output (BZ)

Output port (R42)

Clock output (FOUT)

[Buzzer inverted output (#BZ)]

Output port (R41)

Output port (R40)

Clock inverted output (#FOUT)

High

Off

High

Off

High

Off

Low

R41R42R43

R33

R32

F7BH

R/W R

HZR3

–

R32–R33 output high-impedance control

Output High-Z

00HZR3

HZR3 (F7BH [D3], R/W)

Controls high impedance loading to output ports R32 and R33.

When "1" is written: Data output

When "0" is written: High impedance

Reading: Valid

By writing "1" in the control register HZR3, the output register data (R32 and R33) is generated in the

terminal; writing "0" will generate high impedance state.

During initial reset, this register is set to "0" and the ports acquire high impedance state.

When DC output is selected

R32, R33, R40 –R43 (F53H [D2] and [D3], F54H, R/W)

Sets the output data for the output ports.

When "1" is written: High level

When "0" is written: Low level

Reading: Valid

Output port terminals will generate the data written into the corresponding registers (R32, R33, R40–R43)

as it is. The output port terminal goes high (VDD) when "1" is written to the register, and goes low (VSS)

when "0" is written.

At initial reset, only R40–R43 are set to "1" and the other output registers become undefined.

CHAPTER 6: INPUT/OUTPUT PORTS

32 EPSON S1C60N07 TECHNICAL MANUAL

When special output is selected

R43 (F54H [D3], R/W) when BZ and #BZ output is selected

Performs the output control of buzzer signal (BZ, #BZ).

When "0" is written: Buzzer signal output

When "1" is written: Low level (DC)

Reading: Valid

When "0" is set on R43, BZ signal is generated from R43 terminal; at the same time, #BZ signal (BZ

inverted signal) is generated from R42 terminal if R42 is set to #BZ output.

When "1" is set on R43, R43 terminal (and R42 terminal too, when #BZ output is selected) output goes

low (VSS).

Note, however, that R42 at #BZ output selection may be used as a 1-bit general register in which

Read/Write operation is possible, and the data of said register will not affect #BZ (R42 terminal output).

At initial reset, R43 and R42 are set to "1".

R33 (F53H [D3], R/W) when PTCLK (DC) output is selected

Controls the output of the programmable timer operating clock (PTCLK).

When "0" is written: Clock output

When "1" is written: High level (DC)

Reading: Valid

With "1" written on PTCOUT (F79H [D3]), the operating clock of the programmable timer may be

generated externally by writing "0" on R33 register. Moreover, the output will go high (V DD) by writing

"1".

However, when PTCOUT is "0", the output becomes regular DC output.

R40, R42 (F54H [D0, D2], R/W) when FOUT and #FOUT output is selected

Controls the #FOUT and FOUT (clock) output.

When "0" is written: Clock output

When "1" is written: High level (DC)

Reading: Valid

When R42 is set to FOUT output, clock with the specified frequency is generated from R42 terminal by

writing "0" on R42 register.

By writing "1", the R42 terminal will go high (VDD).

The same applies to R40. The clock phase when #FOUT signal is output from R40 is antiphase to that of

R42.

At initial reset, R40 and R42 are set to "1".

6.2.5 Programming notes

(1) When BZ, #BZ, FOUT, #FOUT, and PTCLK (DC) are selected by mask option, a hazard may be

observed in the output waveform when the data of the output register changes.

(2) Because the R32 and R33 ports gain high impedance during initial reset, be careful when using them

as interface with external devices and the like.

CHAPTER 6: INPUT/OUTPUT PORTS

S1C60N07 TECHNICAL MANUAL EPSON 33

6.3 I/O Port (Pxx)

6.3.1 Configuration of I/O ports

The S1C60N07 has 4 bits of general I/O ports (P00 –P03) built-in.

Figure 6.3.1.1 shows the configuration of the I/O port.

Data bus

Address

Pull up control

Address

Data register

Address

I/O control

Address

Fig. 6.3.1.1 Configuration of I/O port

6.3.2 Mask option

Output specification (during output) for the I/O port may be selected by mask option (selected with the 4

bits group). Two types of output specification may be selected: complementary output and N channel

(Nch) open drain output. However, even if Nch open drain is selected, application on the terminal of

voltage exceeding the power current voltage is not permitted.

6.3.3 I/O control register and input/output mode

Input or output mode can be set for the four bits of I/O port P00–P03 by writing data to the I/O control

To set the input mode, "0" is written to the I/O control register. When an I/O port is set to input mode, it

becomes high impedance state and works as an input port.

The output mode is set when "1" is written to the I/O control register. When an I/O port set to output mode

works as an output port, it outputs a high level (VDD) when the data of output register is "1", and a low

level (VSS) when the data of output register is "0".

6.3.4 Pull up resistor

Pull up resistors can be added to four bits of I/O ports by writing data to the pull up control register PUP0.

When "0" is written to the pull up control register, the I/O port terminals are pulled up. When "1" is written,

the pull up resistors are disconnected.

CHAPTER 6: INPUT/OUTPUT PORTS

34 EPSON S1C60N07 TECHNICAL MANUAL

6.3.5 Control of I/O ports

The control registers for the I/O ports are explained below.

Table 6.3.5.1 Control register of I/O ports

Address Comment

D3 D2 D1 D0 Name Init 1 0

F60H

P00

R/W

P03

P02

P01

P00

I/O port (P00–P03)

High

Low

P01P02P03

F7DH

IOC0

RR/W

IOC0

–

I/O control (P00–P03)

Output Input

000

F7EH

PUP0 0

PUP0

–

I/O pull up resistor On/Off (P00–P03)

Off On

000

IOC0 (F7DH [D0], R/W)

Input/output direction of I/O ports are set in units of 4 bits.

When "1" is written: Output mode

When "0" is written: Input mode

Reading: Valid

By writing "1" to IOC0, the I/O ports enter the output mode, while writing "0" they enter the input mode.

At initial reset, IOC0 is set to "0" and the I/O ports are all in the input mode.

PUP0 (F7EH [D0], R/W)

Whether the I/O ports will be pulled up or not is set in units of 4 bits.

When "0" is written: Pull up ON

When "1" is written: Pull up OFF

Reading: Valid

By writing "0" to PUP0, the I/O ports are pulled up, while writing "1" turns the pull up function OFF.

At initial reset, PUP0 is set at "0", and all I/O ports are pulled up.

P00–P03 (F60H, R/W)

• During writing operation

When "1" is written: High level

When "0" is written: Low level

When the I/O port is set at output port, the data written is generated on the I/O port terminal as it is.

When "1" is written as port data, the port terminal goes high (VDD) and goes low (VSS) when "0" is

written.

Note, however, that even at input mode, port data writing is also possible.

• During reading operation

When "1" is read: High level

When "0" is read: Low level

Reading the I/O port terminal voltage level. When the I/O port is at input mode, voltage level input of

the port terminal is read; when set at output mode, output voltage level is read. When the terminal

voltage is at high (VDD) level, port data reading is "1"; at low (VSS) level, it is "0".

CHAPTER 6: INPUT/OUTPUT PORTS

S1C60N07 TECHNICAL MANUAL EPSON 35

6.3.6 Programming notes

(1) When the I/O port is set at output mode, and low impedance load is connected to the port terminal, the

data written and read may differ.

(2) If the state of the I/O port meets all of the following 4 conditions, the reading data will be undefined:

• The input/output mode is set at output mode

• Output specification is set at Nch open drain

• The content of the data register is "1"

• The pull up resistor turned is OFF

CHAPTER 7: LCD DRIVER

36 EPSON S1C60N07 TECHNICAL MANUAL

CHAPTER 7 LCD DRIVER

The S1C60N07 has 16 common terminals and 40 segment terminals and can drive a maximum

of 640 (40 × 16) dots (8 characters × 2 lines) LCD.

This LCD driver performs the following control through the software.

• Drive duty can be set to 1/16 or 1/8 duty.

• LCD contrast can be adjusted through a 16 steps range.

• All dots of the LCD panel can be switched ON and OFF.

7.1 Drive Duty

Because the power for LCD driving is generated by the internal circuit of the CPU, there is no need to

provide for it externally. Driving is done by 1/16 duty or 1/8 duty dynamic drive through 4 electric

potentials (1/4 bias) : VL1, VL2, VL4, and VL5. The 5 electric potentials are entered in VL1, VL2, VL3, VL4

and VL5 terminals and 1/5 bias driving may then be set.

Drive duty may be selected from the software. Dot number differences due to the selected duty are shown

in Table 7.1.1.

Table 7.1.1 Differences due to selected duty

Duty Common terminal in use Maximum dot number Frame frequency ∗

1/16 COM0–15 640 dots 32 Hz

1/8 COM0–7 320 dots 32 Hz

∗ Frame frequency = fOSC1/1,024

Figure 7.1.1 shows the drive waveform for 1/16 duty (1/5 bias), and Figure 7.1.2 shows the drive

waveform for 1/8 duty (1/4 bias).

CHAPTER 7: LCD DRIVER

S1C60N07 TECHNICAL MANUAL EPSON 37

VDD

VSS

VDD

VL1

VL2

VL3

VL4

VL5

VDD

VL1

VL2

VL3

VL4

VL5

VDD

VL1

VL2

VL3

VL4

VL5

VDD

VL1

VL2

VL3

VL4

VL5

VDD

VL1

VL2

VL3

VL4

VL5

-VL5

V (GND)DD

VL1

VL2

VL3

VL4

VL5

-VL4

-VL3

-VL2

-VL1

-VL5

VL1

VL2

VL3

VL4

VL5

-VL4

-VL3

-VL2

-VL1

SEG1~COM0

SEG0~COM0

SEG1

SEG0

COM2

COM1

COM0

0123 150123 15

V (GND)

COM0

SEG0

Fig. 7.1.1 Drive waveform for 1/16 duty (1/5 bias)

Note: 1/5 bias may only be utilized when power for LCD driving is supplied externally; when internal

power circuit is used, 1/4 bias is utilized.

CHAPTER 7: LCD DRIVER

38 EPSON S1C60N07 TECHNICAL MANUAL

COM0

COM1

COM2

SEG0

SEG1

SEG0~COM0

SEG1~COM0

0123456701234567 VDD

VSS

VDD

VL1

VL2

VL4

VL5

(V )L3

VDD

VL1

VL2

VL4

VL5

(V )L3

VDD

VL1

VL2

VL4

VL5

(V )L3

VDD

VL1

VL2

VL4

VL5

(V )L3

VDD

VL1

VL2

VL4

VL5

(V )L3

V (GND)DD

VL1

VL2

VL4

VL5

(V )L3

-VL5

-VL4

-VL2

-VL1

(-V )L3

V (GND)DD

VL1

VL2

VL4

VL5

(V )L3

-VL5

-VL4

-VL2

-VL1

(-V )L3

COM0

SEG0

Fig. 7.1.2 Drive waveform for 1/8 duty (1/4 bias)

CHAPTER 7: LCD DRIVER

S1C60N07 TECHNICAL MANUAL EPSON 39

7.2 Mask Option

Disconnecting the internal power for LCD driving will enable electric potentials to be supplied

externally. In such case, the 5 electric potentials are entered in VL1, VL2, VL3, VL4 and VL5 terminals and

1/5 bias driving may then be set. Since 1/5 bias driving provides better display quality, when low power

current consumption is not required (i.e., when power is supplied from AC outlet), select external power

mode. However, note that in order to maintain a stable display, power source must be one which will

remain stable even when heavy load such as buzzer, etc. is driven.

Moreover, in the external power mode, the contrast adjustment function cannot be used. Accommo date

this limitation by utilizing the external circuit as necessary.

A sample circuit of external power for LCD driving when power is supplied externally is shown in

Figure 7.2.1.

VDD

VL1

VL2

VL3

VL4

VSS

Rxx

S1C60N07

VDD

VSS

VL5 Power save circuit

Fig. 7.2.1 Sample circuit of external power for LCD driving when power is supplied externally

7.3 Display Data Memory

The display data memory of the S1C60N07 is allocated to the built-in RAM addresses E00H–E4FH and

E80H–ECFH.

Figure 7.3.1 shows the correspondence between the display data memory and the LCD dot matrix.

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM9

COM10

COM11

COM12

COM13

COM14

COM15

SEG0

E00H

■

E01H

E80H

E81H

SEG1

E02H

■

E03H

E82H

E83H

SEG2

E04H

■

E05H

E84H

E85H

SEG3

E06H • • •

■

E07H • • •

E86H • • •

E87H • • •

SEG39

E4EH

■

E4FH

ECEH

ECFH

Memory address Data bit

Fig. 7.3.1 LCD dot matrix and segment memory correspondence

When the segment memory bit is assigned as "1", the corresponding LCD dot lights up, and when

assigned as "0", the dot dies out.

At 1/16 duty drive and 1/8 duty drive, COM0 to COM15 lines and COM0 to COM7 lines light up,

respectively.

At initial reset, the display data memory content becomes undefined and hence, there is need to initialize

by software.

CHAPTER 7: LCD DRIVER

40 EPSON S1C60N07 TECHNICAL MANUAL

7.4 Control of LCD Driver

The control registers for the LCD driver are explained below.

Table 7.4.1 Control registers of LCD driver

Address Comment

D3 D2 D1 D0 Name Init 1 0

F71H

HLMOD

R/W

ALOFF

ALON

LDUTY

HLMOD

All LCD dots fade out control

All LCD dots displayed control

LCD drive duty switch

Heavy load protection mode

All off

All on

1/8

HLMOD

Normal

1/16

Normal

LDUTYALONALOFF

F72H

LC0 LC3

LC2

LC1

LC0

LC1LC2LC3

LCD contrast adjustment

LC3–LC0 = 0 light

LC3–LC0 = 15 dark

RR/W

F7FH

LCDOFF 0

LCDOFF

–

LCD display control

Normal Off

000

R/W

LDUTY (F71H [D1], R/W)

Sets the LCD drive duty.

When "1" is written: 1/8 duty

When "0" is written: 1/16 duty

Reading: Valid

Writing "1" or "0" on LDUTY will set is to 1/8 duty or 1/16 duty, respectively.

At initial reset, LDUTY is set at "0".

ALON (F71H [D2], R/W)

Displays the all LCD dots on.

When "1" is written: All LCD dots displayed

When "0" is written: Normal operation

Reading: Valid

Writing "1" to ALON will display all the LCD dots on; writing "0" will set the LCD display back to

normal. LCD panel testing may be conducted with this function.

Total LCD displaying at ALON = "1" is a static operation and does not affect the content of the display

data memory.

ALON precedes ALOFF.

At initial reset, ALON is set at "0".

ALOFF (F71H [D3], R/W)

Fade outs the all LCD dots.

When "1" is written: All LCD dots fade out

When "0" is written: Normal operation

Reading: Valid

When "1" is written on ALOFF, all LCD dots will fade out; writing "0" will set it back to normal.

All fading out of LCD at ALOFF = "1" is due to light out signals and does not affect the content of the

display data memory.

Flashing of the entire LCD panel is performed by this function.

At initial reset, ALOFF is set to "1".

CHAPTER 7: LCD DRIVER

S1C60N07 TECHNICAL MANUAL EPSON 41

LC0, LC1, LC2, LC3 (F72H, R/W)

Will adjust the LCD contrast.

Contrast may be adjusted to 16 levels as shown in Table 7.4.2.

Table 7.4.2 LCD contrast

LC3 LC2 LC1 LC0 Contrast

00000 light

10001 ↑

20010

30011

40100

50101

60110

70111

81000

91001

A1010

B1011

C1100

D1101

E1110 ↓

F 1 1 1 1 dark

At room temperature, use setting number 7 or 8 as standard.

The voltage of the LCD system power terminals VL1, VL2, VL4 and VL5 changes through thi s function.

Because at initial reset, the contents of LC0–LC3 are undefined, initialize it by the software.

LCDOFF (F7FH [D0], R/W)

Control the LCD system voltage circuit ON and OFF.

When "1" is written: Normal operation

When "0" is written: Display OFF

Reading: Valid

When "1" is written to LCDOFF, the LCD system voltage circuit turns ON and generate the LCD drive

volatges. When "0" is written, all the drive voltages go to VSS level and the display turns OFF.

At initial reset, this register is set to "1".

7.5 Programming Note

Because at initial reset, the contents of display data memory and LC0 –LC3 are undefined, there is need to

initialize by software.

CHAPTER 8: TIMERS

42 EPSON S1C60N07 TECHNICAL MANUAL

CHAPTER 8 TIMERS

8.1 Clock Timer

8.1.1 Configuration of clock timer

The S1C60N07 has a clock timer with OSC1 (crystal oscillation) as basic oscillation built-in. The clock

timer is configured with an 8 bits binary counter with 256 Hz signal divided from OSC1 as input clock,

allowing 128 Hz –1 Hz of data to be read by the software.

Figure 8.1.1.1 shows the configuration of the clock timer.

32 Hz, 8 Hz, 2 Hz, 1 Hz

256 Hz

Clock timer reset signal Interrupt request

OSC1 oscillation

circuit Divider

Data bus

128 Hz–16 Hz 8 Hz–1 Hz

Interrupt

control

Fig. 8.1.1.1 Configuration of clock timer

8.1.2 Interrupt function

The clock timer has interrupt capability, and interrupt is generated by the falling edge of 32 Hz, 8 Hz, 2 Hz,

and 1 Hz signals. Figure 8.1.2.1 shows the timing chart of the clock timer.

Clock timer timing chart

FrequencyRegisterAddress

F21H

4 Hz

2 Hz

32 Hz interrupt request

8 Hz interrupt request

1 Hz interrupt request

F20H

2 Hz interrupt request

D3 1 Hz

128 Hz

16 Hz

8 Hz

32 Hz

64 Hz

Fig. 8.1.2.1 Timing chart of clock timer

The clock timer interrupt is generated at the falling edge of the frequencies (32 Hz, 8 Hz, 2 Hz, and 1 Hz).

At this time, the corresponding interrupt factor flag (IT32, IT8, IT2, and IT1) is set to "1".

Selection of whether to mask the separate interrupts can be made with the interrupt mask registers (EIT32,

EIT8, EIT2, and EIT1). However, regardless of the interrupt mask register setting, the interrupt factor flag

is set to "1" at the falling edge of the corresponding signal.

CHAPTER 8: TIMERS

S1C60N07 TECHNICAL MANUAL EPSON 43

8.1.3 Control of clock timer

The control registers for the clock timer are explained below.

Table 8.1.3.1 Control registers of clock timer

Address Comment

D3 D2 D1 D0 Name Init 1 0

F00H

IT32

IT1

IT2

IT8

IT32

Interrupt factor flag (clock timer 1 Hz)

Interrupt factor flag (clock timer 2 Hz)

Interrupt factor flag (clock timer 8 Hz)

Interrupt factor flag (clock timer 32 Hz)

Yes

IT8IT2IT1

F10H

EIT32

R/W

EIT1

EIT2

EIT8

EIT32

Interrupt mask register (clock timer 1 Hz)

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

Enable

Mask

EIT8EIT2EIT1

F20H

TM0

TM3

TM2

TM1

TM0

Clock timer data (16 Hz)

Clock timer data (32 Hz)

Clock timer data (64 Hz)

Clock timer data (128 Hz)

TM1TM2TM3

F21H

TM7

TM6

TM5

TM4

Clock timer data (1 Hz)

Clock timer data (2 Hz)

Clock timer data (4 Hz)

Clock timer data (8 Hz)

TM4TM5TM6TM7

F76H

WDRST 0

TMRST

WDRST

–

Reset

Clock timer reset

Watchdog timer reset

Reset

Reset –

–

TMRST00

TMRST (F76H [D1], W)

This bit resets the clock timer.

When "1" is written: Cl ock timer reset

When "0" is written: No operation

Reading: Always "0"

By writing "1" on TMRST, the clock timer is reset and all timer data are set to "0".

Because this bit is only for writing, it is always "0" during reading.

TM0–TM7 (F20H, F21H, R)

Will read the data of the clock timer.

TMx (x = 0–7) and frequency correspondence are as follows:

F20H F21H

TM0: 128 Hz TM4: 8 Hz

TM1: 64 Hz TM5: 4 Hz

TM2: 32 Hz TM6: 2 Hz

TM3: 16 Hz TM7: 1 Hz

The above 8 bits are only for reading and render writing operation invalid.

At initial reset, timer data is initialized to "0".

EIT32, EIT8, EIT2, EIT1 (F10H, R/W)

These are the interrupt mask registers of the clock timer.

When "1" is written: Enabled

When "0" is written: Masked

Reading: Valid

EIT32, EIT8, EIT2, and EIT1 correspond to 32 Hz, 8 Hz, 2 Hz, and 1 Hz timer interrupts, respectively.

Be sure that writing to the interrupt mask register is done with the interrupt in the DISABLE state (DI).

Writing to the interrupt mask register while in the ENABLE state (EI) may cause malfunction.

At initial reset, these registers are all set to "0" (mask).

CHAPTER 8: TIMERS

44 EPSON S1C60N07 TECHNICAL MANUAL

IT32, IT8, IT2, IT1 (F00H, R)

These are the interrupt factor flags of the clock timer.

When "1" is read: Interrupt has occurred

When "0" is read: Interrupt has not occurred

Writing: Invalid

IT32, IT8, IT2, and IT1 correspond to 32 Hz, 8 Hz, 2 Hz, and 1 Hz timer interrupts, respectively.

The occurrence of clock timer interrupt can be determined by the software through these flags. However,

regardless of interrupt masking, these flags are set to "1" due to the falling edge of the corresponding

signal.

Be sure that the interrupt factor flag reading is done with the interrupt in the DISABLE state (DI).

Reading the interrupt factor flag while i n the ENABLE state (EI) may cause malfunction.

At initial reset, these flags are set to "0".

8.1.4 Programming notes

(1) When the clock timer has been reset, the interrupt factor flag (IT) may sometimes be set to "1".

Consequently, perform flag read (reset the flag) as necessary at reset.

(2) Because the watchdog timer counts up during reset as in the above (1), reset the watchdog timer as

necessary.

(3) When the low-order digits (TM0–TM3) and high-order digits (TM4–TM7) are consecutively read,

proper reading may not be obtained due to the carry from the low-order digits into the high-order digits

(when the reading of the low-order digits and high-order digits span the timing of the carry). For this

reason, perform multiple reading of timer data, make comparisons and use matching data as result.

(4) Be sure that writing to the interrupt mask register is done with the interrupt in the DISABLE state (DI).

Writing to the interrupt mask register while in the ENABLE state (EI) may cause malfunction.

(5) Be sure that the interrupt factor flag reading is done with the interrupt in the DISABLE state (DI).

Reading the interrupt factor flag while in the ENABLE state (EI) may cause malfunction.

CHAPTER 8: TIMERS

S1C60N07 TECHNICAL MANUAL EPSON 45

8.2 Stopwatch Timer

8.2.1 Configuration of stopwatch timer

The S1C60N07 has 1/100 sec unit (SWL) and 1/10 sec unit (SWH) stopwatch timer built-in. The

stopwatch timer is configured with a 2 levels 4 bits BCD counter which has an input clock approximating

100 Hz signal (signal divided from OSC1 to the closest 100 Hz) and data can be read in units of 4 bits by

software.

Figure 8.2.1.1 shows the configuration of the stopwatch timer.

10 Hz, 1 Hz

256 Hz 10 Hz

Stopwatch timer reset signal

Stopwatch timer RUN/STOP signal Interrupt request

OSC1 oscillation

circuit Divider

Data bus

SWL counter SWH counter

Interrupt

control

Fig. 8.2.1.1 Configuration of stopwatch timer

The stopwatch timer can be used as a separate timer from the clock timer. In particular, digital watch

stopwatch functions can be realized easily with software.

8.2.2 Count-up pattern

The stopwatch timer is configured of 4 bits BCD counters SWL and SWH.

The counter SWL, at the stage preceding the stopwatch timer, has an approximated 100 Hz signal for the

input clock. It counts up every 1/100 sec, and generates an approximated 10 Hz signal. The counter SWH

has an approximated 10 Hz signal generated by the counter SWL for the input clock. In count-up every

1/10 sec, and generated 1 Hz signal.

Figure 8.2.2.1 shows the count-up pattern of the stopwatch timer.

256 26

256

256 25

256

256 2

256 3

256 2

256

256 3

256

256 2

256

256 2

256

256 3

256

256 2

256

256 25

256

x 6 + x 4 = 1 (sec)

0 1 2 3 4 5 6 7 8 9 0

1 Hz

signal

generation

Approximate

10 Hz

signal

generation

SWH count value

Count time (sec)

(sec)

SWL count value

Count time (sec)

SWL count value

Count time (sec)

SWH count-up pattern

SWL count-up pattern 1

SWL count-up pattern 2

Approximate

10 Hz

signal

generation

Fig. 8.2.2.1 Count-up pattern of stopwatch timer

SWL generates an approximated 10 Hz signal from the basic 256 Hz signal. The count-up intervals are

2/256 sec and 3/256 sec, so that finally two patterns are generated: 25/256 sec and 26/256 sec intervals.

Consequently, these patterns do not amount to an accurate 1/100 sec.

SWH counts the approximated 10 Hz signals generated by the 25/256 sec and 26/256 sec intervals in the

ratio of 4 : 6, to generate a 1 Hz signal. The count-up intervals are 25/256 sec and 26/256 sec, which do

not amount to an accurate 1/10 sec.

CHAPTER 8: TIMERS

46 EPSON S1C60N07 TECHNICAL MANUAL

8.2.3 Interrupt function

Stopwatch timers SWL and SWH, through their respective overflows, can generate 10 Hz (approximate

10 Hz) and 1 Hz interrupts.

Figure 8.2.3.1 shows the timing chart for the stopwatch timer.

Address

Stopwatch timer (SWL) timing chart

Stopwatch timer (SWH) timing chart

10 Hz interrupt request

1 Hz interrupt request

F23H

1/10sec

(BCD)

F22H

1/100sec

(BCD)

Fig. 8.2.3.1 Timing chart for stopwatch timer

The stopwatch interrupts are generated by the overflow of their respective counters SWL and SWH

(changing "9" to "0"). At this time, the corresponding interrupt factor flags (ISW0 and ISW1) are set to

"1".

The respective interrupts can be masked separately through the interrupt mask registers (EISW0 and

EISW1). However, regardless of the setting of the interrupt mask registers, the interrupt factor flags are set

to "1" by the overflow of their corresponding counters.

CHAPTER 8: TIMERS

S1C60N07 TECHNICAL MANUAL EPSON 47

8.2.4 Control of stopwatch timer

The control registers for the stopwatch timer are explained below.

Table 8.2.4.1 Control registers of stopwatch timer

Address Comment

D3 D2 D1 D0 Name Init 1 0

F01H

ISW0

ISW1

ISW0

–

Interrupt factor flag (stopwatch 1 Hz)

Interrupt factor flag (stopwatch 10 Hz)

ISW100

F11H

EISW0

R/W

EISW1

EISW0

–

Interrupt mask register (stopwatch 1 Hz)

Interrupt mask register (stopwatch 10 Hz)

Enable

Enable Mask

Mask

EISW100

F22H

SWL3

SWL2

SWL1

SWL0

F23H

SWH0

SWH3

SWH2

SWH1

SWH0

SWH1SWH2SWH3

SWL0SWL1SWL2SWL3

Stopwatch timer

1/100 sec data (BCD)

MSB

LSB

Stopwatch timer

1/10 sec data (BCD)

MSB

LSB

F77H

SWRST

SWRUN

–

Reset

Stopwatch timer reset

Stopwatch timer Run/Stop

Reset

Run –

Stop

00 SWRUN

R/W

SWRST

SWRST (F77H [D1], W)

This bit resets the stopwatch timer.

When "1" is written: Stopwatch timer reset

When "0" is written: No operation

Reading: Always "0"

By writing "1" on SWRST, the stopwatch timer is reset. All timer data is set to "0".

When the stopwatch ti mer is reset in the RUN mode, it will re-start counting immediately after the reset

and at STOP mode, the reset data is maintained.

Because this bit is for writing only, it is always "0" during reading.

SWRUN (F77H [D0], R/W)

This register controls RUN/STOP of the stopwatch timer.

When "1" is written: RUN

When "0" is written: STOP

Reading: Valid

By writing "1" on SWRUN, the stopwatch timer performs counting operation. Writing "0" will make the

stopwatch stop counting.

Even if the stopwatch is stopped, the timer data at that point is kept.

When data of the counter is read at run mode, proper reading may not be obtained due to the carry from

low-order digits (SWL) into high-order digits (SWH) (i.e., in case SWL and SWH reading span the timing

of the carry). To avoid this occurrence, perform the reading after suspending the counter once and then set

the SWRUN to "1" again.

Moreover, it is required that the suspension period not exceed 976 µs (1/4 cycle of 256 Hz).

At initial reset, SWRUN is set to "0".

SWL0–SWL3 (F22H, R)

Will read the stopwatch timer data to the 1/100 sec digits (BCD).

Since these bits are for reading only, writing operation is invalidated.

At initial reset, timer data is set to "0".

CHAPTER 8: TIMERS

48 EPSON S1C60N07 TECHNICAL MANUAL

SWH0–SWH3 (F23H, R)

Will read the stopwatch timer data to the 1/10 sec digits (BCD).

Since these bits are for reading only, writing operation is invalidated.

At initial reset, timer data is set to "0".

EISW0, EISW1 (F11H [D0, D1], R/W)

These are the interrupt mask registers of the stopwatch timer.

When "1" is written: Enabled

When "0" is written: Masked

Reading: Valid

EISW0 and EISW1 correspond to 10 Hz and 1 Hz stopwatch timer interrupts, respectively.

Be sure that writing to the interrupt mask register is done with the interrupt in the DISABLE state (D I).

Writing to the interrupt mask register while in the ENABLE state (EI) may cause malfunction.

At initial reset, these registers are all set to "0" (mask).

ISW0, ISW1 (F01H [D0, D1], R)

These are the interrupt factor flags of the stopwatch timer.

When "1" is read: Interrupt has occurred

When "0" is read: Interrupt has not occurred

Writing: Invalid

ISW0 and ISW1 correspond to 10 Hz and 1 Hz stopwatch timer interrupts, respectively.

The occurrence of stopwatch timer interrupt can be determined by the software through these flags.

However, regardless of interrupt masking, these flags are set to "1" by the overflow of the corresponding

counters.

Be sure that the interrupt factor flag reading is done with the interrupt in the DISABLE state (DI).

Reading the interrupt factor flag while in the ENABLE state (EI) may cause malfunction.

At initial reset, these flags are set to "0".

8.2.5 Programming notes

(1) When data of the counter is read at run mode, perform the reading after suspending the counter once

and then set SWRUN to "1" again. Moreover, it is required that the suspension period not exceed 976

µs (1/4 cycle of 256 Hz).

(2) Be sure that writing to the interrupt mask register is done with the interrupt in the DISABLE state (DI).

Writing to the interrupt mask register while in the ENABLE state (EI) may cause malfunction.

(3) Be sure that the interrupt factor flag reading is done with the interrupt in the DISABLE state (DI).

Reading the interrupt factor flag while in the ENABLE state (EI) may cause malfunction.

CHAPTER 8: TIMERS

S1C60N07 TECHNICAL MANUAL EPSON 49

8.3 Programmable Timer

8.3.1 Configuration of programmable timer

The S1C60N07 has a programmable timer with OSC1 (crystal oscillation) as basic oscillation built-in.

The programmable timer is configured with an 8 bits pre-settable down counter and it has been down-

count at initial value by 256 Hz –8,192 Hz signal or by the input signal of input port K03.

The initial value of count data can be set by software to the reload register; at the point where the down-

counter value is "0", the programmable timer reloads the initial value and continues to down-count.

The down-counter data may be read through the software. Moreover, the input clock being selected may

be generated to output port R33.

Figure 8.3.1.1 shows the configuration of the programmable timer.

256 Hz–8,192 Hz

K03

Selector

Divider

OSC1

oscillation

circuit

Noise

reject

circuit

Programmable timer reset signal

Programmable timer RUN/STOP signal Interrupt

control

Reload

8-bit

down counter

Data bus

Interrupt request

R33

Fig. 8.3.1.1 Configuration of programmable timer

One input clock may be selected by software from any of the following 8 types:

(1) K03 input (with noise rejector)

(2) K03 input (direct)

(3) 256 Hz

(4) 512 Hz

(5) 1,024 Hz

(6) 2,048 Hz

(7) 4, 096 Hz

(8) 8,192 Hz

Note, however, that down-count is done at falling edges of the input signal as shown in Figure 8.3.1.2.

Input clock

Down count Down count

Fig. 8.3.1.2 Timing of down-counts

Type (1) K03 input (with noise rejector) is for counting by key entry, the input signal fro m which passes

the 256 Hz sampling noise reject circuit. With this, no more than 2 ms of chattering is purged, and at least

4 ms signal is received.

CHAPTER 8: TIMERS

50 EPSON S1C60N07 TECHNICAL MANUAL

8.3.2 Interrupt function

The programmable timer generates interrupt after the down-count from the initial setting is completed and

the content of the down-counter indicates 00H.

After interrupt generation, the programmable timer reloads the initial count value into the down-counter

and resumes counting.

Figure 8.3.2.1 shows the timing chart of the programmable timer.

Interrupt

request

Note: When "A6H" is set into reload register

PTRST

PTRUN

Input clock

Timer data

high-order

address (F25H)

Timer data

low-order

address (F24H)

Fig. 8.3.2.1 Timing chart of programmable timer

When the down-counter values PT0–PT7 have become 00H the interrupt factor flag IPT is set to "1" and

an interrupt is generated. The interrupt can be masked through the interrupt mask register EIPT. However,

regardless of the setting of the interrupt mask register, the interrupt factor flag is set to "1" when the

down-counter equals 00H.

CHAPTER 8: TIMERS

S1C60N07 TECHNICAL MANUAL EPSON 51

8.3.3 Control of programmable timer

The control registers for the programmable timer are explained below.

Table 8.3.3.1 Control registers of programmable timer

Address Comment

D3 D2 D1 D0 Name Init 1 0

F02H

IPT

–

0No

000

F12H

EIPT

R/W

EIPT

–

0Enable

Yes

Mask

Interrupt factor flag (programmable timer)

Interrupt mask register (programmble timer)

F24H

PT0

PT3

PT2

PT1

PT0

PT1PT2PT3

F25H

PT4

PT7

PT6

PT5

PT4

PT5PT6PT7

F26H

RD0

R/W

RD3

RD2

RD1

RD0

RD1RD2RD3

F27H

RD4

R/W

RD7

RD6

RD5

RD4

RD5RD6RD7

Programmable timer data (low-order)

MSB

LSB

Programmable timer data (high-order)

MSB

LSB

Programmable timer

reload data (low-order)

MSB

LSB

Programmable timer

reload data (high-order)

MSB

LSB

F78H

PTRST

PTRUN

–

Reset

Programmable timer reset

Programmable timer Run/Stop

Reset

Run –

Stop

F79H

PTC0

R/W

PTCOUT

PTC2

PTC1

PTC0

Programmable timer clock output

On Off

PTC1PTC2PTCOUT

Programmable timer input clock selection

PTRUN

R/W

PTRST

PTC0, PTC1, PTC2 (F79H [D0–D2], R/W)

Selects the input clock.

The PTC0–PTC2 setting and input clock correspondence is shown in Table 8.3.3.2.

Table 8.3.3.2 Input clock setting

PTC2 PTC1 PTC0 Input clock

0 0 0 K03 input (with noise rejector)

0 0 1 K03 input (direct)

0 1 0 256 Hz

0 1 1 512 Hz

1 0 0 1,024 Hz

1 0 1 2,048 Hz

1 1 0 4,096 Hz

1 1 1 8,192 Hz

PTCOUT (F79H [D3], R/W)

Generates the input clock being selected to output port R33.

Refer to Section 6.2, "Output Port" regarding control methods.

CHAPTER 8: TIMERS

52 EPSON S1C60N07 TECHNICAL MANUAL

RD0–RD3, RD4–RD7 (F26H, F27H, R/W)

These are reload registers for setting the initial value of the timer.

Sets the low-order 4 bits of the 8 bits timer data to RD0–RD3, and the high-order 4 bits to RD4–RD7.

The set timer data is loaded to the down-counter when the programmable timer is reset or when the

content of the down-counter is 00H.

When data of reload registers is set at "00H", the down-counter becomes a 256-value counter.

At initial reset, this register will be undefined.

PTRST (F78H [D1], W)

This bit resets the programmable timer.

When "1" is written: Programmable timer reset

When "0" is written: No operation

Reading: Always "0"

By writing "1" on PTRST, the programmable timer is reset.

The contents set in RD0–RD7 are loaded into the down-counter.

When the programmable timer is reset in the RUN mode, it will re-start counting immediately after

loading and at STOP mode, the load data is maintained.

Because this bit is only for writing, it is always "0" during reading.

PTRUN (F78H [D0], R/W)

This register controls RUN/STOP of the programmable timer.

When "1" is written: RUN

When "0" is written: STOP

Reading: Valid

By writing "1" on PTRUN, the programmable timer performs counting opera tion. Writing "0" will make

the programmable timer stop counting.

Even if the programmable timer is stopped, the timer data at that point is kept.

When data of the counter is read at the RUN mode, proper reading may not be obtained due to the carry

from the low-order digits (PT0–PT3) into the high-order digits (PT4–PT7) (when the reading of the

low-order digits and high-order digits span the timing of the carry). To avoid this occurrence, perform the

reading after suspending the programmable timer once, and set the PTRUN to "1" again. Moreover, it is

required that the suspension period be within 1/4 cycle of the input clock (in case of 1/2 duty).

At initial reset, PTRUN is set to "0".

PT0–PT3, PT4–PT7 (F24H, F25H, R)

Will read the data from the down-counter of the programmable timer.

Will read the low-order 4 bits of the 8 bits counter data PT0–PT3, and the high-order 4 bits PT4–PT7.

Because these 8 bits are only for reading, writing operation is rendered invalid.

At initial reset, timer data will be undefined.

EIPT (F12H [D0], R/W)

This is the interrupt mask register of the programmable timer.

When "1" is written: Enabled

When "0" is written: Masked

Reading: Valid

Be sure that writing to the interrupt mask register is done with the interrupt in the DISABLE state (DI).

Writing to the interrupt mask register while in the ENABLE state (EI) may cause malfunction.

At initial reset, this register is set to "0" (mask).

CHAPTER 8: TIMERS

S1C60N07 TECHNICAL MANUAL EPSON 53

IPT (F02H [D0], R)

This is the interrupt factor flag of the programmable timer.

When "1" is read: Interrupt has occurred

When "0" is read: Interrupt has not occurred

Writing: Invalid

From the status of this flag, the software can decide whether the programmable timer interrupt. Note,

however, that even if the interrupt is masked, this flag will be set to "1" by the counter value will become

"00H".

Be sure that the interrupt factor flag reading is done with the interrupt in the DISABLE state (DI).

Reading the interrupt factor flag while in the ENABLE state (EI) may cause malfunction.

At init ial reset, this flag is set to "0".

8.3.4 Programming notes

(1) When initiating programmable timer count, perform programming by the following steps:

1. Set the initial data to RD0–RD7.

2. Reset the programmable timer by writing "1" to PTRST.

3. Start the down-count by writing "1" to PTRUN.

(2) When the reload register (RD0 –RD7) value is set at "00H", the down-counter becomes a 256-value

counter.

(3) When data of the timer is read consecutively in 8 bits in the RUN mode, perform the reading after

suspending the timer once and then set the PTRUN to "1" again. Moreover, it is required that the

suspension period be within 1/4 cycle of the input clock (in case of 1/2 duty). Accordingly, when the

input clock is a fast clock faster than a 256 Hz, high speed processing by OSC3 is required.

(4) Be sure that writing to the interrupt mask register is done with the interrupt in the DISABLE state (DI).

Writing to the interrupt mask register while in the ENABLE state (EI) may cause malfunction.

(5) Be sure that the interrupt factor flag reading is done with the interrupt in the DISABLE state (DI).

Reading the interrupt factor flag while in the ENABLE state (EI) may cause malfunction.

CHAPTER 9: SOUND GENERATOR

54 EPSON S1C60N07 TECHNICAL MANUAL

CHAPTER 9 SOUND GENERATOR

9.1 Configuration of Sound Generator

The S1C60N07 is capable of generating buzzer signals (BZ and #BZ) to drive a piezo-electric buzzer.

The buzzer signal frequency may be selected by software from 8 types of signal divided from fOSC1

(32.768 kHz). Also, digital envelope which is duty ratio controlled may be added to the buzzer signal.

In addition, 1-shot output circuit is built-in to output key operation check sound, and the like.

Figure 9.1.1 shows the sound generator configuration. Figure 9.1.2 shows the sound generator timing

chart.

256 Hz

32.768 kHz

[ENVRST] [ENVRT]

[BZFQ0–BZFQ2]

[ENVON]

R43 (BZ)

R42 (#BZ)

[R43]

[R42]Output port

Envelope

addition circuit

Programmable

dividing circuit

Envelope generation

circuit

[ ]: Register

1-shot output circuit

[BZSHOT] [SHOTPW]

Fig. 9.1.1 Configuration of sound generator

BZFQ0–2

ENVON

R43 (register)

BZ (R43 terminal)

#BZ (R42 terminal)

Fig. 9.1.2 Timing chart of sound generator

9.2 Mask Option

(1) Selection can be made whether to output the BZ signal from the R43 terminal.

(2) Selection can be made whether to output the #BZ signal from the R42 terminal.

However, if the BZ signal is not output the #BZ signal cannot be output.

See Section 6.2, "Output Port" for details of the above mask option.

CHAPTER 9: SOUND GENERATOR

S1C60N07 TECHNICAL MANUAL EPSON 55

9.3 Frequency Setting

The frequencies of the buzzer signals (BZ, #BZ) are set by writing data to registers BZFQ0–BZFQ2.

Table 9.3.1 lists the register set ting values and the frequencies that can be set.

Table 9.3.1 Setting of frequencies of buzzer signals

BZFQ2 BZFQ1 BZFQ0 Buzzer frequency (Hz)

0 0 0 4,096.0

0 0 1 3,276.8

0 1 0 2,730.7

0 1 1 2,340.6

1 0 0 2,048.0

1 0 1 1,638.4

1 1 0 1,365.3

1 1 1 1,170.3

Note: A hazard may be observed in the output waveform of the BZ and #BZ signals when switches the

buzzer frequency while the BZ and #BZ signals being output.

9.4 Digital Envelope

A duty ratio control data envelope (with duty ratio change in 8 steps) can be added to the buzzer signal

(BZ, #BZ).

Duty ratio refers to the ratio of pulse width to the pulse cycle; given that high level output time is TH, and

low level output time is TL, BZ output becomes TH/(TH+TL).

#BZ output becomes TL/(TH+TL) owing to the inverted output of the BZ output. Moreover, care is

necessary as the duty ratio differs according to the buzzer frequency.

Envelope addition is performed by writing "1" to ENVON; when "0" is written, the duty ratio is fixed at

the maximum (1/2 dut y). Moreover, when envelope is added, writing "1" to ENVRST will cause the BZ

signal duty ratio to be returned to maximum.

The decay time of the envelope (time for the duty ratio to change) can be selected with the register

ENVRT. This time is 62.5 ms (16 Hz) when "0" is written, and 125 ms (8 Hz) when "1" is written.

However, a maximum difference of 4 ms is taken from envelope-ON until the first change.

Table 9.4.1 lists the duty ratio and buzzer frequencies.

Figure 9.4.1 shows the digital envelope timing chart.

Table 9.4.1 Duty ratio and buzzer frequencies

Buzzer frequencies

Duty ratio 4,096.6 3,276.8 2,730.7 2,340.6

2,048.0 1,638.4 1,365.3 1,170.3

Level 1 (max.) 8/16 8/20 12/24 12/28

Level 2 7/16 7/20 11/24 11/28

Level 3 6/16 6/20 10/24 10/28

Level 4 5/16 5/20 9/24 9/28

Level 5 4/16 4/20 8/24 8/28

Level 6 3/16 3/20 7/24 7/28

Level 7 2/16 2/20 6/24 6/28

Level 8 (min.) 1/16 1/20 5/24 5/28

CHAPTER 9: SOUND GENERATOR

56 EPSON S1C60N07 TECHNICAL MANUAL

BZFQ0–2

ENON

ENVRST

ENVRT

R43 (register)

t01

t02

t03

t04

t05

t06

t07

t01 t11

t12 t13 t14 t15 t16 t17

Level 1 (MAX)

8 (MIN)

BZ signal

duty ratio

No change of duty level

t01

t02–07

= 62.5 msec

–4 t11

t12–17

= 125 msec

–4

Fig. 9.4.1 Digital envelope timing chart

9.5 1-shot Output

In order to cause the buzzer to ring in a short period of time as in the case of key operation check sound,

1-shot output function is built-in. The time duration for buzzer signal to be output (BZ and #BZ) may be

selected by SHOTPW; when "0" is written on SHOTPW, it is set to 31.25 ms and to 62.5 ms when "1"

written.

Actual output operation is performed by writing "1" on BZSHOT; after performing the previously

described writing operation, it synchronizes with the internal 256 Hz signal and buzzer signal is output in

output port R43 (R42).

Moreover, after the set time has lapsed, it synchronizes with the same 256 Hz previously described and the

buzzer signal is automatically turned off. Also, by reading BZSHOT, whether the 1-shot circuit is in

operation or not may be determined with the software.

Figure 9.5.1 shows the timing chart of the 1-shot output.

256 Hz

SHOTPW

BZSHOT • W

(trigger)

BZSHOT • R

(status)

BZ (R43 terminal)

#BZ (R42 terminal)

Fig. 9.5.1 Timing chart of 1-shot output

CHAPTER 9: SOUND GENERATOR

S1C60N07 TECHNICAL MANUAL EPSON 57

9.6 Control of Sound Generator

The control registers for the sound generator are explained below.

Table 9.6.1 Control registers of sound generator

Address Comment

D3 D2 D1 D0 Name Init 1 0

F54H

R40

R/W

R43

R42

R41

R40

Output port (R43)

Buzzer output (BZ)

Output port (R42)

Clock output (FOUT)

[Buzzer inverted output (#BZ)]

Output port (R41)

Output port (R40)

Clock inverted output (#FOUT)

High

Off

High

Off

High

Off

Low

R41R42R43

F74H

BZFQ0

R/W

SHOTPW

BZFQ2

BZFQ1

BZFQ0

1-shot buzzer pulse width

62.5 ms 31.25 ms

BZFQ1BZFQ2SHOTPW

Buzzer frequency selection

F75H

ENVON

BZSHOT

RESET

1-shot buzzer trigger (W)

Status (R)

Envelope reset

Envelope cycle selection

Envelope On/Off

Trigger

BUSY

Reset

1.0 sec

–

READY

–

0.5 sec

Off

ENVRTENVRSTBZSHOT

WR/W

ENVRST

ENVRT

ENVON

BZFQ0–BZFQ2 (F74H [D0–D2], R/W)

Will select the buzzer signal frequency.

Table 9.6.2 Setting of frequencies of buzzer signals

BZFQ2 BZFQ1 BZFQ0 Buzzer frequency (Hz)

0 0 0 4,096.0

0 0 1 3,276.8

0 1 0 2,730.7

0 1 1 2,340.6

1 0 0 2,048.0

1 0 1 1,638.4

1 1 0 1,365.3

1 1 1 1,170.3

At initial reset, 4,096 Hz is selected.

ENVRST (F75H [D2], W)

This is the reset input to make the duty ratio of the buzzer signal the maximum.

When "1" is written: Reset input

When "0" is written: No operation

Reading: Always "0"

When envelope is added to the buzzer signal, by writing "1" on ENVRST, the envelope is reset and duty

ratio becomes maximum. When envelope is not added, or when buzzer signal is not being output, reset

operation is ineffective.

ENVON (F75H [D0], R/W)

This controls adding the envelope to the buzzer signal.

When "1" is written: Envelope added (ON)

When "0" is written: No envelope (OFF)

Reading: Valid

By writing "1" on ENVON, envelope is added to the buzzer signal. Writing "0" means envelope will not

be added.

At initial reset, ENVON is set to "0" and envelope OFF will be selected.

CHAPTER 9: SOUND GENERATOR

58 EPSON S1C60N07 TECHNICAL MANUAL

ENVRT (F75H [D1], R/W)

Selects the attenuation time of the envelope added to the buzzer signal.

When "1" is written: 1.0 sec (125 ms × 7 = 875 ms)

When "0" is written: 0.5 sec (62.5 ms × 7 = 437.5 ms)

Reading: Valid

The attenuation time of digital envelopes is determined by the time change for duty ratio. When "1" is

written on ENVRT, attenuation time is set in 125 ms (8 Hz) units (125 ms × 7 = 875 ms), and in 62.5 ms

(16 Hz) unit (62.5 ms × 7 = 437.5 ms) when "0" is written.

However, there is a maximum error of 4 ms from envelope ON to the first change in both cases.

At initial reset, ENVRT is set to "0".

R43, R42 (F54H [D3, D2], R/W)

Controls the output of the buzzer signals (BZ, #BZ).

When "0" is written: Buzzer signal output

When "1" is written: Low level (DC)

Reading: Valid

When "0" is set on R43, BZ signal is generated from R43 terminal, and if R42 is set to #BZ output, #BZ

signal (inverted signal of BZ) is generated at the same time.

When "1" is set on R43, R43 terminal (R42 too, if #BZ output is selected) becomes of low (V SS) level

output.

However, R42 with #BZ output selected, may be used as a 1-bit general register capable of read/write

function, the data of which register does not affect #BZ (R42 terminal output).

At initial reset, both R43 and R42 are set to "1".

Note: BZ and #BZ output signals may produce hazards during ON/OFF switching.

SHOTPW (F74H [D3], R/W)

Sets the output time duration of the 1-shot buzzer.

When "1" is written: 62.5 ms

When "0" is written: 31.25 ms

Reading: Valid

Output time duration is set to 62.5 ms or 31.25 ms by writing "1" or "0", respectively, on SHOTPW.

At initial reset, SHOTPW is set to "0".

BZSHOT (F75H [D3], W, R)

Controls the output of the 1-shot buzzer.

• During writing operation

When "1" is written: Trigger

When "0" is written: No operation

When "1" is written on BZSHOT, the 1-shot circuit operates and the buzzer signal (BZ and #BZ) is

output.

The 1-shot buzzer operates only when the regular buzzer output is in the OFF (R43 = "1") state and

writing to BZSHOT becomes invalid in the ON (R43 = "0") state.

• During reading operation

When "1" is read: Busy

When "0" is read: Ready

The BZSHOT reads "1" when the 1-shot buzzer is ringing and "0" when it is not ringing. The period of

"1" is from the time of the trigger until the buzzer output is turned OFF.

At initial reset, "0" is read.

CHAPTER 9: SOUND GENERATOR

S1C60N07 TECHNICAL MANUAL EPSON 59

9.7 Programming Notes

(1) The BZ and #BZ signals may generate hazards in the following cases:

• When the content of R43 register is changed, BZ and #BZ signals are switched ON or OFF.

• When the contents of buzzer frequency selection registers (BZFQ0 –BZFQ2) while the buzzer

signal (BZ and #BZ) is being output.

(2) The 1-shot buzzer operates only when the regular buzzer output is in the OFF (R43 = "1") state and

writing to BZSHOT becomes invalid in the ON (R43 = "0") state.

CHAPTER 10: INTERRUPT AND HALT

60 EPSON S1C60N07 TECHNICAL MANUAL

CHAPTER 10 INTERRUPT AND HALT

The S1C60N07 has the following interrupt functions built-in, and masking is possible for each

one.

External interrupt • Input interrupt (1 system)

Internal interrupt • Clock timer interrupt (3 systems)

• Stopwatch timer interrupt (2 systems)

• Programmable timer interrupt (1 system)

To allow the interrupt to function, it is necessary that the interrupt mask register of the required system be

set to "1" (enable) and, at the same time, the interrupt flag be set to "1" (EI).

When interrupt occurs, the interrupt flag is automatically reset to "0" (DI), prohibiting the any consequent

interrupts.

The CPU stops the operating clock when a HALT instruction is executed and then enters the HALT state.

Re-running the CPU from the HALT state requires issuance of interrupt request.

If return through interrupt request is not effective, return is effected from initial reset by the watchdog

timer.

Figure 10.1 shows the configuration of the interrupt circuit.

See the explanations of the relevant circuits for interrupt details.

Interrupt factor flag

Interrupt mask register

Interrupt flag

INT

(interrupt request)

Program counter

(low-order 4 bits)

Interrupt

vector

generation

circuit

ISW1

EISW1

ISW0

EISW0

IT1

EIT1

IT2

EIT2

IT8

EIT8

K00

IK0

IT32

EIT32

IPT

EIPT

EIK00

K01

EIK01

K02

EIK02

K03

EIK03

Fig. 10.1 Configuration of interrupt circuit

CHAPTER 10: INTERRUPT AND HALT

S1C60N07 TECHNICAL MANUAL EPSON 61

10.1 Interrupt Factor Flag and Interrupt Mask

The corresponding interrupt factor flag is set to "1" with the individual interrupt element.

If the following conditions exist, interrupt for the CPU occurs when the interrupt factor flag is set to "1".

• The corresponding interrupt mask regi ster is set at "1" (enable).

• The interrupt flag is set at "1" (EI).

The interrupt factor flag is reset to "0" at the read-only register by reading the data.

Be sure that the interrupt factor flag reading is done with the interrupt in the DISABLE state (DI). Reading

the interrupt factor flag while in the ENABLE state (EI) may cause malfunction.

At initial reset, the interrupt factor flag is reset to "0".

The interrupt can be masked by the corresponding interrupt mask register.

The interrupt mask register is a register capable of read/write operation; by writing "1", it is enabled

(interrupt is allowed) and by writing "0", it is masked (interrupt is prohibited).

Be sure that writing to the interrupt mask register is done with the interrupt in the DISABLE state (DI).

Writing to the interrupt mask register while in the ENABLE state (EI) may cause malfunction.

At initial reset, the interrupt mask register is set to "0".

The interrupt factor flag is set to "1" by interrupt factor even if the interrupt is masked. (The input

interrupt factor flag IK0 will be eliminated.)

Table 10.1.1 shows the correspondence between interrupt factor flags and interrupt mask registers.

Table 10.1.1 Interrupt factor flags and interrupt mask registers

Interrupt factor Interrupt factor flag Interrupt mask register

Falling edge of clock timer (1 Hz) IT1 (F00H [D3]) EIT1 (F10H [D3])

Falling edge of clock timer (2 Hz) IT2 (F00H [D2]) EIT2 (F10H [D2])

Falling edge of clock timer (8 Hz) IT8 (F00H [D1]) EIT8 (F10H [D1])

Falling edge of clock timer (32 Hz) IT32 (F00H [D0]) EIT32 (F10H [D0])

Overflow of stopwatch timer (SWH) (1 Hz) ISW1 (F01H [D1]) EISW1 ( F11H [D1])

Overflow of stopwatch timer (SWL) (10 Hz) ISW0 (F01H [D0]) EISW0 ( F11H [D0])

Changing of input (K00– K03) status IK0 (F04H [D0]) EIK03 (F14H [D3])

EIK02 (F14H [D2])

EIK01 (F14H [D1])

EIK00 (F14H [D0])

Counter value of programmable timer = 00H IPT (F02H [D0]) EIPT (F12H [D0])

CHAPTER 10: INTERRUPT AND HALT

62 EPSON S1C60N07 TECHNICAL MANUAL

10.2 Interrupt Vector

When an interrupt request is issued to the CPU, the CPU starts interrupt processing.

Interrupt processing is accomplished by the following steps after the instruction being executed is

completed.

1. The address (value of the program counter) of the program which should be run next is saved in the

stack area (RAM).

2. The vector address (1 page 02H–0CH) for each interrupt request is set to the program counter.

3. Branch instruction written to the vector is effected (branch to software interrupt processing routine).

Note: Time equivalent to 12 cycles of CPU system clock is required for steps 1 and 2.

The interrupt request and interrupt vector correspondence is shown in Table 10.2.1.

Table 10.2.1 Interrupt request and interrupt vectors

Interrupt vector

(PCP and PCS) Interrupt request Priority

102H Clock timer interrupt Low

104H Stopwatch timer interrupt ↑

106H Input (K00–K03) interrupt ↓

10CH Programmable timer interrupt High

When multiple interrupts simultaneously occur, the high priority vector address is set to the program

counter.

10.3 Programming Notes

(1) The interrupt factor flag is set when the interrupt conditions are established, regardless of the setting

of the interrupt mask register. Note, however, that the input interrupt factor flag (IK0) will be

eliminated.

(2) When an interrupt occurs, the interrupt flag will be reset by the hardware and it will become DI status.

After completion of the interrupt processing, set to the EI status through the software as needed.

Moreover, the nesting level may be set to be programmable by setting to the EI state at the beginning

of the interrupt processing routine.

(3) The interrupt factor flags must always be reset before setting the EI status. When the interrupt mask

the interrupt factor flag.

(4) The interrupt factor flag will be reset by reading through the software. Because of this, when multiple

interrupt factor flags are to be assigned to the same address, perform the flag check after the contents

of the address has been stored in the RAM. Direct checking with the FAN instruction will cause all the

interrupt factor flag to be reset.

(5) Be sure that the interrupt factor flag reading is done with the interrupt in the DISABLE state (DI).

Reading the interrupt factor flag while in the ENABLE state (EI) may cause malfunction.

(6) Be sure that writing to the interrupt mask register is done with the interrupt in the DISABLE state (DI).

Writing to the interrupt mask register while in the ENABLE state (EI) may cause malfunction.

(7) When multiple interrupts simultaneously occur, the high priority vector address is set to the program

counter.

CHAPTER 10: INTERRUPT AND HALT

S1C60N07 TECHNICAL MANUAL EPSON 63

(8) If an interrupt occurs while the CPU is processing some other interrupt request of which the priority is

lower than the new one but the CPU has not fetched the interrupt vector, the CPU may shift to a vector

address (one of among 102H, 104H, 106H and 10CH) that is different from the new interrupt.

Therefore, make sure the interrupt factor flag has been set immediately after the branch instruction

stored in the vector address is executed and quit the interrupt processing if it has not been set.

Furthermore, place a branch instruction for executing the interrupt processing routine in the vector

address 10CH because the CPU may shift to that address. By setting the start address of the

programmable timer interrupt processing routine as the branch destination, the priority level by

hardware can be maintained.

If the program does not have the individual proc essing routine for each interrupt (for example, in the

case of all interrupts using the same processing routine in which the type of interrupt is judged by

reading the interrupt flags, or in the case of the main routine checking all the interrupt flags by

branching the flow the RET instruction stored in all the vector address), place the instruction the same

as the other interrupt vectors in address 10CH.

When the interrupt function is not used, it is not necessary to pay attention to the above mentioned

precautions.

CHAPTER 11: SUMMARY OF NOTES

64 EPSON S1C60N07 TECHNICAL MANUAL

CHAPTER 11 SUMMARY OF NOTES

11.1 Notes for Low Current Consumption

The S1C60N07 contains control registers for each of the circuits so that current consumption can be

lowered. These control registers lower the current consumption through programs that operate the

circuits at the minimum levels.

The following text explains the circuits that can control operation and their control registers. Refer to

these when putting programs together.

Table 11.1.1 Circuits and control registers

Circuits (and Items) Control registers Order of consumed current

CPU HALT instruction See electrical characteristics (Chapter 13)

CPU operation frequency CLKCHG, OSCC See electrical characteristics (Chapter 13)

Internal regulated voltage VSC0, VSC1 See electrical characteristics (Chapter 13)

Heavy load protection mode HLMOD See electrical characteristics (Chapter 13)

Below are the circuit status at initial reset.

CPU: Operating

CPU operating frequency: OSC1 side (CLKCHG = "0"),

OSC3 oscillation circuit is stopped (OSCC = "0")

Internal regulated voltage: -1.2 V (VSC0, VSC1 = "0")

When CR oscillation is selected by mask option, the internal regulated

voltage becomes -2.1 V.

Heavy load protection mode: Normal operating mode (HLMOD = "0")

Also, be careful about panel selection because the current consumption can differ by the order of several

µA on account of the LCD panel characteristics.

CHAPTER 11: SUMMARY OF NOTES

S1C60N07 TECHNICAL MANUAL EPSON 65

11.2 Summary of Notes by Function

Here, the cautionary notes are summed up by function category. Keep these notes well in mined when

programming.

Memory

Memory is not mounted in unused area within the memory map and in memory area not indicated in this

manual. For this reason, normal operation cannot be assured for programs that have been prepared with

access to these areas.

Heavy load protection mode

(1) When driving heavy loads, set it to heavy load protection mode. Unless it is necessary, be careful not

to set the heavy load protection mode with the software.

(2) Perform heavy load driving only after setting up at least 1 ms wait time through the software, after

switching to the heavy load protection mode. (See Figure 3.2.2.1.)

(3) When the heavy load pr otection mode is to canceled after completion of heavy load driving, set up at

least 2 seconds wait time through the software. (See Figure 3.2.2.1.)

Watchdog timer

(1) The watchdog timer must reset within 3-second cycles by the software.

(2) When the clock timer is reset (TMRST ← "1"), the watchdog timer is counted up; reset the watchdog

immediately after if necessary.

Oscillation circuit