INTEGRATED CIRCUITS 74LV574 Octal D-type flip-flop; positive edge-trigger (3-State) Product specification Supersedes data of 1997 Feb 03 IC24 Data Handbook 1998 Jun 10 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger (3-State) FEATURES 74LV574 DESCRIPTION * Wide operating voltage: 1.0 to 5.5V * Optimized for Low Voltage applications: 1.0 to 3.6V * Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V * Typical VOLP (output ground bounce) 0.8V at VCC = 3.3V, The 74LV574 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT574. The 74LV574 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and non-inverting 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. Tamb = 25C * Typical VOHV (output VOH undershoot) 2V at VCC = 3.3V, The eight flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. Tamb = 25C * Common 3-State output enable input * Output capability: bus driver * ICC category: MSI When OE is LOW, the contents of the eight flip-flops is available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. QUICK REFERENCE DATA GND = 0V; Tamb = 25C; tr =tf 2.5 ns SYMBOL PARAMETER tPHL/tPLH Propagation delay CP to Qn fmax Maximum clock frequency CI Input capacitance CPD Power dissipation capacitance per flip-flop CONDITIONS TYPICAL UNIT 13 ns CL = 15pF VCC = 3.3V CL = 15pF, VCC = 3.3V 77 MHz 3.5 pF 25 pF Notes 1 and 2 NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in W) PD = CPD VCC2 x fi (CL VCC2 fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL VCC2 fo) = sum of the outputs. 2. The condition is VI = GND to VCC ORDERING AND PACKAGE INFORMATION TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 20-Pin Plastic DIL -40C to +125C 74LV574 N 74LV574 N SOT146-1 20-Pin Plastic SO -40C to +125C 74LV574 D 74LV574 D SOT163-1 20-Pin Plastic SSOP Type II -40C to +125C 74LV574 DB 74LV574 DB SOT339-1 20-Pin Plastic TSSOP Type I -40C to +125C 74LV574 PW 74LV574PW DH SOT360-1 PACKAGES PIN DESCRIPTION FUNCTION TABLE PIN NUMBER SYMBOL FUNCTION 1 OE Output enabled input (active LOW) 2, 3, 4, 5, 6, 7, 8, 9 D0-D7 Data inputs 19, 18, 17, 16, 15, 14, 13, 12 Q0-Q7 3-State flip-flop outputs 10 GND Ground (0V) 11 CP Clock input (LOW-to-HIGH, edge-triggered) 20 VCC Positive supply voltage H h L l Z 1998 Jun 10 2 OPERATING MODES CP Dn INTERNAL FLIP-FLOPS OUTPUTS OE INPUTS Load and read register L L l h L H L H Load register and disable outputs H H l h L H Z Z Q0 to Q7 = HIGH voltage level = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition = LOW voltage level = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition = High impedance OFF-state = LOW-to-HIGH clock transition 853-1990 19545 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger (3-State) PIN CONFIGURATION LOGIC SYMBOL (IEEE/IEC) 11 OE 74LV574 1 20 VCC D0 2 19 Q0 D1 3 18 Q1 D2 4 17 Q2 D3 5 16 Q3 D4 6 15 Q4 D5 7 14 Q5 D6 8 13 Q6 D7 9 12 Q7 GND 10 11 CP 1 2 C1 EN 19 1D 3 18 4 17 5 16 6 15 7 14 8 13 9 12 SV00714 SV00716 LOGIC SYMBOL FUNCTIONAL DIAGRAM 11 2 D0 3 CP 2 D0 Q0 19 3 D1 Q1 18 Q2 17 Q3 16 Q4 15 Q0 19 4 D2 D1 Q1 18 5 D3 4 D2 Q2 17 5 D3 Q3 16 6 D4 Q4 15 7 D5 Q5 14 8 D6 Q6 13 9 D7 Q7 12 OE FF1 to FF8 3-STATE OUTPUTS 6 D4 7 D5 Q5 14 8 D6 Q6 13 9 D7 Q7 12 11 CP 1 OE 1 SV00715 1998 Jun 10 SV00717 3 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger (3-State) 74LV574 LOGIC DIAGRAM D0 D1 D Q D2 D CP Q D CP FF1 D3 Q D CP FF2 D4 Q D CP FF3 D5 Q D CP FF4 D6 Q D CP FF5 D7 Q D CP FF6 Q CP FF7 FF8 CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 SV00342 ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) PARAMETER SYMBOL VCC DC supply voltage IIK DC input diode current IOK IO IGND, ICC Tstg PTOT CONDITIONS RATING UNIT -0.5 to +7.0 V VI < -0.5 or VI > VCC + 0.5V 20 mA DC output diode current VO < -0.5 or VO > VCC + 0.5V 50 mA DC output source or sink current - bus driver outputs -0.5V < VO < VCC + 0.5V 35 mA 70 mA -65 to +150 C DC VCC or GND current for types with -bus driver outputs Storage temperature range Power dissipation per package -plastic DIL -plastic mini-pack (SO) -plastic shrink mini-pack (SSOP and TSSOP) for temperature range: -40 to +125C above +70C derate linearly with 12mW/K above +70C derate linearly with 8 mW/K above +60C derate linearly with 5.5 mW/K 750 500 400 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER VI Input voltage VO Output voltage Tamb tr, tf CONDITIONS MIN TYP. MAX UNIT See Note1 1.0 3.3 5.5 V 0 - VCC V 0 - VCC V +85 +125 C 500 200 100 50 ns/V DC supply voltage Operating ambient temperature range in free air Input rise and fall times See DC and AC characteristics VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V to 5.5V -40 -40 - - - - - - - - NOTES: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V. 1998 Jun 10 4 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger (3-State) 74LV574 DC CHARACTERISTICS FOR THE LV FAMILY Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER -40C to +85C TEST CONDITIONS MIN VIH VIL HIGH level Input voltage LOW level Input voltage TYP1 HIGH level output voltage; BUS driver outputs LOW level output voltage all outputs out uts voltage; VOL LOW level output voltage; BUS driver outputs MIN 0.9 0.9 VCC = 2.0V 1.4 1.4 VCC = 2.7 to 3.6V 2.0 2.0 VCC = 4.5 to 5.5V 0.7*VCC UNIT MAX V 0.7*VCC VCC = 1.2V 0.3 0.3 VCC = 2.0V 0.6 0.6 VCC = 2.7 to 3.6V 0.8 0.8 0.3*VCC 0.3*VCC VCC = 1.2V; VI = VIH or VIL; -IO = 100A VOH MAX VCC = 1.2V VCC = 4.5 to 5.5 HIGH level output voltage out uts voltage; all outputs -40C to +125C V 1.2 VCC = 2.0V; VI = VIH or VIL; -IO = 100A 1.8 2.0 1.8 VCC = 2.7V; VI = VIH or VIL; -IO = 100A 2.5 2.7 2.5 VCC = 3.0V; VI = VIH or VIL; -IO = 100A 2.8 3.0 2.8 VCC = 4.5V;VI = VIH or VIL; -IO = 100A 4.3 4.5 4.3 VCC = 3.0V;VI = VIH or VIL; -IO = 8mA 2.40 2.82 2.20 VCC = 4.5V;VI = VIH or VIL; -IO = 16mA 3.60 4.20 3.50 V VCC = 1.2V; VI = VIH or VIL; IO = 100A VCC = 2.0V; VI = VIH or VIL; IO = 100A 0 0 0.2 0.2 VCC = 2.7V; VI = VIH or VIL; IO = 100A 0 0.2 0.2 VCC = 3.0V;VI = VIH or VIL; IO = 100A 0 0.2 0.2 VCC = 4.5V;VI = VIH or VIL; IO = 100A 0 0.2 0.2 VCC = 3.0V;VI = VIH or VIL; IO = 8mA 0.20 0.40 0.50 VCC = 4.5V;VI = VIH or VIL; IO = 16mA 0.35 0.55 0.65 1.0 1.0 A 5 10 A V Input leakage current VCC = 5.5V; VI = VCC or GND IOZ 3-State output OFF-state current VCC = 5.5V; VI = VIH or VIL; VO = VCC or GND ICC Quiescent supply current; MSI VCC = 5.5V; VI = VCC or GND; IO = 0 20.0 160 A ICC Additional quiescent supply current per input VCC = 2.7V to 3.6V; VI = VCC -0.6V 500 850 A II NOTE: 1. All typical values are measured at Tamb = 25C. 1998 Jun 10 5 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger (3-State) 74LV574 AC CHARACTERISTICS GND = 0V; tr = tf 2.5ns; CL = 50pF; RL = 1K SYMBOL tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tW tsu th fmax PARAMETER Propagation delay CP to Qn 3-State 3 State output out ut enable time OE to t Q Qn 3 State output 3-State out ut disable time OE to t Q Qn Clock pulse width HIGH or LOW Set-up time Dn to CP Hold time Dn to CP Maximum clock ulse frequency pulse WAVEFORM VCC(V) MIN TYP 1.2 - 2.0 - LIMITS -40 to +125 C MAX MIN 80 - - - 27 34 - 43 2.7 - 20 25 - 31 - 152 20 - 25 4.5 to 5.5 - - 17 - 21 1.2 - 70 - - - 2.0 - 24 34 - 43 2.7 - 18 25 - 31 3.0 to 3.6 - 132 20 - 25 4.5 to 5.5 - - 17 - 21 1.2 - 75 - - - 2.0 - 27 27 - 34 Figure 2, 4 2.7 - 21 21 - 26 3.0 to 3.6 - 162 17 - 21 4.5 to 5.5 - - 15 - 18 2.0 34 9 - 41 - 2.7 25 6 - 30 - 3.0 to 3.6 20 52 - 24 - 1.2 - 10 - - - 2.0 22 4 - 26 - 2.7 16 3 - 19 - 3.0 to 3.6 13 22 - 15 - 1.2 - -10 - - - 2.0 5 -4 - 5 - 2.7 5 -3 - 5 - 3.0 to 3.6 5 -22 - 5 - 2.0 15 40 - 12 - 2.7 19 58 - 16 - 3.0 to 3.6 24 702 - 20 - Figure 2, 4 Figure 1 Figure 3 Figure 3 Figure 1 6 UNIT MAX 3.0 to 3.6 Figure 1, 4 NOTE: 1. Unless otherwise stated, all typical values are at Tamb = 25C. 2. Typical value measured at VCC = 3.3V. 1998 Jun 10 LIMITS -40 to +85 C CONDITION ns ns ns ns ns ns MHz Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger (3-State) 74LV574 AC WAVEFORMS VM = 1.5V at VCC 2.7V and 3.6V VM = 0.5 * VCC at VCC 2.7V and 4.5V VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3V at VCC 2.7V and 3.6V VX = VOL + 0.1VCC at VCC < 2.7V and 4.5V VY = VOH - 0.3V at VCC 2.7V and 3.6V VY = VOH - 0.1VCC at VCC < 2.7V and 4.5V VI VM(1) CP INPUT GND t su IIII IIIIII II IIII IIIIII II IIII IIIIIIII th VI Dn INPUT VM GND 1/fmax VI CP INPUT t su th VOH VM GND Qn OUTPUT VM VOL tW NOTE: the shaded areas indicate when the input is permitted to change for predictable output performance. tPLH tPHL VOH Qn OUTPUT SV00345 VM Figure 3. VOL NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SV00718 Figure 1. Clock (CP) to output (Qn) propagation delays, the clock pulse (CP) and the maximum clock pulse frequency TEST CIRCUIT VI OE INPUT Data set-up and hold times for the Dn input to the CP input VM VCC 2 * VCC Open GND GND tPLZ tPZL VCC OUTPUT LOW-to-OFF OFF-to-LOW VM D.U.T. VX VOL RT 50 pF RL = 1k Test Circuit for Outputs VY DEFINITIONS VM RL = Load resistor CL = Load capacitance includes jig and probe capacitiance. RT = Termination resistance should be equal to ZOUT of pulse generators. GND outputs enabled CL tPZH tPHZ VOH OUTPUT HIGH-to-OFF OFF-to-HIGH RL = 1k VO VI PULSE GENERATOR outputs disabled outputs enabled SWITCH POSITION SV00344 S1 VCC tPLH/tPHL Open < 2.7V VCC tPLZ/tPZL 2 * VCC 2.7-3.6V 2.7V tPHZ/tPZH GND TEST Figure 2. 3-state enable and disable times 4.5V VI VCC SV00896 Figure 4. 1998 Jun 10 7 Load circuitry for switching times Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger (3-State) DIP20: plastic dual in-line package; 20 leads (300 mil) 1998 Jun 10 8 74LV574 SOT146-1 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger (3-State) SO20: plastic small outline package; 20 leads; body width 7.5 mm 1998 Jun 10 9 74LV574 SOT163-1 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger (3-State) SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm 1998 Jun 10 10 74LV574 SOT339-1 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger (3-State) TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm 1998 Jun 10 11 74LV574 SOT360-1 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger (3-State) 74LV574 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 print code Document order number: 1998 Jun 10 12 Date of release: 05-96 9397-750-04454