74LV574
Octal D-type flip-flop;
positive edge-trigger (3-State)
Product specification
Supersedes data of 1997 Feb 03
IC24 Data Handbook
1998 Jun 10
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
74LV574Octal D-type flip-flop; positive edge-trigger (3-State)
2
1998 Jun 10 853-1990 19545
FEATURES
•Wide operating voltage: 1.0 to 5.5V
•Optimized for Low V oltage applications: 1.0 to 3.6V
•Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V
•Typical VOLP (output ground bounce) 0.8V at VCC = 3.3V,
Tamb = 25°C
•Typical VOHV (output VOH undershoot) 2V at VCC = 3.3V,
Tamb = 25°C
•Common 3-State output enable input
•Output capability: bus driver
•ICC category: MSI
DESCRIPTION
The 74LV574 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT574.
The 74LV574 is an octal D-type flip–flop featuring separate D-type
inputs for each flip-flop and non-inverting 3-state outputs for bus
oriented applications. A clock (CP) and an output enable (OE) input
are common to all flip-flops.
The eight flip-flops will store the state of their individual D-inputs that
meet the set-up and hold times requirements on the LOW-to-HIGH
CP transition.
When OE is LOW , the contents of the eight flip-flops is available at
the outputs. When OE is HIGH, the outputs go to the high
impedance OFF-state. Operation of the OE input does not affect the
state of the flip-flops.
QUICK REFERENCE DATA
GND = 0V ; Tamb = 25°C; tr =tf 2.5 ns
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
tPHL/tPLH Propagation delay
CP to Qn
CL = 15pF
VCC = 3.3V 13 ns
fmax Maximum clock frequency CL = 15pF, VCC = 3.3V 77 MHz
CIInput capacitance 3.5 pF
CPD Power dissipation capacitance per flip-flop Notes 1 and 2 25 pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD VCC2 x fi (CL VCC2 fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V ;
(CL VCC2 fo) = sum of the outputs.
2. The condition is VI = GND to VCC
ORDERING AND PACKAGE INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH
AMERICA NORTH AMERICA PKG. DWG. #
20-Pin Plastic DIL –40°C to +125°C74LV574 N 74LV574 N SOT146-1
20-Pin Plastic SO –40°C to +125°C74LV574 D 74LV574 D SOT163-1
20-Pin Plastic SSOP Type II –40°C to +125°C74LV574 DB 74LV574 DB SOT339-1
20-Pin Plastic TSSOP Type I –40°C to +125°C74LV574 PW 74LV574PW DH SOT360-1
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
1 OE Output enabled input (active LOW)
2, 3, 4, 5,
6, 7, 8, 9 D0–D7 Data inputs
19, 18, 17, 16,
15, 14, 13, 12 Q0–Q7 3-State flip-flop outputs
10 GND Ground (0V)
11 CP Clock input (LOW-to-HIGH,
edge-triggered)
20 VCC Positive supply voltage
FUNCTION TABLE
OPERATING INPUTS INTERNAL OUTPUTS
MODES OE CP Dn FLIP-FLOPS Q0 to Q7
Load and read
register L
L↑
↑l
hL
HL
H
Load register and
disable outputs H
H↑
↑l
hL
HZ
Z
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the
LOW-to-HIGH CP transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the
LOW-to-HIGH CP transition
Z = High impedance OFF-state
↑= LOW–to–HIGH clock transition
Philips Semiconductors Product specification
74LV574Octal D-type flip-flop; positive edge-trigger (3-State)
1998 Jun 10 3
PIN CONFIGURATION
SV00714
1
2
3
4
5
6
7
8
9
10
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND CP
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
VCC
20
19
18
17
16
15
14
13
12
11
LOGIC SYMBOL
SV00715
CP
11
Q7
2D0 Q0 19
9D7 12
8D6 Q6 13
7D5 Q5 14
6D4 Q4 15
5D3 Q3 16
4D2 Q2 17
3D1 Q1 18
1
OE
LOGIC SYMBOL (IEEE/IEC)
SV00716
19
18
17
16
15
14
13
12
2
3
4
5
6
7
8
9
C1
EN
1D
11
1
FUNCTIONAL DIAGRAM
SV00717
FF1 to FF8 3–STATE
OUTPUTS
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D0
D1
D2
D3
D4
D5
D6
D7
CP
1
19
18
17
16
15
14
13
12
2
3
4
5
6
7
8
9
11
OE
Philips Semiconductors Product specification
74LV574Octal D-type flip-flop; positive edge-trigger (3-State)
1998 Jun 10 4
LOGIC DIAGRAM
SV00342
D
D0
Q0
D1 D2 D3 D4 D5 D6 D7
Q1 Q2 Q3 Q4 Q5 Q6 Q7
CP
OE
Q
CP
D Q
CP
D Q
CP
D Q
CP
D Q
CP
D Q
CP
D Q
CP
D Q
CP
FF1 FF2 FF3 FF4 FF5 FF6 FF7 FF8
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC DC supply voltage –0.5 to +7.0 V
±IIK DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA
±IOK DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA
±IODC output source or sink current
– bus driver outputs –0.5V < VO < VCC + 0.5V 35 mA
±IGND,
±ICC
DC VCC or GND current for types with
–bus driver outputs 70 mA
Tstg Storage temperature range –65 to +150 °C
PTOT
Power dissipation per package
–plastic DIL
–plastic mini-pack (SO)
–plastic shrink mini-pack (SSOP and TSSOP)
for temperature range: –40 to +125°C
above +70°C derate linearly with 12mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
750
500
400 mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS MIN TYP. MAX UNIT
VCC DC supply voltage See Note11.0 3.3 5.5 V
VIInput voltage 0 – VCC V
VOOutput voltage 0 – VCC V
Tamb Operating ambient temperature range in free
air See DC and AC
characteristics –40
–40 +85
+125 °C
tr, tfInput rise and fall times VCC = 1.0V to 2.0V
VCC = 2.0V to 2.7V
VCC = 2.7V to 3.6V
VCC = 3.6V to 5.5V
–
–
–
–
–
–
–
–
500
200
100
50 ns/V
NOTES:
1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
Philips Semiconductors Product specification
74LV574Octal D-type flip-flop; positive edge-trigger (3-State)
1998 Jun 10 5
DC CHARACTERISTICS FOR THE LV FAMILY
Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS
SYMBOL PARAMETER TEST CONDITIONS -40°C to +85°C -40°C to +125°CUNIT
MIN TYP1MAX MIN MAX
VCC = 1.2V 0.9 0.9
VIH
HIGH level Input VCC = 2.0V 1.4 1.4
V
V
IH voltage VCC = 2.7 to 3.6V 2.0 2.0
V
VCC = 4.5 to 5.5V 0.7*VCC 0.7*VCC
VCC = 1.2V 0.3 0.3
VIL
LOW level Input VCC = 2.0V 0.6 0.6
V
V
IL voltage VCC = 2.7 to 3.6V 0.8 0.8
V
VCC = 4.5 to 5.5 0.3*VCC 0.3*VCC
VCC = 1.2V ; VI = VIH or VIL; –IO = 100µA 1.2
HIGH level output
VCC = 2.0V ; VI = VIH or VIL; –IO = 100µA 1.8 2.0 1.8
HIGH
l
eve
l
ou
t
pu
t
voltage
;
all out
p
uts
VCC = 2.7V ; VI = VIH or VIL; –IO = 100µA 2.5 2.7 2.5
VOH
voltage
all
out uts
VCC = 3.0V ; VI = VIH or VIL; –IO = 100µA 2.8 3.0 2.8
V
VOH
VCC = 4.5V ;VI = VIH or VIL; –IO = 100µA 4.3 4.5 4.3
V
HIGH level output
voltage
;
BUS driver
VCC = 3.0V ;VI = VIH or VIL; –IO = 8mA 2.40 2.82 2.20
voltage;
BUS
driver
outputs VCC = 4.5V ;VI = VIH or VIL; –IO = 16mA 3.60 4.20 3.50
VCC = 1.2V ; VI = VIH or VIL; IO = 100µA 0
LOW level output
VCC = 2.0V ; VI = VIH or VIL; IO = 100µA 0 0.2 0.2
LOW
l
eve
l
ou
t
pu
t
voltage
;
all out
p
uts
VCC = 2.7V ; VI = VIH or VIL; IO = 100µA 0 0.2 0.2
VOL
voltage
all
out uts
VCC = 3.0V ;VI = VIH or VIL; IO = 100µA 0 0.2 0.2
V
VOL
VCC = 4.5V ;VI = VIH or VIL; IO = 100µA 0 0.2 0.2
V
LOW level output
voltage
;
BUS driver
VCC = 3.0V ;VI = VIH or VIL; IO = 8mA 0.20 0.40 0.50
voltage;
BUS
driver
outputs VCC = 4.5V ;VI = VIH or VIL; IO = 16mA 0.35 0.55 0.65
IIInput leakage
current VCC = 5.5V ; VI = VCC or GND 1.0 1.0 µA
IOZ 3-State output
OFF-state current VCC = 5.5V ; VI = VIH or VIL;
VO = VCC or GND 5 10 µA
ICC Quiescent supply
current; MSI VCC = 5.5V ; VI = VCC or GND; IO = 0 20.0 160 µA
∆ICC Additional
quiescent supply
current per input VCC = 2.7V to 3.6V; VI = VCC –0.6V 500 850 µA
NOTE:
1. All typical values are measured at Tamb = 25°C.
Philips Semiconductors Product specification
74LV574Octal D-type flip-flop; positive edge-trigger (3-State)
1998 Jun 10 6
AC CHARACTERISTICS
GND = 0V ; tr = tf ≤ 2.5ns; C L = 50pF; RL = 1KΩ
SYMBOL PARAMETER WAVEFORM CONDITION LIMITS
–40 to +85 °CLIMITS
–40 to +125 °CUNIT
VCC(V) MIN TYP MAX MIN MAX
1.2 – 80 – – –
Propagation delay
2.0 – 27 34 – 43
tPHL/tPLH
P
ropaga
ti
on
d
e
l
ay
CP to Qn
Figure 1, 4 2.7 – 20 25 – 31 ns
CP
to
Qn
3.0 to 3.6 – 15220 – 25
4.5 to 5.5 – – 17 – 21
1.2 – 70 – – –
3-State output 2.0 – 24 34 – 43
tPZH/tPZL
3 State
out ut
enable time
OE tQ
Figure 2, 4 2.7 – 18 25 – 31 ns
OE
to
Q
n3.0 to 3.6 – 13220 – 25
4.5 to 5.5 – – 17 – 21
1.2 – 75 – – –
3-State output 2.0 – 27 27 – 34
tPHZ/tPLZ
3 State
out ut
disable time
OE tQ
Figure 2, 4 2.7 – 21 21 – 26 ns
OE
to
Q
n3.0 to 3.6 – 16217 – 21
4.5 to 5.5 – – 15 – 18
Clock pulse width
2.0 34 9 – 41 –
tW
Cl
oc
k
pu
l
se w
idth
HIGH or LOW
Figure 1 2.7 25 6 – 30 – ns
HIGH
or
LOW
3.0 to 3.6 20 52– 24 –
1.2 – 10 – – –
t
Set-up time
Figure 3
2.0 22 4 – 26 –
ns
t
su Dn to CP
Figure
3
2.7 16 3 – 19 –
ns
3.0 to 3.6 13 22– 15 –
1.2 – –10 – – –
th
Hold time
Figure 3
2.0 5 –4 – 5 –
ns
t
hDn to CP
Figure
3
2.7 5 –3 – 5 –
ns
3.0 to 3.6 5 –22– 5 –
Maximum clock
2.0 15 40 – 12 –
fmax
M
ax
i
mum c
l
oc
k
p
ulse frequency
Figure 1 2.7 19 58 – 16 – MHz
ulse
frequency
3.0 to 3.6 24 702– 20 –
NOTE:
1. Unless otherwise stated, all typical values are at Tamb = 25°C.
2. Typical value measured at VCC = 3.3V.
Philips Semiconductors Product specification
74LV574Octal D-type flip-flop; positive edge-trigger (3-State)
1998 Jun 10 7
AC WAVEFORMS
VM = 1.5V at VCC 2.7V and 3.6V
VM = 0.5 * VCC at VCC 2.7V and 4.5V
VOL and VOH are the typical output voltage drop that occur with the
output load.
VX = VOL + 0.3V at VCC 2.7V and 3.6V
VX = VOL + 0.1VCC at VCC < 2.7V and 4.5V
VY = VOH – 0.3V at VCC 2.7V and 3.6V
VY = VOH – 0.1VCC at VCC < 2.7V and 4.5V
SV00718
GND
VOL
VI
VOH
VM
CP INPUT
Qn OUTPUT VM
tPLH
tPHL
1/fmax
tW
Figure 1. Clock (CP) to output (Qn) propagation delays, the
clock pulse (CP) and the maximum clock pulse frequency
outputs
disabled
SV00344
VI
OE INPUT
GND
VCC
OUTPUT
LOW-to-OFF
OFF-to-LOW
VOL
VOH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
VM
tPLZ
tPHZ
tPZL
VY
outputs
enabled outputs
enabled
VX
VM
tPZH
VM
Figure 2. 3-state enable and disable times
tsu
tsu
ÏÏ
ÏÏ
ÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
SV00345
CP INPUT
Dn INPUT
Qn OUTPUT VM
th
VM
VM(1)
th
VI
GND
VI
GND
VOH
VOL
NOTE: the shaded areas indicate when the input is permitted to change
for predictable output performance.
Figure 3. Data set-up and hold times for the Dn input to the CP
input
NOTE:
The shaded areas indicate when the input is permitted to change for
predictable output performance.
TEST CIRCUIT
SWITCH POSITION
PULSE
GENERATOR
RT
VID.U.T.
VO
CLRL = 1k
VCC
Test Circuit for Outputs
DEFINITIONS
VCC VI
< 2.7V VCC
TEST
tPLH/tPHL
RT = Termination resistance should be equal to ZOUT of pulse generators.
2.7V
2.7–3.6V
4.5V VCC
50 pF
SV00896
S1
tPLZ/tPZL
tPHZ/tPZH
Open
2 * VCC
GND
RL = 1k
Open
2 * VCC
GND
RL = Load resistor
CL = Load capacitance includes jig and probe capacitiance.
Figure 4. Load circuitry for switching times
Philips Semiconductors Product specification
74LV574Octal D-type flip-flop; positive edge-trigger (3-State)
1998 Jun 10 8
DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1
Philips Semiconductors Product specification
74LV574Octal D-type flip-flop; positive edge-trigger (3-State)
1998 Jun 10 9
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
Philips Semiconductors Product specification
74LV574Octal D-type flip-flop; positive edge-trigger (3-State)
1998 Jun 10 10
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
Philips Semiconductors Product specification
74LV574Octal D-type flip-flop; positive edge-trigger (3-State)
1998 Jun 10 11
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
Philips Semiconductors Product specification
74LV574Octal D-type flip-flop; positive edge-trigger (3-State)
1998 Jun 10 12
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
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or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
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Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
DEFINITIONS
Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 05-96
Document order number: 9397-750-04454
