M34D64 - STMicroelectronics - Datasheet.Directory

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PRELIMINARY DATA

November 2000

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M34D64

64 Kbit Serial I²C Bus EEPROM

With Hardware Write Control on Top Quarter of Memory

■Compatib le wit h I2C Extended Addressing

■Two Wire I2C Serial Interface

Supports 400 kHz Protocol

■2.5V to 5.5V Single Supply Voltage:

■Hardware Write Control of the top quarter of

memory

■BYTE and PAG E WRIT E (u p to 32 Byte s)

■RANDOM and SEQ UEN TIAL READ Modes

■Self-Tim ed P ro gr ammin g Cyc le

■Automatic Addres s Incrementing

■Enhanced E SD/La tch-Up Behavior

■More than 1 Million Erase/Write Cycles

■More than 40 Year Data Retention

DESCRIPTION

These electrically erasable programmable

memory (EEPROM) devices are fabricated with

STMicroelectronics’ High Endurance, CMOS

technology. This guarantees an endurance

typically well above one million Erase/Write

cycles, with a data retention of 40 years. The

memories are organized as 8192x8 bits, and

operate down to 2.5 V .

These memory devices are compatible with the

I2C extended memory standard. This is a two wire

serial interface that u ses a bi-directiona l data bus

and serial clock. The memory carries a built-in 4- Figure 1. Logic Diagram

AI02850B

E0-E2 SDA

VCC

M34D64

SCL

VSS

Table 1. Signal Names

E0, E1, E2 Chip Enable Inputs

SDA Serial Data/Address Input/

Output

SCL Serial Clock

WC Write Control

VCC Supply Volta ge

VSS Ground

SO8 (MN)

150 mil width

M34D64

2/15

bit unique Device Type Identifier code (1010) in

accordance with the I2C bus defi niti on.

The memory behaves as a slave device in t he I2C

protocol, with all memory operat ions sync hronized

by the serial clock. Read and Write operations are

initiated by a START condition, generated by the

bus master. T he START condit ion is foll owed by a

Device Select Code and RW bit (as described in

Table 3) , terminated by an acknowledge bit.

When writing data to the memory, the memory

inserts an acknowledge bit during the 9th bit time ,

following the bus master’s 8-bit transmission.

When data is read by the bus master, the bus

master ackn owledg es t he receipt of t he data b yte

in the same way. Data transfers are terminated by

a STOP condition after an Ack for WRITE, and

after a NoAck for READ.

Power On Reset: VCC Lock-Out Write Pr otect

In order to prevent data corruption and inadvertent

write operations during power up, a Power On

Reset (POR) circuit is included. The internal reset

is held active until the VCC voltage has reached

the POR threshold value, and all operations are

disabled – the device will not respond to any

command. In the same way, when VCC drops from

the operating voltage, below the POR threshold

value, all operations are disabled and the device

will not respond to any command. A stable and

valid VCC must be applied before applying any

logic signal.

SIGNAL DESCRIPTION

Serial Clock (SCL)

The SCL input pin is used to strobe all data in and

out of the mem ory. In applications where this line

is used by slaves to synchronize the bus to a

slower clock, the master must have an open drain

output, and a pull-up resistor must be connected

from the SC L line to VCC. ( F igure 3 indicates how

Figure 2A. DIP Connections

Figu re 2B . SO C on ne cti ons

SDAVSS SCL

WCE1

E0 VCC

AI02851B

M34D64

AI02852B

5SDAVSS SCL

WCE1

E0 VCC

M34D64

Table 2. Absolute Maximum Ratings 1

Note: 1. Exc ept for t he rating “Operating Temperatu re Range”, stresse s above those listed in the T abl e “Abs ol ute Maximum Ratings” m ay

cause permanent damage to the device. These are stress ratings only, and operat ion of the dev ice at t hese or any other conditions

above thos e ind i cated in the Operatin g secti ons of this s pecifi cation is not i m plied. Expo sure t o Abso l ute Maxi m um R at i ng condi-

tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.

2. JEDEC Std J E SD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)

Symbol Parameter Value Unit

TAAmbient Operating Temperature –40 to 125 °C

TSTG Storage Temperature –65 to 150 °C

TLEAD Lead Temperature during Soldering SO8: 40 sec 215 °C

VIO Input or Output range –0.6 to 6.5 V

VCC Supply Voltage –0.3 to 6.5 V

VESD Electrostatic Discharge Voltage (Human Body model) 24000 V

3/15

M34D64

the value of the pull-up resistor can be calculated).

In most applications, though, this method of

synchronization is not employed , and so the pull-

up resistor is not necessary, provided that the

master has a push-pull (rather than open drain)

output.

Serial Data (SDA)

The SDA pin is bi-directional, and is used to

transfer data in or out of the memory. It is an open

drain output that may be wire-OR’ed with other

open drain or open collector signals on the bus. A

pull up resistor must be connected from the SDA

bus to VCC. (Figure 3 indicates how the value of

the pull-up resistor can be calculated).

Chip Enable (E2, E1, E0)

These chip enable inputs are used t o set the v alue

that is to be looked f or on the three least significant

bits (b3, b2, b1) of the 7-bit device select code.

These inputs must be tied to VCC or VSS to

establish t he device select code.

Write Control (WC)

The hardware Write Con trol pin (WC) is useful for

protecting the top quarter of the memory (as

shown in Figure 4) from i nadvert ent erase or write.

The Write Control signal is used to enable

(WC=VIL) or disable (WC =VIH) write instructions to

the top quarter of the memory area. When

unconnected, the WC input is internally read as

VIL, and write operations are allow ed.

DEVICE OPERATION

The memory device supports the I2C protocol.

This is summarized in Figure 5, and is compared

with other seria l bu s prot ocols in Application Note

AN1001

. Any device that sends data on to the bus

is defined to be a transmitter, and any dev ice that

reads the data to be a receiver. The device that

controls the dat a t ransfe r is k nown as the master,

and the other as the slave. A data transfer can only

be initiated b y the m aster, which wi ll also provide

the serial clock for synchronization. The memory

device is always a slave device in all

communication.

Start Condition

START is identified by a high to low transition of

the SDA lin e whi le the clock, SCL, i s stab le i n the

Figure 3. Maximum RL Value versu s Bus Capacitance (CBUS) for an I2C Bus

AI01665

VCC

CBUS

SDA

MASTER

SCL CBUS

100

CBUS (pF)

Maximum RP value (kΩ)

10 1000

fc = 400kHz

fc = 100kHz

Figu re 4. Memory M a p s h owi ng Write Co nt ro l

Area

AI03114B

1FFh

Write Controlled

Area

100h

000h

80h

180h

M34D64

4/15

high state. A START condition must precede any

data transfer command. The memory device

continuously monitors (except during a

programming cycle) the SDA and SCL lines for a

START condition, and wi ll not respond unless one

is given.

Stop Condition

STOP is identif ied by a l ow t o hi gh transiti on of the

SDA line while the clock SCL is stable in the high

state. A STOP condition terminates

communication between the memory device and

the bus mast er. A STOP condition at the end of a

Read command, after (and only after) a NoAck,

forces the memory device into its standby stat e. A

STOP condition at the end of a Write command

triggers the internal EEPROM write cycle.

Acknowledge Bit (ACK)

An acknowledge signal is used to indicate a

successful byte transfer. The bus transmitter,

whether it be master or slave, releases the SDA

bus after sendi ng eight bi ts of data. During t he 9th

clock pulse period, the receiver pulls the SDA bus

low to acknowledge the receipt of the eight data

bits.

Data Input

During data input, the memory dev ice samples the

SDA bus signal on the rising edge of the clock,

SCL. For correct device operation, the SDA signal

must be stable during the clock low-to-high

transition, and the data must change

only

when

the SCL line is lo w .

Memory Addressing

To start communication between the bus master

and the slave memory, the master mu st initiate a

START condition. Following this, the master sends

the 8-bit byte, shown in Table 3, on the SDA bus

line (most significant bit first). This consists of the

7-bit Device Select Code, and the 1-bit Read/Write

Designator (RW). The Device Select Code is

Figure 5. I2C Bus Protocol

SCL

SDA

SCL

SDA

START

Condition

SDA

Input SDA

Change

AI00792B

STOP

Condition

123 789

MSB ACK

START

Condition

SCL 123 789

MSB ACK

STOP

Condition

5/15

M34D64

further subdivided into: a 4-bit Device Type

Identifier, and a 3-bit Chip Enable “Address” (E2,

E1 , E0) .

To address the memory array, the 4-bit Device

Type Identifier is 1010b.

If all three chip enable inputs are connected, up to

eight memory devices can be connected on a

single I2C bus. Each one is given a unique 3-bit

code on its Chip Enable inputs. When the Dev ice

Select Code is received on the SDA bus, the

memory o nly responds if the Chip Select Code is

the same as the patt ern applied to its Chip Enable

pins.

The 8th b it is the R W bit. This is set to ‘1’ for read

and ‘0’ for write operations. If a match occurs on

the Device Select Code, the corresponding

memory gives an acknowledgment on the SDA

bus during the 9th bit time. If the memory does not

match the Device Select Code, it deselects itself

from t he bus, and goes into stand-by mode.

There are two modes both for read and write.

These are summarized in Table 6 and described

later. A communication between the master and

the slave is ended with a STO P condition.

Each data byte in the memory has a 16-bit (two

byte wide) address. The Most Significant Byte

(Table 4) is sent first, followed by the Least

significant By te (Table 5). B its b 15 to b0 form the

address of the byte in memory. Bits b15 to b13 are

treated as Don’t Care bit s.

Write Operations

Following a ST ART con dition t he master sen ds a

Device Select Code with the R W bit set to ’0’, as

shown in Table 6. The memory acknowledges this,

and waits for two address bytes. The memory

responds to each address byte with an

acknowledge bit, and then waits for t he data byt e.

Writing to the memory may be inhibited if the WC

input pin is taken high. Any write command with

WC=1 (during a period of time from the START

condition until the end of the two address bytes)

will not modify the contents of the top quarter of

t he memory.

Byte Write

In the Byte Write mode, after the Device Select

Code and the address bytes, the master sends

one data byte. If the addressed location is write

protected by the WC pin, the location is not

modified. The master terminates the transfer by

generating a STOP c ondition.

Page Write

The Page Write m ode allows up to 32 byt es to be

written in a single write cycle, provided that they

are all located in the same “row” in the memory:

that is the most significant memory address bits

(b12-b5) are the same. If more bytes are sent than

Table 3. Device Select Code 1

No te : 1 . The m ost sign ifican t bit, b7, is sent firs t.

Device Type Identifier Chip Enable RW

b7 b6 b5 b4 b3 b2 b1 b0

Device Select Code 1 0 1 0 E2 E1 E0 RW

Table 4. Mos t Significant Byte

Not e: 1. b15 to b13 are Don’ t Care.

Table 5. Least Significant Byte

b15 b14 b13 b12 b11 b10 b9 b8

b7 b6 b5 b4 b3 b2 b1 b0

Table 6. Operating Modes

No te: 1 . X = VIH or VIL.

Mode RW bit WC 1 Bytes Initial Sequence

Current Address Read 1 X 1 START, Device Select, RW = ‘1’

Random Address Read 0X1

START, Device Select, RW = ‘0’, Address

1 X reSTART, Device Select, RW = ‘1’

Sequential Read 1 X ≥ 1 Similar to Current or Random Address Read

Byte Write 0 VIL 1 START, Device Select, RW = ‘0’

Page Write 0 VIL ≤ 32 START, Device Select, RW = ‘0’

M34D64

6/15

Figu re 6. Wri t e Mode Sequences

STOP

START

BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN

START

PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1 DATA IN 2

AI02853

PAGE WRITE

(cont'd)

STOP

DATA IN N

ACK

R/W

ACK ACK ACK

ACK ACK ACK ACK

R/W

ACKACK

During the internal write cycle, the SDA input is

disabled internally, and the device does not

respond to any requests.

Minimizing System Delays by Polli ng On ACK

During the internal write cycle, the memory

disconnects itself from the bus, and copies the

data from its interna l latches to the m emory cells.

The maximum write time (tw) is shown in Table 9,

but the typi cal time is short er. To make use of t his,

an Ack polling sequence can be used by the

master.

The sequence, as shown in Figure 7, is:

– Initial condition: a Write is in progress.

– Step 1: the master issues a START condition

followed by a Dev ice Select Code (the first byte

of the new instruction).

– Step 2: if the memory is busy with the internal

write cycle, no Ack will be returned and the

master goes back to Step 1. If th e memory has

terminated the internal write cycle, it responds

will fit u p t o the end of the r ow, a c ondit ion know n

as ‘roll-over’ occurs. Data starts to become

overwritten (in a way not formally specified in this

data sheet).

The master sends from one up to 32 bytes of data,

each of wh ich is ackno wledged by the memory if

the WC pin is low. If the WC pin is high, the

contents of the addressed memory location are

not modified. After each byte is transferred, the

internal byte address counter (the 5 least

significant bits only) is incremented. The transfer is

terminated by the master generating a STOP

condition.

When the master generates a STOP condition

immediat ely after the Ack bi t (in t he “10th bit” tim e

slot), either at the end of a byte write or a page

write, the internal memory write cycle is triggered.

A STOP condition at any other time does not

trigger the internal writ e cycle.

7/15

M34D64

Current Address Read

The device has an internal address counter which

is incremented each time a byte is read. For the

Current Address Read mode, following a START

condition, the master sends a Device Select Code

with the RW bit set to 1. The memory

acknowledges this, and outputs the byte

addressed by the internal address counter. The

counter is then incremented. The master

terminates the transfer with a STOP condition, as

shown in Figure 8,

without

acknowledging the by te

output.

Sequenti al Re ad

This mode can be initiated with either a Current

Address Read or a Random Address Read. The

master

does

acknowledg e t he data byte output in

this case, and the memory continues to output the

next byte in sequence. To t erm inate the stream of

bytes, the master must

not

acknowledge the last

byte output, and

must

generate a STOP condition.

with an Ac k, indi cating that t he memory is ready

to receive the second part of the next instruction

(the first byte of this instruction having been sent

during Step 1).

Read Operation s

Read operations are performed independently of

the state of the WC pin.

Random Address Read

A dummy write is performed to load the address

into the address counter, as shown in Figure 8.

Then,

without

sending a STOP condition, the

master sends another START condition, and

repeats the Device Select Code, with the RW bit

set to ‘1’. The memory acknowledges this, and

outputs the contents of the addressed byte. The

maste r must

not

acknowledge the byte output, and

terminates t h e transfer with a STOP condition.

Figu re 7. Wri t e C yc le Pol l in g Fl owchart usi ng ACK

WRITE Cycle

in Progress

AI01847B

Operation is

Addressing the

Memory

START Condition

DEVICE SELECT

with RW = 0

ACK

Returned

YES

YESNO

ReSTART

STOP

Proceed

WRITE Operation Proceed

Random Address

READ Operation

Send

Byte Address

First byte of instruction

with RW = 0 already

decoded by the device

YESNO START

Condition

M34D64

8/15

The output data comes from consecutive

addresses, with the internal address counter

automatical ly i ncremen ted af ter each byte output.

After the last memory address, the address

counter ‘rolls-over’ and the memory continues to

output data from the start of the memory block.

Acknowledge in Read Mode

In all read modes, the memory waits, after each

byte read, for an acknowledgment during the 9th

bit time. If the master does not pull the SDA line

low during this time, the memory terminates the

data transfer and switches to its standby state.

Figure 8. Read Mode Sequ ences

No te : 1 . The s e ven most si gnific ant bits of t he Device Select Code of a Ra ndom Read (in the 1st and 4th byt es) must be id ent ical .

START

DEV SEL * BYTE ADDR BYTE ADDR

START

DEV SEL DATA OUT 1

AI01105C

DATA OUT N

STOP

START

CURRENT

ADDRESS

READ DEV SEL DATA OUT

RANDOM

ADDRESS

READ

STOP

START

DEV SEL * DATA OUT

SEQUENTIAL

CURRENT

READ

STOP

DATA OUT N

START

DEV SEL * BYTE ADDR BYTE ADDR

SEQUENTIAL

RANDOM

READ

START

DEV SEL * DATA OUT 1

STOP

ACK

R/W

NO ACK

ACK

R/W

ACK ACK ACK

R/W

ACK ACK ACK NO ACK

R/W

NO ACK

ACK ACK ACK

R/W

ACK ACK

R/W

ACK NO ACK

9/15

M34D64

Table 7. DC Characteristics

(TA = –40 to 85 ° C; VCC = 2.5 to 5.5 V)

Table 8. Input Parameters 1 (TA = 25 °C , f = 4 00 kHz)

Not e: 1. S ampled only, not 100% tested.

Symbol Parameter Test Condition Min. Max. Unit

ILI Input Leakage Current

(SCL, SDA) 0V

≤ VIN ≤ VCC ± 2 µA

ILO Output Leakage Current 0 V ≤ VOUT ≤ VCC, SDA in Hi-Z ± 2 µA

ICC Supply Current VCC =2.5V, fc=400kHz (rise/fall time < 30ns) 1mA

CC1 Supply Current (Stand-by) VIN = VSS or VCC , VCC = 5 V 10 µA

ICC2 Supply Current (Stand-by) VIN = VSS or VCC , VCC = 2.5 V 2µA

IL Input Low Voltage

(E0-E2, SCL, SDA) –0.3 0.3 VCC V

VIH Input High Voltage

(E0-E2, SCL, SDA) 0.7VCC VCC+1 V

VILW Input Low Voltage (WC) –0.3 0.5 V

VIHW Input High Voltage (WC) 0.7VCC VCC+1 V

VOL Output Low

Voltage IOL = 2.1 mA, VCC = 2.5 V 0.4 V

Symbol Parameter Test Condition Min. Max. Unit

CIN Input Capacitance (SDA) 8 pF

Input Capacitance (other pins) 6 pF

ZWCL WC Input Impedance VIN < VILW 50 300 kΩ

ZWCH WC Input Impedance VIN > VIHW 500 kΩ

tNS Pulse width ignored

(Input Filter on SCL and SDA) Single glitch 50 ns

M34D64

10/15

Table 9. AC Characteri stics

No te : 1 . For a reSTA RT condition, or foll owing a wri te cycle.

2. Sam p l ed onl y, not 10 0% tes t ed.

3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.

4. Thi s i s preliminary data.

Symbol Alt. Parameter

M34D64

Unit

VCC=2.5 to 5.5 V

TA=–40 to 85°C

Min Max

tCH1CH2 tRClock Rise Time 300 ns

tCL1CL2 tFClock Fall Time 300 ns

tDH1DH2 2tRSDA Rise Time 20 300 ns

tDL1DL2 2tFSDA Fall Time 20 300 ns

tCHDX 1tSU:STA Clock High to Input Transition 600 ns

tCHCL tHIGH Clock Pulse Width High 600 ns

tDLCL tHD:STA Input Low to Clock Low (START) 600 ns

tCLDX tHD:DAT Clock Low to Input Transition 0 µs

tCLCH tLOW Clock Pulse Width Low 1.3 µs

tDXCX tSU:DAT Input Transition to Clock Transition 100 ns

tCHDH tSU:STO Clock High to Input High (STOP) 600 ns

tDHDL tBUF Input High to Input Low (Bus Free) 1.3 µs

tCLQV 3tAA Clock Low to Data Out Valid 200 900 ns

tCLQX tDH Data Out Hold Time After Clock Low 200 ns

fCfSCL Clock Frequency 400 kHz

tWtWR Write Time 10 ms

Table 10. AC Measurement Conditions

Input Rise and Fall Times ≤ 50 ns

Input Pulse Voltages 0.2VCC to 0.8VCC

Input and Output Timing

Reference Voltages 0.3VCC to 0.7VCC

Figure 9. AC Testing Input Output Waveforms

AI00825

0.8VCC

0.2VCC

0.7VCC

0.3VCC

11/15

M34D64

Figure 10. AC Waveforms

SCL

SDA In

SCL

SDA Out

SCL

SDA In

tCHCL

tDLCL

tCHDX

START

Condition

tCLCH

tDXCXtCLDX

SDA

Input

SDA

Change tCHDH tDHDL

STOP

Condition

Data Valid

tCLQV tCLQX

tCHDH

STOP

Condition

tCHDX

START

Condition

Write Cycle

AI00795C

START

Condition

M34D64

12/15

Table 11. Ordering Information Scheme

Example: M34D64 –W MN 6 T

Memory Capacity Option

64 64 Kbit (8K x 8) T Tape and Reel Packing

Operating Voltage

W 2.5 V to 5.5 V

Package Temperature Range

MN SO8 (150 mil width) 6 –40 °C to 85 °C

ORDERING INF ORMATION

Devices are shipped from the factory with the

memory c ontent set at all 1s (F Fh).

The notation used for the device number is as

shown in Table 11. For a list of available options

(speed, package, etc.) or for f urt her information on

any aspect of this device, please contact your

nearest ST Sales Office.

13/15

M34D64

Figure 11. SO8 narrow (MN)

No te : 1. Drawing is not to scale.

SO-a

LA1 α

h x 45˚

Table 12. SO 8 - 8 lead Plastic Small Outline, 150 mils body wi dth

Symb. mm inches

Typ. Min. Max. Typ. Min. Max.

A 1.35 1.75 0.053 0.069

A1 0.10 0.25 0.004 0.010

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.010

D 4.80 5.00 0.189 0.197

E 3.80 4.00 0.150 0.157

e 1.27 – – 0.050 – –

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.40 0.90 0.016 0.035

α0° 8° 0° 8°

N8 8

CP 0.10 0.004

M34D64

14/15

Table 13. R evision History

Date Description of Revision

23-Mar-1999 Document written

09-Jun-1999 Memory Map illustration added. Line removed from Tab-2

16-Nov-2000 M34D32 removed; PSDIP8 package removed; 4.5 to 5.5V and 1.8 to 3.6V ranges removed; 0 to 70°C

and -20 to 85°C ranges removed

15/15

M34D64

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