© Semiconductor Components Industries, LLC, 2014
January, 2014 − Rev. 0
1Publication Order Number:
NCV4275C/D
NCV4275C
450 mA Low-Drop Voltage
Regulator with Reset
The NCV4275C is an integrated low dropout regulator designed
for use in harsh automotive environments. It includes wide
operating temperature and input voltage ranges. The output is
regulated at 5.0 V or 3.3 V and is rated to 450 mA of output current.
It also provides a number of features, including overcurrent
protection, overtemperature protection and a programmable
microprocessor reset. The NCV4275C is available in the DPAK and
D2PAK surface mount packages. The output is stable over a wide
output capacitance and ESR range. The NCV4275C is pin for pin
compatible with NCV4275A.
Features
•5.0 V or 3.3 V ±2% Output Voltage Options
•450 mA Output Current
•Very Low Current Consumption
•Active Reset Output
•Reset Low Down to VQ = 1.0 V
•500 mV (max) Dropout Voltage
•Fault Protection
♦+45 V Peak Transient Voltage
♦−42 V Reverse Voltage
♦Short Circuit Protection
♦Thermal Overload Protection
•AEC−Q100 Qualified and PPAP Capable
•These are Pb−Free Devices
Applications
•Auto Body Electronics
+
−
I
D
Q
GND
RO
Current Limit and
Saturation Sense
Bandgap
Reference
Thermal
Shutdown
Reset
Generator
Figure 1. Block Diagram
Error
Amplifier
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D2PAK
5−PIN
DS SUFFIX
CASE 936A
1
5
DPAK
5−PIN
DT SUFFIX
CASE 175AA
ORDERING INFORMATION
15
MARKING
DIAGRAMS
1
1
x = 5 (5.0 V Output)
or 3 (3.3 V Output)
A = Assembly Location
WL, L = Wafer Lot
Y = Year
WW = Work Week
G = Pb−Free Package
4275CxG
ALYWW
NC
V4275Cx
AWLYWWG
See detailed ordering and shipping information on page 13 of
sheet.
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PIN FUNCTION DESCRIPTION
Pin No.
Symbol Description
DPAK−5
D2PAK−5
1 I Input; Battery Supply Input Voltage. Bypass to ground with a ceramic capacitor.
2 RO Reset Output; Open Collector Active Reset (accurate when I > 1.0 V).
3, TAB GND Ground; Pin 3 internally connected to tab.
4 D Reset Delay; timing capacitor to GND for Reset Delay function.
5 Q Output; ±2.0%, 450 mA output. Bypass with 22 mF capacitor, ESR < 4.5 W (5.0 V Version),
3.5 W (3.3 V Version).
MAXIMUM RATINGS
Rating Symbol Min Max Unit
Input Voltage VI−42 45 V
Input Peak Transient Voltage VI−45 V
Output Voltage VQ−1.0 16 V
Reset Output Voltage VRO −0.3 25 V
Reset Output Current IRO −5.0 5.0 mA
Reset Delay Voltage VD−0.3 7.0 V
Reset Delay Current ID−2.0 2.0 mA
ESD Susceptibility (Note 1) − Human Body Model
− Machine Model
− Charge Device Model
ESDHBM
ESDMM
ESDCDM
4.0
200
1000
−
−
−
kV
V
V
Junction Temperature TJ−40 150 °C
Storage Temperature Tstg −55 150 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device incorporates ESD protection and is tested by the followign methods: ESD Human Body Model tested per AEC−Q100−002, ESD
Machine Model tested per AEC−Q100−003, ESD Charged Device Model tested per AEC−Q100−011, Latch−up tested per AEC−Q100−004.
OPERATING RANGE
Rating Symbol Min Max Unit
Input Voltage Operating Range, 5.0 V Output VI5.5 42 V
Input Voltage Operating Range, 3.3 V Output VI4.4 42 V
Junction Temperature TJ−40 150 °C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the
Recommended Operating Ranges limits may affect device reliability.
LEAD TEMPERATURE SOLDERING REFLOW AND MSL (Note 2)
Rating Symbol Min Max Unit
Lead Free, 60 sec−150 sec above 217°C TSLD −265 Peak °C
Moisture Sensitivity Level MSL 1
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THERMAL CHARACTERISTICS
Characteristic Test Conditions (Typical Value) Unit
DPAK 5−PIN PACKAGE
Min Pad Board (Note 3) 1 in Pad Board (Note 4)
Junction−to−Tab (RqJT) 5.1 5.5 °C/W
Junction−to−Ambient (RqJA) 82.4 58.1 °C/W
D2PAK 5−PIN PACKAGE
0.4 sq. in. Spreader Board (Note 5) 1.2 sq. in. Spreader Board (Note 6)
Junction−to−Tab (RqJT) 4.5 4.8 °C/W
Junction−to−Ambient (RqJA) 66.0 49.0 °C/W
2. PRR IPC / JEDEC J−STD−020C
3. 1 oz. copper, 0.26 inch2 (168 mm2) copper area, 0.062″thick FR4.
4. 1 oz. copper, 1.14 inch2 (736 mm2) copper area, 0.062″thick FR4.
5. 1 oz. copper, 0.373 inch2 (241 mm2) copper area, 0.062″thick FR4.
6. 1 oz. copper, 1.222 inch2 (788 mm2) copper area, 0.062″thick FR4.
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ELECTRICAL CHARACTERISTICS (VI = 13.5 V; −40°C < TJ < 150°C; unless otherwise noted.)
Characteristic Symbol Test Conditions Min Typ Max Unit
Output
Output Voltage VQ100 mA v IQ v 400 mA
6.0 V v VI v 28 V (5.0 V Version)
4.4 V v VI v 28 V (3.3 V version)
4.9
3.23
(2%)
5.0
3.3
5.1
3.37
(2%)
V
Output Voltage VQ100 mA v IQ v 200 mA
6.0 V v VI v 40 V (5.0 V Version)
4.4 V v VI v 40 V (3.3 V version)
4.9
3.23
(2%)
5.0
3.3
5.1
3.37
(2%)
V
Output Current Limitation IQVQ = 0.9 x VQ,typ 450 650 −mA
Quiescent Current
Iq = II − IQ
IqIQ = 1.0 mA, TJ = 25°C−135 150 mA
IQ = 1.0 mA −150 200 mA
IQ = 250 mA −10 15 mA
IQ = 400 mA −23 35 mA
Dropout Voltage (Note 7) Vdr IQ = 300 mA
Vdr = VI − VQ
−250 500 mV
Load Regulation DVQIQ = 5.0 mA to 400 mA −30 15 30 mV
Line Regulation DVQDVI = 8.0 V to 32 V,
IQ = 5.0 mA
−15 5.0 15 mV
Power Supply Ripple Rejection PSRR fr = 100 Hz, Vr = 0.5 Vpp −60 −dB
Temperature Output Voltage
Drift
dVQ/dT −− −0.5 −mV/K
Reset Timing D and Output RO
Reset Switching Threshold
5.0 V Version
3.3 V Version
VQ,rt Vout decreasing
Vin > 5.5 V
Vin > 4.4 V
90
90
93
93
96
96
% Vout
Reset Output Low Voltage VROL Rext ≥ 5.0 kW, VQ ≥ 1.0 V −0.2 0.4 V
Reset Output Leakage Current IROH VROH = 5.0 V −0 10 mA
Reset Charging Current ID,C VD = 1.0 V 3.0 5.5 9.0 mA
Upper Timing Threshold VDU −− 1.5 1.8 2.2 V
Lower Timing Threshold VDL −− 0.2 0.4 0.7 V
Reset Delay Time trd CD = 47 nF 10 16 22 ms
Reset Reaction Time trr CD = 47 nF −1.5 4.0 ms
Thermal Shutdown
Shutdown Temperature (Note 8) TSD −− 150 −210 °C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Only for 5 V Version. Measured when the output voltage VQ has dropped 100 mV from the nominal value obtained at VI = 13.5 V.
8. Guaranteed by design, not tested in production.
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TYPICAL PERFORMANCE CHARACTERISTICS
3.26
3.28
3.3
3.32
3.34
3.36
−40 −20 0 20 40 60 80 100 120 140 160
Figure 2. Output Stability with Output
Capacitor ESR
Figure 3. Output Stability with Output
Capacitor ESR
Figure 4. Output Stability with Output
Capacitor ESR
Figure 5. Output Stability with Output
Capacitor ESR
Figure 6. Output Voltage VQ vs. Temperature TJFigure 7. Output Voltage VQ vs. Temperature TJ
0.01
0.1
1
10
IQ, OUTPUT CURRENT (mA)
ESR (W)
CQ = 22 mF
Stable ESR Region
0 100 200 300 400
VQ(nom) = 5.0 V
CQ = 22 mF
Stable ESR Region
0 100 200 300 400
VQ(nom) = 3.3 V
0.01
0.1
1
10
IQ, OUTPUT CURRENT (mA)
ESR (W)
0.1
1
10
100
0.01
IQ, OUTPUT CURRENT (mA)
ESR (W)
CQ = 1 mF
Stable ESR Region
0 100 200 300 400
VQ(nom) = 5.0 V
0.1
1
10
100
IQ, OUTPUT CURRENT (mA)
ESR (W)
CQ = 1 mF
Stable ESR Region
0 100 200 300 400
VQ(nom) = 3.3 V
VQ, OUTPUT VOLAGE (V)
TJ, JUNCTION TEMPERATURE (°C)
VIN = 13.5 V,
IOUT = 200 mA
VQ(nom) = 5.0 V
VQ, OUTPUT VOLAGE (V)
TJ, JUNCTION TEMPERATURE (°C)
VQ(nom) = 3.3 V
5.0 V Version 3.3 V Version
4.90
4.93
4.95
4.98
5.00
5.03
5.05
5.08
5.10
−40 −20 0 20 40 60 80 100 120 140 160
VIN = 13.5 V,
IOUT = 200 mA
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TYPICAL PERFORMANCE CHARACTERISTICS
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0246810
Figure 8. Output Voltage VQ vs. Input Voltage VIN Figure 9. Output Voltage VQ vs. Input Voltage VIN
Figure 10. Output Current IQ vs. Temperature
TJ
Figure 11. Output Current IQ vs. Temperature
TJ
Figure 12. Output Current IQ vs. Input Voltage
VIN
Figure 13. Output Current IQ vs. Input Voltage
VIN
VQ, OUTPUT VOLTAGE (V)
VIN, INPUT VOLTAGE (V)
VQ(nom) = 5.0 V
VQ, OUTPUT VOLTAGE (V)
VIN, INPUT VOLTAGE (V)
VQ(nom) = 3.3 V
IQ, OUTPUT CURRENT LIMITATION (A)
TJ, JUNCTION TEMPERATURE (°C)
IQ, OUTPUT CURRENT LIMITATION (A)
TJ, JUNCTION TEMPERATURE (°C)
ILIM, ISC, CURRENT LIMIT (mA)
VIN, INPUT VOLTAGE (V)
IILIM, ISC, CURRENT LIMIT (mA)
VI, INPUT VOLTAGE (V)
5.0 V Version 3.3 V Version
0
1
2
3
4
5
6
0246810
IOUT = 200 mA
TJ = 25°C
IOUT = 200 mA
TJ = 25°C
500
550
600
650
700
−40 −20 0 20 40 60 80 100 120 140 160
VIN = 13.5 V
VQ(nom) = 5.0 V
500
550
600
650
700
−40 −20 0 20 40 60 80 100 120 140 160
VIN = 13.5 V
VQ(nom) = 3.3 V
0
100
200
300
400
500
600
700
0 5 10 15 20 25 30 35 40
VQ(nom) = 5.0 V
TJ = 25°C
TJ = 125°C
0
100
200
300
400
500
600
700
0 5 10 15 20 25 30 35 40
TJ = 25°C
TJ = 125°C
VQ(nom) = 3.3 V
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TYPICAL PERFORMANCE CHARACTERISTICS
Figure 14. Current Consumption Iq vs.
Output Current IQ
Figure 15. Current Consumption Iq vs.
Output Current IQ
Iq, CURRENT CONSUMPTION (mA)
IQ, OUTPUT CURRENT (mA)
VIN = 13.5 V,
TJ = 25°C
Figure 16. Current Consumption Iq vs.
Output Current IQ
Figure 17. Current Consumption Iq vs.
Output Current IQ
Figure 18. Charge Current ID,C vs. Temperature
TJ
Figure 19. Delay Switching Threshold VDU, VDL
vs. Temperature TJ
VQ(nom) = 5.0 V
Iq, CURRENT CONSUMPTION (mA)
IQ, OUTPUT CURRENT (mA)
VQ(nom) = 5.0 V
IDC, CHARGE CURRENT (mA)
TJ, JUNCTION TEMPERATURE (°C)
Iq, CURRENT CONSUMPTION (mA)
IQ, OUTPUT CURRENT (mA)
VQ(nom) = 3.3 V
Iq, CURRENT CONSUMPTION (mA)
IQ, OUTPUT CURRENT (mA)
IDC, CHARGE CURRENT (mA)
TJ, JUNCTION TEMPERATURE (°C)
0
0.5
1
1.5
2
2.5
3
0 20406080100120 0
0.5
1
1.5
2
2.5
3
0 20 40 60 80 100 120
VIN = 13.5 V,
TJ = 25°C
0
5
10
15
20
25
30
0 50 100 150 200 250 300 350 400 450
VIN = 13.5 V,
TJ = 25°C
0
5
10
15
20
25
30
0 50 100 150 200 250 300 350 400 450
VQ(nom) = 3.3 V
VIN = 13.5 V,
TJ = 25°C
0
1
2
3
4
5
6
7
8
9
10
−40 −20 0 20 40 60 80 100 120 140 160
VIN = 13.5 V,
VD = 1 V
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
2
2.2
−40 −20 0 20 40 60 80 100 120 140 160
1.6
1.8
VIN = 13.5 V
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TYPICAL PERFORMANCE CHARACTERISTICS
0
100
200
300
400
500
600
700
800
0 100 200 300 400 500 600
Figure 20. Drop Voltage Vdr vs. Output Current
IQ
Vdr, DROPOUT VOLTAGE (mV)
IQ, OUTPUT CURRENT (mA)
TJ = 125°C
VQ(nom) = 5.0 V
TJ = 25°C
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APPLICATION INFORMATION
VICI1
1000 mF
CI2
100 nF
CD
47 nF
III
D
ID
1
4
5
2
3
GND
CQ
22 mF
IRO
IQ
Q
RO
Rext
5.0 k
VQ
VRO
Figure 21. Test Circuit
NCV4275C
Iq
Circuit Description
The NCV4275C is an integrated low dropout regulator
that provides 5.0 V or 3.3 V, 450 mA protected output and
a signal for power on reset. The regulation is provided by
a PNP pass transistor controlled by an error amplifier with
a bandgap reference, which gives it the lowest possible
drop out voltage and best possible temperature stability.
The output current capability is 450 mA, and the base drive
quiescent current is controlled to prevent over saturation
when the input voltage is low or when the output is
overloaded. The regulator is protected by both current limit
and thermal shutdown. Thermal shutdown occurs above
150°C to protect the IC during overloads and extreme
ambient temperatures. The delay time for the reset output
is adjustable by selection of the timing capacitor. See
Figure 21, Test Circuit, for circuit element nomenclature
illustration.
Regulator
The error amplifier compares the reference voltage to a
sample of the output voltage (VQ) and drives the base of a
PNP series pass transistor by a buffer. The reference is a
bandgap design to give it a temperature−stable output.
Saturation control of the PNP is a function of the load
current and input voltage. Over saturation of the output
power device is prevented, and quiescent current in the
ground pin is minimized.
Regulator Stability Considerations
The input capacitors (CI1 and CI2) are necessary to
stabilize the input impedance to avoid voltage line
influences. Using a resistor of approximately 1.0 W in
series with CI2 can stop potential oscillations caused by
stray inductance and capacitance.
The output capacitor helps determine three main
characteristics of a linear regulator: startup delay, load
transient response and loop stability. The capacitor value
and type should be based on cost, availability, size and
temperature constraints. A tantalum, aluminum or ceramic
capacitors can be used. The range of stability versus
capacitance, load current and capacitive ESR is illustrated
in Figures 2 to 5. Minimum ESR for CQ = 22 mF is native
ESR of ceramic capacitors. The aluminum electrolytic
capacitor is the least expensive solution, but, if the circuit
operates at low temperatures (−25°C to −40°C), both the
capacitance and ESR of the capacitor will vary considerably.
The capacitor manufacturer’s data sheet usually provides this
information.
The value for the output capacitor CQ shown in
Figure 21, Test Circuit, should work for most applications;
however, it is not necessarily the optimized solution.
Stability is guaranteed for CQ ≥ 22 mF and an ESR ≤ 4.5 W
(5.0 V Version), 3.5 W (3.3 V Version). ESR characteristics
were measured with ceramic capacitors and additional
resistors to emulate ESR. Murata ceramic capacitors were
used, GRM32ER71A226ME20 (22 mF, 10 V, X7R, 1210),
GRM31MR71E105KA01 (1 mF, 25 V, X7R, 1206).
Reset Output
The reset output is used as the power on indicator to the
microcontroller. This signal indicates when the output
voltage is suitable for reliable operation of the controller.
It pulls low when the output is not considered to be ready.
RO is pulled up to VQ by an external resistor, typically
5.0 kW in value. The input and output conditions that
control the Reset Output and the relative timing are
illustrated in Figure 22, Reset Timing.
Output voltage regulation must be maintained for the
delay time before the reset output signals a valid condition.
The delay for the reset output is defined as the amount of
time it takes the timing capacitor on the delay pin to charge
from a residual voltage of 0.0 V to the upper timing
threshold voltage VDU. The charging current for this is ID,C
and D pin voltage in steady state is typically 2.4 V. By using
typical IC parameters with a 47 nF capacitor on the D pin,
the following time delay for 5.0 V regulator is derived:
tRD = CDVDU / ID,C
tRD = 47 nF (1.8 V) / 5.5 mA = 15.4 ms
Other time delays can be obtained by changing the
capacitor value.
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Figure 22. Reset Timing
VI
VQ
VD
VRO
Reset
Delay Time
Reset
Reaction Time
Power−on−Reset Thermal
Shutdown
Voltage Dip
at Input
Undervoltage Secondary
Spike
Overload
at Output
< Reset Reaction Time
t
t
t
t
VQ,rt
Upper Timing Threshold VDU
Lower Timing Threshold VDL
dVD
dt +Reset Charge Current
CD
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Calculating Power Dissipation
in a Single Output Linear Regulator
The maximum power dissipation for a single output
regulator (Figure 23) is:
PD(max) +[VI(max) *VQ(min)]I
Q(max) (1)
)VI(max)Iq
where
VI(max) is the maximum input
voltage,
VQ(min) is the minimum output
voltage,
IQ(max) is the maximum output
current for the application,
Iq is the quiescent current the regulator consumes
at IQ(max).
Once the value of PD(max) is known, the maximum
permissible value of RqJA can be calculated:
RqJA +150°C*TA
PD(2)
The value of RqJA can then be compared with those in the
package section of the data sheet. Those packages with
RqJA
’s less than the calculated value in Equation 2 will keep
the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
SMART
REGULATOR®
Iq
Control
Features
IQ
II
Figure 23. Single Output Regulator with Key
Performance Parameters Labeled
VIVQ
}
Heatsinks
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and
the outside environment will have a thermal resistance.
Like series electrical resistances, these resistances are
summed to determine the value of RqJA:
RqJA +RqJC )RqCS )RqSA (3)
where
RqJC is the junction−to−case thermal resistance,
RqCS is the case−to−heatsink thermal resistance,
RqSA is the heatsink−to−ambient thermal resistance.
RqJC appears in the package section of the data sheet.
Like RqJA, it too is a function of package type. RqCS and
RqSA are functions of the package type, heatsink and the
interface between them. These values appear in heatsink
data sheets of heatsink manufacturers.
Thermal, mounting, and heatsinking considerations are
discussed in the ON Semiconductor application note
AN1040/D.
40
60
80
100
120
140
0 100 200 300 400 500 600 700 800
40
60
80
100
120
140
160
0 100 200 300 400 500 600 700 800
Figure 24. qJA vs. Copper Spreader Area,
DPAK 5−Lead
Figure 25. qJA vs. Copper Spreader Area,
D2PAK 5−Lead
COPPER AREA SPREADER AREA (mm2)
RqJA, THERMAL RESISTANCE (C°/W)
DPAK 2 oz
DPAK 1 oz
COPPER AREA SPREADER AREA (mm2)
RqJA, THERMAL RESISTANCE (C°/W)
D2PAK 2 oz
D2PAK 1 oz
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TIME (sec)
R(t) C°/W
Cu Area 167 mm2
Cu Area 736 mm2
Figure 26. Single−Pulse Heating Curves, DPAK 5−Lead
PULSE TIME (sec)
R(t) C°/W
Cu Area 167 mm2
Cu Area 736 mm2
Figure 27. Single−Pulse Heating Curves, D2PAK 5−Lead
0.1
1
10
100
0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
0.1
1
10
100
0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
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100
10
1.0
0.1
0.01
PULSE WIDTH (sec)
RqJA 788 mm2 C°/W
0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000
Non−normalized Response
50% Duty Cycle
20%
10%
5%
2%
1%
100
10
1.0
0.1
0.01
PULSE WIDTH (sec)
RqJA 736 mm2 C°/W
0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000
Non−normalized Response
50% Duty Cycle
Figure 28. Duty Cycle for 1” Spreader Boards, DPAK 5−Lead
20%
10%
5%
2%
1%
Figure 29. Duty Cycle for 1” Spreader Boards, D2PAK 5−Lead
ORDERING INFORMATION
Device Output Voltage Package Shipping†
NCV4275CDS50R4G
5.0 V
D2PAK
(Pb−Free) 800 / Tape & Reel
NCV4275CDT50RKG DPAK
(Pb−Free) 2500 / Tape & Reel
NCV4275CDS33R4G
3.3 V
D2PAK
(Pb−Free) 800 / Tape & Reel
NCV4275CDT33RKG DPAK
(Pb−Free) 2500 / Tape & Reel
†For information on tape and reel specifications,including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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PACKAGE DIMENSIONS
D
A
K
B
R
V
S
F
L
G
5 PL
M
0.13 (0.005) T
E
C
U
J
H
−T−SEATING
PLANE
Z
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.235 0.245 5.97 6.22
B0.250 0.265 6.35 6.73
C0.086 0.094 2.19 2.38
D0.020 0.028 0.51 0.71
E0.018 0.023 0.46 0.58
F0.024 0.032 0.61 0.81
G0.180 BSC 4.56 BSC
H0.034 0.040 0.87 1.01
J0.018 0.023 0.46 0.58
K0.102 0.114 2.60 2.89
L0.045 BSC 1.14 BSC
R0.170 0.190 4.32 4.83
S0.025 0.040 0.63 1.01
U0.020 −−− 0.51 −−−
V0.035 0.050 0.89 1.27
Z0.155 0.170 3.93 4.32
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
R1 0.185 0.210 4.70 5.33
R1
1234 5
DPAK 5, CENTER LEAD CROP
DT SUFFIX
CASE 175AA
ISSUE A
6.4
0.252
0.8
0.031
10.6
0.417
5.8
0.228
SCALE 4:1 ǒmm
inchesǓ
0.34
0.013
5.36
0.217
2.2
0.086
SOLDERING FOOTPRINT*
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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PACKAGE DIMENSIONS
D2PAK, 5 LEAD
DS SUFFIX
CASE 936A−02
ISSUE C
5 REF
A
123
K
B
S
H
D
G
C
E
ML
P
N
R
V
U
TERMINAL 6
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS A
AND K.
4. DIMENSIONS U AND V ESTABLISH A MINIMUM
MOUNTING SURFACE FOR TERMINAL 6.
5. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH OR GATE PROTRUSIONS. MOLD FLASH
AND GATE PROTRUSIONS NOT TO EXCEED 0.025
(0.635) MAXIMUM.
DIM
A
MIN MAX MIN MAX
MILLIMETERS
0.386 0.403 9.804 10.236
INCHES
B0.356 0.368 9.042 9.347
C0.170 0.180 4.318 4.572
D0.026 0.036 0.660 0.914
E0.045 0.055 1.143 1.397
G0.067 BSC 1.702 BSC
H0.539 0.579 13.691 14.707
K0.050 REF 1.270 REF
L0.000 0.010 0.000 0.254
M0.088 0.102 2.235 2.591
N0.018 0.026 0.457 0.660
P0.058 0.078 1.473 1.981
R5 REF
S0.116 REF 2.946 REF
U0.200 MIN 5.080 MIN
V0.250 MIN 6.350 MIN
__
45
M
0.010 (0.254) T
−T−
OPTIONAL
CHAMFER
8.38
0.33
1.016
0.04
16.02
0.63
10.66
0.42
3.05
0.12
1.702
0.067
SCALE 3:1 ǒmm
inchesǓ
SOLDERING FOOTPRINT*
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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