S-1004 Series
www.ablicinc.com
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING)
VOLTAGE DETECTOR WITH SENSE PIN
© ABLIC Inc., 2014 Rev.2.1_02
1
The S-1004 Series is a high-accuracy voltage detector developed using CMOS technology. The detection voltage is fixed
internally with an accuracy of 1.0% (VDET(S) 2.2 V). It operates with current consumption of 500 nA typ.
Apart from the power supply pin, the detection voltage input pin (SENSE pin) is also prepared, so the output is stable even
if the SENSE pin falls to 0 V.
The release signal can be delayed by setting a capacitor externally, and the release delay time accuracy at Ta = 25C is
15%.
Two output forms Nch open-drain output and CMOS output are available.
Features
Detection voltage: 1.0 V to 5.0 V (0.1 V step)
Detection voltage accuracy: 1.0% (2.2 V VDET(S) 5.0 V)
22 mV (1.0 V VDET(S) 2.2 V)
Current consumption: 500 nA typ.
Operation voltage range: 0.95 V to 10.0 V
Hysteresis width: 5% 2%
Release delay time accuracy: 15% (CD = 4.7 nF, Ta = 25°C)
Output form: Nch open-drain output (Active "L")
CMOS output (Active "L")
Operation temperature range: Ta = 40°C to 85°C
Lead-free (Sn 100%), halogen-free
Applications
Power supply monitor for microcomputer and reset for CPU
Constant voltage power supply monitor for TV, Blu-ray recorder and home appliance
Power supply monitor for portable devices such as notebook PC, digital still camera and mobile phone
Packages
SOT-23-5
SNT-6A
www.ablic.com
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series Rev.2.1_02
2
Block Diagrams
1. S-1004 Series NA / NB type (Nch open-drain output)
VSS
*1
*1
V
REF


OUT
VDD
CD
Delay
circuit
*1
*1
SENSE
Function Status
Output logic Active "L"
*1. Parasitic diode
Figure 1
2. S-1004 Series CA / CB type (CMOS output)
VSS
*1
V
REF


OUT
VDD
CD
Delay
circuit
*1
*1
SENSE
*1
*1
Function Status
Output logic Active "L"
*1. Parasitic diode
Figure 2
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_02 S-1004 Series
3
Product Name Structure
Users can select the output form and detection voltage value for the S-1004 Series.
Refer to "1. Product name" regarding the contents of product name, "2. Function list of product types" regarding
the product types, "3. Packages" regarding the package drawings and "4. Product name list" regarding details of
product name.
1. Product name
S-1004 x x xx I - xxxx U
Package abbreviation and IC packing specifications*1
M5T1: SOT-23-5, Tape
I6T1: SNT-6A, Tape
Detection voltage value
10 to 50
(e.g., when the detection voltage is 1.0 V, it is expressed as 10.)
Environmental code
U: Lead-free (Sn 100%), halogen-free
Operation temperature
I: Ta = 40C to 85C
Output form*3
N: Nch open-drain output (Active "L")*4
C: CMOS output (Active "L")*4
Pin configuration*2
A, B
*1. Refer to the tape drawing.
*2. Refer to " Pin Configurations".
*3. Refer to "2. Function list of product types".
*4. If you request the product with output logic active "H", contact our sales office.
2. Function list of product types
Table 1
Product Type Output Form Output Logic Pin Configuration Package
NA Nch open-drain output Active "L" A SOT-23-5, SNT-6A
NB Active "L" B SOT-23-5
CA CMOS output Active "L" A SOT-23-5, SNT-6A
CB Active "L" B SOT-23-5
3. Packages
Table 2 Package Drawing Codes
Package Name Dimension Tape Reel Land
SOT-23-5 MP005-A-P-SD MP005-A-C-SD MP005-A-R-SD
SNT-6A PG006-A-P-SD PG006-A-C-SD PG006-A-R-SD PG006-A-L-SD
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series Rev.2.1_02
4
4. Product name list
4. 1 S-1004 Series NA type
Output form: Nch open-drain output (Active "L")
Table 3
Detection Voltage SOT-23-5 SNT-6A
1.0 V 22 mV S-1004NA10I-M5T1U S-1004NA10I-I6T1U
1.1 V 22 mV S-1004NA11I-M5T1U S-1004NA11I-I6T1U
1.2 V 22 mV S-1004NA12I-M5T1U S-1004NA12I-I6T1U
1.3 V 22 mV S-1004NA13I-M5T1U S-1004NA13I-I6T1U
1.4 V 22 mV S-1004NA14I-M5T1U S-1004NA14I-I6T1U
1.5 V 22 mV S-1004NA15I-M5T1U S-1004NA15I-I6T1U
1.6 V 22 mV S-1004NA16I-M5T1U S-1004NA16I-I6T1U
1.7 V 22 mV S-1004NA17I-M5T1U S-1004NA17I-I6T1U
1.8 V 22 mV S-1004NA18I-M5T1U S-1004NA18I-I6T1U
1.9 V 22 mV S-1004NA19I-M5T1U S-1004NA19I-I6T1U
2.0 V 22 mV S-1004NA20I-M5T1U S-1004NA20I-I6T1U
2.1 V 22 mV S-1004NA21I-M5T1U S-1004NA21I-I6T1U
2.2 V 1.0% S-1004NA22I-M5T1U S-1004NA22I-I6T1U
2.3 V 1.0% S-1004NA23I-M5T1U S-1004NA23I-I6T1U
2.4 V 1.0% S-1004NA24I-M5T1U S-1004NA24I-I6T1U
2.5 V 1.0% S-1004NA25I-M5T1U S-1004NA25I-I6T1U
2.6 V 1.0% S-1004NA26I-M5T1U S-1004NA26I-I6T1U
2.7 V 1.0% S-1004NA27I-M5T1U S-1004NA27I-I6T1U
2.8 V 1.0% S-1004NA28I-M5T1U S-1004NA28I-I6T1U
2.9 V 1.0% S-1004NA29I-M5T1U S-1004NA29I-I6T1U
3.0 V 1.0% S-1004NA30I-M5T1U S-1004NA30I-I6T1U
3.1 V 1.0% S-1004NA31I-M5T1U S-1004NA31I-I6T1U
3.2 V 1.0% S-1004NA32I-M5T1U S-1004NA32I-I6T1U
3.3 V 1.0% S-1004NA33I-M5T1U S-1004NA33I-I6T1U
3.4 V 1.0% S-1004NA34I-M5T1U S-1004NA34I-I6T1U
3.5 V 1.0% S-1004NA35I-M5T1U S-1004NA35I-I6T1U
3.6 V 1.0% S-1004NA36I-M5T1U S-1004NA36I-I6T1U
3.7 V 1.0% S-1004NA37I-M5T1U S-1004NA37I-I6T1U
3.8 V 1.0% S-1004NA38I-M5T1U S-1004NA38I-I6T1U
3.9 V 1.0% S-1004NA39I-M5T1U S-1004NA39I-I6T1U
4.0 V 1.0% S-1004NA40I-M5T1U S-1004NA40I-I6T1U
4.1 V 1.0% S-1004NA41I-M5T1U S-1004NA41I-I6T1U
4.2 V 1.0% S-1004NA42I-M5T1U S-1004NA42I-I6T1U
4.3 V 1.0% S-1004NA43I-M5T1U S-1004NA43I-I6T1U
4.4 V 1.0% S-1004NA44I-M5T1U S-1004NA44I-I6T1U
4.5 V 1.0% S-1004NA45I-M5T1U S-1004NA45I-I6T1U
4.6 V 1.0% S-1004NA46I-M5T1U S-1004NA46I-I6T1U
4.7 V 1.0% S-1004NA47I-M5T1U S-1004NA47I-I6T1U
4.8 V 1.0% S-1004NA48I-M5T1U S-1004NA48I-I6T1U
4.9 V 1.0% S-1004NA49I-M5T1U S-1004NA49I-I6T1U
5.0 V 1.0% S-1004NA50I-M5T1U S-1004NA50I-I6T1U
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_02 S-1004 Series
5
4. 2 S-1004 Series NB type
Output form: Nch open-drain output (Active "L")
Table 4
Detection Voltage SOT-23-5
1.0 V 22 mV S-1004NB10I-M5T1U
1.1 V 22 mV S-1004NB11I-M5T1U
1.2 V 22 mV S-1004NB12I-M5T1U
1.3 V 22 mV S-1004NB13I-M5T1U
1.4 V 22 mV S-1004NB14I-M5T1U
1.5 V 22 mV S-1004NB15I-M5T1U
1.6 V 22 mV S-1004NB16I-M5T1U
1.7 V 22 mV S-1004NB17I-M5T1U
1.8 V 22 mV S-1004NB18I-M5T1U
1.9 V 22 mV S-1004NB19I-M5T1U
2.0 V 22 mV S-1004NB20I-M5T1U
2.1 V 22 mV S-1004NB21I-M5T1U
2.2 V 1.0% S-1004NB22I-M5T1U
2.3 V 1.0% S-1004NB23I-M5T1U
2.4 V 1.0% S-1004NB24I-M5T1U
2.5 V 1.0% S-1004NB25I-M5T1U
2.6 V 1.0% S-1004NB26I-M5T1U
2.7 V 1.0% S-1004NB27I-M5T1U
2.8 V 1.0% S-1004NB28I-M5T1U
2.9 V 1.0% S-1004NB29I-M5T1U
3.0 V 1.0% S-1004NB30I-M5T1U
3.1 V 1.0% S-1004NB31I-M5T1U
3.2 V 1.0% S-1004NB32I-M5T1U
3.3 V 1.0% S-1004NB33I-M5T1U
3.4 V 1.0% S-1004NB34I-M5T1U
3.5 V 1.0% S-1004NB35I-M5T1U
3.6 V 1.0% S-1004NB36I-M5T1U
3.7 V 1.0% S-1004NB37I-M5T1U
3.8 V 1.0% S-1004NB38I-M5T1U
3.9 V 1.0% S-1004NB39I-M5T1U
4.0 V 1.0% S-1004NB40I-M5T1U
4.1 V 1.0% S-1004NB41I-M5T1U
4.2 V 1.0% S-1004NB42I-M5T1U
4.3 V 1.0% S-1004NB43I-M5T1U
4.4 V 1.0% S-1004NB44I-M5T1U
4.5 V 1.0% S-1004NB45I-M5T1U
4.6 V 1.0% S-1004NB46I-M5T1U
4.7 V 1.0% S-1004NB47I-M5T1U
4.8 V 1.0% S-1004NB48I-M5T1U
4.9 V 1.0% S-1004NB49I-M5T1U
5.0 V 1.0% S-1004NB50I-M5T1U
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series Rev.2.1_02
6
4. 3 S-1004 Series CA type
Output form: CMOS output (Active "L")
Table 5
Detection Voltage SOT-23-5 SNT-6A
1.0 V 22 mV S-1004CA10I-M5T1U S-1004CA10I-I6T1U
1.1 V 22 mV S-1004CA11I-M5T1U S-1004CA11I-I6T1U
1.2 V 22 mV S-1004CA12I-M5T1U S-1004CA12I-I6T1U
1.3 V 22 mV S-1004CA13I-M5T1U S-1004CA13I-I6T1U
1.4 V 22 mV S-1004CA14I-M5T1U S-1004CA14I-I6T1U
1.5 V 22 mV S-1004CA15I-M5T1U S-1004CA15I-I6T1U
1.6 V 22 mV S-1004CA16I-M5T1U S-1004CA16I-I6T1U
1.7 V 22 mV S-1004CA17I-M5T1U S-1004CA17I-I6T1U
1.8 V 22 mV S-1004CA18I-M5T1U S-1004CA18I-I6T1U
1.9 V 22 mV S-1004CA19I-M5T1U S-1004CA19I-I6T1U
2.0 V 22 mV S-1004CA20I-M5T1U S-1004CA20I-I6T1U
2.1 V 22 mV S-1004CA21I-M5T1U S-1004CA21I-I6T1U
2.2 V 1.0% S-1004CA22I-M5T1U S-1004CA22I-I6T1U
2.3 V 1.0% S-1004CA23I-M5T1U S-1004CA23I-I6T1U
2.4 V 1.0% S-1004CA24I-M5T1U S-1004CA24I-I6T1U
2.5 V 1.0% S-1004CA25I-M5T1U S-1004CA25I-I6T1U
2.6 V 1.0% S-1004CA26I-M5T1U S-1004CA26I-I6T1U
2.7 V 1.0% S-1004CA27I-M5T1U S-1004CA27I-I6T1U
2.8 V 1.0% S-1004CA28I-M5T1U S-1004CA28I-I6T1U
2.9 V 1.0% S-1004CA29I-M5T1U S-1004CA29I-I6T1U
3.0 V 1.0% S-1004CA30I-M5T1U S-1004CA30I-I6T1U
3.1 V 1.0% S-1004CA31I-M5T1U S-1004CA31I-I6T1U
3.2 V 1.0% S-1004CA32I-M5T1U S-1004CA32I-I6T1U
3.3 V 1.0% S-1004CA33I-M5T1U S-1004CA33I-I6T1U
3.4 V 1.0% S-1004CA34I-M5T1U S-1004CA34I-I6T1U
3.5 V 1.0% S-1004CA35I-M5T1U S-1004CA35I-I6T1U
3.6 V 1.0% S-1004CA36I-M5T1U S-1004CA36I-I6T1U
3.7 V 1.0% S-1004CA37I-M5T1U S-1004CA37I-I6T1U
3.8 V 1.0% S-1004CA38I-M5T1U S-1004CA38I-I6T1U
3.9 V 1.0% S-1004CA39I-M5T1U S-1004CA39I-I6T1U
4.0 V 1.0% S-1004CA40I-M5T1U S-1004CA40I-I6T1U
4.1 V 1.0% S-1004CA41I-M5T1U S-1004CA41I-I6T1U
4.2 V 1.0% S-1004CA42I-M5T1U S-1004CA42I-I6T1U
4.3 V 1.0% S-1004CA43I-M5T1U S-1004CA43I-I6T1U
4.4 V 1.0% S-1004CA44I-M5T1U S-1004CA44I-I6T1U
4.5 V 1.0% S-1004CA45I-M5T1U S-1004CA45I-I6T1U
4.6 V 1.0% S-1004CA46I-M5T1U S-1004CA46I-I6T1U
4.7 V 1.0% S-1004CA47I-M5T1U S-1004CA47I-I6T1U
4.8 V 1.0% S-1004CA48I-M5T1U S-1004CA48I-I6T1U
4.9 V 1.0% S-1004CA49I-M5T1U S-1004CA49I-I6T1U
5.0 V 1.0% S-1004CA50I-M5T1U S-1004CA50I-I6T1U
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_02 S-1004 Series
7
4. 4 S-1004 Series CB type
Output form: CMOS output (Active "L")
Table 6
Detection Voltage SOT-23-5
1.0 V 22 mV S-1004CB10I-M5T1U
1.1 V 22 mV S-1004CB11I-M5T1U
1.2 V 22 mV S-1004CB12I-M5T1U
1.3 V 22 mV S-1004CB13I-M5T1U
1.4 V 22 mV S-1004CB14I-M5T1U
1.5 V 22 mV S-1004CB15I-M5T1U
1.6 V 22 mV S-1004CB16I-M5T1U
1.7 V 22 mV S-1004CB17I-M5T1U
1.8 V 22 mV S-1004CB18I-M5T1U
1.9 V 22 mV S-1004CB19I-M5T1U
2.0 V 22 mV S-1004CB20I-M5T1U
2.1 V 22 mV S-1004CB21I-M5T1U
2.2 V 1.0% S-1004CB22I-M5T1U
2.3 V 1.0% S-1004CB23I-M5T1U
2.4 V 1.0% S-1004CB24I-M5T1U
2.5 V 1.0% S-1004CB25I-M5T1U
2.6 V 1.0% S-1004CB26I-M5T1U
2.7 V 1.0% S-1004CB27I-M5T1U
2.8 V 1.0% S-1004CB28I-M5T1U
2.9 V 1.0% S-1004CB29I-M5T1U
3.0 V 1.0% S-1004CB30I-M5T1U
3.1 V 1.0% S-1004CB31I-M5T1U
3.2 V 1.0% S-1004CB32I-M5T1U
3.3 V 1.0% S-1004CB33I-M5T1U
3.4 V 1.0% S-1004CB34I-M5T1U
3.5 V 1.0% S-1004CB35I-M5T1U
3.6 V 1.0% S-1004CB36I-M5T1U
3.7 V 1.0% S-1004CB37I-M5T1U
3.8 V 1.0% S-1004CB38I-M5T1U
3.9 V 1.0% S-1004CB39I-M5T1U
4.0 V 1.0% S-1004CB40I-M5T1U
4.1 V 1.0% S-1004CB41I-M5T1U
4.2 V 1.0% S-1004CB42I-M5T1U
4.3 V 1.0% S-1004CB43I-M5T1U
4.4 V 1.0% S-1004CB44I-M5T1U
4.5 V 1.0% S-1004CB45I-M5T1U
4.6 V 1.0% S-1004CB46I-M5T1U
4.7 V 1.0% S-1004CB47I-M5T1U
4.8 V 1.0% S-1004CB48I-M5T1U
4.9 V 1.0% S-1004CB49I-M5T1U
5.0 V 1.0% S-1004CB50I-M5T1U
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series Rev.2.1_02
8
Pin Configurations
1. S-1004 Series NA / CA type
1. 1 SOT-23-5
132
45
Top view
Figure 3
Table 7 Pin Configuration A
Pin No. Symbol Description
1 OUT Voltage detection output pin
2 VDD Power supply pin
3 VSS GND pin
4 CD Connection pin for delay capacitor
5 SENSE Detection voltage input pin
1. 2 SNT-6A
5
4
6
2
3
1
Top view
Figure 4
Table 8 Pin Configuration A
Pin No. Symbol Description
1 OUT Voltage detection output pin
2 VDD Power supply pin
3 SENSE Detection voltage input pin
4 CD Connection pin for delay capacitor
5
NC*1 No connection
6 VSS GND pin
*1. The NC pin is electrically open.
The NC pin can be connected to the VDD pin or the VSS pin.
2. S-1004 Series NB / CB type
2. 1 SOT-23-5
132
45
Top view
Figure 5
Table 9 Pin Configuration B
Pin No. Symbol Description
1 OUT Voltage detection output pin
2 VSS GND pin
3 VDD Power supply pin
4 SENSE Detection voltage input pin
5 CD Connection pin for delay capacitor
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_02 S-1004 Series
9
Absolute Maximum Ratings
Table 10
(Ta = 25°C unless otherwise specified)
Item Symbol Absolute Maximum Rating Unit
Power supply voltage VDDVSS 12.0 V
CD pin input voltage VCD V
SS 0.3 to VDD 0.3 V
SENSE pin input voltage VSENSE V
SS 0.3 to 12.0 V
Output voltage Nch open-drain output product VOUT VSS 0.3 to 12.0 V
CMOS output product VSS 0.3 to VDD 0.3 V
Output current IOUT 50 mA
Power dissipation SOT-23-5 PD 600*1 mW
SNT-6A 400*1 mW
Operation ambient temperature To
pr
40 to 85 °C
Storage temperature Tst
g
40 to 125 °C
*1. When mounted on board
[Mounted board]
(1) Board size: 114.3 mm 76.2 mm t1.6 mm
(2) Name: JEDEC STANDARD51-7
Caution The absolute maximum ratings are rated values exceeding which the product could suffer
physical damage. These values must therefore not be exceeded under any conditions.
0 50 100 150
0
Ambient Temperature (Ta) [C]
200
100
300
500
700
400
600
SNT-6A
SOT-23-5
Power Dissipation (PD) [mW]
Figure 6 Power Dissipation of Package (When Mounted on Board)
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series Rev.2.1_02
10
Electrical Characteristics
1. Nch open-drain output product
Table 11
(Ta = 25°C unless otherwise specified)
Item Symbol Condition Min. Typ. Max. Unit Test
Circuit
Detection voltage*1 VDET 0.95 V VDD 10.0 V
1.0 V VDET(S) 2.2 V VDET(S)
0.022 VDET(S) VDET(S)
0.022 V 1
2.2 V VDET(S) 5.0 V VDET(S)
0.99 VDET(S) VDET(S)
1.01 V 1
Hysteresis width VHYS VDET
0.03
VDET
0.05
VDET
0.07 V 1
Current
consumption*2 ISS V
DD = 10.0 V, VSENSE = VDET(S) 1.0 V 0.50 0.90 A 2
Operation voltage VDD 0.95 10.0 V 1
Output current IOUT
Output transistor
Nch
VDS*3 = 0.5 V
VSENSE = 0.0 V
VDD = 0.95 V 0.59 1.00 mA 3
VDD = 1.2 V 0.73 1.33 mA 3
VDD = 2.4 V 1.47 2.39 mA 3
VDD = 4.8 V 1.86 2.50 mA 3
Leakage current ILEAK
Output transistor
Nch
VDD = 10.0 V, VDS*3 = 10.0 V, VSENSE = 10.0 V
0.08 A 3
Detection voltage
temperature
coefficient*4
VDET
Ta VDET Ta = 40°C to 85°C 100350ppm/C1
Detection
delay time*5 tDET V
DD = 5.0 V 40 s 4
Release
delay time*6 tRESET V
DD = VDET(S) 1.0 V, CD = 4.7 nF 10.79 12.69 14.59 ms 4
SENSE pin
resistance RSENSE 1.0 V VDET
(
S
)
1.2 V 5.0 19.0 42.0 M 2
1.2 V VDET
(
S
)
5.0 V 6.0 30.0 98.0 M 2
*1. VDET: Actual detection voltage value, VDET(S): Set detection voltage value (the center value of the detection voltage
range in Table 3 or Table 4)
*2. The current flowing through the SENSE pin resistance is not included.
*3. V
DS: Drain-to-source voltage of the output transistor
*4. The temperature change of the detection voltage [mV/°C] is calculated by using the following equation.
VDET
Ta []
mV/°C *1 = VDET(S) (typ.)[]
V*2 VDET
Ta VDET []
ppm/°C *3 1000
*1. Temperature change of the detection voltage
*2. Set detection voltage
*3. Detection voltage temperature coefficient
*5. The time period from when the pulse voltage of 6.0 V VDET(S) 2.0 V or 0 V is applied to the SENSE pin to when
VOUT reaches VDD / 2, after the output pin is pulled up to 5.0 V by the resistance of 470 k.
*6. The time period from when the pulse voltage of 0.95 V 10.0 V is applied to the SENSE pin to when VOUT reaches
VDD 90%, after the output pin is pulled up to VDD by the resistance of 100 k.
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_02 S-1004 Series
11
2. CMOS output product
Table 12
(Ta = 25°C unless otherwise specified)
Item Symbol Condition Min. Typ. Max. Unit Test
Circuit
Detection voltage*1 VDET 0.95 V VDD 10.0 V
1.0 V VDET(S) 2.2 V VDET(S)
0.022 VDET(S) VDET(S)
0.022 V 1
2.2 V VDET(S) 5.0 V VDET(S)
0.99 VDET(S) VDET(S)
1.01 V 1
Hysteresis width VHYS VDET
0.03
VDET
0.05
VDET
0.07 V 1
Current
consumption*2 ISS V
DD = 10.0 V, VSENSE = VDET(S) 1.0 V 0.50 0.90 A 2
Operation voltage VDD 0.95 10.0 V 1
Output current IOUT
Output transistor
Nch
VDS*3 = 0.5 V
VSENSE = 0.0 V
VDD = 0.95 V 0.59 1.00 mA 3
VDD = 1.2 V 0.73 1.33 mA 3
VDD = 2.4 V 1.47 2.39 mA 3
VDD = 4.8 V 1.86 2.50 mA 3
Output transistor
Pch VDD = 4.8 V 1.62 2.60 mA 5
VDS*3 = 0.5 V
VSENSE = 10.0 V VDD = 6.0 V 1.78 2.86  mA 5
Detection voltage
temperature
coefficient*4
VDET
Ta VDET Ta = 40°C to 85°C 100350 ppm/C1
Detection
delay time*5 tDET V
DD = 5.0 V 40 s 4
Release
delay time*6 tRESET V
DD = VDET(S) 1.0 V, CD = 4.7 nF 10.79 12.69 14.59 ms 4
SENSE pin
resistance RSENSE 1.0 V VDET
(
S
)
1.2 V 5.0 19.0 42.0 M 2
1.2 V VDET
(
S
)
5.0 V 6.0 30.0 98.0 M 2
*1. VDET: Actual detection voltage value, VDET(S): Set detection voltage value (the center value of the detection voltage
range in Table 5 or Table 6)
*2. The current flowing through the SENSE pin resistance is not included.
*3. V
DS: Drain-to-source voltage of the output transistor
*4. The temperature change of the detection voltage [mV/°C] is calculated by using the following equation.
VDET
Ta []
mV/°C *1 = VDET(S) (typ.)[]
V*2 VDET
Ta VDET []
ppm/°C *3 1000
*1. Temperature change of the detection voltage
*2. Set detection voltage
*3. Detection voltage temperature coefficient
*5. The time period from when the pulse voltage of 6.0 V VDET(S) 2.0 V or 0 V is applied to the SENSE pin to when
VOUT reaches VDD / 2.
*6. The time period from when the pulse voltage of 0.95 V 10.0 V is applied to the SENSE pin to when VOUT reaches
V
DD 90%.
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series Rev.2.1_02
12
Test Circuits
VDD VDD
VSS
OUT
R
100 k
V
SENSE
V

CD
VDD
VDD
VSS
OUT
V
SENSE
V
CD
Figure 7 Test Circuit 1 Figure 8 Test Circuit 1
(Nch open-drain output product) (CMOS output product)
VDD
OUT
A
VDD
VSS

SENSE
A

CD
VDS
VDD
AV
V

VDD
VSS
OUT
SENSE
CD
Figure 9 Test Circuit 2 Figure 10 Test Circuit 3
VDD VDD
VSS
OUT
R
470 k or 100 k
SENSE
P.G.
Oscilloscope
CD
VDD
VDD
VSS
OUT
SENSE
P.G.
Oscilloscope
CD
Figure 11 Test Circuit 4 Figure 12 Test Circuit 4
(Nch open-drain output product) (CMOS output product)
VDD
VDS
AV
V
VDD
VSS
OUT
SENSE


CD
Figure 13 Test Circuit 5
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_02 S-1004 Series
13
Standard Circuits
1. Nch open-drain output product
VDD
OUT
VSS
R
100 k
SENSE
CD
*1
CD
*1. The delay capacitor (CD) should be connected directly to the CD pin and the VSS pin.
Figure 14
2. CMOS output product
VDD
OUT
VSS
SENSE
CD
*1
CD
*1. The delay capacitor (CD) should be connected directly to the CD pin and the VSS pin.
Figure 15
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series Rev.2.1_02
14
Explanation of Terms
1. Detection voltage (VDET)
The detection voltage is a voltage at which the output in Figure 18 or Figure 19 turns to "L". The detection voltage
varies slightly among products of the same specification. The variation of detection voltage between the specified
minimum (VDET min.) and the maximum (VDET max.) is called the detection voltage range (Refer to Figure 16).
Example: In the S-1004Cx18, the detection voltage is either one in the range of 1.778 V VDET 1.822 V.
This means that some S-1004Cx18 have VDET = 1.778 V and some have VDET = 1.822 V.
2. Release voltage (VDET)
The release voltage is a voltage at which the output in Figure 18 or Figure 19 turns to "H". The release voltage
varies slightly among products of the same specification. The variation of release voltage between the specified
minimum (VDET min.) and the maximum (VDET max.) is called the release voltage range (Refer to Figure 17). The
range is calculated from the actual detection voltage (VDET) of a product and is in the range of VDET 1.03
VDET VDET 1.07.
Example: For the S-1004Cx18, the release voltage is either one in the range of 1.832 V VDET 1.949 V.
This means that some S-1004Cx18 have VDET = 1.832 V and some have VDET = 1.949 V.
V
SENSE
V
DET
min.
V
DET
max.
V
OUT
t
DET
Detection voltage
Detection voltage
range
V
SENSE
V
DET
min.
V
DET
max.
V
OUT
Release voltage
range
t
RESET
Release voltage
Figure 16 Detection Voltage Figure 17 Release Voltage
VDD VDD
VSS
OUT
R
100 k
V
SENSE
V

CD
VDD
VDD
VSS
OUT
V
SENSE
V
CD
Figure 18 Test Circuit of Detection Voltage Figure 19 Test Circuit of Detection Voltage
and Release Voltage and Release Voltage
(Nch open-drain output product) (CMOS output product)
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_02 S-1004 Series
15
3. Hysteresis width (VHYS)
The hysteresis width is the voltage difference between the detection voltage and the release voltage (the voltage at
point B the voltage at point A = VHYS in "Figure 23 Timing Chart of S-1004 Series NA / NB Type" and "Figure
25 Timing Chart of S-1004 Series CA / CB Type"). Setting the hysteresis width between the detection voltage
and the release voltage, prevents malfunction caused by noise on the input voltage.
4. Release delay time (tRESET)
The release delay time is the time period from when the input voltage to the SENSE pin exceeds the release
voltage (VDET) to when the output from the OUT pin inverts. The release delay time changes according to the
delay capacitor (CD).
t
RESET
V
SENSE
OUT
V
DET
Figure 20 Release Delay Time
5. Feed-through current
The feed-through current is a current that flows instantaneously to the VDD pin at the time of detection and release
of a voltage detector. The feed-through current is large in CMOS output product, small in Nch open-drain output
product.
6. Oscillation
In applications where an input resistor is connected (Figure 21), taking a CMOS output (active "L") product for
example, the feed-through current which is generated when the output goes from "L" to "H" (at the time of release)
causes a voltage drop equal to [feed-through current] [input resistance]. Since the VDD pin and the SENSE pin
are shorted as in Figure 21, the SENSE pin voltage drops at the time of release. Then the SENSE pin voltage
drops below the detection voltage and the output goes from "H" to "L". In this status, the feed-through current stops
and its resultant voltage drop disappears, and the output goes from "L" to "H". The feed-through current is then
generated again, a voltage drop appears, and repeating the process finally induces oscillation.
(CMOS output product)
R
A
V
IN
GND
V
DD
R
B
VDD
VSS
OUT
SENSE
CD
Figure 21 Example for Bad Implementation Due to Detection Voltage Change
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series Rev.2.1_02
16
Operation
1. Basic operation
1. 1 S-1004 Series NA / NB type
(1) When the power supply voltage (VDD) is the minimum operation voltage or higher, and the SENSE pin voltage
(VSENSE) is the release voltage (VDET) or higher, the Nch transistor is turned off to output VDD ("H") when the
output is pulled up. Since the Nch transistor (N1) is turned off, the input voltage to the comparator is
(RB RC ) VSENSE
RA RB RC .
(2) Even if VSENSE decreases to VDET or lower, V
DD is output when VSENSE is higher than the detection voltage
(VDET).
When VSENSE decreases to VDET or lower (point A in Figure 23), the Nch transistor is turned on. And then VSS
("L") is output from the OUT pin after the elapse of the detection delay time (tDET).
At this time, N1 is turned on, and the input voltage to the comparator is RB VSENSE
RA RB .
(3) Even if VSENSE further decreases to the IC's minimum operation voltage or lower, the output from the OUT pin is
stable when VDD is minimum operation voltage or higher.
(4) Even if VSENSE exceeds VDET, VSS is output when VSENSE is lower than VDET.
(5) When VSENSE increases to VDET or higher (point B in Figure 23), the Nch transistor is turned off. And then VDD
is output from the OUT pin after the elapse of the release delay time (tRESET) when the output is pulled up.
VSS
*1
*1
V
REF

 OUT
VDD
*1
SENSE
N1
R
B
R
C
R
A
V
DD
V
R
100 k
V
SENSE
Nch
Delay
circuit
*1
CD
C
D
*1. Parasitic diode
Figure 22 Operation of S-1004 Series NA / NB Type
A
B
V
SENSE
V
SS
V
DD
V
SS
(1) (2) (3) (5)(4)
t
DET
t
RESET
Hysteresis width
(V
HYS
)
Minimum operation voltage
Output from OUT pin
Release voltage (V
DET
)
Detection voltage (V
DET
)
Figure 23 Timing Chart of S-1004 Series NA / NB Type
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_02 S-1004 Series
17
1. 2 S-1004 Series CA / CB type
(1) When the power supply voltage (VDD) is the minimum operation voltage or higher, and the SENSE pin voltage
(VSENSE) is the release voltage (VDET) or higher, the Nch transistor is turned off and the Pch transistor is turned
on to output VDD ("H"). Since the Nch transistor (N1) is turned off, the input voltage to the comparator is
(RB RC ) VSENSE
RA RB RC .
(2) Even if VSENSE decreases to VDET or lower, V
DD is output when VSENSE is higher than the detection voltage
(VDET).
When VSENSE decreases to VDET or lower (point A in Figure 25), the Nch transistor is turned on and the Pch
transistor is turned off. And then VSS ("L") is output from the OUT pin after the elapse of the detection delay time
(tDET).
At this time, N1 is turned on, and the input voltage to the comparator is RB VSENSE
RA RB .
(3) Even if VSENSE further decreases to the IC's minimum operation voltage or lower, the output from the OUT pin is
stable when VDD is minimum operation voltage or higher.
(4) Even if VSENSE exceeds VDET, VSS is output when VSENSE is lower than VDET.
(5) When VSENSE increases to VDET or higher (point B in Figure 25), the Nch transistor is turned off and the Pch
transistor is turned on. And then VDD is output from the OUT pin after the elapse of the release delay time
(tRESET).
VSS
*1
V
REF

 OUT
VDD
*1
SENSE
N1
R
B
R
C
R
A
V
DD
V
V
SENSE
Nch
Pch
Delay
circuit
*1
CD
*1
*1
C
D
*1. Parasitic diode
Figure 24 Operation of S-1004 Series CA / CB Type
A
B
V
SENSE
V
SS
V
DD
V
SS
(1) (2) (3) (5)(4)
t
DET
t
RESET
Hysteresis width
(V
HYS
)
Minimum operation voltage
Output from OUT pin
Release voltage (V
DET
)
Detection voltage (V
DET
)
Figure 25 Timing Chart of S-1004 Series CA / CB Type
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series Rev.2.1_02
18
2. SENSE pin
2. 1 Error when detection voltage is set externally
By connecting a node that was resistance-divided by the resistor (RA) and the resistor (RB) to the SENSE pin as
seen in Figure 26, the detection voltage can be set externally.
For conventional products without the SENSE pin, RA cannot be too large since the resistance-divided node must
be connected to the VDD pin. This is because a feed-through current will flow through the VDD pin when it goes
from detection to release, and if RA is large, problems such as oscillation or larger error in the hysteresis width may
occur.
In the S-1004 Series, RA and RB are easily made larger since the resistance-divided node can be connected to the
SENSE pin through which no feed-through current flows. However, be careful of error in the current flowing through
the internal resistance (RSENSE) that will occur.
Although RSENSE in the S-1004 Series is large (5 M min.) to make the error small, RA and RB should be selected
such that the error is within the allowable limits.
2. 2 Selection of RA and RB
In Figure 26, the relation between the external setting detection voltage (VDX) and the actual detection voltage
(VDET) is ideally calculated by the equation below.
VDX = VDET ()
1 RA
RB ··· (1)
However, in reality there is an error in the current flowing through RSENSE.
When considering this error, the relation between VDX and VDET is calculated as follows.
VDX = VDET ()
1 RA
RB || RSENSE
= VDET
1 RA
RB RSENSE
RB RSENSE
= VDET ()
1 RA
RB RA
RSENSE VDET ··· (2)
By using equations (1) and (2), the error is calculated as VDET RA
RSENSE .
The error rate is calculated as follows by dividing the error by the right-hand side of equation (1).
RA RB
RSENSE (RA RB) 100 [%] = RA || RB
RSENSE 100 [%] ··· (3)
As seen in equation (3), the smaller the resistance values of RA and RB compared to RSENSE, the smaller the error
rate becomes.
Also, the relation between the external setting hysteresis width (VHX) and the hysteresis width (VHYS) is calculated
by equation below. Error due to RSENSE also occurs to the relation in a similar way to the detection voltage.
VHX = VHYS ()
1 RA
RB ··· (4)
VSS
OUT
VDD
SENSE
R
A
R
B
V
DX
V
DET
CD
R
SENSE
Figure 26 Detection Voltage External Setting Circuit
Caution If RA and RB are large, the SENSE pin input impedance becomes higher and may cause a
malfunction due to noise. In this case, connect a capacitor between the SENSE pin and the VSS
pin.
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_02 S-1004 Series
19
2. 3 Power on sequence
Apply power in the order, the VDD pin then the SENSE pin.
As seen in Figure 27, when VSENSE VDET, the OUT pin output (VOUT) rises and the S-1004 Series becomes the
release status (normal operation).
V
DD
V
SENSE
V
OUT
V
DET
t
RESET
Figure 27
Caution If power is applied in the order the SENSE pin then the VDD pin, an erroneous release may occur
even if VSENSE VDET.
2. 4 Precautions when shorting between the VDD pin and the SENSE pin
2. 4. 1 Input resistor
Do not connect the input resistor (RA) when shorting between the VDD pin and the SENSE pin.
A feed-through current flows through the VDD pin at the time of release. When connecting the circuit shown as
Figure 28, the feed-through current of the VDD pin flowing through RA will cause a drop in VSENSE at the time of
release.
At that time, oscillation may occur if VSENSE VDET.
VSS
OUT
VDD
SENSE
R
A
V
DD
CD
Figure 28
2. 4. 2 Parasitic resistance and parasitic capacitance
Due to the difference in parasitic resistance and parasitic capacitance of the VDD pin and the SENSE pin,
power may be applied to the SENSE pin first.
Note that an erroneous release may occur if this happens (refer to "2. 3 Power on sequence").
Caution In CMOS output product, make sure that the VDD pin input impedance does not become too
high, regardless of the above. Since a feed-through current is large, a malfunction may occur if
the VDD pin voltage changes greatly at the time of release.
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series Rev.2.1_02
20
2. 5 Malfunction when VDD falls
As seen in Figure 29, note that if the VDD pin voltage (VDD) drops steeply below 1.2 V when VDET V
SENSE
VDET, erroneous detection may occur.
When VDD_Low 1.2 V, erroneous detection does not occur.
When VDD_Low 1.2 V, the more the VDD falling amplitude increases or the shorter the falling time becomes, the
easier the erroneous detection.
Perform thorough evaluation in actual application.
V
DD
V
SENSE
V
OUT
V
DET
V
DET
V
DD_High
V
OUT
falling influenced by V
DD
falling
(erroneous detection)
V
DD_Low
(Voltage drops below 1.2 V.)
Figure 29
The S-1004Cx50 example in Figure 30 shows an example of erroneous detection boundary conditions.
0.1
V
DD_High
[V]
0
t
F
[s]
12
10
10001 10010
2
4
8
6
Danger of erroneous
detection
Figure 30
Remark Test conditions
Product name: S-1004Cx50
V
SENSE: VDET(S) 0.1 V
V
DD_High: VDD pin voltage before falling
V
DD_Low: VDD pin voltage after falling (0.95 V)
VDD: VDD_High VDD_Low
t
F: Falling time of VDD from VDD_High VDD 10% to VDD_Low VDD 10%
V
DD_High
V
DD_Low
V
DD_High
V
DD
10%
V
DD_Low
V
DD
10%
V
DD
t
F
Figure 31
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_02 S-1004 Series
21
3. Delay circuit
The delay circuit has the function that adjusts the release delay time (tRESET) from when the SENSE pin voltage
(VSENSE) reaches release voltage (VDET) to when the output from OUT pin inverts.
tRESET is determined by the delay coefficient, the delay capacitor (CD), and the release delay time when the CD pin
is open (tRESET0), and calculated by the equation below.
tRESET [ms] = Delay coefficient CD [nF] tRESET0 [ms]
Table 13
Operation
Temperature
Delay Coefficient
Min. Typ. Max.
Ta = 85°C 1.78 2.29 3.13
Ta = 25°C 2.30 2.66 3.07
Ta = 40°C 2.68 3.09 3.57
Table 14
Operation
Temperature
Release Delay Time when CD Pin is Open (tRESET0)
Min. Typ. Max.
Ta = 85°C 0.020 ms 0.049 ms 0.130 ms
Ta = 25°C 0.021 ms 0.059 ms 0.164 ms
Ta = 40°C 0.024 ms 0.074 ms 0.202 ms
Caution 1. Mounted board layout should be made in such a way that no current flows into or flows from
the CD pin since the impedance of the CD pin is high, otherwise correct delay time cannot be
provided.
2. There is no limit for the capacitance of CD as long as the leakage current of the capacitor can
be ignored against the built-in constant current value (30 nA to 200 nA).
3. The detection delay time (tDET) cannot be adjusted by CD.
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series Rev.2.1_02
22
4. Other characteristics
4. 1 Temperature characteristics of detection voltage
The shaded area in Figure 32 shows the temperature characteristics of detection voltage in the operation
temperature range.
40 25
0.945 mV/°C
V
DET
[V]
85 Ta [°C]
0.945 mV/°C
V
DET25*1
*1. VDET25 is a detection voltage value at Ta = 25°C.
Figure 32 Temperature Characteristics of Detection Voltage (Example for VDET = 2.7 V)
4. 2 Temperature characteristics of release voltage
The temperature change VDET
Ta of the release voltage is calculated by using the temperature change
VDET
Ta of the detection voltage as follows:
VDET
Ta = VDET
VDET VDET
Ta
The temperature change of the release voltage and the detection voltage has the same sign consequently.
4. 3 Temperature characteristics of hysteresis voltage
The temperature change of the hysteresis voltage is expressed as VDET
Ta VDET
Ta and is calculated as
follows:
VDET
Ta VDET
Ta = VHYS
VDET VDET
Ta
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_02 S-1004 Series
23
Precautions
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
In CMOS output product of the S-1004 Series, the feed-through current flows at the time of detection and release. If
the VDD pin input impedance is high, malfunction may occur due to the voltage drop by the feed-through current
when releasing.
In CMOS output product, oscillation may occur if a pull-down resistor is connected and falling speed of the SENSE
pin voltage (VSENSE) is slow near the detection voltage when the VDD pin and the SENSE pin are shorted.
When designing for mass production using an application circuit described herein, the product deviation and
temperature characteristics of the external parts should be taken into consideration. ABLIC Inc. shall not bear any
responsibility for patent infringements related to products using the circuits described herein.
ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by
products including this IC of patents owned by a third party.
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series Rev.2.1_02
24
Characteristics (Typical Data)
1. Detection voltage (VDET), Release voltage (VDET) vs. Temperature (Ta)
S-1004Cx10 VDD = 5.0 V
1.2
V
DET
, V
DET
[V]
40 857550250
25
Ta [C]
1.1
1.0
0.9
0.8
V
DET
V
DET
S-1004Cx24 VDD = 5.0 V
2.6
40 857550250
25
Ta [C]
2.5
2.4
2.3
2.2
V
DET
, V
DET
[V]
V
DET
V
DET
S-1004Cx50 VDD = 5.0 V
5.4
40 857550250
25
Ta [C]
5.2
5.0
4.8
4.6
V
DET
, V
DET
[V]
V
DET
V
DET
2. Hysteresis width (VHYS) vs. Temperature (Ta)
S-1004Cx10 VDD = 5.0 V
V
HYS
[%]
40 857550250
25
Ta [C]
7.0
6.0
5.0
4.0
3.0
S-1004Cx24 VDD = 5.0 V
V
HYS
[%]
40 857550250
25
Ta [C]
7.0
6.0
5.0
4.0
3.0
S-1004Cx50 VDD = 5.0 V
V
HYS
[%]
40 857550250
25
Ta [C]
7.0
6.0
5.0
4.0
3.0
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_02 S-1004 Series
25
3. Detection voltage (VDET) vs. Power supply voltage (VDD)
S-1004Cx10
1.030
1.020
1.010
1.000
0.990
0.980
0.970
0.0 2.0 4.0 6.0 8.0 10.0
V
DD
[V]
V
DET
[V]
Ta = 85
C
Ta = 25
C
Ta =
40
C
S-1004Cx24
2.430
2.420
2.410
2.400
2.390
2.380
2.370
0.0 2.0 4.0 6.0 8.0 10.0
V
DD
[V]
V
DET
[V]
Ta = 85
C
Ta = 25
C
Ta =
40
C
S-1004Cx50
5.050
0.0 2.0 4.0 6.0 8.0 10.0
V
DD
[V]
V
DET
[V]
5.025
5.000
4.975
4.950
Ta = 85
C
Ta = 25
C
Ta =
40
C
4. Hysteresis width (VHYS) vs. Power supply voltage (VDD)
S-1004Cx10
0.0 2.0 4.0 6.0 8.0 10.0
V
DD
[V]
7.0
6.0
5.0
4.0
3.0
V
HYS
[%]
Ta = 85
C
Ta = 25
C
Ta =
40
C
S-1004Cx24
0.0 2.0 4.0 6.0 8.0 10.0
V
DD
[V]
7.0
6.0
5.0
4.0
3.0
V
HYS
[%]
Ta = 85
C
Ta =
40
C
Ta = 25
C
S-1004Cx50
0.0 2.0 4.0 6.0 8.0 10.0
VDD [V]
7.0
6.0
5.0
4.0
3.0
VHYS [%]
Ta =
40
C
Ta = 25
C
Ta = 85
C
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series Rev.2.1_02
26
5. Current consumption (ISS) vs. Power supply voltage (VDD)
S-1004Cx10 Ta = 25°C,
V
SENSE = VDET(S) 0.1 V (during detection)
1.00
0.0 2.0 4.0 6.0 8.0 10.0
V
DD
[V]
0.80
0.60
0.40
0.20
0.00
I
SS
[A]
S-1004Cx10 Ta = 25°C,
V
SENSE = VDET(S) 1.0 V (during release)
1.00
0.0 2.0 4.0 6.0 8.0 10.0
V
DD
[V]
0.80
0.60
0.40
0.20
0.00
I
SS
[A]
S-1004Cx24 Ta = 25°C,
V
SENSE = VDET(S) 0.1 V (during detection)
1.00
0.0 2.0 4.0 6.0 8.0 10.0
V
DD
[V]
0.80
0.60
0.40
0.20
0.00
I
SS
[A]
S-1004Cx24 Ta = 25°C,
V
SENSE = VDET(S) 1.0 V (during release)
1.00
0.0 2.0 4.0 6.0 8.0 10.0
V
DD
[V]
0.80
0.60
0.40
0.20
0.00
I
SS
[A]
S-1004Cx50 Ta = 25°C,
V
SENSE = VDET(S) 0.1 V (during detection)
1.00
0.0 2.0 4.0 6.0 8.0 10.0
VDD [V]
0.80
0.60
0.40
0.20
0.00
ISS [A]
S-1004Cx50 Ta = 25°C,
V
SENSE = VDET(S) 1.0 V (during release)
1.00
0.0 2.0 4.0 6.0 8.0 10.0
VDD [V]
0.80
0.60
0.40
0.20
0.00
ISS [A]
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_02 S-1004 Series
27
6. Current consumption (ISS) vs. SENSE pin input voltage (VSENSE)
S-1004Cx10 Ta = 25°C,
V
DD = VDET(S) 1.0 V, VSENSE = 0.0 V 10.0 V
1.00
0.0 2.0 4.0 6.0 8.0 10.0
V
SENSE
[V]
0.80
0.60
0.40
0.20
0.00
I
SS
[A]
S-1004Cx24 Ta = 25°C,
V
DD = VDET(S) 1.0 V, VSENSE = 0.0 V 10.0 V
1.00
0.0 2.0 4.0 6.0 8.0 10.0
V
SENSE
[V]
0.80
0.60
0.40
0.20
0.00
I
SS
[A]
S-1004Cx50 Ta = 25°C,
V
DD = VDET(S) 1.0 V, VSENSE = 0.0 V 10.0 V
1.00
0.0 2.0 4.0 6.0 8.0 10.0
V
SENSE
[V]
0.80
0.60
0.40
0.20
0.00
I
SS
[A]
7. Current consumption (ISS) vs. Temperature (Ta)
S-1004Cx10 VDD = VDET(S) 1.0 V,
V
SENSE = VDET(S) 1.0 V (during release)
0.30
40 857550250
25
Ta [C]
0.25
0.20
0.15
0.10
0.05
0.00
I
SS
[A]
S-1004Cx24 VDD = VDET(S) 1.0 V,
V
SENSE = VDET(S) 1.0 V (during release)
0.30
40 857550250
25
Ta [C]
0.25
0.20
0.15
0.10
0.05
0.00
I
SS
[A]
S-1004Cx50 VDD = VDET(S) 1.0 V,
V
SENSE = VDET(S) 1.0 V (during release)
0.30
40 857550250
25
Ta [C]
0.25
0.20
0.15
0.10
0.05
0.00
I
SS
[A]
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series Rev.2.1_02
28
8. Nch transistor output current (IOUT) vs. VDS 9. Pch transistor output current (IOUT) vs. VDS
S-1004Nx12 Ta = 25°C,
V
SENSE = 0.0 V (during detection)
20.0
0.0
0.0 6.0
I
OUT
[mA]
V
DS
[V]
5.04.03.02.01.0
15.0
10.0
5.0
V
DD
= 6.0 V
V
DD
= 4.8 V
V
DD
= 3.6 V
V
DD
= 2.4 V
V
DD
= 1.2 V
V
DD
= 0.95 V
S-1004Cx12 Ta = 25°C,
V
SENSE = VDET(S) 1.0 V (during release)
40.0
0.0
0.0 10.0
I
OUT
[mA]
V
DS
[V]
2.0 4.0 6.0 8.0
30.0
20.0
10.0
V
DD
= 8.4 V
V
DD
= 1.2 V
V
DD
= 0.95 V
V
DD
= 7.2 V
V
DD
= 6.0 V
V
DD
= 4.8 V
V
DD
= 3.6 V
V
DD
= 2.4 V
10. Nch transistor output current (I
OUT
) vs. Power supply voltage (V
DD
) 11. Pch transistor output current (I
OUT
) vs.
Power supply voltage (V
DD
)
S-1004Nx12 VDS = 0.5 V,
V
SENSE = 0.0 V (during detection)
4.0
0.0
0.0 10.0
IOUT [mA]
VDD [V]
3.0
2.0
1.0
2.0 4.0 6.0 8.0
Ta = 40C
Ta = 25C
Ta = 85C
S-1004Cx12 VDS = 0.5 V,
V
SENSE = VDET(S) 1.0 V (during release)
5.0
0.0
0.0 10.0
I
OUT
[mA]
V
DD
[V]
2.0 4.0 6.0 8.0
4.0
3.0
2.0
1.0
Ta = 40C
Ta = 25C
Ta = 85C
12. Minimum operation voltage (VOUT) vs. Power supply voltage (VDD)
S-1004Nx10 VSENSE = VDD,
Pull-up to VDD, Pull-up resistance: 100 k
1.8
0.0
0.0 1.6
V
OUT
[V]
V
DD
[V]
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
1.41.21.00.80.60.40.2
Ta = 40CTa = 25C
Ta = 85C
S-1004Nx10 VSENSE = VDD,
Pull-up to 10 V, Pull-up resistance: 100 k
12.0
0.0
0.0 1.6
V
OUT
[V]
V
DD
[V]
1.41.21.00.80.60.40.2
10.0
8.0
6.0
4.0
2.0
Ta = 40C
Ta = 25C
Ta = 85C
13. Minimum operation voltage (VOUT) vs. SENSE pin input voltage (VSENSE)
S-1004Nx10 VDD = 0.95 V,
Pull-up to VDD, Pull-up resistance: 100 k
1.8
0.0
0.0 1.6
V
OUT
[V]
V
SENSE
[V]
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
1.41.21.00.80.60.40.2
Ta = 40C
Ta = 25C
Ta = 85C
S-1004Nx10 VDD = 0.95 V,
Pull-up to 10 V, Pull-up resistance: 100 k
12.0
0.0
0.0 1.6
V
OUT
[V]
V
SENSE
[V]
1.41.21.00.80.60.40.2
10.0
8.0
6.0
4.0
2.0
Ta = 40C
Ta = 25C
Ta = 85C
Remark V
DS: Drain-to-source voltage of the output transistor
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_02 S-1004 Series
29
14. Dynamic response vs. Output pin capacitance (COUT) (CD pin; open)
S-1004Cx10 Ta = 25°C,
V
DD = VDET(S) 1.0 V
0.00001
Response time [ms]
0.001
Output pin capacitance [F]
1
0.01
0.1
0.10.0001 0.010.001
t
PLH
t
PHL
S-1004Cx24 Ta = 25°C,
V
DD = VDET(S) 1.0 V
0.00001
Response time [ms]
0.001
Output pin capacitance [F]
1
0.01
0.1
0.10.0001 0.010.001
t
PHL
t
PLH
S-1004Cx50 Ta = 25°C,
V
DD = VDET(S) 1.0 V
0.00001
Response time [ms]
0.001
Output pin capacitance [F]
1
0.01
0.1
0.10.0001 0.010.001
t
PLH
t
PHL
S-1004Nx10 Ta = 25°C,
V
DD = VDET(S) 1.0 V
0.00001
Response time [ms]
0.01
Output pin capacitance [F]
100
10
1
0.1
0.10.0001 0.010.001
t
PHL
t
PLH
S-1004Nx24 Ta = 25°C,
V
DD = VDET(S) 1.0 V
0.00001
Response time [ms]
0.01
Output pin capacitance [F]
100
10
1
0.1
0.10.0001 0.010.001
t
PHL
t
PLH
S-1004Nx50 Ta = 25°C,
V
DD = VDET(S) 1.0 V
0.00001
Response time [ms]
0.01
Output pin capacitance [F]
100
10
1
0.1
0.10.0001 0.010.001
tPHL
tPLH
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series Rev.2.1_02
30
1 s
tPLH
VIH*1
SENSE pin voltage
Output voltage
VIL*2
VDD
VDD 10%
VDD 90%
tPHL
1 s
*1. V
IH = 10 V
*2. VIL = 0.95 V
Figure 33 Test Condition of Response Time
VDD VDD
VSS
OUT
R
100 k
SENSE
P.G.
Oscilloscope
CD
VDD
VDD
VSS
OUT
SENSE
P.G.
Oscilloscope
CD
Figure 34 Test Circuit of Response Time Figure 35 Test Circuit of Response Time
(Nch open-drain output product) (CMOS output product)
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_02 S-1004 Series
31
15. Release delay time (tRESET)
vs.
CD pin capacitance (CD) (Without output pin capacitance)
S-1004Cx10 Ta = 25°C,
V
DD = VDET(S) 1.0 V
0.01 0.1 1 10 100
0.01
10000
1000
1000
100
10
1
0.1
tRESET [ms]
CD [nF]
S-1004Cx24 Ta = 25°C,
V
DD = VDET(S) 1.0 V
0.01 0.1 1 10 100
0.01
10000
1000
1000
100
10
1
0.1
tRESET [ms]
CD [nF]
S-1004Cx50 Ta = 25°C,
V
DD = VDET(S) 1.0 V
0.01 0.1 1 10 100
0.01
10000
1000
1000
100
10
1
0.1
tRESET [ms]
CD [nF]
16. Release delay time (tRESET)
vs.
Temperature (Ta)
S-1004Cx10
CD = 4.7 nF, VDD = VDET(S) 1.0 V
15
14
13
12
11
t
RESET
[ms]
40 857550250
25
Ta [C]
16
S-1004Cx24
CD = 4.7 nF, VDD = VDET(S) 1.0 V
15
14
13
12
11
t
RESET
[ms]
40 857550250
25
Ta [C]
16
S-1004Cx50
CD = 4.7 nF, VDD = VDET(S) 1.0 V
15
14
13
12
11
t
RESET
[ms]
40 857550250
25
Ta [C]
16
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series Rev.2.1_02
32
17. Release delay time (tRESET)
vs.
Power supply voltage (VDD)
S-1004Cx10 Ta = 25°C,
C
D = 4.7 nF
8.0
6.0 10.02.0 4.0
11
15
V
DD
[V]
14
13
12
t
RESET
[ms]
16
0.0
1 s
t
RESET
V
IH*1
SENSE pin voltage
Output voltage
V
IL*2
V
DD
V
SS
V
DD
90%
*1. V
IH = 10 V
*2. VIL = 0.95 V
Figure 36 Test Condition of Release Delay Time
VDD VDD
VSS
OUT
R
100 k
SENSE
P.G.
Oscilloscope
CD
CD
VDD
VDD
VSS
OUT
SENSE
P.G.
Oscilloscope
CD
CD
Figure 37 Test Circuit of Release Delay Time Figure 38 Test Circuit of Release Delay Time
(Nch open-drain output product) (CMOS output product)
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_02 S-1004 Series
33
Application Circuit Examples
1. Microcomputer reset circuits
In microcomputers, when the power supply voltage is lower than the minimum operation voltage, an unspecified
operation may be performed or the contents of the memory register may be lost. When power supply voltage
returns to the normal level, the microcomputer needs to be initialized. Otherwise, the microcomputer may
malfunction after that. Reset circuits to protect microcomputer in the event of current being momentarily switched
off or lowered.
Using the S-1004 Series which has the low minimum operation voltage, the high-accuracy detection voltage and
the hysteresis width, reset circuits can be easily constructed as seen in Figure 39 and Figure 40.
GND
V
DD
V
DD1
Microcomputer
VDD
VSS
SENSE
OUT
CD
GND
V
DD
V
DD1
Microcom
p
uter
VDD
VSS
SENSE
OUT
CD
Figure 39 Example of Reset Circuit Figure 40 Example of Reset Circuit
(Nch open-drain output product) (CMOS output product)
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series Rev.2.1_02
34
2. Change of detection voltage
If there is not a product with a specified detection voltage value in the S-1004 Series, the detection voltage can be
changed by using a resistance divider or a diode, as seen in Figure 41 to Figure 44.
In Figure 41 and Figure 42, hysteresis width also changes.
R
A
V
IN
GND
V
DD
R
B
R
100 k
VSS
OUT
VDD
SENSE
CD
R
A
V
IN
GND
V
DD
R
B
VSS
OUT
VDD
SENSE
CD
Figure 41 Detection voltage change Figure 42 Detection voltage change
when using a resistance divider when using a resistance divider
(Nch open-drain output product) (CMOS output product)
Remark Detection voltage = RA RB
RB VDET
Hysteresis width =
RA RB
RB VHYS
V
f1
V
IN
GND
V
DD
R
100 k
VDD
VSS
OUT
SENSE
CD
V
f1
V
IN
GND
V
DD
VDD
VSS
OUT
SENSE
CD
Figure 43 Detection voltage change Figure 44 Detection voltage change
when using a diode when using a diode
(Nch open-drain output product) (CMOS output product)
Remark Detection voltage = Vf1 (VDET)
Caution 1. The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
2. Set the constants referring to "2. 1 Error when detection voltage is set externally" in
" Operation".
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
2.9±0.2
1.9±0.2
0.95±0.1
0.4±0.1
0.16 +0.1
-0.06
123
4
5
No. MP005-A-P-SD-1.3
MP005-A-P-SD-1.3
SOT235-A-PKG Dimensions
mm
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
ø1.5 +0.1
-0 2.0±0.05
ø1.0 +0.2
-0 4.0±0.1 1.4±0.2
0.25±0.1
3.2±0.2
123
45
No. MP005-A-C-SD-2.1
MP005-A-C-SD-2.1
SOT235-A-Carrier Tape
Feed direction
4.0±0.1(10 pitches:40.0±0.2)
mm
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
12.5max.
9.0±0.3
ø13±0.2
(60°) (60°)
QTY. 3,000
No. MP005-A-R-SD-1.1
MP005-A-R-SD-1.1
SOT235-A-Reel
Enlarged drawing in the central part
mm
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
mm
SNT-6A-A-PKG Dimensions
PG006-A-P-SD-2.1
No. PG006-A-P-SD-2.1
0.2±0.05
0.48±0.02
0.08 +0.05
-0.02
0.5
1.57±0.03
123
45
6
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
Feed direction
4.0±0.1
2.0±0.05
4.0±0.1
ø1.5 +0.1
-0
ø0.5
1.85±0.05 0.65±0.05
0.25±0.05
mm
PG006-A-C-SD-2.0
SNT-6A-A-Carrier Tape
No. PG006-A-C-SD-2.0
+0.1
-0
1
2
4
3
56
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
12.5max.
9.0±0.3
ø13±0.2
(60°) (60°)
QTY.
No. PG006-A-R-SD-1.0
PG006-A-R-SD-1.0
Enlarged drawing in the central part
SNT-6A-A-Reel
5,000
mm
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
mm
SNT-6A-A
-Land Recommendation
PG006-A-L-SD-4.1
No. PG006-A-L-SD-4.1
0.3
0.2
0.52
1.36
0.52
1
2
Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package.
2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm
or less from the land pattern surface.
3. Match the mask aperture size and aperture position with the land pattern.
4. Refer to "SNT Package User's Guide" for details.
1. (0.25 mm min. / 0.30 mm typ.)
2. (1.30 mm ~ 1.40 mm)
0.03 mm
SNT
1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.).
2. Do not widen the land pattern to the center of the package ( 1.30 mm ~ 1.40 mm ).
1.
2. (1.30 mm ~ 1.40 mm)
(0.25 mm min. / 0.30 mm typ.)
Disclaimers (Handling Precautions)
1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5. Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7. The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8. The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9. In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07
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