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128MX8, 64MX16 1Gb DDR3 SDRAM WITH ECC
MARCH 2018
FEATURES
Standard Voltage: VDD and VDDQ = 1.5V ± 0.075V
High speed data transfer rates with system
frequency up to 800 MHz
8 internal banks for concurrent operation
8n-bit pre-fetch architecture
Programmable CAS Latency
Programmable Additive Latency: 0, CL-1,CL-2
Programmable CAS WRITE latency (CWL) based
on tCK
Programmable Burst Length: 4 and 8
Programmable Burst Sequence: Sequential or
Interleave
BL switch on the fly
Auto Self Refresh(ASR)
Self Refresh Temperature(SRT)
Refresh Interval:
7.8 μs (8192 cycles/64 ms) Tc= -40°C to 85°C
3.9 μs (8192 cycles/32 ms) Tc= 85°C to 105°C
1.95 μs (8192 cycles/16ms)Tc=105°C to 125°C
Partial Array Self Refresh
Asynchronous RESET pin
TDQS (Termination Data Strobe) supported (x8
only)
OCD (Off-Chip Driver Impedance Adjustment)
Dynamic ODT (On-Die Termination)
Driver strength : RZQ/7, RZQ/6 (RZQ = 240 )
Write Leveling
Operating temperature:
Automotive, A1 (TC = -40°C to +95°C)
Automotive, A2 (TC = -40°C to +105°C)
Automotive, A3 (TC= -40°C to +125°C)
ECC
Single bit error correction (per 64-bits)
Restrictions on Burst Length and Data Mask
OPTIONS
Configuration:
128Mx8
64Mx16
Package:
96-ball FBGA (9mm x 13mm) for x16
78-ball FBGA (8mm x 10.5mm) for x8
ADDRESS TABLE
Parameter
128Mx8
64Mx16
Row Addressing
A0-A13
A0-A12
Column Addressing
A0-A9
A0-A9
Bank Addressing
BA0-2
BA0-2
Page size
1KB
2KB
Auto Precharge Addressing
A10/AP
A10/AP
BL switch on the fly
A12/BC#
A12/BC#
SPEED BIN
Speed Option
15H
125K
Units
JEDEC Speed Grade
DDR3-1333H
DDR3-1600K
CL-nRCD-nRP
9-9-9
11-11-11
tCK
tRCD,tRP(min)
13.5
13.75
ns
Note: Faster speed options may be backward compatible to slower speed options. Refer to timing tables (8.3)
Copyright © 2018 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised
to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product
can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use
in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
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1. DDR3 PACKAGE BALLOUT
1.1 DDR3 SDRAM package ballout 78-ball FBGA – x8
1
2
3
4
5
6
7
8
9
A
VSS
VDD
NC
NU/TDQS#
VSS
VDD
B
VSS
VSSQ
DQ0
DM/TDQS
VSSQ
VDDQ
C
VDDQ
DQ2
DQS
DQ1
DQ3
VSSQ
D
VSSQ
DQ6
DQS#
VDD
VSS
VSSQ
E
VREFDQ
VDDQ
DQ4
DQ7
DQ5
VDDQ
F
NC1
VSS
RAS#
CK
VSS
NC
G
ODT
VDD
CAS#
CK#
VDD
CKE
H
NC
CS#
WE#
A10/AP
ZQ
NC
J
VSS
BA0
BA2
NC(A15)
VREFCA
VSS
K
VDD
A3
A0
A12/BC#
BA1
VDD
L
VSS
A5
A2
A1
A4
VSS
M
VDD
A7
A9
A11
A6
VDD
N
VSS
RESET#
A13
NC(A14)
A8
VSS
Note:
NC balls have no internal connection. NC(A14) and NC(A15) are one of NC pins and reserved for higher densities.
1.2 DDR3 SDRAM package ballout 96-ball FBGA – x16
1
2
3
4
5
6
7
8
9
A
VDDQ
DQU5
DQU7
DQU4
VDDQ
VSS
B
VSSQ
VDD
VSS
DQSU#
DQU6
VSSQ
C
VDDQ
DQU3
DQU1
DQSU
DQU2
VDDQ
D
VSSQ
VDDQ
DMU
DQU0
VSSQ
VDD
E
VSS
VSSQ
DQL0
DML
VSSQ
VDDQ
F
VDDQ
DQL2
DQSL
DQL1
DQL3
VSSQ
G
VSSQ
DQL6
DQSL#
VDD
VSS
VSSQ
H
VREFDQ
VDDQ
DQL4
DQL7
DQL5
VDDQ
J
NC
VSS
RAS#
CK
VSS
NC
K
ODT
VDD
CAS#
CK#
VDD
CKE
L
NC
CS#
WE#
A10/AP
ZQ
NC
M
VSS
BA0
BA2
NC(A15)
VREFCA
VSS
N
VDD
A3
A0
A12/BC#
BA1
VDD
P
VSS
A5
A2
A1
A4
VSS
R
VDD
A7
A9
A11
A6
VDD
T
VSS
RESET#
NC(A13)
NC(A14)
A8
VSS
Note:
NC balls have no internal connection. NC(A13), NC(A14) and NC(A15) are one of NC pins and reserved for higher densities.
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1.3 Pinout Description - JEDEC Standard
Symbol
Type
Function
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK#.
CKE
Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and
device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and
Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is
asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have become stable during
the power on and initialization sequence, they must be maintained during all operations
(including Self-Refresh). CKE must be maintained high throughout read and write accesses.
Input buffers, excluding CK, CK#, ODT and CKE, are disabled during power-down. Input
buffers, excluding CKE, are disabled during Self-Refresh.
CS#
Input
Chip Select: All commands are masked when CS# is registered HIGH. CS# provides for
external Rank selection on systems with multiple Ranks. CS# is considered part of the
command code.
ODT
Input
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the
DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQSU, DQSU#, DQSL,
DQSL#, DMU, and DML signal. The ODT pin will be ignored if MR1 and MR2 are programmed
to disable RTT.
RAS#. CAS#.
WE#
Input
Command Inputs: RAS#, CAS# and WE# (along with CS#) define the command being entered.
DM, (DMU),
(DML)
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH coincident with that input data during a Write access. DM is sampled on both
edges of DQS. For x8 device, the function of DM or TDQS/TDQS# is enabled by Mode
Register A11 setting in MR1.
BA0 - BA2
Input
Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write, or Precharge
command is being applied. Bank address also determines which mode register is to be
accessed during a MRS cycle.
A0 - A13
Input
Address Inputs: Provide the row address for Active commands and the column address for
Read/ Write commands to select one location out of the memory array in the respective bank.
(A10/AP and A12/BC# have additional functions; see below). The address inputs also provide
the op-code during Mode Register Set commands.
A10 / AP
Input
Auto-precharge: A10 is sampled during Read/Write commands to determine whether
Autoprecharge should be performed to the accessed bank after the Read/Write operation.
(HIGH: Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a Precharge
command to determine whether the Precharge applies to one bank (A10 LOW) or all banks
(A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses.
A12 / BC#
Input
Burst Chop: A12 / BC# is sampled during Read and Write commands to determine if burst chop
(on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See command truth
table for details.
RESET#
Input
Active Low Asynchronous Reset: Reset is active when RESET# is LOW, and inactive when
RESET# is HIGH. RESET# must be HIGH during normal operation. RESET# is a CMOS rail-
to-rail signal with DC high and low at 80% and 20% of VDD, i.e., 1.20V for DC high and 0.30V
for DC low.
DQ(DQL, DQU)
Input /
Output
Data Input/ Output: Bi-directional data bus.
DQS,
DQS#, DQSU,
DQSU#, DQSL,
DQSL#
Input /
Output
Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered
in write data. For the x16, DQSL corresponds to the data on DQL0-DQL7; DQSU corresponds
to the data on DQU0-DQU7. The data strobes DQS, DQSL, and DQSU are paired with
differential signals DQS#, DQSL#, and DQSU#, respectively, to provide differential pair
signaling to the system during reads and writes. DDR3 SDRAM supports differential data
strobe only and does not support single-ended.
TDQS, TDQS#
Output
Termination Data Strobe: TDQS/TDQS# is applicable for x8 DRAMs only. When enabled via
Mode Register A11 = 1 in MR1, the DRAM will enable the same termination resistance function
on TDQS/TDQS# that is applied to DQS/DQS#. When disabled via mode register A11 = 0 in
MR1, DM/TDQS will provide the data mask function and TDQS# is not used. x16 DRAMs must
disable the TDQS function via mode register A11 = 0 in MR1.
NC
No Connect: No internal electrical connection is present.
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VDDQ
Supply
DQ Power Supply: 1.5 V +/- 0.075 V
VSSQ
Supply
DQ Ground
VDD
Supply
Power Supply: 1.5 V +/- 0.075 V
VSS
Supply
Ground
VREFDQ
Supply
Reference voltage for DQ
VREFCA
Supply
Reference voltage for CA
ZQ
Supply
Reference Pin for ZQ
Note: Input only pins (BA0-BA2, A0-A13, RAS#, CAS#, WE#, CS#, CKE, ODT, and RESET#) do not supply termination.
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2. FUNCTION DESCRIPTION
2.1 Simplified State Diagram
Abbreviation
Function
Abbreviation
Function
Abbreviation
Function
ACT
Active
Read
RD, RDS4, RDS8
PDE
Enter Power-down
PRE
Precharge
Read A
RDA, RDAS4, RDAS8
PDX
Exit Power-down
PREA
Precharge All
Write
WR, WRS4, WRS8
SRE
Self-Refresh entry
MRS
Mode Register Set
Write A
WRA, WRAS4, WRAS8
SRX
Self-Refresh exit
REF
Refresh
RESET
Start RESET Procedure
MPR
Multi-Purpose Register
ZQCL
ZQ Calibration Long
ZQCS
ZQ Calibration Short
Power
On
Power
applied
RESET
From
Any state
Reset
Procedure
Initialization
ZQCL
ZQ
Calibration
ZQCL
ZQCS
Idle
MRS,MPR,
Write
Leveling
Self
Refresh
SRE
SRX
REF
Refreshing
Precharge
Power
Down
PDX
PDE
ACT
Activating
Bank
Active
Active
Power
Down
PDE
PDX
Reading
Writing
Writing
Reading
Precharging
Automatic
Sequence
Command
Sequence
Write
Write
Write A
Write
Write A
Write A
PRE,PREA
Read
Read A
Read
Read A
PRE,PREA
PRE,PREA
Read A
Read
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2.2 RESET and Initialization Procedure
2.2.1 Power-up Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power (RESET# is recommended to be maintained below 0.2 x VDD; all other inputs may be undefined).
RESET# needs to be maintained for minimum 200 us with stable power. CKE is pulled “Low” anytime before
RESET# being de-asserted (min. time 10 ns). The power voltage ramp time between 300mV to VDD(min) must be
no greater than 200 ms; and during the ramp, VDD > VDDQ and (VDD - VDDQ) < 0.3 volts.
VDD and VDDQ are driven from a single power converter output, AND
The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD
on one side and must be larger than or equal to VSSQ and VSS on the other side. In addition, VTT is limited to
0.95 V max once power ramp is finished, AND
Vref tracks VDDQ/2.
OR
Apply VDD without any slope reversal before or at the same time as VDDQ.
Apply VDDQ without any slope reversal before or at the same time as VTT & Vref.
The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD
on one side and must be larger than or equal to VSSQ and VSS on the other side.
2. After RESET# is de-asserted, wait for another 500 us until CKE becomes active. During this time, the DRAM will
start internal state initialization; this will be done independently of external clocks.
3. Clocks (CK, CK#) need to be started and stabilized for at least 10 ns or 5 tCK (which is larger) before CKE goes
active. Since CKE is a synchronous signal, the corresponding set up time to clock (tIS) must be met. Also, a NOP or
Deselect command must be registered (with tIS set up time to clock) before CKE goes active. Once the CKE is
registered “High” after Reset, CKE needs to be continuously registered “High” until the initialization sequence is
finished, including expiration of tDLLK and tZQinit.
4. The DDR3 SDRAM keeps its on-die termination in high-impedance state as long as RESET# is asserted. Further,
the SDRAM keeps its on-die termination in high impedance state after RESET# deassertion until CKE is registered
HIGH. The ODT input signal may be in undefined state until tIS before CKE is registered HIGH. When CKE is
registered HIGH, the ODT input signal may be statically held at either LOW or HIGH. If RTT_NOM is to be enabled
in MR1, the ODT input signal must be statically held LOW. In all cases, the ODT input signal remains static until the
power up initialization sequence is finished, including the expiration of tDLLK and tZQinit.
5. After CKE is being registered high, wait minimum of Reset CKE Exit time, tXPR, before issuing the first MRS
command to load mode register. (tXPR=max (tXS ; 5 x tCK)
6. Issue MRS Command to load MR2 with all application settings. (To issue MRS command for MR2, provide “Low” to
BA0 and BA2, “High” to BA1.)
7. Issue MRS Command to load MR3 with all application settings. (To issue MRS command for MR3, provide “Low” to
BA2, “High” to BA0 and BA1.)
8. Issue MRS Command to load MR1 with all application settings and DLL enabled. (To issue "DLL Enable" command,
provide "Low" to A0, "High" to BA0 and "Low" to BA1 – BA2).
9. Issue MRS Command to load MR0 with all application settings and “DLL reset”. (To issue DLL reset command,
provide "High" to A8 and "Low" to BA0-2).
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10. Issue ZQCL command to starting ZQ calibration.
11. Wait for both tDLLK and tZQinit completed.
12. The DDR3 SDRAM is now ready for normal operation.
Figure2.1.1 Reset and Initialization Sequence at Power-on Ramping
Ta
CK,CK#
VDD,VDDQ
RESET#
CKE
CMMAND
BA
ODT
RTT
Tb
T=200µS
Tmin=10nS
T=500µS
tCKSRX
tIS
tIS
tIS
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Tc
Td
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tXPR
tMRD
tMRD
tMRD
tMOD
tZQinit
tDLLK
tIS
Valid
Valid
Valid
Valid
MRD
MRD
MRD
MRD
ZQCL
1)
MR2
MR3
MR1
MR0
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Te
Tf
Tg
Th
Ti
Tj
Tk
Note1. From time point “Td” until “Tk” NOP or DES commands must be
applied between MRS and ZQCL commands.
Time
Break
DON’T
CARE
Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW
1)
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2.2.2 Reset Initialization with Stable Power
The following sequence is required for RESET at no power interruption initialization.
1. Asserted RESET below 0.2 * VDD anytime when reset is needed (all other inputs may be undefined). RESET
needs to be maintained for minimum 100 ns. CKE is pulled “LOW” before RESET being de-asserted (min. time 10
ns).
2. Follow Power-up Initialization Sequence steps 2 to 11.
3. The Reset sequence is now completed; DDR3 SDRAM is ready for normal operation.
Figure2.1.2 Reset Procedure at Power Stable Condition
2.3 Register Definition
2.3.1 Programming the Mode Registers
For application flexibility, various functions, features, and modes are programmable in four Mode Registers, provided by
the DDR3 SDRAM, as user defined variables and they must be programmed via a Mode Register Set (MRS) command.
As the default values of the Mode Registers (MR#) are not defined, contents of Mode Registers must be fully initialized
and/or re-initialized, i.e. written, after power up and/or reset for proper operation. Also the contents of the Mode Registers
can be altered by re-executing the MRS command during normal operation. When programming the mode registers, even
if the user chooses to modify only a sub-set of the MRS fields, all address fields within the accessed mode register must
be redefined when the MRS command is issued. MRS command and DLL Reset do not affect array contents, which
means these commands can be executed any time after power-up without affecting the array contents The mode register
Ta
CK,CK#
VDD,VDDQ
RESET#
CKE
CMMAND
BA
ODT
RTT
Tb
T=100nS
Tmin=10nS
T=500µS
tCKSRX
tIS
tIS
tIS
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tXPR
tMRD
tMRD
tMRD
tMOD
tZQinit
tDLLK
tIS
Valid
Valid
Valid
Valid
MRD
MRD
MRD
MRD
ZQCL
1)
MR2
MR3
MR1
MR0
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Te
Tf
Tg
Th
Ti
Tj
Tk
Note1. From time point “Td” until “Tk” NOP or DES commands must be
applied between MRS and ZQCL commands.
Time
Break
DON’T
CARE
Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW
1)
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set command cycle time, tMRD is required to complete the write operation to the mode register and is the minimum time
required between two MRS commands shown as below.
Figure2.3.1a tMRD Timing
The MRS command to Non-MRS command delay, tMOD, is require for the DRAM to update the features except DLL
reset, and is the minimum time required from an MRS command to a non-MRS command excluding NOP and DES shown
as the following figure.
Figure 2.3.1b tMOD Timing
The mode register contents can be changed using the same command and timing requirements during normal operation
as long as the DRAM is in idle state, i.e., all banks are in the precharged state with tRP satisfied, all data bursts are
completed and CKE is high prior to writing into the mode register. If the RTT_NOM Feature is enabled in the Mode
Register prior and/or after an MRS Command, the ODT Signal must continuously be registered LOW ensuring RTT is in
an off State prior to the MRS command. The ODT Signal maybe registered high after tMOD has expired. If the RTT_NOM
Feature is disabled in the Mode Register prior and after an MRS command, the ODT Signal can be registered either LOW
or HIGH before, during and after the MRS command. The mode registers are divided into various fields depending on the
functionality and/or modes.
CK#
CK
Command
Address
CKE
Settings
ODT
ODT
RTT_Nom ENABLED prior and/or after MRS command
RTT_Nom DISABLED prior and after MRS command
ODTLoff + 1
Old Settings
( (
) )
Time
Break
DON’T
CARE
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
MRS
Valid
Valid
NOP/
DEC
Valid
Valid
Valid
Valid
MRS
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
NOP/
DEC
NOP/
DEC
NOP/
DEC
tMRD
tMRD
New Settings
CK#
CK
Command
Address
CKE
Settings
ODT
ODT
RTT_Nom ENABLED prior and/or after MRS command
RTT_Nom DISABLED prior and after MRS command
ODTLoff + 1
Old Settings
( (
) )
Time
Break
DON’T
CARE
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
MRS
Valid
Valid
NOP/
DEC
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
NOP/
DEC
NOP/
DEC
NOP/
DEC
tMOD
New Settings
NOP/
DEC
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2.3.2 Mode Register MR0
The mode register MR0 stores the data for controlling various operating modes of DDR3 SDRAM. It controls burst length,
read burst type, CAS latency, test mode, DLL reset, WR and DLL control for precharge Power-Down, which include
vendor specific options to make DDR3 SDRAM useful for various applications. The mode register is written by asserting
low on CS#, RAS#, CAS#, WE#, BA0, BA1, and BA2, while controlling the states of address pins according to the
following figure.
1. A13 must be programmed to 0 during MRS.
2. WR (write recovery for autoprecharge)min in clock cycles is calculated by dividing tWR(in ns) by tCK(in ns) and rounding up to the next integer:
WRmin[cycles] = Roundup(tWR[ns] / tCK[ns]). The WR value in the mode register must be programmed to be equal or larger than WRmin. The
programmed WR value is used with tRP to determine tDAL.
3. The table only shows the encodings for a given Cas Latency. For actual supported Cas Latency, please refer to speedbin tables for each
frequency
4. The table only shows the encodings for Write Recovery. For actual Write recovery timing, please refer to AC timing table.
5. Configuration of BC4 may restrict operation of ECC function
Figure 2.3.2 — MR0 Definition
2.3.2.1 Burst Length, Type and Order
Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected via bit A3
as shown in Figure 2.3.2. The ordering of accesses within a burst is determined by the burst length, burst type, and the
starting column address as shown in Table below. The burst length is defined by bits A0-A1. Burst length options include
fixed BC4, fixed BL8, and ‘on the fly’ which allows BC4 or BL8 to be selected coincident with the registration of a Read or
BA2
BA1
BA0
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Field
0
0
0
0*
1
PPD
WR
DLL
TM
CAS Latency
RBT
CL
BL
Mode Register 0
A8
DLL Reset
A7
mode
A3
Read Burst Type
A1
A0
BL
0
No
0
Nomal
0
Nibble Sequential
0
0
8 (Fixed)
1
Yes
1
Test
1
Interleave
0
1
BC4 or 8 (on the fly) *5
1
0
BC4 (Fixed) *5
A12
DLL Control for
Write recovery for autoprecharge
1
1
Reserved
Precharge PD
A11
A10
A9
WR(cycles)
0
Slow exit (DLL off)
0
0
0
Reserved
A6
A5
A4
A2
CAS Latency
1
Fast exit (DLL on)
0
0
1
5
*2
0
0
0
0
Reserved
0
1
0
6
*2
0
0
1
0
5
BA1
BA0
MR Select
0
1
1
7
*2
0
1
0
0
6
0
0
MR0
1
0
0
8
*2
0
1
1
0
7
0
1
MR1
1
0
1
10
*2
1
0
0
0
8
1
0
MR2
1
1
0
12
*2
1
0
1
0
9
1
1
MR3
1
1
1
14
*2
1
1
0
0
10
1
1
1
0
11
0
0
0
1
12
0
0
1
1
13
0
1
0
1
Reserved
0
1
1
1
Reserved
1
0
0
1
Reserved
1
0
1
1
Reserved
1
1
0
1
Reserved
1
1
1
1
Reserved
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Write command via A12/BC#. Configuartion of BL4 or usage of BC4 may restrict the ECC Functionality. Please refer to
ECC Feature.
Burst
Length
READ/
WRITE
Starting
Column
ADDRESS
(A2,A1,A0)
burst type = Sequential
(decimal)
A3 = 0
burst type = Interleaved
(decimal)
A3 = 1
Notes
4
Chop
READ
0
0,1,2,3,T,T,T,T
0,1,2,3,T,T,T,T
1, 2, 3, 6
1
1,2,3,0,T,T,T,T
1,0,3,2,T,T,T,T
1, 2, 3, 6
10
2,3,0,1,T,T,T,T
2,3,0,1,T,T,T,T
1, 2, 3, 6
11
3,0,1,2,T,T,T,T
3,2,1,0,T,T,T,T
1, 2, 3, 6
100
4,5,6,7,T,T,T,T
4,5,6,7,T,T,T,T
1, 2, 3, 6
101
5,6,7,4,T,T,T,T
5,4,7,6,T,T,T,T
1, 2, 3, 6
110
6,7,4,5,T,T,T,T
6,7,4,5,T,T,T,T
1, 2, 3, 6
111
7,4,5,6,T,T,T,T
7,6,5,4,T,T,T,T
1, 2, 3, 6
WRITE
0,V,V
0,1,2,3,X,X,X,X
0,1,2,3,X,X,X,X
1, 2, 4, 5, 6
1,V,V
4,5,6,7,X,X,X,X
4,5,6,7,X,X,X,X
1, 2, 4, 5, 6
8
READ
0
0,1,2,3,4,5,6,7
0,1,2,3,4,5,6,7
2
1
1,2,3,0,5,6,7,4
1,0,3,2,5,4,7,6
2
10
2,3,0,1,6,7,4,5
2,3,0,1,6,7,4,5
2
11
3,0,1,2,7,4,5,6
3,2,1,0,7,6,5,4
2
100
4,5,6,7,0,1,2,3
4,5,6,7,0,1,2,3
2
101
5,6,7,4,1,2,3,0
5,4,7,6,1,0,3,2
2
110
6,7,4,5,2,3,0,1
6,7,4,5,2,3,0,1
2
111
7,4,5,6,3,0,1,2
7,6,5,4,3,2,1,0
2
WRITE
V,V,V
0,1,2,3,4,5,6,7
0,1,2,3,4,5,6,7
2, 4
Notes:
1. In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles earlier than for the BL8 mode. This means
that the starting point for tWR and tWTR will be pulled in by two clocks. In case of burst length being selected on-the-fly via A12/BC#, the internal
write operation starts at the same point in time like a burst of 8 write operation. This means that during on-the-fly control, the starting point for tWR
and tWTR will not be pulled in by two clocks.
2. 0...7 bit number is value of CA[2:0] that causes this bit to be the first read during a burst.
3. T: Output driver for data and strobes are in high impedance.
4. V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins.
5. X: Don’t Care.
6. Use of this burst length may restrict ECC functionality
2.3.2.2 CAS Latency
The CAS Latency is defined by MR0 (bits A9-A11) as shown in Figure 2.3.2. CAS Latency is the delay, in clock cycles,
between the internal Read command and the availability of the first bit of output data. DDR3 SDRAM does not support
any half-clock latencies. The overall Read Latency (RL) is defined as Additive Latency (AL) + CAS Latency (CL); RL = AL
+ CL. For more information on the supported CL and AL settings based on the operating clock frequency, refer to
“Standard Speed Bins”.
2.3.2.3 Test Mode
The normal operating mode is selected by MR0 (bit A7 = 0) and all other bits set to the desired values shown in Figure
2.3.2. Programming bit A7 to a ‘1’ places the DDR3 SDRAM into a test mode that is only used by the DRAM Manufacturer
and should NOT be used. No operations or functionality is specified if A7 = 1.
2.3.2.4 DLL Reset
The DLL Reset bit is self-clearing, meaning that it returns back to the value of ‘0’ after the DLL reset function has been
issued. Once the DLL is enabled, a subsequent DLL Reset should be applied. Any time that the DLL reset function is
used, tDLLK must be met before any functions that require the DLL can be used (i.e., Read commands or ODT
synchronous operations).
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2.3.2.5 Write Recovery
The programmed WR value MR0 (bits A9, A10, and A11) is used for the auto precharge feature along with tRP to
determine tDAL. WR (write recovery for auto-precharge) min in clock cycles is calculated by dividing tWR (in ns) by tCK
(in ns) and rounding up to the next integer: WRmin[cycles] = Roundup(tWR[ns]/tCK[ns]). The WR must be programmed to
be equal to or larger than tWR(min).
2.3.2.6 Precharge PD DLL
MR0 (bit A12) is used to select the DLL usage during precharge power-down mode. When MR0 (A12 = 0), or ‘slow-exit’,
the DLL is frozen after entering precharge power-down (for potential power savings) and upon exit requires tXPDLL to be
met prior to the next valid command. When MR0 (A12 = 1), or ‘fast-exit’, the DLL is maintained after entering precharge
power-down and upon exiting power-down requires tXP to be met prior to the next valid command.
2.3.3 Mode Register MR1
The Mode Register MR1 stores the data for enabling or disabling the DLL, output driver strength, Rtt_Nom impedance,
additive latency, Write leveling enable, TDQS enable and Qoff. The Mode Register 1 is written by asserting low on CS#,
RAS#, CAS#, WE#, high on BA0 and low on BA1 and BA2, while controlling the states of address pins according to
Figure 2.3.3.
* 1 : A8, A10, and A13 must be programmed to 0 during MRS.
* TDQS must be disabled for x16 option. Figure 2.3.3 MR1 Definition
BA2
BA1
BA0
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Field
0
0
1
0*
1
Qoff
TDQS
0*
1
Rtt
0*
1
Level
Rtt
D.I.C
AL
Rtt
D.I.C
DLL
Mode Register 1
A11
TDQS enable
A7
Write leveling enable
A9
A6
A2
Rtt_Nom
*3
A0
DLL Enable
0
Disabled
0
Disabled
0
0
0
ODT disabled
0
Enable
1
Enabled
1
Enabled
0
0
1
RZQ/4
1
Disable
0
1
0
RZQ/2
A4
A3
Additive Latency
0
1
1
RZQ/6
0
0
0 (AL disabled)
1
0
0
RZQ/12
*4
0
1
CL-1
1
0
1
RZQ/8
*4
1
0
CL-2
1
1
0
Reserved
1
1
Reserved
1
1
1
Reserved
Note: RZQ = 240
A12
Qoff
*2
*3:In Write leveling Mode (MR1[bit7] = 1) with
0
Output buffer enabled
MR1[bit12]=1, all RTT_Nom settings are allowed; in
1
Output buffer disabled
*2
Write Leveling Mode (MR1[bit7] = 1) with
*2: Outputs disabled - DQs, DQSs, DQS#s.
MR1[bit12]=0, only RTT_Nom settings of RZQ/2,
RZQ/4 and RZQ/6 are allowed.
BA1
BA0
MR Select
*4:If RTT_Nom is used during Writes, only the
0
0
MR0
values RZQ/2, RZQ/4 and RZQ/6 are allowed.
0
1
MR1
1
0
MR2
A5
A1
Output Driver Impedance Control
1
1
MR3
0
0
RZQ/6
0
1
RZQ/7
1
0
Reserved
1
1
Reserved
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2.3.3.1 DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning
to normal operation after having the DLL disabled. During normal operation (DLL-on) with MR1 (A0 = 0), the DLL is
automatically disabled when entering Self-Refresh operation and is automatically re-enabled upon exit of Self-Refresh
operation. Any time the DLL is enabled and subsequently reset, tDLLK clock cycles must occur before a Read or
synchronous ODT command can be issued to allow time for the internal clock to be synchronized with the external clock.
Failing to wait for synchronization to occur may result in a violation of the tDQSCK, tAON or tAOF parameters. During
tDLLK, CKE must continuously be registered high. DDR3 SDRAM does not require DLL for any Write operation, except
when RTT_WR is enabled and the DLL is required for proper ODT operation. For more detailed information on DLL
Disable operation refer to “DLL-off Mode”.
The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must be disabled by
continuously registering the ODT pin low and/or by programming the RTT_Nom bits MR1{A9,A6,A2} to {0,0,0} via a mode
register set command during DLL-off mode.
The dynamic ODT feature is not supported at DLL-off mode. User must use MRS command to set Rtt_WR, MR2 {A10,
A9} = {0,0}, to disable Dynamic ODT externally.
2.3.3.2 Output Driver Impedance Control
The output driver impedance of the DDR3 SDRAM device is selected by MR1 (bits A1 and A5) as shown in Figure 2.3.3.
2.3.3.3 ODT Rtt Values
DDR3 SDRAM is capable of providing two different termination values (Rtt_Nom and Rtt_WR). The nominal termination
value Rtt_Nom is programmed in MR1. A separate value (Rtt_WR) may be programmed in MR2 to enable a unique RTT
value when ODT is enabled during writes. The Rtt_WR value can be applied during writes even when Rtt_Nom is
disabled.
2.3.3.4 Additive Latency (AL)
Additive Latency (AL) operation is supported to make command and data bus efficient for sustainable bandwidths in
DDR3 SDRAM. In this operation, the DDR3 SDRAM allows a read or write command (either with or without auto-
precharge) to be issued immediately after the active command. The command is held for the time of the Additive Latency
(AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of the AL and CAS Latency (CL)
register settings. Write Latency (WL) is controlled by the sum of the AL and CAS Write Latency (CWL) register settings. A
summary of the AL register options are shown in Table below.
A4
A3
Additive Latency (AL) Settings
0
0
0 (AL Disabled)
0
1
CL - 1
1
0
CL - 2
1
1
Reserved
NOTE: AL has a value of CL - 1 or CL - 2 as per the CL values programmed in the MR0 register.
2.3.3.5 Write leveling
For better signal integrity, DDR3 memory module adopted fly-by topology for the commands, addresses, control signals,
and clocks. The fly-by topology has the benefit of reducing the number of stubs and their length, but it also causes flight
time skew between clock and strobe at every DRAM on the DIMM. This makes it difficult for the Controller to maintain
tDQSS, tDSS, and tDSH specification. Therefore, the DDR3 SDRAM supports a ‘write leveling’ feature to allow the
controller to compensate for skew.
2.3.3.6 Output Disable
The DDR3 SDRAM outputs may be enabled/disabled by MR1 (bit A12) as shown in Figure 2.3.3. When this feature is
enabled (A12 = 1), all output pins (DQs, DQS, DQS#, etc.) are disconnected from the device, thus removing any loading
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of the output drivers. This feature may be useful when measuring module power, for example. For normal operation, A12
should be set to ‘0’.
2.3.3.7 TDQS, TDQS#
TDQS (Termination Data Strobe) is a feature of X8 DDR3 SDRAM that provides additional termination resistance outputs
that may be useful in some system configurations. The TDQS function is available in X8 DDR3 SDRAM only and must be
disabled via the mode register A11=0 in MR1 for X16 configuration.
2.3.4 Mode Register MR2
The Mode Register MR2 stores the data for controlling refresh related features, Rtt_WR impedance, and CAS write
latency. The Mode Register 2 is written by asserting low on CS#, RAS#, CAS#, WE#, high on BA1 and low on BA0 and
BA2, while controlling the states of address pins according to the below.
* 1 : A5, A8, A11 ~ A13 must be programmed to 0 during MRS.
* 2 : The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled. During write leveling, Dynamic ODT is not available.
Figure 2.3.4 MR2 Definition
2.3.4.1 Partial Array Self-Refresh (PASR)
If PASR (Partial Array Self-Refresh) is enabled, data located in areas of the array beyond the specified address range
shown in Figure 2.3.4 will be lost if Self-Refresh is entered. Data integrity will be maintained if tREFI conditions are met
and no Self-Refresh command is issued.
2.3.4.2 CAS Write Latency (CWL)
The CAS Write Latency is defined by MR2 (bits A3-A5), as shown in Figure 2.3.4. CAS Write Latency is the delay, in clock
cycles, between the internal Write command and the availability of the first bit of input data. DDR3 SDRAM does not
support any half-clock latencies. The overall Write Latency (WL) is defined as Additive Latency (AL) + CAS Write Latency
BA2
BA1
BA0
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Field
0
1
0
0*
1
Rtt_WR
0*
1
SRT
ASR
CWL
PASR
Mode Register 2
A7
Self-Refresh Temperature (SRT) Range
A2
A1
A0
Partial Array Self-Refresh (Optional)
0
Normal operating temperature range
0
0
0
Full Array
1
Extended operating temperature range
0
0
1
HalfArray (BA[2:0]=000,001,010, &011)
0
1
0
Quarter Array (BA[2:0]=000, & 001)
0
1
1
1/8th Array (BA[2:0] = 000)
A6
Auto Self-Refresh (ASR)
1
0
0
3/4 Array (BA[2:0] = 010,011,100,101,110, & 111)
0
Manual SR Reference (SRT)
1
0
1
HalfArray (BA[2:0] = 100, 101, 110, &111)
1
ASR enable
1
1
0
Quarter Array (BA[2:0]=110, &111)
1
1
1
1/8th Array (BA[2:0]=111)
A10
A9
Rtt_WR
*2
A5
A4
A3
CAS write Latency (CWL)
0
0
Dynamic ODT off (Write does not affect Rtt value)
0
0
0
5 (tCK(avg) 2.5 ns)
0
1
RZQ/4
0
0
1
6 (2.5 ns > tCK(avg) 1.875 ns)
1
0
RZQ/2
0
1
0
7 (1.875 ns > tCK(avg) 1.5 ns)
1
1
Reserved
0
1
1
8 (1.5 ns > tCK(avg) 1.25 ns)
1
0
0
9 (1.25 ns > tCK(avg) 1.07ns)
BA1
BA0
MR Select
1
0
1
10 (1.07 ns > tCK(avg) 0.935 ns)
0
0
MR0
1
1
0
Reserved
0
1
MR1
1
1
1
Reserved
1
0
MR2
1
1
MR3
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(CWL); WL = AL + CWL. For more information on the supported CWL and AL settings based on the operating clock
frequency, refer to “Standard Speed Bins”.
2.3.4.3 Auto Self-Refresh (ASR) and Self-Refresh Temperature (SRT)
For more details refer to “Extended Temperature Usage”. DDR3 SDRAMs support Self-Refresh operation at all supported
temperatures. Applications requiring Self-Refresh operation in the Extended Temperature Range must use the ASR
function or program the SRT bit appropriately.
2.3.4.4 Dynamic ODT (Rtt_WR)
DDR3 SDRAM introduces a new feature “Dynamic ODT”. In certain application cases and to further enhance signal
integrity on the data bus, it is desirable that the termination strength of the DDR3 SDRAM can be changed without issuing
an MRS command. MR2 Register locations A9 and A10 configure the Dynamic ODT setings. In Write leveling mode, only
RTT_Nom is available. For details on Dynamic ODT operation, refer to “Dynamic ODT”.
2.3.5 Mode Register MR3
The Mode Register MR3 controls Multi-purpose registers. The Mode Register 3 is written by asserting low on CS#, RAS#,
CAS#, WE#, high on BA1 and BA0, and low on BA2 while controlling the states of address pins according to the below.
* 1 : A3 - A13 must be programmed to 0 during MRS.
* 2 : The predefined pattern will be used for read synchronization.
* 3 : When MPR control is set for normal operation (MR3 A[2] = 0) then MR3 A[1:0] will be ignored.
Figure 2.3.5 MR3 Definition
2.3.5.1 Multi-Purpose Register (MPR)
The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit sequence. To
enable the MPR, a Mode Register Set (MRS) command must be issued to MR3 register with bit A2=1. Prior to issuing the
MRS command, all banks must be in the idle state (all banks precharged and tRP met). Once the MPR is enabled, any
subsequent RD or RDA commands will be redirected to the Multi Purpose Register. When the MPR is enabled, only RD
or RDA commands are allowed until a subsequent MRS command is issued with the MPR disabled (MR3 bit A2=0).
Power down mode, Self-Refresh and any other non-RD/RDA command is not allowed during MPR enable mode. The
RESET function is supported during MPR enable mode.
The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit sequence. The
basic concept of the MPR is shown in Figure 2.3.5.1.
BA2
BA1
BA0
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Field
0
1
1
0*
1
MPR
MPR Loc
Mode Register 3
MRP Operation
MPR Address
A2
MPR
A1
A0
MPR location
0
Normal operation
*3
0
0
Predefined pattern
*2
1
Dataflow from MPR
0
1
RFU
1
0
RFU
1
1
RFU
BA1
BA0
MR Select
0
0
MR0
0
1
MR1
1
0
MR2
1
1
MR3
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Figure 2.3.5.1 MPR Block Diagram
To enable the MPR, a MODE Register Set (MRS) command must be issued to MR3 Register with bit A2 = 1. Prior to
issuing the MRS command, all banks must be in the idle state (all banks precharged and tRP met). Once the MPR is
enabled, any subsequent RD or RDA commands will be redirected to the Multi Purpose Register.
The resulting operation, when a RD or RDA command is issued, is defined by MR3 bits A[1:0] when the MPR is enabled.
When the MPR is enabled, only RD or RDA commands are allowed until a subsequent MRS command is issued with the
MPR disabled (MR3 bit A2 = 0).
Note that in MPR mode RDA has the same functionality as a READ command which means the auto precharge part of
RDA is ignored. Power-Down mode, Self-Refresh and any other non-RD/RDA command is not allowed during MPR
enable mode. The RESET function is supported during MPR enable mode.
MPR MR3 Register Definition
MR3 A[2]
MR3 A[1:0]
Function
MPR
MPR-Loc
0b
don’t care (0b or 1b)
Normal operation, no MPR transaction. All subsequent Reads will come from
DRAM array. All subsequent Write will go to DRAM array.
1b
See MPR Definition
table
Enable MPR mode, subsequent RD/RDA commands defined by MR3 A[1:0].
Memory Core
(all banks
precharged)
Multipurpose
Register pre-defined
data for read
MR3[A2]
DQ, DM, DQS, DQS#
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MPR Register Address Definition
The following Table provides an overview of the available data locations, how they are addressed by MR3 A[1:0] during a
MRS to MR3, and how their individual bits are mapped into the burst order bits during a Multi Purpose Register Read.
MPR MR3 Register Definition
MR3
A[2]
MR3
A[1:0]
Function
Burst
Length
Read Address
A[2:0]
Burst Order and Data Pattern
1b
00b
Read predefined pattern
for system Calibration
BL8
000b
Burst order 0,1,2,3,4,5,6,7
Pre-defined Data Pattern [0,1,0,1,0,1,0,1]
BC4
000b
Burst order 0,1,2,3
Pre-defined Data Pattern [0,1,0,1]
BC4
100b
Burst order 4,5,6,7
Pre-defined Data Pattern [0,1,0,1]
1b
01b
RFU
BL8
000b
Burst order 0,1,2,3,4,5,6,7
BC4
000b
Burst order 0,1,2,3
BC4
100b
Burst order 4,5,6,7
1b
10b
RFU
BL8
000b
Burst order 0,1,2,3,4,5,6,7
BC4
000b
Burst order 0,1,2,3
BC4
100b
Burst order 4,5,6,7
1b
11b
RFU
BL8
000b
Burst order 0,1,2,3,4,5,6,7
BC4
000b
Burst order 0,1,2,3
BC4
100b
Burst order 4,5,6,7
NOTE: Burst order bit 0 is assigned to LSB and the burst order bit 7 is assigned to MSB of the selected MPR agent
MPR Functional Description
One bit wide logical interface via all DQ pins during READ operation.
Register Read on x16:
o DQL[0] and DQU[0] drive information from MPR.
o DQL[7:1] and DQU[7:1] either drive the same information as DQL[0], or they drive 0b.
Addressing during for Multi Purpose Register reads for all MPR agents:
o BA[2:0]: don’t care
o A[1:0]: A[1:0] must be equal to ‘00’b. Data read burst order in nibble is fixed
o A[2]: For BL=8, A[2] must be equal to 0b, burst order is fixed to [0,1,2,3,4,5,6,7], *) For Burst Chop 4 cases, the
burst order is switched on nibble base A[2]=0b, Burst order: 0,1,2,3 *) A[2]=1b, Burst order: 4,5,6,7 *)
o A[9:3]: don’t care
o A10/AP: don’t care
o A12/BC: Selects burst chop mode on-the-fly, if enabled within MR0.
o A11, A13: don’t care
Regular interface functionality during register reads:
o Support two Burst Ordering which are switched with A2 and A[1:0]=00b.
o Support of read burst chop (MRS and on-the-fly via A12/BC)
o All other address bits (remaining column address bits including A10, all bank address bits) will be ignored by
the DDR3 SDRAM.
o Regular read latencies and AC timings apply.
o DLL must be locked prior to MPR Reads.
NOTE: *) Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent.
NOTE: Good reference for the example of MPR feature is the JEDEC standard No.93-3D, 4.10.4 Protocol example.
Relevant Timing Parameters
AC timing parameters are important for operating the Multi Purpose Register: tRP, tMRD, tMOD, and tMPRR. For more
details refer to “Electrical Characteristics & AC Timing”
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2.4 DDR3 SDRAM Command Description and Operation
2.4.1 Command Truth Table
[BA=Bank Address, RA=Row Address, CA=Column Address, BC#=Burst Chop, X=Don’t Care, V=Valid]
Function
Abbreviation
CKE
CS#
RAS#
CAS#
WE#
BA0-
BA2
A11,
A13
A12/
BC#
A10/
AP
A0-
A9
Notes
Previous
Cycle
Current
Cycle
Mode Register Set
MRS
H
H
L
L
L
L
BA
OP Code
Refresh
REF
H
H
L
L
L
H
V
V
V
V
V
Self Refresh Entry
SRE
H
L
L
L
L
H
V
V
V
V
V
7,9,12
Self Refresh Exit
SRX
L
H
H
X
X
X
X
X
X
X
X
7,8,9,
12
L
H
H
H
V
V
V
V
V
Single Bank Precharge
PRE
H
H
L
L
H
L
BA
V
V
L
V
Precharge all Banks
PREA
H
H
L
L
H
L
V
V
V
H
V
Bank Activate
ACT
H
H
L
L
H
H
BA
Row Address(RA)
Write (Fixed BL8 or BC4)
WR
H
H
L
H
L
L
BA
RFU
V
L
CA
Write (BC4, on the Fly)
WRS4
H
H
L
H
L
L
BA
RFU
L
L
CA
Write (BL8, on the Fly)
WRS8
H
H
L
H
L
L
BA
RFU
H
L
CA
Write with Auto Precharge (Fixed BL8 or BC4)
WRA
H
H
L
H
L
L
BA
RFU
V
H
CA
Write with Auto Precharge (BC4, on the Fly)
WRAS4
H
H
L
H
L
L
BA
RFU
L
H
CA
Write with Auto Precharge (BL8, on the Fly)
WRAS8
H
H
L
H
L
L
BA
RFU
H
H
CA
Read (Fixed BL8 or BC4)
RD
H
H
L
H
L
H
BA
RFU
V
L
CA
Read (BC4, on the Fly)
RDS4
H
H
L
H
L
H
BA
RFU
L
L
CA
Read (BL8, on the Fly)
RDS8
H
H
L
H
L
H
BA
RFU
H
L
CA
Read with Auto Precharge (Fixed BL8 or BC4)
RDA
H
H
L
H
L
H
BA
RFU
V
H
CA
Read with Auto Precharge (BC4, on the Fly)
RDAS4
H
H
L
H
L
H
BA
RFU
L
H
CA
Read with Auto Precharge (BL8, on the Fly)
RDAS8
H
H
L
H
L
H
BA
RFU
H
H
CA
No Operation
NOP
H
H
L
H
H
H
V
V
V
V
V
10
Device Deselected
DES
H
H
H
X
X
X
X
X
X
X
X
11
Power Down Entry
PDE
H
L
L
H
H
H
V
V
V
V
V
6,12
H
X
X
X
X
X
X
X
X
Power Down Exit
PDX
L
H
L
H
H
H
V
V
V
V
V
6,12
H
X
X
X
X
X
X
X
X
ZQ Calibration Long
ZQCL
H
H
L
H
H
L
X
X
X
H
X
ZQ Calibration Short
ZQCS
H
H
L
H
H
L
X
X
X
L
X
Notes:
1. All DDR3 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE# and CKE at the rising edge of the clock. The MSB of BA, RA and CA
are device density and configuration dependant.
2. RESET# is Low enable command which will be used only for asynchronous reset so must be maintained HIGH during any function.
3. Bank addresses (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register.
4. “V” means “H or L (but a defined logic level)” and “X” means either “defined or undefined (like floating) logic level”.
5. Burst reads or writes cannot be terminated or interrupted and Fixed/on-the-Fly BL will be defined by MRS.
6. The Power Down Mode does not perform any refresh operation.
7. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
8. Self Refresh Exit is asynchronous.
9. VREF(Both VrefDQ and VrefCA) must be maintained during Self Refresh operation. VrefDQ supply may be turned OFF and VREFDQ may take any
value between VSS and VDD during Self Refresh operation, provided that VrefDQ is valid and stable prior to CKE going back High and that first
Write operation or first Write Leveling Activity may not occur earlier than 512 nCK after exit from Self Refresh.
10. The No Operation command should be used in cases when the DDR3 SDRAM is in an idle or wait state. The purpose of the No Operation command
(NOP) is to prevent the DDR3 SDRAM from registering any unwanted commands between operations. A No Operation command will not terminate a
pervious operation that is still executing, such as a burst read or write cycle.
11. The Deselect command performs the same function as No Operation command.
12. Refer to the CKE Truth Table for more detail with CKE transition.
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2.4.1. CKE Truth Table
Current State2
CKE
Command (N)3
RAS#, CAS#, WE#,
CS#
Action (N)3
Notes
Previous Cycle1 (N-1)
Current Cycle1(N)
Power-Down
L
L
X
Maintain Power-Down
14,15
L
H
DESELECT or NOP
Power-Down Exit
11,14
Self-Refresh
L
L
X
Maintain Self-Refresh
15,16
L
H
DESELECT or NOP
Self-Refresh Exit
8,12,16
Bank(s) Active
H
L
DESELECT or NOP
Active Power-Down Entry
11,13,14
Reading
H
L
DESELECT or NOP
Power-Down Entry
11,13,14,17
Writing
H
L
DESELECT or NOP
Power-Down Entry
11,13,14,17
Precharging
H
L
DESELECT or NOP
Power-Down Entry
11,13,14,17
Refreshing
H
L
DESELECT or NOP
Precharge Power-Down Entry
11
All Bank Idle
H
L
DESELECT or NOP
Precharge Power-Down Entry
11,13,14,18
H
L
REFRESH
Self-Refresh
9.13.18
Notes:
1. CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.
2. Current state is defined as the state of the DDR3 SDRAM immediately prior to clock edge N.
3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N), ODT is not included here.
4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self-Refresh.
6. CKE must be registered with the same value on tCKEmin consecutive positive clock edges. CKE must remain at the valid input level the entire time it
takes to achieve the tCKEmin clocks of registeration. Thus, after any CKE transition, CKE may not transition from its valid level during the time
period of tIS + tCKEmin + tIH.
7. DESELECT and NOP are defined in the Command Truth Table.
8. On Self-Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXS period. Read or ODT commands
may be issued only after tXSDLL is satisfied.
9. Self-Refresh mode can only be entered from the All Banks Idle state.
10. Must be a legal command as defined in the Command Truth Table.
11. Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.
12. Valid commands for Self-Refresh Exit are NOP and DESELECT only.
13. Self-Refresh cannot be entered during Read or Write operations.
14. The Power-Down does not perform any refresh operations.
15. “X” means “don’t care“ (including floating around VREF) in Self-Refresh and Power-Down. It also applies to Address pins.
16. VREF (Both Vref_DQ and Vref_CA) must be maintained during Self-Refresh operation.VrefDQ supply may be turned OFF and VREFDQ may take
any value between VSS and VDD during Self Refresh operation, provided that VrefDQ is valid and stable prior to CKE going back High and that first
Write operation or first Write Leveling Activity may not occur earlier than 512 nCK after exit from Self Refresh.
17. If all banks are closed at the conclusion of the read, write or precharge command, then Precharge Power-Down is entered, otherwise Active Power-
Down is entered.
18. ‘Idle state’ is defined as all banks are closed (tRP, tDAL, etc. satisfied), no data bursts are in progress, CKE is high, and all timings from previous
operations are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, etc.) as well as all Self-Refresh exit and Power-Down Exit parameters are
satisfied (tXS, tXP, tXPDLL, etc).
2.4.2 No Operation (NOP) Command
The No operation (NOP) command is used to instruct the selected DDR3 SDRAM to perform a NOP ( CS# low and
RAS#,CAS#,WE# high). This prevents unwanted commands from being registered during idle or wait states. Operations
already in progress are not affected.
2.4.3 Deselect(DES) Command
The Deselect function (CS# HIGH) prevents new commands from being executed by the DDR3 SDRAM. The DDR3
SDRAM is effectively deselected. Operations already in progress are not affected.
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2.4.4 DLL-off Mode
DDR3 DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent operations until A0 bit
set back to “0”. The MR1 A0 bit for DLL control can be switched either during initialization or later. The DLL-off Mode
operations listed below are an optional feature for DDR3. The maximum clock frequency for DLL-off Mode is specified by
the parameter tCKDLL_OFF. There is no minimum frequency limit besides the need to satisfy the refresh interval, tREFI.
Due to latency counter and timing restrictions, only one value of CAS Latency (CL) in MR0 and CAS Write Latency (CWL)
in MR2 are supported. The DLL-off mode is only required to support setting of both CL=6 and CWL=6. DLL-off mode will
affect the Read data Clock to Data Strobe relationship (tDQSCK) but not the data Strobe to Data relationship (tDQSQ,
tQH). Special attention is needed to line up Read data to controller time domain.
Comparing with DLL-on mode, where tDQSCK starts from the rising clock edge (AL+CL) cycles after the Read command,
the DLL-off mode tDQSCK starts (AL+CL-1) cycles after the read command. Another difference is that tDQSCK may not
be small compared to tCK (it might even be larger than tCK) and the difference between tDQSCKmin and tDQSCKmax is
significantly larger than in DLL-on mode. The timing relations on DLL-off mode READ operation have shown at the
following Timing Diagram (CL=6, BL=8)
Note: The tDQSCK is used here for DQS, DQS, and DQ to have a simplified diagram; the DLL_off shift will affect both timings in the same way and the
skew between all DQ, DQS, and DQS# signals will still be tDQSQ.
Figure 2.4.4 DLL-off mode READ Timing Operation
CK#
CK
Command
Address
DQS,DQS#(DLL_on)
DQ(DLL_on)
DQS,DQS#(DLL_off)
DQ(DLL_off)
DQS,DQS#(DLL_off)
DQ(DLL_off)
tDQSCK(DLL_off)_min
tDQSCK(DLL_off)_max
RL (DLL_off) = AL+(CL-1) = 5
RL (DLL_on) = AL+CL =6 (CL=6,AL=0)
CL=6
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Don’t Care
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2.4.5 DLL on/off switching procedure
DDR3 DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent operation until A0 bit
set back to “0”.
2.4.5.1 DLL “on” to DLL “off” Procedure
To switch from DLL “on” to DLL “off” requires te frequency to be changed during Self-Refresh outlined in the following
procedure:
1. Starting from Idle state (all banks pre-charged, all timing fulfilled, and DRAMs On-die Termination resistors, RTT,
must be in high impedance state before MRS to MR1 to disable the DLL).
2. Set MR1 Bit A0 to “1” to disable the DLL.
3. Wait tMOD.
4. Enter Self Refresh Mode; wait until (tCKSRE) satisfied.
5. Change frequency, in guidance with “Input Clock Frequency Change” section.
6. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs.
7. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until all tMOD timings from
any MRS command are satisfied. In addition, if any ODT features were enabled in the mode registers when Self
Refresh mode was entered, the ODT signal must continuously be registered LOW until all tMOD timings from any
MRS command are satisfied. If both ODT features were disabled in the mode registers when Self Refresh mode was
entered, ODT signal can be registered LOW or HIGH.
8. Wait tXS, and then set Mode Registers with appropriate values (especially an update of CL, CWL, and WR may be
necessary. A ZQCL command may also be issued after tXS).
9. Wait for tMOD, and then DRAM is ready for next command.
2.4.5.2 DLL “off” to DLL “on” Procedure
To switch from DLL “off” to DLL “on” (with required frequency change) during Self-Refresh:
1. Starting from Idle state (All banks pre-charged, all timings fulfilled and DRAMs On-die Termination resistors (RTT)
must be in high impedance state before Self-Refresh mode is entered.)
2. Enter Self Refresh Mode, wait until tCKSRE satisfied.
3. Change frequency, in guidance with "Input clock frequency change".
4. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs.
5. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until tDLLK timing from
subsequent DLL Reset command is satisfied. In addition, if any ODT features were enabled in the mode registers
when Self Refresh mode was entered, the ODT signal must continuously be registered LOW until tDLLK timings from
subsequent DLL Reset command is satisfied. If both ODT features are disabled in the mode registers when Self
Refresh mode was entered, ODT signal can be registered LOW or HIGH.
6. Wait tXS, then set MR1 bit A0 to “0” to enable the DLL.
7. Wait tMRD, then set MR0 bit A8 to “1” to start DLL Reset.
8. Wait tMRD, then set Mode Registers with appropriate values (especially an update of CL, CWL and WR may be
necessary. After tMOD satisfied from any proceeding MRS command, a ZQCL command may also be issued during
or after tDLLK.)
9. Wait for tMOD, then DRAM is ready for next command (Remember to wait tDLLK after DLL Reset before applying
command requiring a locked DLL!). In addition, wait also for tZQoper in case a ZQCL command was issued.
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2.4.6. Input clock frequency change
Once the DDR3 SDRAM is initialized, the DDR3 SDRAM requires the clock to be “stable” during almost all states of
normal operation. This means that, once the clock frequency has been set and is to be in the “stable state”, the clock
period is not allowed to deviate except for what is allowed for by the clock jitter and SSC (spread spectrum clocking)
specifications.
The input clock frequency can be changed from one stable clock rate to another stable clock rate under two conditions:
(1) Self-Refresh mode and (2) Precharge Power-down mode. Outside of these two modes, it is illegal to change the clock
frequency.
For the first condition, once the DDR3 SDRAM has been successfully placed in to Self-Refresh mode and tCKSRE has
been satisfied, the state of the clock becomes a don’t care. Once a don’t care, changing the clock frequency is
permissible, provided the new clock frequency is stable prior to tCKSRX. When entering and exiting Self-Refresh mode
for the sole purpose of changing the clock frequency, the Self-Refresh entry and exit specifications must still be met.
The DDR3 SDRAM input clock frequency is allowed to change only within the minimum and maximum operating
frequency specified for the particular speed grade. Any frequency change below the minimum operating frequency would
require the use of DLL_on- mode -> DLL_off -mode transition sequence, refer to “DLL on/off switching procedure”.
The second condition is when the DDR3 SDRAM is in Precharge Power-down mode (either fast exit mode or slow exit
mode). If the RTT_NOM feature was enabled in the mode register prior to entering Precharge power down mode, the
ODT signal must continuously be registered LOW ensuring RTT is in an off state. If the RTT_NOM feature was disabled in
the mode register prior to entering Precharge power down mode, RTT will remain in the off state. The ODT signal can be
registered either LOW or HIGH in this case. A minimum of tCKSRE must occur after CKE goes LOW before the clock
frequency may change. The DDR3 SDRAM input clock frequency is allowed to change only within the minimum and
maximum operating frequency specified for the particular speed grade. During the input clock frequency change, ODT
and CKE must be held at stable LOW levels. Once the input clock frequency is changed, stable new clocks must be
provided to the DRAM tCKSRX before Precharge Power-down may be exited; after Precharge Power-down is exited and
tXP has expired, the DLL must be RESET via MRS. Depending on the new clock frequency, additional MRS commands
may need to be issued to appropriately set the WR, CL, and CWL with CKE continuously registered high. During DLL re-
lock period, ODT must remain LOW and CKE must remain HIGH. After the DLL lock time, the DRAM is ready to operate
with new clock frequency.
2.4.7 Write leveling
For better signal integrity, the DDR3 memory module adopted fly-by topology for the commands, addresses, control
signals, and clocks. The fly-by topology has benefits from reducing number of stubs and their length, but it also causes
flight time skew between clock and strobe at every DRAM on the DIMM. This makes it difficult for the Controller to
maintain tDQSS, tDSS, and tDSH specification. Therefore, the DDR3 SDRAM supports a ‘write leveling’ feature to allow
the controller to compensate for skew.
The memory controller can use the ‘write leveling’ feature and feedback from the DDR3 SDRAM to adjust the DQS -
DQS# to CK - CK# relationship. The memory controller involved in the leveling must have adjustable delay setting on
DQS - DQS# to align the rising edge of DQS - DQS# with that of the clock at the DRAM pin. The DRAM asynchronously
feeds back CK - CK#, sampled with the rising edge of DQS - DQS#, through the DQ bus. The controller repeatedly delays
DQS - DQS# until a transition from 0 to 1 is detected. The DQS - DQS# delay established though this exercise would
ensure tDQSS specification.
Besides tDQSS, tDSS and tDSH specification also needs to be fulfilled. One way to achieve this is to combine the actual
tDQSS in the application with an appropriate duty cycle and jitter on the DQS - DQS# signals. Depending on the actual
tDQSS in the application, the actual values for tDQSL and tDQSH may have to be better than the absolute limits provided
in the chapter "AC Timing Parameters" in order to satisfy tDSS and tDSH specification. A conceptual timing of this
scheme is shown in Figure 2.4.7.
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Figure 2.4.7 Write Leveling Concept
DQS - DQS# driven by the controller during leveling mode must be terminated by the DRAM based on ranks populated.
Similarly, the DQ bus driven by the DRAM must also be terminated at the controller.
One or more data bits carry the leveling feedback to the controller across the DRAM configurations X8 and X16. On a X16
device, both byte lanes should be leveled independently.
Therefore, a separate feedback mechanism should be available for each byte lane. The upper data bits should provide
the feedback of the upper diff_DQS(diff_UDQS) to clock relationship whereas the lower data bits would indicate the lower
diff_DQS(diff_LDQS) to clock relationship.
2.4.7.1 DRAM setting for write leveling & DRAM termination function in that mode
DRAM enters into Write leveling mode if A7 in MR1 set ’High’ and after finishing leveling, DRAM exits from write leveling
mode if A7 in MR1 set ’Low’. Note that in write leveling mode, only DQS/DQS# terminations are activated and deactivated
via ODT pin, unlike normal operation.
MR setting involved in the leveling procedure
Function
MR1
Enable
Disable
Write leveling enable
A7
1
0
Output buffer mode (Qoff)
A12
0
1
DRAM termination function in the leveling mode
ODT pin @DRAM
DQS/DQS# termination
DQs termination
De-asserted
Off
Off
Asserted
On
Off
NOTE: In Write Leveling Mode with its output buffer disabled (MR1[bit7] = 1 with MR1[bit12] = 1) all RTT_Nom settings are allowed; in Write Leveling
Mode with its output buffer enabled (MR1[bit7] = 1 with MR1[bit12] = 0) only RTT_Nom settings of RZQ/2, RZQ/4 and RZQ/6 are allowed.
CK#
CK
diff_DQS
Source
Destination
CK#
CK
diff_DQS
DQ
diff_DQS
DQ
Push DQS to capture
0-1 transition
0 or 1
0
0
0
0 or 1
1
1
1
T0
T1
T2
T3
T4
T5
T6
T7
T0
T1
T2
T3
T4
T5
T6
Tn
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2.4.7.2 Procedure Description
The Memory controller initiates Leveling mode of all DRAMs by setting bit 7 of MR1 to 1. When entering write leveling
mode, the DQ pins are in undefined driving mode. During write leveling mode, only NOP or DESELECT commands are
allowed, as well as an MRS command to exit write leveling mode. Since the controller levels one rank at a time, the output
of other ranks must be disabled by setting MR1 bit A12 to 1.
The Controller may assert ODT after tMOD, at which time the DRAM is ready to accept the ODT signal.
The Controller may drive DQS low and DQS# high after a delay of tWLDQSEN, at which time the DRAM has applied on-
die termination on these signals. After tDQSL and tWLMRD, the controller provides a single DQS, DQS# edge which is
used by the DRAM to sample CK - CK# driven from controller. tWLMRD(max) timing is controller dependent.
DRAM samples CK - CK# status with rising edge of DQS - DQS# and provides feedback on the DQ bus asynchronously
after tWLO timing. In this product, the DQ0 for x8 or DQ0 and DQ8 for x16 ("prime DQ bit(s)") provide the leveling
feedback. The DRAM's remaining DQ bits are driven Low statically after the first sampling procedure. There is a DQ
output uncertainty of tWLOE defined to allow mismatch on DQ bits. The tWLOE period is defined from the transition of the
earliest DQ bit to the corresponding transition of the latest DQ bit. There are no read strobes (DQS/DQS#) needed for
these DQs. Controller samples incoming DQ and decides to increment or decrement DQS - DQS# delay setting and
launches the next DQS/DQS# pulse after some time, which is controller dependent. Once a 0 to 1 transition is detected,
the controller locks DQS - DQS# delay setting and write leveling is achieved for the device. Figure 2.4.7.2 describes the
timing diagram and parameters for the overall Write Leveling procedure.
Notes:
1. The JEDEC specification for DDR3 DRAM has the option to drive leveling feedback on a single prime DQ or all DQs. For best compatibility with
future DDR3 products, applications should use the lowest order DQ for each byte lane (DQ0 for x8, or DQ0 and DQ8 for x16).
2. MRS: Load MR1 to enter write leveling mode.
3. NOP: NOP or Deselect.
4. diff_DQS is the differential data strobe (DQS, DQS#). Timing reference points are the zero crossings. DQS is shown with solid line, DQS# is shown
with dotted line.
5. CK, CK# : CK is shown with solid dark line, where as CK# is drawn with dotted line.
6. DQS, DQS# needs to fulfill minimum pulse width requirements tDQSH(min) and tDQSL(min) as defined for regular Writes; the max pulse width is
system dependent.
CK#(5)
CK
CMD
MRS
NOP
NOP
tMOD
NOP
NOP
NOP
T1
tWLH
tWLS
T2
tWLH
tWLS
NOP
NOP
NOP
NOP
NOP
NOP
DON’T CARE
Undefined
Driving Mode
Time Break
ODT
diff_DQS(4)
Prime DQ(1)
Late Remaining
DQs
Early Remaining
DQs
(2)
(3)
tWLDQSEN
tDQSL(6)
tDQSH(6)
tDQSL(6)
tDQSH(6)
tWLMRD
tWLO
tWLO
tWLO
tWLO
tWLOE
Figure 2.4.7.2 Write leveling sequence [DQS - DQS# is capturing CK-CK# low at T1 and CK-CK# high at T2]
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2.4.7.3 Write Leveling Mode Exit
The following sequence describes how the Write Leveling Mode should be exited:
1. After the last rising strobe edge, stop driving the strobe signals. Note: From now on, DQ pins are in undefined driving
mode, and will remain undefined, until tMOD after the respective MR command.
2. Drive ODT pin low (tIS must be satisfied) and continue registering low.
3. After the RTT is switched off, disable Write Level Mode via MRS command.
4. After tMOD is satisfied, any valid command may be registered. (MR commands may be issued after tMRD ).
2.4.8 Extended Temperature Usage
a. Auto Self-refresh supported
b. Extended Temperature Range supported
c. Double refresh required for operation in the Extended Temperature Range (applies only for devices supporting the
Extended Temperature Range)
Mode Register Description
Field
Bits
Description
Auto Self-Refresh (ASR)
when enabled, DDR3 SDRAM automatically provides Self-Refresh power management functions for all
supported operating temperature values. If not enabled, the SRT bit must be programmed to indicate TOPER
ASR
MR2 (A6)
during subsequent Self-Refresh operation
0 = Manual SR Reference (SRT)
1 = ASR enable
Self-Refresh Temperature (SRT) Range
If ASR = 0, the SRT bit must be programmed to indicate TOPER during subsequent Self-Refresh operation
SRT
MR2 (A7)
If ASR = 1, SRT bit must be set to 0b
0 = Normal operating temperature range
1 = Extended operating temperature range
2.4.8.1 Auto Self-Refresh mode - ASR Mode
DDR3 SDRAM provides an Auto Self-Refresh mode (ASR) for application ease. ASR mode is enabled by setting MR2 bit
A6 = 1b and MR2 bit A7 = 0b. The DRAM will manage Self-Refresh entry in either the Normal or Extended (optional)
Temperature Ranges. In this mode, the DRAM will also manage Self-Refresh power consumption when the DRAM
operating temperature changes, lower at low temperatures and higher at high temperatures.
If the ASR option is not supported by the DRAM, MR2 bit A6 must be set to 0b.
If the ASR mode is not enabled (MR2 bit.A6 = 0b), the SRT bit (MR2 A7) must be manually programmed with the
operating temperature range required during Self-Refresh operation.
Support of the ASR option does not automatically imply support of the Extended Temperature Range. Refer to Operating
Temperature Range for restrictions on operating conditions.
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2.4.8.2 Self-Refresh Temperature Range - SRT
SRT applies to devices supporting Extended Temperature Range only. If ASR = 0b, the Self-Refresh Temperature (SRT)
Range bit must be programmed to guarantee proper self-refresh operation. If SRT = 0b, then the DRAM will set an
appropriate refresh rate for Self-Refresh operation in the Normal Temperature Range. If SRT = 1b then the DRAM will set
an appropriate, potentially different, refresh rate to allow Self-Refresh operation in either the Normal or Extended
Temperature Ranges. The value of the SRT bit can effect self-refresh power consumption, please refer to the IDD table
for details.
For parts that do not support the Extended Temperature Range, MR2 bit A7 must be set to 0b and the DRAM should not
be operated outside the Normal Temperature Range.
Self-Refresh mode summary
MR2
A[6]
MR2
A[7]
Self-Refresh operation
Allowed Operating Temperature Range for
Self-Refresh Mode
0
0
Self-refresh rate appropriate for the Normal Temperature Range
Normal (0 to 85°C)
0
1
Self-refresh rate appropriate for either the Normal or Extended
Temperature Ranges. The DRAM must support Extended
Temperature Range. The value of the SRT bit can affect self-
refresh power consumption, please refer to the IDD table for
details.
Normal (0 to 85°C) and
Extended (85 to 105°C)
1
0
ASR enabled (for devices supporting ASR and Normal
Temperature Range). Self-Refresh power consumption is
temperature dependent
Normal (0 to 85°C)
1
0
ASR enabled (for devices supporting ASR and Extended
Temperature Range). Self-Refresh power consumption is
temperature dependent
Normal (0 to 85°C) and
Extended (85 to 105 °C)
1
1
Illegal
Note: Self-Refresh Mode operation above 95° C permitted only for Automotive grades (A2 and A3); refer to 3.2 Component Operating Temperature
Range.
2.5 ECC Function
The DRAM has an error correcting feature which reduces the likelihood of occurrences of bit errors. When carrying out a
Write command for an address location, the ECC module uses the data in the burst to calculate an additional set of ECC
bits that are stored in the DRAM memory in a location adjacent to the data. When later carrying out a Read command for
that same location, the ECC module analyzes and compares the data from memory and the ECC bits. If a bit had
changed its value within 64-bits of the stored data, that bit will have a corrected value during the Read burst. If more than
one bit had changed value with 64-bits of the stored data, the ECC feature cannot correct all the bits during the Read
burst.
For the ECC module to consistently calculate the ECC bits for full memory coverage, it is required to use enough data bits
during the Read and Write bursts. The requirement is to use Burst Length of 8, and not to use Burst Chop, nor Burst
Length of 4. The mode register settings and the command sequences should be followed. For the data to be consistently
available to the array and ECC module, using the Data Mask is not recommended.
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3. ABSOLUTE MAXIMUM RATINGS AND AC & DC OPERATING CONDITIONS
3.1 Absolute Maximum DC Ratings.
Symbol
Parameter
Rating
Units
Note
VDD
Voltage on VDD pin relative to Vss
-0.4 V ~ 1.975 V
V
1,3
VDDQ
Voltage on VDDQ pin relative to Vss
-0.4 V ~ 1.975 V
V
1,3
VIN, VOUT
Voltage on any pin relative to Vss
-0.4 V ~ 1.975 V
V
1
TSTG
Storage Temperature
-55 to +150
°C
1,2
Notes:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM.
3. VDD and VDDQ must be within 300 mV of each other at all times; and VREF must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less
than 500 mV; VREF may be equal to or less than 300 mV
3.2 Component Operating Temperature Range
Symbol
Parameter
Rating
Units
Notes
TOPER
Commercial
Tc = 0 to 85
°C
1,2
Tc = 85 to 95
°C
1,3
Industrial
Tc = -40 to 85
°C
1,2
Tc = 85 to 95
°C
1,3
Automotive (A1)
Tc = -40 to 85
°C
1,2
Tc = 85 to 95
°C
1,3
Automotive (A2)
Tc = -40 to 85
°C
1,2
Tc = 85 to 105
°C
1,3
Automotive (A3)
Tc = -40 to 85
°C
1,2
Tc = 85 to 105
°C
1,3
Tc = 105 to 125
°C
1,4
Notes:
1. Operating Temperature TOPER is the case surface temperature (Tc) on the center / top side of the DRAM.
2. This temperature range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature
must be maintained in this range under all operating conditions.
3. Some applications require operation of the DRAM in the Extended Temperature Range (85°C < Tc 105°C). For each permitted temperature range,
full specifications are supported, but the following additional conditions apply:
a ) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs.
b) If Self-Refresh operation is required for this range, it is mandatory to use either the Manual Self-Refresh mode with Extended Temperature Range
capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b).
4. For operation with Tc up to 125°C, reduce the Refresh interval tREFI to 1.95μs. No type of Self Refresh mode is supported on this range.
3.3 Recommended DC Operating Conditions (SSTL_1.5)
Symbol
Parameter
Rating
Unit
Notes
Min
Typ
Max
VDD
Supply Voltage
1.425
1.5
1.575
V
1,2
VDDQ
Supply Voltage
for Output
1.425
1.5
1.575
V
1,2
Notes:
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
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3.4 Thermal Resistance
Package
PcB
Substrate
Theta-ja
(Airflow = 0m/s)
Theta-ja
(Airflow = 1m/s)
Theta-ja
(Airflow = 2m/s)
Theta-jc
Units
78-ball
4-layer
22.5
19.4
18.6
6.4
C/W
96-ball
4-layer
21.0
18.0
17.3
6.8
C/W
4. AC & DC INPUT MEASUREMENT LEVELS
4.1. AC and DC Logic Input Levels for Single-Ended Signals
4.1.1 AC and DC Input Levels for Single-Ended Command and Address Signals
Symbol
Parameter
DDR3-800/1066/1333/1600
DDR3-1866/2133
Units
Note
Min.
Max.
Min.
Max.
V
1
VIH.CA(DC100)
DC input logic high
Vref + 0.100
VDD
Vref + 0.100
VDD
V
1
VIL.CA(DC100)
DC input logic low
VSS
Vref - 0.100
VSS
Vref - 0.100
V
1, 2, 5
VIH.CA(AC175)
AC input logic high
Vref + 0.175
Note2
--
--
V
1, 2, 5
VIL.CA(AC175)
AC input logic low
Note2
Vref - 0.175
--
--
V
1, 2, 5
VIH.CA(AC150)
AC input logic high
Vref + 0.150
Note2
--
--
V
1, 2, 5
VIL.CA(AC150)
AC input logic low
Note2
Vref - 0.150
--
--
V
1, 2, 5
VIH.CA(AC135)
AC input logic high
--
--
Vref + 0.135
Note2
V
1, 2, 5
VIL.CA(AC135)
AC input logic low
--
--
Note2
Vref - 0.135
V
1, 2, 5
VIH.CA(AC125)
AC input logic high
--
--
Vref + 0.125
Note2
V
1, 2, 5
VIL.CA(AC125)
AC input logic low
--
--
Note2
Vref - 0.125
V
1, 2, 5
VREFCA(DC)
Reference Voltage for
ADD, CMD inputs
0.49 * VDD
0.51* VDD
0.49 * VDD
0.51* VDD
V
3, 4
Notes:
1. For input only pins except RESET.Vref=VrefCA(DC)
2. See "Overshoot and Undershoot Specifications"
3. The ac peak noise on Vref may not allow Vref to deviate from Vref(DC) by more than +/- 1.0% VDD.
4. For reference: DDR3 has approx. VDD/2 +/- 15mV.
5. To allow VREFCA margining, all DRAM Command and Address Input Buffers MUST use external VREF (provided by system) as the input for their
VREFCA pins. All VIH/L input level MUST be compared with the external VREF level at the 1st stage of the Command and Address input buffer
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4.1.2 AC and DC Logic Input Levels for Single-Ended Signals & DQ and DM
Symbol
Parameter
DDR3-800/1066
DDR3-1333/1600
DDR3-1866/2133
Units
Note
Min.
Max.
Min.
Max.
Min.
Max.
V
1
VIH.DQ(DC100)
DC input logic high
Vref +
0.100
VDD
Vref +
0.100
VDD
Vref +
0.100
VDD
V
1
VIL.DQ(DC100)
DC input logic low
VSS
Vref -
0.100
VSS
Vref -
0.100
VSS
Vref -
0.100
V
1, 2, 5
VIH.DQ(AC175)
AC input logic high
Vref +
0.175
Note2
--
--
--
--
V
1, 2, 5
VIL.DQ(AC175)
AC input logic low
Note2
Vref -
0.175
--
--
--
--
V
1, 2, 5
VIH.DQ(AC150)
AC input logic high
Vref +
0.150
Note2
Vref +
0.150
Note2
--
--
V
1, 2, 5
VIL.DQ(AC150)
AC input logic low
Note2
Vref -
0.150
Note2
Vref -
0.150
--
--
V
1, 2, 5
VIH.DQ(AC135)
AC input logic high
Vref +
0.135
Note2
Vref +
0.135
Note2
Vref +
0.135
Note2
V
1, 2, 5
VIL.DQ(AC135)
AC input logic low
Note2
Vref -
0.135
Note2
Vref -
0.135
Note2
Vref -
0.135
V
1, 2, 5
VREFDQ(DC)
Reference Voltage
for DQ, DM inputs
0.49 *
VDD
0.51*
VDD
0.49 *
VDD
0.51*
VDD
0.49 *
VDD
0.51*
VDD
V
3, 4
Notes:
1. For input only pins except RESET#. Vref = VrefDQ(DC)
2. See "Overshoot and Undershoot Specifications"
3. The ac peak noise on Vref may not allow Vref to deviate from Vref(DC) by more than ± 1.0% VDD.
4. For reference: DDR3 has approx. VDD/2 ±15mV.
5. Single-ended swing requirement for DQS-DQS#, is 350mV (peak to peak). Differential swing requirement for DQS-DQS#, is 700mV (peak to pe
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4.2 Vref Tolerances
The dc-tolerance limits and ac-moist limits for the reference voltages VrefCA and VrefDQ are illustrated in the following
figure. It shows a valid reference voltage Vref(t) as a function of time. (Vref stands for VrefCA and VrefDQ likewise).
Vref(DC) is the linear average of Vref(t) over a very long period of time (e.g.,1 sec). This average has to meet the min/max
requirement in previous page. Furthermore Vref(t) may temporarily deviate from Vref(DC) by no more than ±1% VDD.
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and VIL(DC) are dependent on
Vref. “Vref” shall be understood as Vref(DC). The clarifies that dc-variations of Vref affect the absolute voltage a signal
has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System
timing and voltage budgets need to account for Vref(DC) deviations from the optimum position within the data-eye of the
input signals.
This also clarifies that the DRAM setup/hold specification and de-rating values need to include time and voltage
associated with Vref ac-noise. Timing and voltage effects due to ac-noise on Vref up to the specified limit (±1% of VDD)
are included in DRAM timing and their associated de-ratings.
Figure 4.2 Illustration of Vref(DC) tolerance and Vrefac-noise limits
Voltage
Vref(D
C)
Vref ac-noise
Vref(t)
Vref(DC)
max
Vref(DC)
min
VDD
VSS
time
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4.3. AC and DC Logic Input Levels for Differential Signals
4.3.1 Differential signal definition
Figure 4.3.1 Definition of differential ac-swing and “time above ac-level”
4.3.2 Differential swing requirements for clock (CK - CK#) and strobe (DQS - DQS#)
4.3.2.1 Differential AC and DC Input Levels
Symbol
Parameter
DDR3-800, 1066, 1333, 1600, 1866, 2133
unit
Notes
Min
Max
VIHdiff
Differential input logic high
+0.200
Note3
V
1
VILdiff
Differential input logic low
Note3
-0.200
V
1
VIHdiff(ac)
Differential input high ac
2 x ( VIH(ac) – Vref )
Note3
V
2
VILdiff(ac)
Differential input low ac
Note3
2 x ( Vref - VIL(ac) )
V
2
Notes:
1. Used to define a differential signal slew-rate.
2. For CK - CK# use VIH/VIL(ac) of ADD/CMD and VREFCA; for DQS - DQS#, DQSL, DQSL#, DQSU, DQSU# use VIH/VIL(ac) of DQs and VREFDQ; if
a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here.
3. These values are not defined; however, the single-ended signals CK, CK#, DQS, DQS#, DQSL, DQSL#, DQSU, DQSU# need to be within the
respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot.
tDVAC
VIH.DIFF.AC.MIN
VIH.DIFF.MIN
VIL.DIFF.MAX
VIL.DIFF.AC.MAX
Half cycle
tDVAC
time
Differential Input Voltage (i.e. DQS–DQS#, CK–CK#)
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4.3.2.2 Minimum required time before ringback (tDVAC) for CK - CK# and DQS - DQS#
Slew
Rate
[V/ns]
DDR3-800/1066/1333/1600
DDR3-1866/2133
tDVAC [ps] @
|VIH/Ldiff(AC)| =
350mV
tDVAC [ps] @
|VIH/Ldiff(AC)| =
300mV
tDVAC [ps] @
|VIH/Ldiff(AC)| =
(DQS - DQS#) only
tDVAC [ps] @
|VIH/Ldiff(AC)| =
300mV
tDVAC [ps] @
|VIH/Ldiff(AC)| =
(CK - CK#) only
> 4.0
75
175
214
134
139
4
57
170
214
134
139
3
50
167
191
112
118
2
38
119
146
67
77
1.8
34
102
131
52
63
1.6
29
81
113
33
45
1.4
22
54
88
9
23
1.2
Note
19
56
Note
Note
1
Note
Note
11
Note
Note
< 1
Note
Note
Note
Note
Note
Note: The rising input differential signal shall become equal to or greater than VIHdiff(ac) level; and the falling input differential signal shall become
equal to or less than VILdiff(ac) level.
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4.3.3. Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK#, DQS#, DQSL#, or DQSU#) has also to
comply with certain requirements for single-ended signals.
CK and CK# have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH(ac) / VIL(ac) )
for ADD/CMD signals) in every half-cycle. DQS, DQSL, DQSU, DQS#, DQSL# have to reach VSEHmin / VSELmax
(approximately the ac-levels (VIH(ac) / VIL(ac) ) for DQ signals) in every half-cycle preceding and following a valid
transition.
4.3.3.1. Single-ended levels for CK, DQS, DQSL, DQSU, CK#, DQS#, DQSL# or DQSU#
Symbol
Parameter
DDR3-800, 1066, 1333, & 1600
Unit
Notes
Min
Max
VSEH
Single-ended high-level for strobes
(VDDQ/2) + 0.175
note3
V
1, 2
Single-ended high-level for CK, CK
(VDDQ/2) + 0.175
note3
V
1, 2
VSEL
Single-ended low-level for strobes
note3
(VDDQ/2) - 0.175
V
1, 2
Single-ended Low-level for CK, CK
note3
(VDDQ/2) - 0.175
V
1, 2
Notes:
1. For CK, CK# use VIH/VIL(ac) of ADD/CMD; for strobes (DQS, DQS#, DQSL, DQSL#, DQSU, DQSU#) use VIH/VIL(ac) of DQs.
2. VIH(ac)/VIL(ac) for DQs is based on VREFDQ; VIH(ac)/VIL(ac) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a
signal group, then the reduced level applies also here
3. These values are not defined, however the single-ended signals CK, CK#, DQS, DQS#, DQSL, DQSL#, DQSU, DQSU# need to be within the
respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot.
Figure 4.3.3 Single-ended requirement for differential signals.
VSS or VSSQ
VSELmax
VDD/2 or VDDQ/2
VSEHmin
VSEL
VSEH
CK or DQS
time
VDD or VDDQ
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4.4 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross
point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in the following table. The
differential input cross point voltage Vix is measured from the actual cross point of true and completement signal to the
midlevel between of VDD and VSS.
Figure 4.4. Vix Definition
4.4.1 Cross point voltage for differential input signals (CK, DQS)
Symbol
Parameter
DDR3/3L-800, 1066, 1333, 1600, 1866, 2133
Unit
Note
Min.
Max.
Vix
Differential Input Cross Point Voltage relative to
VDD/2 for CK, CK
-150
150
mV
2
-175
175
mV
1
Differential Input Cross Point Voltage relative to
VDD/2 for DQS, DQS
-150
150
mV
2
Note:
1. Extended range for Vix is only allowed for clock and if single-ended clock input signals CK and CK# are monotonic with a single-ended swing VSEL /
VSEH of at least VDD/2 +/-250 mV, and when the differential slew rate of CK - CK# is larger than 3 V/ns.
2. The following must be true: (VDD/2) + VIX(min) – VSEL > 25 mV and VSEH – ((VDD/2) + VIX (max.)) > 25mV
4.5 Slew Rate Definitions for Single-Ended Input Signals
See “Address / Command Setup, Hold and Derating” for single-ended slew rate definitions for address and command
signals.
See “Data Setup, Hold and Slew Rate Derating” for single-ended slew rate definitions for data signals.
VDD
CK#,DQS#
VDD/2
CK,DQS
VSS
VIX
VIX
VIX
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4.6. Slew Rate Definition for Differential Input Signals
4.6.1 Differential Input Slew Rate Definition
Description
Measured
Defined by
From
To
Differential input slew rate for rising edge (CK-CK# & DQS-
DQS#)
VILdiffmax
VIHdiffmin
[VIHdiffmin-VILdiffmax] /
DeltaTRdiff
Differential input slew rate for falling edge (CK-CK# & DQS-
DQS#)
VIHdiffmin
VILdiffmax
[VIHdiffmin-VILdiffmax] / DeltaTFdiff
Note : The differential signal (i.e., CK-CK# & DQS-DQS#) must be linear between these thresholds.
Figure 4.6.1 Input Nominal Slew Rate Definition for DQS, DQS# and CK, CK#
Differential Input Voltage(i.e.
DQS-DQS#, CK-CK#)
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5. AC AND DC OUTPUT MEASUREMENT LEVELS
5.1 Single Ended AC and DC Output Levels
Symbol
Parameter
Value
Unit
Notes
VOH(DC)
DC output high measurement level (for IV curve linearity)
0.8xVDDQ
V
VOM(DC)
DC output mid measurement level (for IV curve linearity)
0.5xVDDQ
V
VOL(DC)
DC output low measurement level (fro IV curve linearity)
0.2xVDDQ
V
VOH(AC)
AC output high measurement level (for output SR)
VTT+0.1xVDDQ
V
1
VOL(AC)
AC output low measurement level (for output SR)
VTT-0.1xVDDQ
V
1
NOTE 1. The swing of ± 0.1 × VDDQ is based on approximately 50% of the static single-ended output high or low swing with a driver impedance of 40
and an effective test load of 25 to VTT = VDDQ/2.
5.2 Differential AC and DC Output Levels
Symbol
Parameter
Value
Unit
Notes
VOHdiff(AC)
AC differential output high measurement level (for output SR)
+0.2 x VDDQ
V
1
VOLdiff(AC)
AC differential output low measurement level (for output SR)
-0.2 x VDDQ
V
1
NOTE 1. The swing of ± 0.2 × VDDQ is based on approximately 50% of the static single-ended output high or low swing with a driver impedance of 40
and an effective test load of 25 to VTT = VDDQ/2 at each of the differential outputs.
5.3 Single Ended Output Slew Rate
5.3.1 Single Ended Output Slew Rate Definition
Description
Measured
Defined by
From
To
Single ended output slew rate for rising edge
VOL(AC)
VOH(AC)
[VOH(AC)-VOL(AC)] / DeltaTRse
Single ended output slew rate for falling edge
VOH(AC)
VOL(AC)
[VOH(AC)-VOL(AC)] / DeltaTFse
Figure 5.3.1 Single Ended Output Slew Rate Definition
5.3.2 Output Slew Rate (single-ended)
Parameter
Symbol
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
DDR3-1866
DDR3-2133
Unit
Min.
Max.
Min.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
Single-
ended
Output
Slew Rate
DDR3
SRQse
2.5
5
2.5
5
2.5
5
2.5
5
2.5
5
2.5
5
V/ns
Note: SR: Slew Rate. Q: Query Output (like in DQ, which stands for Data-in, Query -Output). se: Single-ended signals. For Ron = RZQ/7 setting.
Single Ended Output Voltage(i.e. DQ)
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5.4 Differential Output Slew Rate
5.4.1 Differential Output Slew Rate Definition
Description
Measured
Defined by
From
To
Differential output slew rate for rising
VOLdiff(AC)
VOHdiff(AC)
[VOHdiff(AC)-VOLdiff(AC)]/DeltaTRdiff
Differential output slew rate for falling
VOHdiff(AC)
VOLdiff(AC)
[VOHdiff(AC)-VOLdiff(AC)]/DeltaTFdiff
Note: Output slew rate is verified by design and characterization, and not 100% tested in production.
Figure 5.4.1 Differential Output Slew Rate Definition
5.4.2 Differential Output Slew Rate
Parameter
Symbol
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
DDR3-1866
DDR3-2133
Unit
Min.
Max.
Min.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
Differential
Output
Slew Rate
DDR3
SRQdiff
5
10
5
10
5
10
5
10
5
10
5
10
V/ns
Description: SR: Slew Rate, Q: Query Output (like in DQ, which stands for Data-in, Query-Output), diff: Differential Signals, For Ron = RZQ/7 setting
5.5 Reference Load for AC Timing and Output Slew Rate
The following figure represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters
of the device as well as output slew rate measurements. It is not intended as a precise representation of any particular
system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS
or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their
production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.
Figure 5.5 Reference Load for AC Timing and Output Slew Rate
CK,CK#
DUT
DQ,
DQS,
DQS#
VDDQ
25ohm
VTT=VDDQ/2
Timing Reference Point
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5.6 Overshoot and Undershoot Specifications
5.6.1 AC Overshoot/Undershoot Specification for Address and Control Pins
Item
DDR3-
800
DDR3-
1066
DDR3-
1333
DDR3-
1600
DDR3-
1866
DDR3-
2133
Units
Maximum peak amplitude allowed for
overshoot area
0.4
0.4
0.4
0.4
0.4
0.4
V
Maximum peak amplitude allowed for
undershoot area
0.4
0.4
0.4
0.4
0.4
0.4
V
Maximum overshoot area above VDD
0.67
0.5
0.4
0.33
0.28
0.25
V-ns
undershoot area below VSS
0.67
0.5
0.4
0.33
0.28
0.25
V-ns
Note : A0-A13, BA0-BA2, CS#, RAS#, CAS#, WE#, CKE, ODT
5.6.2 AC Overshoot/Undershoot Specification for Clock, Data, Strobe, and Mask
Item
DDR3-
800
DDR3-
1066
DDR3-
1333
DDR3-
1600
DDR3-
1866
DDR3-
2133
Units
Maximum peak amplitude allowed for
overshoot area
0.4
0.4
0.4
0.4
0.4
0.4
V
Maximum peak amplitude allowed for
undershoot area
0.4
0.4
0.4
0.4
0.4
0.4
V
Maximum overshoot area above VDD
0.25
0.19
0.15
0.13
0.11
0.10
V-ns
undershoot area below VSS
0.25
0.19
0.15
0.13
0.11
0.10
V-ns
Note : CK, CK#, DQ, DQS, DQS#, DM
Maximum Amplitude
Overshoot Area
Undershoot Area
Maximum Amplitude
VDD
VSS
Volts(V)
Time(ns)
Maximum Amplitude
VDDQ
VSSQ
Volts(V)
Time(ns)
Maximum Amplitude
Overshoot Area
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5.7 34Ohm Output Driver DC Electrical Characteristics
A Functional representation of the output buffer is shown as below. Output driver impedance RON is defined by the value
ofthe external reference resistor RZQ as follows:
RON34 = RZQ / 7 (nominal 34.4ohms +/-10% with nominal RZQ=240ohms)
The individual pull-up and pull-down resistors (RONPu and RONPd) are defined as follows:
RONPu = [VDDQ-Vout] / | Iout | ------------------- under the condition that RONPd is turned off (1)
RONPd = Vout / | Iout | -------------------------------under the condition that RONPu is turned off (2)
Figure 5.7 Output Driver : Definition of Voltages and Currents
5.7.1 Output Driver DC Electrical Characteristics
DDR3 (assuming 1.5V, RZQ = 240ohms; entire operating temperature range; after proper ZQ calibration)
RONNom
Resistor
Min
Nom
Max
Unit
Notes
34 ohms
RON34Pd
0.6
1
1.1
RZQ/7
1,2,3
0.9
1
1.1
RZQ/7
1,2,3
0.9
1
1.4
RZQ/7
1,2,3
RON34Pu
0.9
1
1.4
RZQ/7
1,2,3
0.9
1
1.1
RZQ/7
1,2,3
0.6
1
1.1
RZQ/7
1,2,3
40 ohms
RON40Pd
0.6
1
1.1
RZQ/6
1,2,3
0.9
1
1.1
RZQ/6
1,2,3
0.9
1
1.4
RZQ/6
1,2,3
RON40Pu
0.9
1
1.4
RZQ/6
1,2,3
0.9
1
1.1
RZQ/6
1,2,3
0.6
1
1.1
RZQ/6
1,2,3
Mismatch between pull-up and pull-down, MMPuPd
-10
+10
%
1,2,4
Notes:
1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or
voltage changes after calibration, see following section on voltage and temperature sensitivity.
2. The tolerance limits are specified under the condition that VDDQ=VDD and that VSSQ=VSS.
3. Pull-down and pull-up output driver impedances are recommended to be calibrated at 0.5xVDDQ. Other calibration schemes may be used to
achieve the linearity spec shown above, e.g. calibration at 0.2 * VDDQ and 0.8 x VDDQ.
4. Measurement definition for mismatch between pull-up and pull-down, MMPuPd:
Measure RONPu and RONPd, both at 0.5 x VDDQ:
MMPuPd = [RONPu - RONPd] / RONNom x 100
VDDQ
DQ
VSSQ
To other circuitry
RONPu
RONPd
IPu
IPd
Output
Driver
Chip in Drive Mode
Iout
Vout
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5.7.2 Output Driver Temperature and Voltage sensitivity
If temperature and/or voltage after calibration, the tolerance limits widen according to the following table below.
Delta T = T - T(@calibration); Delta V = VDDQ - VDDQ(@calibration); VDD = VDDQ
5.7.2.1 Output Driver Sensitivity Definition
Items
Min.
Max.
Unit
RONPU@VOHdc
0.6 - dRONdTH*lDelta Tl - dRONdVH*lDelta Vl
1.1 + dRONdTH*lDelta Tl - dRONdVH*lDelta Vl
RZQ/7
RON@VOMdc
0.9 - dRONdTM*lDelta Tl - dRONdVM*lDelta Vl
1.1 + dRONdTM*lDelta Tl - dRONdVM*lDelta Vl
RZQ/7
RONPD@VOLdc
0.6 - dRONdTL*lDelta Tl - dRONdVL*lDelta Vl
1.1 + dRONdTL*lDelta Tl - dRONdVL*lDelta Vl
RZQ/7
Note: dRONdT and dRONdV are not subject to production test but are verified by design and characterization.
5.7.2.2 Output Driver Voltage and Temperature Sensitivity
Speed Bin
DDR3-800/1066/1333
DDR3-1600/1866/2133
Unit
Items
Min.
Max
Min.
Max
dRONdTM
0
1.5
0
1.5
%/°C
dRONdVM
0
0.15
0
0.13
%/mV
dRONdTL
0
1.5
0
1.5
%/°C
dRONdVL
0
0.15
0
0.13
%/mV
dRONdTH
0
1.5
0
1.5
%/°C
dRONdVH
0
0.15
0
0.13
%/mV
Note: dRONdT and dRONdV are not subject to production test but are verified by design and characterization.
5.8 On-Die Termination (ODT) Levels and I-V Characteristics
5.8.1 On-Die Termination (ODT) Levels and I-V Characteristics
On-Die Termination effective resistance RTT is defined by bits A9, A6, and A2 of the MR1 Register.
ODT is applied to the DQ, DM, DQS/DQS, and TDQS/TDQS (x8 devices only) pins.
A functional representation of the on-die termination is shown in the following figure. The individual pull-up and pull-down
resistors (RTTPu and RTTPd) are defined as follows:
RTTPu = [VDDQ - Vout] / | Iout | ------------------ under the condition that RTTPd is turned off (3)
RTTPd = Vout / | Iout | ------------------------------ under the condition that RTTPu is turned off (4)
Figure 5.8.1 On-Die Termination : Definition of Voltages and Currents
5.8.2 ODT DC Electrical Characteristics
The following table provides an overview of the ODT DC electrical characteristics. The values for RTT60Pd120, RTT60Pu120, RTT120Pd240,
RTT120Pu240, RTT40Pd80, RTT40Pu80, RTT30Pd60, RTT30Pu60, RTT20Pd40, RTT20Pu40 are not specification requirements, but can be used as
design guide lines
VDDQ
DQ
VSSQ
To other circuitry
RTTPu
RTTPd
IPu
IPd
ODT
Chip in Termination Mode
Iout
Vout
Iout = Ipd -Ipu
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ODT DC Electrical Characteristics
(assuming RZQ = 240ohms +/- 1% entire operating temperature range; after proper ZQ calibration)
MR1 A9,
A6, A2
RTT
Resistor
Vout
Min
Nom
Max
(DDR3)
Unit
Notes
0,1,0
120
RTT120Pd240
VOLdc = 0.2 x VDDQ
0.6
1
1.1
RZQ
1,2,3,4
0.5 x VDDQ
0.9
1
1.1
RZQ
1,2,3,4
VOHdc = 0.8 x VDDQ
0.9
1
1.4
RZQ
1,2,3,4
RTT120Pu240
VOLdc = 0.2 x VDDQ
0.9
1
1.4
RZQ
1,2,3,4
0.5 x VDDQ
0.9
1
1.1
RZQ
1,2,3,4
VOHdc = 0.8 x VDDQ
0.6
1
1.1
RZQ
1,2,3,4
RTT120
VIL(ac) to VIH(ac)
0.9
1
1.6
RZQ/2
1,2,5
0,0,1
60
RTT60Pd120
VOLdc = 0.2 x VDDQ
0.6
1
1.1
RZQ/2
1,2,3,4
0.5 x VDDQ
0.9
1
1.1
RZQ/2
1,2,3,4
VOHdc = 0.8 x VDDQ
0.9
1
1.4
RZQ/2
1,2,3,4
RTT60Pu120
VOLdc = 0.2 x VDDQ
0.9
1
1.4
RZQ/2
1,2,3,4
0.5 x VDDQ
0.9
1
1.1
RZQ/2
1,2,3,4
VOHdc = 0.8 x VDDQ
0.6
1
1.1
RZQ/2
1,2,3,4
RTT60
VIL(ac) to VIH(ac)
0.9
1
1.6
RZQ/4
1,2,5
0,1,1
40
RTT40Pd80
VOLdc = 0.2 x VDDQ
0.6
1
1.1
RZQ/3
1,2,3,4
0.5 x VDDQ
0.9
1
1.1
RZQ/3
1,2,3,4
VOHdc = 0.8 x VDDQ
0.9
1
1.4
RZQ/3
1,2,3,4
RTT40Pu80
VOLdc = 0.2 x VDDQ
0.9
1
1.4
RZQ/3
1,2,3,4
0.5 x VDDQ
0.9
1
1.1
RZQ/3
1,2,3,4
VOHdc = 0.8 x VDDQ
0.6
1
1.1
RZQ/3
1,2,3,4
RTT40
VIL(ac) to VIH(ac)
0.9
1
1.6
RZQ/6
1,2,5
1,0,1
30
RTT30Pd60
VOLdc = 0.2 x VDDQ
0.6
1
1.1
RZQ/4
1,2,3,4
0.5 x VDDQ
0.9
1
1.1
RZQ/4
1,2,3,4
VOHdc = 0.8 x VDDQ
0.9
1
1.4
RZQ/4
1,2,3,4
RTT30Pu60
VOLdc = 0.2 x VDDQ
0.9
1
1.4
RZQ/4
1,2,3,4
0.5 x VDDQ
0.9
1
1.1
RZQ/4
1,2,3,4
VOHdc = 0.8 x VDDQ
0.6
1
1.1
RZQ/4
1,2,3,4
RTT30
VIL(ac) to VIH(ac)
0.9
1
1.6
RZQ/8
1,2,5
1,0,0
20
RTT20Pd40
VOLdc = 0.2 x VDDQ
0.6
1
1.1
RZQ/6
1,2,3,4
0.5 x VDDQ
0.9
1
1.1
RZQ/6
1,2,3,4
VOHdc = 0.8 x VDDQ
0.9
1
1.4
RZQ/6
1,2,3,4
RTT20Pu40
VOLdc = 0.2 x VDDQ
0.9
1
1.4
RZQ/6
1,2,3,4
0.5 x VDDQ
0.9
1
1.1
RZQ/6
1,2,3,4
VOHdc = 0.8 x VDDQ
0.6
1
1.1
RZQ/6
1,2,3,4
RTT20
VIL(ac) to VIH(ac)
0.9
1
1.6
RZQ/12
1,2,5
Deviation of VM w.r.t VDDQ/2, DVM
-5
-
+5
%
1,2,5,6
Notes:
1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or
voltage changes after calibration, see following section on voltage and temperature sensitivity.
2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS.
3. Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5 x VDDQ. Other calibration schemes may be used to achieve the
linearity spec shown above.
4. Not a specification requirement, but a design guide line.
5. Measurement definition for RTT:
Apply VIH(ac) to pin under test and measure current I(VIH(ac)), then apply VIL(ac) to pin under test and measure current I(VIL(ac)) respectively.
RTT = [VIH(ac) - VIL(ac)] / [I(VIH(ac)) - I(VIL(ac))]
6. Measurement definition for VM and DVM:
Measure voltage (VM) at test pin (midpoint) with no load: Delta VM = [2VM / VDDQ -1] x 100
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5.8.3 ODT Temperature and Voltage sensitivity
If temperature and/or voltage after calibration, the tolerance limits widen according to the following table.
Delta T = T - T(@calibration); Delta V = VDDQ - VDDQ(@calibration); VDD = VDDQ
5.8.3.1 ODT Sensitivity Definition
min
max
Unit
RTT
0.9 - dRTTdT*lDelta Tl - dRTTdV*lDelta Vl
1.6 + dRTTdT*lDelta Tl + dRTTdV*lDelta Vl
RZQ/2,4,6,8,12
5.8.3.2 ODT Voltage and Temperature Sensitivity
Min
Max
Unit
dRTTdT
0
1.5
%/°C
dRTTdV
0
0.15
%/mV
Note: These parameters may not be subject to production test. They are verified by design and characterization
5.9 ODT Timing Definitions
5.9.1 Test Load for ODT Timings
Different than for timing measurements, the reference load for ODT timings is defined in the following figure.
Figure 5.9.1 ODT Timing Reference Load
5.9.2 ODT Timing Definitions
Definitions for tAON, tAONPD, tAOF, tAOFPD, and tADC are provided in the following table and subsequent figures.
Symbol
Begin Point Definition
End Point Definition
tAON
Rising edge of CK - CK defined by the end point of ODTLon
Extrapolated point at VSSQ
tAONPD
Rising edge of CK - CK with ODT being first registered high
Extrapolated point at VSSQ
tAOF
Rising edge of CK - CK defined by the end point of ODTLoff
End point: Extrapolated point at VRTT_Nom
tAOFPD
Rising edge of CK - CK with ODT being first registered low
End point: Extrapolated point at VRTT_Nom
tADC
Rising edge of CK - CK defined by the end point of ODTLcnw,
ODTLcwn4, or ODTLcwn8
End point: Extrapolated point at VRTT_Wr and
VRTT_Nom respectively
Reference Settings for ODT Timing Measurements
Measured Parameter
RTT_Nom Setting
RTT_Wr Setting
VSW1[V]
VSW2[V]
tAON
RZQ/4
NA
0.05
0.10
RZQ/12
NA
0.10
0.20
tAONPD
RZQ/4
NA
0.05
0.10
RZQ/12
NA
0.10
0.20
tAOFPD
RZQ/4
NA
0.05
0.10
RZQ/12
NA
0.10
0.20
tADC
DDR3
RZQ/12
RZQ/2
0.20
0.30
CK,CK#
DUT
DQ,DM
DQS,
DQS#,
TDQS,
TDQS#
25ohm
VTT=VSSQ
Timing Reference Point
VDDQ
VSSQ
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Figure 5.9.2.1 Definition of tAON
Figure 5.9.2.2 Definition of tAONPD
Begin Point : Rising edge of CK-CK# with
ODT being first register high
End Point : Extrapolated point at VSSQ
CK
CK#
VTT
Vsw2
DQ,DM,DQS,
DQS#,TDQS,
TDQS#
VSSQ
tAONPD
Vsw1
Tsw1
Tsw2
Begin Point : Rising edge of CK-CK#
defined by the end of ODTLon
End Point : Extrapolated point at VSSQ
CK
CK#
VTT
Vsw2
DQ,DM,DQS,
DQS#,TDQS,
TDQS#
VSSQ
tAON
Vsw1
Tsw1
Tsw2
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Figure 5.9.2.3 Definition of tAOF
Figure 5.9.2.4 Definition of tAOFPD
Begin Point : Rising edge of CK-CK# with
defined by the end point of ODTLoff
End Point : Extrapolated point at VRTT_NOM
CK
CK#
VTT
Vsw2
DQ,DM,DQS,
DQS#,TDQS,
TDQS#
VSSQ
tAOF
Vsw1
Tsw1
Tsw2
VRTT_NOM
Begin Point : Rising edge of CK-CK# with
ODT being first registered low
End Point : Extrapolated point at VRTT_NOM
CK
CK#
VTT
Vsw2
DQ,DM,DQS,
DQS#,TDQS,
TDQS#
VSSQ
tAOFPD
Vsw1
Tsw1
Tsw2
VRTT_NOM
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Figure 5.9.2.5 Definition of tADC
Begin Point : Rising edge of CK-CK#
defined by the end point of ODTLcnw
Begin Point : Rising edge of CK-CK# defined by
the end point of ODTLcwn4 or ODTLcwn8
tADC
tADC
End Point : Extrapolated point at VRTT_Wr
End Point : Extrapolated
point at VRTT_NOM
DQ,DM,DQS,
DQS#,TDQS,
TDQS#
CK
CK#
VTT
VSSQ
VRTT_NOM
Tsw11
Tsw21
Tsw22
Tsw12
Vsw2
Vsw1
VRTT_Wr
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6. INPUT / OUTPUT CAPACITANCE
Symbol
Parameter
DDR3-1066
DDR3-1333
DDR3-1600
Units
Notes
Min
Max
Min
Max
Min
Max
C
IO
InInput/output capacitance (DQ, DM,
DQS, DQS#,TDQS,TDQS#)
1.5
3.0
1.5
2.5
1.5
2.3
pF
1,2,3
C
CK
Input capacitance, CK and CK#
0.8
1.6
0.8
1.4
0.8
1.4
pF
2,3
C
DCK
Input capacitance delta, CK and
CK#
0
0.15
0
0.15
0
0.15
pF
2,3,4
C
DDQS
Input/output capacitance delta,
DQS and DQS#
0
0.2
0
0.15
0
0.15
pF
2,3,5
C
I
Input capacitance, CTRL, ADD,
command input-only pins
0.75
1.5
0.75
1.3
0.75
1.3
pF
2,3,7,8
C
DI_CTRL
Input capacitance delta, all CTRL
input-only pins
-0.5
0.3
-0.4
0.2
-0.4
0.2
pF
2,3,7,8
C
DI_ADD_C
MD
Input capacitance delta, all
ADD/CMD input-only pins
-0.5
0.5
-0.4
0.4
-0.4
0.4
pF
2,3,9,10
C
DIO
Input/output capacitance delta, DQ,
DM, DQS, DQS# TDQS,TDQS#
-0.5
0.3
-0.5
0.3
-0.5
0.3
pF
2,3,11
C
ZQ
Input/output capacitance of ZQ pin
-
3
-
3
-
3
pF
2,3,12
Notes:
1. Although the DM, TDQS and TDQS# pins have different functions, the loading matches DQ and DQS
2. This parameter is not subject to production test. It is verified by design and characterization. VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die
termination off.
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
4. Absolute value of CCK-CCK#
5. Absolute value of CIO(DQS)-CIO(DQS#)
6. CI applies to ODT, CS#, CKE, A0-A13, BA0-BA2, RAS#,CAS#,WE#.
7. CDI_CTRL applies to ODT, CS# and CKE
8. CDI_CTRL=CI(CTRL)-0.5*(CI(CK)+CI(CK#))
9. CDI_ADD_CMD applies to A0-A13, BA0-BA2, RAS#, CAS# and WE#
10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CK)+CI(CK#))
11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS#))
12. Maximum external load capacitance on ZQ pin: 5 pF.
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7. IDD SPECIFICATIONS AND MEASUREMENT CONDITIONS
IDD Specifications (x8), 1.5 Operation Voltage (-40˚C to 105˚C)
Symbol
Parameter/Condition
DDR3-1066
DDR3-1333
DDR3-1600
Unit
Max.
Max.
Max.
IDD0
Operating Current 0
-> One Bank Activate-> Precharge
99
108
118
mA
IDD1
Operating Current 1
-> One Bank Activate-> Read->
Precharge
128
140
154
mA
IDD2P0
Precharge Power-Down Current
Slow Exit - MR0 bit A12 = 0
24
24
24
mA
IDD2P1
Precharge Power-Down Current
Fast Exit - MR0 bit A12 = 1
71
75
80
mA
IDD2PQ
Precharge Quiet Standby Current
87
93
100
mA
IDD2N
Precharge Standby Current
91
97
105
mA
IDD3P
Active Power-Down Current
Always Fast Exit
95
102
110
mA
IDD3N
Active Standby Current
127
136
145
mA
IDD4R
Operating Current Burst Read
212
265
395
mA
IDD4W
Operating Current Burst Write
210
259
384
mA
IDD5B
Burst Refresh Current
221
242
265
mA
IDD6
Self-Refresh Current Normal
Temperature Range (0-85°C)
24
24
24
mA
IDD6ET
Self-Refresh Current: extended
temperature range
28
28
28
mA
IDD7
All Bank Interleave Read Current
396
431
470
mA
Notes:
1. 1066 is for reference only
2. Values applicable for all temperature grades; see Component Operating Temperature Range, section 3.2.
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7. IDD SPECIFICATIONS AND MEASUREMENT CONDITIONS
IDD Specifications (x8), 1.5 Operation Voltage (105˚C to 125˚C)
Symbol
Parameter/Condition
DDR3-1066
DDR3-1333
DDR3-1600
Unit
Max.
Max.
Max.
IDD0
Operating Current 0
-> One Bank Activate-> Precharge
109
118
128
mA
IDD1
Operating Current 1
-> One Bank Activate-> Read->
Precharge
132
144
158
mA
IDD2P0
Precharge Power-Down Current
Slow Exit - MR0 bit A12 = 0
28
28
28
mA
IDD2P1
Precharge Power-Down Current
Fast Exit - MR0 bit A12 = 1
86
90
95
mA
IDD2PQ
Precharge Quiet Standby Current
102
108
115
mA
IDD2N
Precharge Standby Current
105
111
119
mA
IDD3P
Active Power-Down Current
Always Fast Exit
110
117
125
mA
IDD3N
Active Standby Current
162
171
180
mA
IDD4R
Operating Current Burst Read
237
290
420
mA
IDD4W
Operating Current Burst Write
230
279
404
mA
IDD5B
Burst Refresh Current
240
261
284
mA
IDD6
Self-Refresh Current Normal
Temperature Range (0-85°C)
28
28
28
mA
IDD6ET
Self-Refresh Current: extended
temperature range
32
32
32
mA
IDD7
All Bank Interleave Read Current
411
446
485
mA
Notes:
1. 1066 is for reference only
2. Values applicable for all temperature grades; see Component Operating Temperature Range, section 3.2.
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IDD Specifications (x16), 1.5 Operation Voltage (-40˚C to 105˚C)
Symbol
Parameter/Condition
DDR3-1066
DDR3-1333
DDR3-1600
Unit
Max.
Max.
Max.
IDD0
Operating Current 0
-> One Bank Activate-> Precharge
121
133
145
mA
IDD1
Operating Current 1
-> One Bank Activate-> Read->
Precharge
160
175
191
mA
IDD2P0
Precharge Power-Down Current
Slow Exit - MR0 bit A12 = 0
24
24
24
mA
IDD2P1
Precharge Power-Down Current
Fast Exit - MR0 bit A12 = 1
71
75
80
mA
IDD2PQ
Precharge Quiet Standby Current
87
93
100
mA
IDD2N
Precharge Standby Current
91
97
105
mA
IDD3P
Active Power-Down Current
Always Fast Exit
95
102
110
mA
IDD3N
Active Standby Current
127
136
145
mA
IDD4R
Operating Current Burst Read
263
328
490
mA
IDD4W
Operating Current Burst Write
259
322
478
mA
IDD5B
Burst Refresh Current
221
242
265
mA
IDD6
Self-Refresh Current Normal
Temperature Range (0-85°C)
24
24
24
mA
IDD6ET
Self-Refresh Current: extended
temperature range
28
28
28
mA
IDD7
All Bank Interleave Read Current
396
431
470
mA
Notes:
1. 1066 is for reference only
2. Values applicable for all temperature grades; see Component Operating Temperature Range, section 3.2.
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IDD Specifications (x16), 1.5 Operation Voltage (105˚C to 125˚C)
Symbol
Parameter/Condition
DDR3-1066
DDR3-1333
DDR3-1600
Unit
Max.
Max.
Max.
IDD0
Operating Current 0
-> One Bank Activate-> Precharge
131
143
155
mA
IDD1
Operating Current 1
-> One Bank Activate-> Read->
Precharge
164
179
195
mA
IDD2P0
Precharge Power-Down Current
Slow Exit - MR0 bit A12 = 0
28
28
28
mA
IDD2P1
Precharge Power-Down Current
Fast Exit - MR0 bit A12 = 1
86
90
95
mA
IDD2PQ
Precharge Quiet Standby Current
102
108
115
mA
IDD2N
Precharge Standby Current
105
111
119
mA
IDD3P
Active Power-Down Current
Always Fast Exit
110
117
125
mA
IDD3N
Active Standby Current
162
171
180
mA
IDD4R
Operating Current Burst Read
288
353
515
mA
IDD4W
Operating Current Burst Write
279
342
498
mA
IDD5B
Burst Refresh Current
240
261
284
mA
IDD6
Self-Refresh Current Normal
Temperature Range (0-85°C)
28
28
28
mA
IDD6ET
Self-Refresh Current: extended
temperature range
32
32
32
mA
IDD7
All Bank Interleave Read Current
411
446
485
mA
Notes:
1. 1066 is for reference only
2. Values applicable for all temperature grades; see Component Operating Temperature Range, section 3.2.
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8. Electrical Characteristics and AC timing for DDR3-800 to DDR3-1600
8.1 Clock Specification
The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max values may result
in malfunction of the DDR3 SDRAM device.
8.1.1 Definition for tCK(avg)
tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock period is
calculated from rising edge to rising edge.
Where N=200
8.1.2 Definition for tCK(abs)
tCK(abs) is defind as the absolute clock period, as measured from one rising edge to the next consecutive rising edge.
tCK(abs) is not subject to production test.
8.1.3 Definition for tCH(avg) and tCL(avg)
tCH(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses:
Where N=200
tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses:
Where N=200
8.1.4 Definition for note for tJIT(per), tJIT(per, Ick)
tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg).
tJIT(per) = min/max of {tCKi-tCK(avg) where i=1 to 200}
tJIT(per) defines the single period jitter when the DLL is already locked.
tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only.
tJIT(per) and tJIT(per,lck) are not subject to production test.
tCK(avg) = (
tCKj ) / N
tCH(avg) = (
tCHj ) / (N x tCK(avg)
tCL(avg) = (
tCLj ) / (N x tCK(avg)
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8.1.5 Definition for tJIT(cc), tJIT(cc, Ick)
tJIT(cc) is defined as the absolute difference in clock period between two consecutive clock cycles:
tJIT(cc) = Max of |{tCKi+1 - tCKi }|
tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked.
tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only.
tJIT(cc) and tJIT(cc,lck) are not subject to production test.
8.1.6 Definition for tERR(nper)
tERR is defined as the cumulative error across n multiple consecutive cycles from tCK(avg). tERR is not subject to
production test.
8.2 Refresh Parameters
Refresh parameters(1,2)
Parameter
Symbol
Units
All Bank Refresh to active/refresh cmd time
tRFC
110
ns
Average periodic refresh interval
tREFI
-40°C < TCASE < 85°C
7.8
μs
85°C < TCASE < 105°C
3.9
μs
105°C < TCASE < 125°C
1.95
μs
Notes:
1. The permissible Tcase operating temperature is specified by temperature grade. The maximum Tcase is 95°C unless A2 grade, for which the
maximum is 105C, or A3 grade for which the maximum is 125C. Refer to 3.2 Component Operating Temperature Range.
2. In general, the Refresh command needs to be issued at the tREFI interval. For flexibility, a maximum of 8 Refresh commands may be
postponed or pulled-in (done in advance). However, in either case, the maximum interval between any two consecutive Refresh commands is
9 x tREFI. At any given time, a maximum of 16 Refresh commands can be issued within 2 x tREFI
8.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin
DDR3-1066MT/s
Speed Bin
DDR3 -1066
Unit
CL-nRCD-nRP
7-7-7 (-187F)
Parameter
Symbol
Min
Max
Internal read command to first data
tAA
13.125
20.000
ns
ACT to internal read or write delay time
tRCD
13.125
-
ns
PRE command period
tRP
13.125
-
ns
ACT to ACT or REF command period
tRC
50.625
-
ns
ACT to PRE command period
tRAS
37.500
9*tREFI
ns
CL=5
CWL =5
tCK(AVG)
3.000
3.300
ns
CWL=6
tCK(AVG)
Reserved
ns
CL=6
CWL =5
tCK(AVG)
2.500
3.300
ns
CWL=6
tCK(AVG)
Reserved
ns
CL=7
CWL =5
tCK(AVG)
Reserved
ns
CWL=6
tCK(AVG)
1.875
<2.5
ns
CL=8
CWL =5
tCK(AVG)
Reserved
ns
CWL=6
tCK(AVG)
1.875
<2.5
ns
Supported CL Settings
5,6,7,8
nCK
Supported CWL Settings
5,6
nCK
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DDR3-1333MT/s
Speed Bin
DDR3 -1333
Unit
CL-nRCD-nRP
9-9-9 (-15H)
Parameter
Symbol
Min
Max
Internal read command to first data
tAA
13.5
20
ns
ACT to internal read or write delay
tRCD
13.5
-
ns
PRE command period
tRP
13.5
-
ns
ACT to ACT or REF period
tRC
49.5
-
ns
ACT to PRE command period
tRAS
36.0
9*tREFI
ns
CL=5
CWL =5
tCK(AVG)
3.0
3.3
ns
CWL=6
tCK(AVG)
Reserved
ns
CWL=7
tCK(AVG)
Reserved
ns
CL=6
CWL =5
tCK(AVG)
2.5
3.3
ns
CWL=6
tCK(AVG)
Reserved
ns
CWL=7
tCK(AVG)
Reserved
ns
CL=7
CWL =5
tCK(AVG)
Reserved
ns
CWL=6
tCK(AVG)
1.875
<2.5
ns
CWL=7
tCK(AVG)
Reserved
ns
CL=8
CWL =5
tCK(AVG)
Reserved
ns
CWL=6
tCK(AVG)
1.875
<2.5
ns
CWL=7
tCK(AVG)
Reserved
ns
CL=9
CWL=5
tCK(AVG)
Reserved
ns
CWL=6
tCK(AVG)
Reserved
ns
CWL=7
tCK(AVG)
1.5
<1.875
ns
CL=10
CWL =5
tCK(AVG)
Reserved
ns
CWL=6
tCK(AVG)
Reserved
ns
CWL=7
tCK(AVG)
1.5
<1.875
ns
Supported CL Settings
5,6,7,8,9,10
nCK
Supported CWL Settings
5,6,7
nCK
Note : *: -15H is compatible with slower speed options
DDR3-1600MT/s
Speed Bin
DDR3-1600
Unit
CL-nRCD-nRP
11-11-11 (-125K)
Parameter
Symbol
Min
Max
Internal read command to first data
tAA
13.75
20
ns
ACT to internal read or write delay
tRCD
13.75
-
ns
PRE command period
tRP
13.75
-
ns
ACT to ACT or REF period
tRC
48.75
-
ns
ACT to PRE command period
tRAS
35
9*tREFI
ns
CL=5
CWL =5
tCK(AVG)
3.0
3.3
ns
CWL=6
tCK(AVG)
Reserved
ns
CWL=7
tCK(AVG)
Reserved
ns
CWL=8
tCK(AVG)
Reserved
ns
CL=6
CWL =5
tCK(AVG)
2.5
3.3
ns
CWL=6
tCK(AVG)
Reserved
ns
CWL=7
tCK(AVG)
Reserved
ns
CWL=8
tCK(AVG)
Reserved
ns
CL=7
CWL =5
tCK(AVG)
Reserved
ns
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CWL=6
tCK(AVG)
1.875
<2.5
ns
CWL=7
tCK(AVG)
Reserved
ns
CWL=8
tCK(AVG)
Reserved
ns
CL=8
CWL =5
tCK(AVG)
Reserved
ns
CWL=6
tCK(AVG)
1.875
<2.5
ns
CWL=7
tCK(AVG)
Reserved
ns
CWL=8
tCK(AVG)
Reserved
ns
CL=9
CWL =5
tCK(AVG)
Reserved
ns
CWL=6
tCK(AVG)
Reserved
ns
CWL=7
tCK(AVG)
1.5
<1.875
ns
CWL=8
tCK(AVG)
Reserved
ns
CL=10
CWL =5
tCK(AVG)
Reserved
ns
CWL=6
tCK(AVG)
Reserved
ns
CWL=7
tCK(AVG)
1.5
<1.875
ns
CWL =8
tCK(AVG)
Reserved
ns
CL=11
CWL =5
tCK(AVG)
Reserved
ns
CWL= 6
tCK(AVG)
Reserved
ns
CWL= 7
tCK(AVG)
Reserved
ns
CWL =8
tCK(AVG)
1.25
<1.5
ns
Supported CL Settings
5,6,7,8,9,10,11
nCK
Supported CWL Settings
5,6,7,8
nCK
Note : *: -125K is backward compatible with slower speed options.
9. ELECTRICAL CHARACTERISTICS & AC TIMING
9.1 Timing Parameter by Speed Bin (DDR3-800, DDR3-1066)
Parameter
Symbol
DDR3-800
DDR3-1066
Units
Notes
Min.
Max.
Min.
Max.
Clock Timing
Minimum Clock Cycle Time (DLL off mode)
tCK(DLL_OFF)
8
-
8
-
ns
6
Average Clock Period
tCK(avg)
Refer to Standard Speed Bins
ps
Average high pulse width
tCH(avg)
0.47
0.53
0.47
0.53
tCK(avg)
Average low pulse width
tCL(avg)
0.47
0.53
0.47
0.53
tCK(avg)
Absolute Clock Period
tCK(abs)
Min.: tCK(avg)min + tJIT(per)min
ps
Max.: tCK(avg)max + tJIT(per)max
Absolute clock HIGH pulse width
tCH(abs)
0.43
-
0.43
-
tCK(avg)
25
Absolute clock LOW pulse width
tCL(abs)
0.43
-
0.43
-
tCK(avg)
26
Clock Period Jitter
tJIT(per)
-100
100
-90
90
ps
Clock Period Jitter during DLL locking period
tJIT(per, lck)
-90
90
-80
80
ps
Cycle to Cycle Period Jitter
tJIT(cc)
200
180
ps
Cycle to Cycle Period Jitter during DLL locking
period
tJIT(cc, lck)
180
160
ps
Duty Cycle Jitter
tJIT(duty)
-
-
-
-
ps
Cumulative error across 2 cycles
tERR(2per)
-147
147
-132
132
ps
Cumulative error across 3 cycles
tERR(3per)
-175
175
-157
157
ps
Cumulative error across 4 cycles
tERR(4per)
-194
194
-175
175
ps
Cumulative error across 5 cycles
tERR(5per)
-209
209
-188
188
ps
Cumulative error across 6 cycles
tERR(6per)
-222
222
-200
200
ps
Cumulative error across 7 cycles
tERR(7per)
-232
232
-209
209
ps
Cumulative error across 8 cycles
tERR(8per)
-241
241
-217
217
ps
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Parameter
Symbol
DDR3-800
DDR3-1066
Units
Notes
Min.
Max.
Min.
Max.
Cumulative error across 9 cycles
tERR(9per)
-249
249
-224
224
ps
Cumulative error across 10 cycles
tERR(10per)
-257
257
-231
231
ps
Cumulative error across 11 cycles
tERR(11per)
-263
263
-237
237
ps
Cumulative error across 12 cycles
tERR(12per)
-269
269
-242
242
ps
Cumulative error across n = 13, 14 . . . 49, 50
cycles
tERR(nper)
tERR(nper)min = (1 + 0.68ln(n)) * tJIT(per)min
ps
24
tERR(nper)max = (1 + 0.68ln(n)) *
tJIT(per)max
Data Timing
DQS, DQS# to DQ skew, per group, per
access
tDQSQ
-
200
-
150
ps
13
DQ output hold time from DQS, DQS#
tQH
0.38
-
0.38
-
tCK(avg)
13,g
DQ low-impedance time from CK, CK#
tLZ(DQ)
-800
400
-600
300
ps
13,14,f
DQ high impedance time from CK, CK#
tHZ(DQ)
-
400
-
300
ps
13,14,f
Data setup time to DQS, DQS# referenced to
Vih(ac) / Vil(ac) levels
tDS(base)
AC175 or AC160
See table for Data Setup and Hold
ps
d,17
Data setup time to DQS, DQS# referenced to
Vih(ac) / Vil(ac) levels
tDS(base)
AC150 or AC135
ps
d,17
Data hold time from DQS, DQS# referenced
to Vih(dc) / Vil(dc) levels
tDH(base)
DC100 or DC90
ps
d,17
DQ and DM Input pulse width for each input
tDIPW
600
-
490
-
ps
28
Data Strobe Timing
DQS,DQS# differential READ Preamble
tRPRE
0.9
Note 19
0.9
Note 19
tCK(avg)
13,19,g
DQS, DQS# differential READ Postamble
tRPST
0.3
Note 11
0.3
Note 11
tCK(avg)
11,13,g
DQS, DQS# differential output high time
tQSH
0.38
-
0.38
-
tCK(avg)
13,g
DQS, DQS# differential output low time
tQSL
0.38
-
0.38
-
tCK(avg)
13,g
DQS, DQS# differential WRITE Preamble
tWPRE
0.9
-
0.9
-
tCK(avg)
DQS, DQS# differential WRITE Postamble
tWPST
0.3
-
0.3
-
tCK(avg)
DQS, DQS# rising edge output access time
from rising CK, CK#
tDQSCK
-400
400
-300
300
ps
13,f
DQS and DQS# low-impedance time
(Referenced from RL - 1)
tLZ(DQS)
-800
400
-600
300
ps
13,14,f
DQS and DQS# high-impedance time
(Referenced from RL + BL/2)
tHZ(DQS)
-
400
-
300
ps
13,14,f
DQS, DQS# differential input low pulse width
tDQSL
0.45
0.55
0.45
0.55
tCK(avg)
29,31
DQS, DQS# differential input high pulse width
tDQSH
0.45
0.55
0.45
0.55
tCK(avg)
30,31
DQS, DQS# rising edge to CK, CK# rising
edge
tDQSS
-0.25
0.25
-0.25
0.25
tCK(avg)
c
DQS, DQS# falling edge setup time to CK,
CK# rising edge
tDSS
0.2
-
0.2
-
tCK(avg)
c,32
DQS, DQS# falling edge hold time from CK,
CK# rising edge
tDSH
0.2
-
0.2
-
tCK(avg)
c,32
Command and Address Timing
DLL locking time
tDLLK
512
-
512
-
nCK
Internal READ Command to PRECHARGE
Command delay
tRTP
tRTPmin.: max(4nCK, 7.5ns)
e
tRTPmax.: -
Delay from start of internal write transaction to
internal read command
tWTR
tWTRmin.: max(4nCK, 7.5ns)
e,18
tWTRmax.:
WRITE recovery time
tWR
15
-
15
-
ns
e,18
Mode Register Set command cycle time
tMRD
4
-
4
-
nCK
Mode Register Set command update delay
tMOD
tMODmin.: max(12nCK, 15ns)
tMODmax.:
ACT to internal read or write delay time
tRCD
Standard Speed Bins
e
IS43/46TR16640ED
IS43/46TR81280ED
Integrated Silicon Solution, Inc. – www.issi.com – 56
Rev. B1
03/12/2018
Parameter
Symbol
DDR3-800
DDR3-1066
Units
Notes
Min
Max
Min
Max
PRE command period
tRP
Standard Speed Bins
e
ACT to ACT or REF command period
tRC
Standard Speed Bins
e
CAS# to CAS# command delay
tCCD
4
-
4
-
nCK
Auto precharge write recovery + precharge time
tDAL(min)
WR + roundup(tRP / tCK(avg))
nCK
Multi-Purpose Register Recovery Time
tMPRR
1
-
1
-
nCK
22
ACTIVE to PRECHARGE command period
tRAS
Standard Speed Bins
e
ACTIVE to ACTIVE command period for 1KB
page size
tRRD
max(4nCK,
10ns)
-
max(4nCK,
7.5ns)
-
e
ACTIVE to ACTIVE command period for 2KB
page size
tRRD
tRRDmin.: max(4nCK, 10ns)
e
tRRDmax.:
Four activate window for 1KB page size
tFAW
40
-
37.5
-
ns
e
Four activate window for 2KB page size
tFAW
50
-
50
-
ns
e
Command and Address setup time to CK,
CK# referenced to Vih(ac) / Vil(ac) levels
tIS(base)
AC175 or AC160
See table for ADD/CMD setup and hold
ps
b,16
Command and Address setup time to CK,
CK# referenced to Vih(ac) / Vil(ac) levels
tIS(base)
AC150 or AC135
ps
b,16,27
Command and Address hold time from CK,
CK# referenced to Vih(dc) / Vil(dc) levels
tIH(base)
DC100 or DC90
ps
b,16
Control and Address Input pulse width for
each input
tIPW
900
-
780
-
ps
28
Calibration Timing
Power-up and RESET calibration time
tZQinit
max (512
nCK, 640ns)
-
max (512
nCK, 640ns)
-
Normal operation Full calibration time
tZQoper
max (256
nCK, 320ns)
-
max (256
nCK, 320ns)
-
Normal operation Short calibration time
tZQCS
max (64
nCK, 80ns)
-
max (64
nCK, 80ns)
-
23
Reset Timing
Exit Reset from CKE HIGH to a valid
command
tXPR
tXPRmin.: max(5nCK, tRFC(min) + 10ns)
tXPRmax.: -
Self Refresh Timings
Exit Self Refresh to commands not requiring a
locked DLL
tXS
tXSmin.: max(5nCK, tRFC(min) + 10ns)
tXSmax.: -
Exit Self Refresh to commands requiring a
locked DLL
tXSDLL
tXSDLLmin.: tDLLK(min)
nCK
2
tXSDLLmax.: -
Minimum CKE low width for Self Refresh entry
to exit timing
tCKESR
tCKESRmin.: tCKE(min) + 1 nCK
tCKESRmax.: -
Valid Clock Requirement after Self Refresh
Entry (SRE) or Power-Down Entry (PDE)
tCKSRE
tCKSREmin.: max(5 nCK, 10 ns)
tCKSREmax.: -
Valid Clock Requirement before Self Refresh
Exit (SRX) or Power-Down Exit (PDX) or
Reset Exit
tCKSRX
tCKSRXmin.: max(5 nCK, 10 ns)
tCKSRXmax.: -
Power Down Timings
Exit Power Down with DLL on to any valid
command; Exit Precharge Power Down with DLL
frozen to commands not requiring a locked DLL
tXP
tXPmin.: max(3nCK, 7.5ns)
tXPmax.: -
Exit Precharge Power Down with DLL frozen
to commands requiring a locked DLL
tXPDLL
tXPDLLmin.: max(10nCK, 24ns)
tXPDLLmax.: -
CKE minimum pulse width
tCKE
tCKEmin.: max(3nCK
7.5ns)
tCKEmin.: max(3nCK
5.625ns)
tCKEmax.: -
tCKEmax.: -
Command pass disable delay
tCPDED
tCPDEDmin.: 1
nCK
tCPDEDmax.: -
IS43/46TR16640ED
IS43/46TR81280ED
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Rev. B1
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Parameter
Symbol
DDR3-800
DDR3-1066
Units
Notes
Min.
Max.
Min.
Max.
Power Down Entry to Exit Timing
tPD
tPDmin.: tCKE(min)
15
tPDmax.: 9*tREFI
Timing of ACT command to Power Down
entry
tACTPDEN
tACTPDENmin.: 1
nCK
20
tACTPDENmax.: -
Timing of PRE or PREA command to Power
Down entry
tPRPDEN
tPRPDENmin.: 1
nCK
20
tPRPDENmax.: -
Timing of RD/RDA command to Power Down
entry
tRDPDEN
tRDPDENmin.: RL+4+1
nCK
tRDPDENmax.: -
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
tWRPDEN
tWRPDENmin.: WL + 4 + (tWR / tCK(avg))
nCK
9
tWRPDENmax.: -
Timing of WRA command to Power Down
entry (BL8OTF, BL8MRS, BC4OTF)
tWRAPDEN
tWRAPDENmin.: WL+4+WR+1
nCK
10
tWRAPDENmax.: -
Timing of WR command to Power Down entry
(BC4MRS)
tWRPDEN
tWRPDENmin.: WL + 2 + (tWR / tCK(avg))
nCK
9
tWRPDENmax.: -
Timing of WRA command to Power Down
entry (BC4MRS)
tWRAPDEN
tWRAPDENmin.: WL + 2 +WR + 1
nCK
10
tWRAPDENmax.: -
Timing of REF command to Power Down
entry
tREFPDEN
tREFPDENmin.: 1
nCK
20,21
tREFPDENmax.: -
Timing of MRS command to Power Down
entry
tMRSPDEN
tMRSPDENmin.: tMOD(min)
tMRSPDENmax.: -
ODT Timings
ODT high time without write command or with
write command and BC4
ODTH4
ODTH4min.: 4
nCK
ODTH4max.: -
ODT high time with Write command and BL8
ODTH8
ODTH8min.: 6
nCK
ODTH8max.: -
Asynchronous RTT turn-on delay (Power-
Down with DLL frozen)
tAONPD
2
8.5
2
8.5
ns
Asynchronous RTT turn-off delay (Power-
Down with DLL frozen)
tAOFPD
2
8.5
2
8.5
ns
RTT turn-on
tAON
-400
400
-300
300
ps
7,f
RTT_Nom and RTT_WR turn-off time from
ODTLoff reference
tAOF
0.3
0.7
0.3
0.7
tCK(avg)
8,f
RTT dynamic change skew
tADC
0.3
0.7
0.3
0.7
tCK(avg)
f
Write Leveling Timings
First DQS/DQS# rising edge after write
leveling mode is programmed
tWLMRD
40
-
40
-
nCK
3
DQS/DQS# delay after write leveling mode is
programmed
tWLDQSEN
25
-
25
-
nCK
3
Write leveling setup time from rising CK, CK#
crossing to rising DQS, DQS# crossing
tWLS
325
-
245
-
ps
Write leveling hold time from rising DQS,
DQS# crossing to rising CK, CK# crossing
tWLH
325
-
245
-
ps
Write leveling output delay
tWLO
0
9
0
9
ns
Write leveling output error
tWLOE
0
2
0
2
ns
IS43/46TR16640ED
IS43/46TR81280ED
Integrated Silicon Solution, Inc. – www.issi.com – 58
Rev. B1
03/12/2018
9.2 Timing Parameter by Speed Bin (DDR3-1333, DDR3-1600)
Parameter
Symbol
DDR3-1333
DDR3-1600
Units
Notes
Min.
Max.
Min.
Max.
Clock Timing
Minimum Clock Cycle Time (DLL off mode)
tCK(DLL_OFF)
8
-
8
-
ns
6
Average Clock Period
tCK(avg)
Refer to Standard Speed Bins
ps
Average high pulse width
tCH(avg)
0.47
0.53
0.47
0.53
tCK(avg)
Average low pulse width
tCL(avg)
0.47
0.53
0.47
0.53
tCK(avg)
Absolute Clock Period
tCK(abs)
Min.: tCK(avg)min + tJIT(per)min
ps
Max.: tCK(avg)max + tJIT(per)max
Absolute clock HIGH pulse width
tCH(abs)
0.43
-
0.43
-
tCK(avg)
25
Absolute clock LOW pulse width
tCL(abs)
0.43
-
0.43
-
tCK(avg)
26
Clock Period Jitter
tJIT(per)
-80
80
-70
70
ps
Clock Period Jitter during DLL locking period
tJIT(per, lck)
-70
70
-60
60
ps
Cycle to Cycle Period Jitter
tJIT(cc)
160
140
ps
Cycle to Cycle Period Jitter during DLL
locking period
tJIT(cc, lck)
140
120
ps
Duty Cycle Jitter
tJIT(duty)
-
-
-
-
ps
Cumulative error across 2 cycles
tERR(2per)
-118
118
-103
103
ps
Cumulative error across 3 cycles
tERR(3per)
-140
140
-122
122
ps
Cumulative error across 4 cycles
tERR(4per)
-155
155
-136
136
ps
Cumulative error across 5 cycles
tERR(5per)
-168
168
-147
147
ps
Cumulative error across 6 cycles
tERR(6per)
-177
177
-155
155
ps
Cumulative error across 7 cycles
tERR(7per)
-186
186
-163
163
ps
Cumulative error across 8 cycles
tERR(8per)
-193
193
-169
169
ps
Cumulative error across 9 cycles
tERR(9per)
-200
200
-175
175
ps
Cumulative error across 10 cycles
tERR(10per)
-205
205
-180
180
ps
Cumulative error across 11 cycles
tERR(11per)
-210
210
-184
184
ps
Cumulative error across 12 cycles
tERR(12per)
-215
215
-188
188
ps
Cumulative error across n = 13, 14 . . . 49, 50
cycles
tERR(nper)
tERR(nper)min = (1 + 0.68ln(n)) * tJIT(per)min
ps
24
tERR(nper)max = (1 + 0.68ln(n)) *
tJIT(per)max
Data Timing
DQS, DQS# to DQ skew, per group, per
access
tDQSQ
-
125
-
100
ps
13
DQ output hold time from DQS, DQS#
tQH
0.38
-
0.38
-
tCK(avg)
13,g
DQ low-impedance time from CK, CK#
tLZ(DQ)
-500
250
-450
225
ps
13,14,f
DQ high impedance time from CK, CK#
tHZ(DQ)
-
250
-
225
ps
13,14,f
Data setup time to DQS, DQS# referenced to
Vih(ac) / Vil(ac) levels
tDS(base)
AC150
See table for Data Setup and Hold
ps
d,17
Data setup time to DQS, DQS# referenced to
Vih(ac) / Vil(ac) levels
tDS(base)
AC135
ps
d,17
Data hold time from DQS, DQS# referenced
to Vih(dc) / Vil(dc) levels
tDH(base)
DC100 or
DC90
ps
d,17
DQ and DM Input pulse width for each input
tDIPW
400
-
360
-
ps
28
Data Strobe Timing
DQS,DQS# differential READ Preamble
tRPRE
0.9
Note 19
0.9
Note
19
tCK(avg)
13,19,g
DQS, DQS# differential READ Postamble
tRPST
0.3
Note 11
0.3
Note
11
tCK(avg)
11,13,g
DQS, DQS# differential output high time
tQSH
0.4
-
0.4
-
tCK(avg)
13,g
DQS, DQS# differential output low time
tQSL
0.4
-
0.4
-
tCK(avg)
13,g
DQS, DQS# differential WRITE Preamble
tWPRE
0.9
-
0.9
-
tCK(avg)
DQS, DQS# differential WRITE Postamble
tWPST
0.3
-
0.3
-
tCK(avg)
IS43/46TR16640ED
IS43/46TR81280ED
Integrated Silicon Solution, Inc. – www.issi.com – 59
Rev. B1
03/12/2018
Parameter
Symbol
DDR3-1333
DDR3-1600
Units
Notes
Min.
Max.
Min.
Max.
DQS, DQS# rising edge output access time
from rising CK, CK#
tDQSCK
-255
255
-225
225
ps
13,f
DQS and DQS# low-impedance time
(Referenced from RL - 1)
tLZ(DQS)
-500
250
-450
225
ps
13,14,f
DQS and DQS# high-impedance time
(Referenced from RL + BL/2)
tHZ(DQS)
-
250
-
225
ps
13,14,f
DQS, DQS# differential input low pulse width
tDQSL
0.45
0.55
0.45
0.55
tCK(avg)
29,31
DQS, DQS# differential input high pulse width
tDQSH
0.45
0.55
0.45
0.55
tCK(avg)
30,31
DQS, DQS# rising edge to CK, CK# rising edge
tDQSS
-0.25
0.25
-0.27
0.27
tCK(avg)
c
DQS, DQS# falling edge setup time to CK,
CK# rising edge
tDSS
0.2
-
0.18
-
tCK(avg)
c,32
DQS, DQS# falling edge hold time from CK,
CK# rising edge
tDSH
0.2
-
0.18
-
tCK(avg)
c,32
Command and Address Timing
DLL locking time
tDLLK
512
-
512
-
nCK
Internal READ Command to PRECHARGE
Command delay
tRTP
tRTPmin.: max(4nCK, 7.5ns)
tRTPmax.: -
Delay from start of internal write transaction to
internal read command
tWTR
tWTRmin.: max(4nCK, 7.5ns)
tWTRmax.:
WRITE recovery time
tWR
15
-
15
-
ns
e,18
Mode Register Set command cycle time
tMRD
4
-
4
-
nCK
Mode Register Set command update delay
tMOD
tMODmin.: max(12nCK, 15ns)
tMODmax.:
ACT to internal read or write delay time
tRCD
Standard Speed Bins
PRE command period
tRP
Standard Speed Bins
ACT to ACT or REF command period
tRC
Standard Speed Bins
CAS# to CAS# command delay
tCCD
4
-
4
-
nCK
Auto precharge write recovery + precharge time
tDAL(min)
WR + roundup(tRP / tCK(avg))
nCK
Multi-Purpose Register Recovery Time
tMPRR
1
-
1
-
nCK
22
ACTIVE to PRECHARGE command period
tRAS
Standard Speed Bins
Parameter
Symbol
DDR3-1333
DDR3-1600
Units
Notes
Min.
Max.
Min.
Max.
ACTIVE to ACTIVE command period for 1KB
page size
tRRD
max(4nCK,
6ns)
-
max(4nCK,
6ns)
-
e
ACTIVE to ACTIVE command period for 2KB
page size
tRRD
tRRDmin.: max(4nCK, 7.5ns)
tRRDmax.:
Four activate window for 1KB page size
tFAW
30
-
30
-
ns
e
Four activate window for 2KB page size
tFAW
45
-
40
-
ns
e
Command and Address setup time to CK,
CK# referenced to Vih(ac) / Vil(ac) levels
tIS(base)
AC175 or AC160
See table for ADD/CMD Setup and Hold
ps
b,16
Command and Address setup time to CK,
CK# referenced to Vih(ac) / Vil(ac) levels
tIS(base)
AC150 or AC135
ps
b,16,27
Command and Address hold time from CK,
CK# referenced to Vih(dc) / Vil(dc) levels
tIH(base)
DC100 or DC90
ps
b,16
Control and Address Input pulse width for
each input
tIPW
620
-
560
-
ps
28
Calibration Timing
Power-up and RESET calibration time
tZQinit
max (512
nCK, 640ns)
-
max (512
nCK, 640ns)
-
Normal operation Full calibration time
tZQoper
max (256
nCK, 320ns)
-
max (256
nCK, 320ns)
-
Normal operation Short calibration time
tZQCS
max (64
nCK, 80ns)
-
max (64
nCK, 80ns)
-
23
IS43/46TR16640ED
IS43/46TR81280ED
Integrated Silicon Solution, Inc. – www.issi.com – 60
Rev. B1
03/12/2018
Parameter
Symbol
DDR3-1333
DDR3-1600
Units
Notes
Min.
Max.
Min.
Max.
Reset Timing
Exit Reset from CKE HIGH to a valid
command
tXPR
tXPRmin.: max(5nCK, tRFC(min) + 10ns)
tXPRmax.: -
Self Refresh Timings
Exit Self Refresh to commands not requiring a
locked DLL
tXS
tXSmin.: max(5nCK, tRFC(min) + 10ns)
tXSmax.: -
Exit Self Refresh to commands requiring a
locked DLL
tXSDLL
tXSDLLmin.: tDLLK(min)
nCK
2
tXSDLLmax.: -
Minimum CKE low width for Self Refresh entry
to exit timing
tCKESR
tCKESRmin.: tCKE(min) + 1 nCK
tCKESRmax.: -
Valid Clock Requirement after Self Refresh
Entry (SRE) or Power-Down Entry (PDE)
tCKSRE
tCKSREmin.: max(5 nCK, 10 ns)
tCKSREmax.: -
Valid Clock Requirement before Self Refresh
Exit (SRX) or Power-Down Exit (PDX) or
Reset Exit
tCKSRX
tCKSRXmin.: max(5 nCK, 10 ns)
tCKSRXmax.: -
Power Down Timings
Exit Power Down with DLL on to any valid
command; Exit Precharge Power Down with
DLL frozen to commands not requiring a
locked DLL
tXP
tXPmin.: max(3nCK, 6ns)
tXPmax.: -
Exit Precharge Power Down with DLL frozen
to commands requiring a locked DLL
tXPDLL
tXPDLLmin.: max(10nCK, 24ns)
tXPDLLmax.: -
CKE minimum pulse width
tCKE
tCKEmin.: max(3nCK
5.625ns)
tCKEmin.: max(3nCK
5ns)
tCKEmax.: -
tCKEmax.: -
Command pass disable delay
tCPDED
tCPDEDmin.: 1
nCK
tCPDEDmax.: -
Power Down Entry to Exit Timing
tPD
tPDmin.: tCKE(min)
15
tPDmax.: 9*tREFI
Timing of ACT command to Power Down
entry
tACTPDEN
tACTPDENmin.: 1
nCK
20
tACTPDENmax.: -
Timing of PRE or PREA command to Power
Down entry
tPRPDEN
tPRPDENmin.: 1
nCK
20
tPRPDENmax.: -
Timing of RD/RDA command to Power Down
entry
tRDPDEN
tRDPDENmin.: RL+4+1
nCK
tRDPDENmax.: -
Parameter
Symbol
DDR3 -1333
DDR3-1600
Units
Notes
Min.
Max.
Min.
Max.
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
tWRPDEN
tWRPDENmin.: WL + 4 + (tWR / tCK(avg))
nCK
9
tWRPDENmax.: -
Timing of WRA command to Power Down
entry (BL8OTF, BL8MRS, BC4OTF)
tWRAPDEN
tWRAPDENmin.: WL+4+WR+1
nCK
10
tWRAPDENmax.: -
Timing of WR command to Power Down entry
(BC4MRS)
tWRPDEN
tWRPDENmin.: WL + 2 + (tWR / tCK(avg))
tWRPDENmax.: -
nCK
9
Timing of WRA command to Power Down
entry (BC4MRS)
tWRAPDEN
tWRAPDENmin.: WL + 2 +WR + 1
nCK
10
tWRAPDENmax.: -
Timing of REF command to Power Down
entry
tREFPDEN
tREFPDENmin.: 1
nCK
20,21
tREFPDENmax.: -
Timing of MRS command to Power Down
entry
tMRSPDEN
tMRSPDENmin.: tMOD(min)
tMRSPDENmax.: -
ODT Timings
ODT high time without write command or with
write command and BC4
ODTH4
ODTH4min.: 4
nCK
ODTH4max.: -
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Parameter
Symbol
DDR3-1333
DDR3-1600
Units
Notes
Min.
Max.
Min.
Max.
ODT high time with Write command and BL8
ODTH8
ODTH8min.: 6
nCK
ODTH8max.: -
Asynchronous RTT turn-on delay (Power-
Down with DLL frozen)
tAONPD
2
8.5
2
8.5
ns
Asynchronous RTT turn-off delay (Power-
Down with DLL frozen)
tAOFPD
2
8.5
2
8.5
ns
RTT turn-on
tAON
-250
250
-225
225
ps
7,f
RTT_Nom and RTT_WR turn-off time from
ODTLoff reference
tAOF
0.3
0.7
0.3
0.7
tCK(avg)
8,f
RTT dynamic change skew
tADC
0.3
0.7
0.3
0.7
tCK(avg)
f
Write Leveling Timings
First DQS/DQS# rising edge after write
leveling mode is programmed
tWLMRD
40
-
40
-
nCK
3
DQS/DQS# delay after write leveling mode is
programmed
tWLDQSEN
25
-
25
-
nCK
3
Write leveling setup time from rising CK, CK#
crossing to rising DQS, DQS# crossing
tWLS
195
-
165
-
ps
Write leveling hold time from rising DQS,
DQS# crossing to rising CK, CK# crossing
tWLH
195
-
165
-
ps
Write leveling output delay
tWLO
0
9
0
7.5
ns
Write leveling output error
tWLOE
0
2
0
2
ns
9.3 Intentionally omitted.
9.4 Timing Notes
9.4.1 Jitter
Specific Note a
Unit “tCK(avg)” represents the actual tCK(avg) of the input clock under operation. Unit “nCK” represents one clock cycle of
the input clock, counting the actual clock edges. ex) tMRD=4 [nCK] means; if one Mode Register Set command is
registered at Tm, another Mode Register Set command may be registered at Tm+4, even if (Tm+4-Tm) is 4 x tCK(avg) +
tERR(4per), min.
Specific Note b
These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc)
transition edge to its respective clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock
jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the
command/address. That is, these parameters should be met whether clock jitter is present or not.
Specific Note c
These parameters are measured from a data strobe signal (DQS(L/U), DQS(L/U)) crossing to its respective clock signal
(CK, CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc), as
these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or
not.
Specific Note d
These parameters are measured from a data signal (DM(L/U), DQ(L/U)0, DQ(L/U)1, etc.) transition edge to its respective
data strobe signal (DQS(L/U), DQS(L/U)) crossing.
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Specific Note e
For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] = RU{tPARAM[ns] / tCK(avg)[ns]}, which is in
clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP
=RU{tRP/tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR3-800 6-6-
6, of which tRP = 15ns, the device will support tnRP = RU{tRP/tCK(avg)} = 6, as long as the input clock jitter specifications
are met, i.e. Precharge command at Tm and Active command at Tm+6 is valid even if (Tm+6-Tm) is less than 15ns due to
input clock jitter.
Specific Note f
When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper), act of
the input clock, where 2 <= m <=12. (output derating are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = -172ps and tERR(mper),act,max
= 193ps, then tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = -400ps - 193ps = -593ps and
tDQSCK,max(derated) = tDQSCK,max - ERR(mper),act,min = 400ps + 172ps = 572ps. Similarly, tLZ(DQ) for DDR3-800
derates to tLZ(DQ),min(derated) = -800ps - 193ps = -993ps and tLZ(DQ),max(derated) = 400ps + 172ps = 572ps.
(Caution on the min/max usage!)
Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 <= n <= 12, and
tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 <= n <= 12.
Specific Note g
When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the
input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800
SDRAM has tCK(avg),act=2500ps, tJIT(per),act,min = -72ps and tJIT(per),act,max = 93ps, then tRPRE,min(derated) =
tRPRE,min + tJIT(per),act,min = 0.9 x tCK(avg),act + tJIT(per),act,min = 0.9 x 2500ps - 72ps = 2178ps. Similarly,
tQH,min(derated) = tQH,min + tJIT(per),act,min = 0.38 x tCK(avg),act + tJIT(per),act,min = 0.38 x 2500ps - 72ps = 878ps.
(Caution on the min/max usage!)
9.4.2 Timing Parameters
1. Actual value dependent upon measurement level definitions.
2. Commands requiring a locked DLL are: READ ( and RAP) are synchronous ODT commands.
3. The max values are system dependent.
4. WR as programmed in mode register.
5. Value must be rouned-up to next higher integer value.
6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.
7. For definition of RTT-on time tAON See “Timing Parameters”.
8. For definition of RTT-off time tAOF See “Timing Parameters”.
9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.
10. WR in clock cycles are programmed in MR0.
11. The maximum read postamble is bonded by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the
right side.
12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this
parameter needs to be derated by TBD.
13. Value is only valid for RON34.
14. Single ended signal parameter.
15. tREFI depends on TOPER.
16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew
rate. Note for DQ and DM signals, VREF(DC)=VRefDQ(DC). For input only pins except RESET,
VRef(DC)=VRefCA(DC).
17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate.
Note for DQ and DM signals, VREF(DC)=VRefDQ(DC). For input only pins except RESET, VRef(DC)=VRefCA(DC).
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18. Start of internal write transaction is defined as follows:
a. For BL8 (fixed by MRS and on-the-fly): Rising clock edge 4 clock cycles after WL.
b. For BC4 (on-the-fly): Rising clock edge 4 clock cycles after WL.
c. For BC4 (fixed by MRS): Rising clock edge 2 clock cycles after WL.
19. The maximum preamble is bound by tLZ(DQS)max on the left side and tDQSCK(max) on the right side.
20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are
in progress, but power-down IDD spec will not be applied until finishing those operations.
21. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there
are cases where additional time such as tXPDLL(min) is also required.
22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.
23. One ZQCS command can effectively correct a minimum of 0.5% (ZQCorrection) of RON and RTT impedance error
within 64 nCK for all speed bins assuming the maximum sensitivities specified in the “Output Driver Voltage and
Temperature Sensitivity” and “ODT Voltage and Temperature Sensitivity” tables. The appropriate interval between
ZQCS commands can be determined from these tables and other application-specific parameters.
24. One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage
(Vdriftrate) drift rates that the SDRAM is subject to in the application, is illustrated. the interval could be defined by the
following formula:
ZQCorrection / [(TSens x Tdriftrate) + (VSens x Vdriftrate)]
, where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and
voltage sensitivities.
For example, if TSens = 1.5%/C, VSens = 0.15%/mV, Tdriftrate = 1 C/sec and Vdriftrate = 15mV/sec, then the interval
between ZQCS commands is calculated as
0.5 / [(1.5x1)+(0.15x15)] = 0.133 128ms
25. n = from 13 cycles to 50 cycles. This row defines 38 parameters.
26. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following
falling edge.
27. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following
rising edge.
28. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100ps of
derating to accommodate for the lower altemate threshold of 150mV and another 25ps to account for the earlier
reference point [(175mV - 150mV) / 1V/ns].
29. Pulse width of a input signal is defined as the width between the first crossing of Vref(dc) and the consecutive
crossing of Vref(dc).
30. tDQSL describes the instantaneous differential input low pulse width on DQS - DQS#, as measured from one falling
edge to the next consecutive rising edge.
31. tDQSH describes the instantaneous differential input high pulse width on DQS - DQS#, as measured from one rising
edge to the next consecutive falling edge.
32. tDQSH,act + tDQSL,act = 1 tCK,act ; with tXYZ,act being the actual measured value of the respective timing
parameter in the application.
33. tDSH,act + tDSS,act = 1 tCK,act ; with tXYZ,act being the actual measured value of the respective timing parameter
in the application
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9.5 Address / Command Setup, Hold and Derating
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the datasheet tIS(base)
and tIH(base) value to the tIS and tIH derating value, respectively. Example: tIS (total setup time) = tIS(base) + tIS
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the
first crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last
crossing of VREF(dc) and the first crossing of Vil(ac)max. If the actual signal is always earlier than the nominal slew rate
line between shaded ‘VREF(dc) to ac region’, use nominal slew rate for derating value . If the actual signal is later than
the nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line to the actual
signal from the ac level to VREF (dc) level is used for derating value.
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vil(dc)max and the
first crossing of VREF(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last
crossing of Vih(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate
line between shaded ‘dc to VREF(dc) region’, use nominal slew rate for derating value. If the actual signal is earlier than
the nominal slew rate line anywhere between shaded ‘dc to VREF(dc) region’, the slew rate of a tangent line to the actual
signal from the dc level to VREF (dc) level is used for derating value.
For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC. Although for slow slew
rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the
rising clock transition, a valid input signal is still required to complete the transition and reach VIH/IL(ac). For slew rates in
between the values listed in the tables, the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
9.5.1 ADD/CMD Setup and Hold Base-Values for 1V/ns
DDR3/
DDR3L
Symbol
Reference
DDR3-
800
DDR3-
1066
DDR3-
1333
DDR3-
1600
DDR3-
1866
DDR3-
2133
Units
DDR3
tIS(base) AC175
VIH/L(ac)
200
125
65
45
-
-
ps
tIS(base) AC150
VIH/L(ac)
350
275
190
170
-
-
ps
tIS(base) AC135
VIH/L(ac)
-
-
-
-
65
60
ps
tIS(base) AC125
VIH/L(ac)
-
-
-
-
150
135
ps
tIH(base) DC100
VIH/L(dc)
275
200
140
120
100
95
ps
Note:
(AC/DC referenced for 1V/ns Address/Command slew rate and 2 V/ns differential CK-CK# slew rate)
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9.5.5 Derating values [ps] for DDR3-800/1066/1333/1600 tIS/tIH - AC/DC based AC175 Threshold
AC175 Threshold -> VIH(ac) = VREF(dc) + 175mV, VIL(ac) = VREF(dc) - 175mV
DDR3
CK, CK# Differential Slew Rate
4.0V/ns
3.0V/ns
2.0V/ns
1.8V/ns
1.6V/ns
1.4V/ns
1.2V/ns
1.0V/ns
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
CMD/ADD
Slew Rate
V/ns
2
88
50
88
50
88
50
96
58
104
66
112
74
120
84
128
100
1.5
59
34
59
34
59
34
67
42
75
50
83
58
91
68
99
84
1
0
0
0
0
0
0
8
8
16
16
24
24
32
34
40
50
0.9
-2
-4
-2
-4
-2
-4
6
4
14
12
22
20
30
30
38
46
0.8
-6
-10
-6
-10
-6
-10
2
-2
10
6
18
14
26
24
34
40
0.7
-11
-16
-11
-16
-11
-16
-3
-8
5
0
13
8
21
18
29
34
0.6
-17
-26
-17
-26
-17
-26
-9
-18
-1
-10
7
-2
15
8
23
24
0.5
-35
-40
-35
-40
-35
-40
-27
-32
-19
-24
-11
-16
-2
-6
5
10
0.4
-62
-60
-62
-60
-62
-60
-54
-52
-46
-44
-38
-36
-30
-26
-22
-10
9.5.6 Derating values [ps] for DDR3-800/1066/1333/1600 tIS/tIH - AC/DC based AC150 Threshold
AC150 Threshold -> VIH(ac) = VREF(dc) + 150mV, VIL(ac) = VREF(dc) - 150mV
DDR3
CK, CK# Differential Slew Rate
4.0V/ns
3.0V/ns
2.0V/ns
1.8V/ns
1.6V/ns
1.4V/ns
1.2V/ns
1.0V/ns
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
CMD/ADD
Slew Rate
V/ns
2
75
50
75
50
75
50
83
58
91
66
99
74
107
84
115
100
1.5
50
34
50
34
50
34
58
42
66
50
74
58
82
68
90
84
1
0
0
0
0
0
0
8
8
16
16
24
24
32
34
40
50
0.9
0
-4
0
-4
0
-4
8
4
16
12
24
20
32
30
40
46
0.8
0
-10
0
-10
0
-10
8
-2
16
6
24
14
32
24
40
40
0.7
0
-16
0
-16
0
-16
8
-8
16
0
24
8
32
18
40
34
0.6
-1
-26
-1
-26
-1
-26
7
-18
15
-10
23
-2
31
8
39
24
0.5
-10
-40
-10
-40
-10
-40
-2
-32
6
-24
14
-16
22
-6
30
10
0.4
-25
-60
-25
-60
-25
-60
-17
-52
-9
-44
-1
-36
7
-26
15
-10
9.5.7 Derating values [ps] for DDR3-1866/2133 tIS/tIH - AC/DC based AC135 Threshold
AC135 Threshold -> VIH(ac) = VREF(dc) + 135mV, VIL(ac) = VREF(dc) - 135mV
DDR3
CK, CK# Differential Slew Rate
4.0V/ns
3.0V/ns
2.0V/ns
1.8V/ns
1.6V/ns
1.4V/ns
1.2V/ns
1.0V/ns
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
CMD/ADD
Slew Rate
V/ns
2
68
50
68
50
68
50
76
58
84
66
92
74
100
84
108
100
1.5
45
34
45
34
45
34
53
42
61
50
69
58
77
68
85
84
1
0
0
0
0
0
0
8
8
16
16
24
24
32
34
40
50
0.9
2
-4
2
-4
2
-4
10
4
18
12
26
20
34
30
42
46
0.8
3
-10
3
-10
3
-10
11
-2
19
6
27
14
35
24
43
40
0.7
6
-16
6
-16
6
-16
14
-8
22
0
30
8
38
18
46
34
0.6
9
-26
9
-26
9
-26
17
-18
25
-10
33
-2
41
8
49
24
0.5
5
-40
5
-40
5
-40
13
-32
21
-24
29
-16
37
-6
45
10
0.4
-3
-60
-3
-60
-3
-60
6
-52
14
-44
22
-36
30
-26
38
-10
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9.5.8 Derating values [ps] for DDR3-1866/2133 tIS/tIH - AC/DC based AC125 Threshold
AC125 Threshold -> VIH(ac) = VREF(dc) + 125mV, VIL(ac) = VREF(dc) - 125mV
DDR3
CK, CK# Differential Slew Rate
4.0V/ns
3.0V/ns
2.0V/ns
1.8V/ns
1.6V/ns
1.4V/ns
1.2V/ns
1.0V/ns
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
CMD/ADD
Slew Rate
V/ns
2
63
50
63
50
63
50
71
58
79
66
87
74
95
84
103
100
1.5
42
34
42
34
42
34
50
42
58
50
66
58
74
68
82
84
1
0
0
0
0
0
0
8
8
16
16
24
24
32
34
40
50
0.9
4
-4
4
-4
4
-4
12
4
20
12
28
20
36
30
44
46
0.8
6
-10
6
-10
6
-10
14
-2
22
6
30
14
38
24
46
40
0.7
11
-16
11
-16
11
-16
19
-8
27
0
35
8
43
18
51
34
0.6
16
-26
16
-26
16
-26
24
-18
32
-10
40
-2
48
8
56
24
0.5
15
-40
15
-40
15
-40
23
-32
31
-24
39
-16
47
-6
55
10
0.4
13
-60
13
-60
13
-60
21
-52
29
-44
37
-36
45
-26
53
-10
9.5.9 Required minimum time tVAC above VIH(ac) {below VIL(ac)} for valid ADD/CMD transition
Slew
Rate
[V/ns]
DDR3
DDR3L
800/1066/1333/1600
1866/2133
800/1066/1333/1600
1866
175mV
[ps]
150mV
[ps]
135mV
[ps]
125mV
[ps]
160mV
[ps]
135mV
[ps]
135mV
[ps]
125mV
[ps]
> 2.0
75
175
168
173
200
213
200
205
2
57
170
168
173
200
213
200
205
1.5
50
167
145
152
173
190
178
184
1
38
130
100
110
120
145
133
143
0.9
34
113
85
96
102
130
118
129
0.8
29
93
66
79
80
111
99
111
0.7
22
66
42
56
51
87
75
89
0.6
Note
30
10
27
13
55
43
59
0.5
Note
Note
Note
Note
Note
10
Note
18
< 0.5
Note
Note
Note
Note
Note
10
Note
18
Note:
The rising input signal shall become equal to or greater than VIH(ac) level; and the falling input signal shall become equal to or less than VIL(ac) level.
IS43/46TR16640ED
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9.5.10 Address / Command Setup, Hold and Derating
9.5.10.1 Nominal slew rate and tVAC for setup time tIS(left) and hold time t IH(right) – ADD/CMD with respect to clock
9.5.10.2 Tangent line for setup time tIS(left) and hold time tIH(right) - ADD/CMD with respect to clock
CK#
CK#
VREF to AC region
CK
VDDQ
VIH(ac)MIN
VIH(dc)MIN
VREF(dc)
VIL(dc)MAX
VIL(ac)MAX
Nominal
slew rate
Nominal
slew rate
tIS
tIH
tVAC
tVAC
tIS
tIH
VSS
TF
TR
Setup slew Rate @
Falling signal
=
[VREF(dc)-VIL(ac)max]
/ ΔTF
Setup slew Rate @ Rising
signal
=
[VIH(ac)min-VREF(dc)]
/ ΔTR
CK
VDDQ
VIH(ac)MIN
VIH(dc)MIN
VREF(dc)
VIL(dc)MAX
VIL(ac)MAX
Nominal
slew rate
Nominal
slew rate
tIS
tIH
tVAC
tIS
tIH
VSS
TR
TF
Hold slew Rate @
Rising signal
=
[VREF(dc)-VIL(dc)max]
/ ΔTR
Hold slew Rate @
Falling signal
=
[VIH(dc)min-VREF(dc)]
/ ΔTF
CK#
CK
VDDQ
VIH(ac)MIN
VIH(dc)MIN
VREF(dc)
VIL(dc)MAX
VIL(ac)MAX
Nominal
slew rate
Nominal
slew rate
tIS
tIH
tVAC
tVAC
tIS
tIH
VSS
TF
TR
Setup slew Rate @
Rising signal
= tangent line
[VIH(ac)min-VREF(dc)]
/ ΔTR
Setup slew Rate @
Falling signal
= tangent line
[VREF(dc)-VIL(ac)max]
/ ΔTF
tangent
line
tangent
line
CK#
CK
VDDQ
VIH(ac)MIN
VIH(dc)MIN
VREF(dc)
VIL(dc)MAX
VIL(ac)MAX
Nominal
slew rate
Nominal
slew rate
tIS
tIH
tIS
tIH
VSS
TR
Hold slew Rate @
Falling signal
= tangent line
[VIH(dc)min-VREF(dc)]
/ ΔTF
Hold slew Rate @
Rising signal
= tangent line
[VREF(dc)-VIL(dc)max]
/ ΔTR
tangent
line
tangent
line
TF
VREF to AC region
VREF to DC
region
VREF to DC region
IS43/46TR16640ED
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9.6 Data Setup, Hold and Slew Rate Derating
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet
tDS(base) and tDH(base) value (see corresponding tables) to the tDS and tDH (see corresponding tables) derating
value respectively. Example: tDS (total setup time) = tDS(base) + tDS.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the
first crossing of V IH(ac) min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last
crossing of VREF(dc) and the first crossing of VIL(ac) max. If the actual signal is always earlier than the nominal slew rate
line between shaded ‘VREF(dc) to ac region’, use nominal slew rate for derating value. If the actual signal is later than the
nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line to the actual
signal from the ac level to VREF(dc) level is used for derating value.
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc) max and
the first crossing of VREF(dc) . Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the
last crossing of VIH(dc) min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew
rate line between shaded ‘dc level to VREF(dc) region’, use nominal slew rate for derating value. If the actual signal is
earlier than the nominal slew rate line anywhere between shaded ‘dc to V REF(dc) region’, the slew rate of a tangent line
to the actual signal from the dc level to VREF(dc) level is used for derating value.
For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC.
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached
VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach
VIH/IL(ac) .
For slew rates in between the values listed in the tables, the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
9.6.1 Data Setup and Hold Base-Values
Symbol
Reference
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
DDR3-1866
DDR3-2133
Units
DDR3
tDS(base) AC175
VIH/L(ac),
SR= 1V/ns
75
25
-
-
-
-
ps
tDS(base) AC150
VIH/L(ac),
SR= 1V/ns
125
75
30
10
-
-
ps
tDS(base) AC135
VIH/L(ac),
SR= 1V/ns
165
115
60
40
-
-
ps
tDS(base) AC135
VIH/L(ac),
SR= 2V/ns
-
-
-
-
68
53
ps
tDH(base) DC100
VIH/L(dc),
SR= 1V/ns
150
100
65
45
-
-
ps
tDH(base) DC100
VIH/L(dc),
SR= 2V/ns
-
-
-
-
70
55
ps
NOTE: (Note: AC/DC referenced for 2V/ns DQ-slew rate and 4V/ns DQS slew rate, or 1V/ns DQ-slew rate and 2V/ns DQS slew rate, as shown.
IS43/46TR16640ED
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Rev. B1
03/12/2018
9.6.5 Derating values [ps] for DDR3-800/1066 tDS/tDH - AC/DC based AC175 Threshold
AC175 Threshold -> VIH(ac) = VREF(dc) + 175mV, VIL(ac) = VREF(dc) - 175mV
DDR3
DQS, DQS# Differential Slew Rate
4.0V/ns
3.0V/ns
2.0V/ns
1.8V/ns
1.6V/ns
1.4V/ns
1.2V/ns
1.0V/ns
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
DQ Slew
Rate
V/ns
2
88
50
88
50
88
50
-
-
-
-
-
-
-
-
-
-
1.5
59
34
59
34
59
34
67
42
-
-
-
-
-
-
-
-
1
0
0
0
0
0
0
8
8
16
16
-
-
-
-
-
-
0.9
-
-
-2
-4
-2
-4
6
4
14
12
22
20
-
-
-
-
0.8
-
-
-
-
-6
-10
2
-2
10
6
18
14
26
24
-
-
0.7
-
-
-
-
-
-
-3
-8
5
0
13
8
21
18
29
34
0.6
-
-
-
-
-
-
-
-
-1
-10
7
-2
15
8
23
24
0.5
-
-
-
-
-
-
-
-
-
-
-11
-16
-2
-6
5
10
0.4
-
-
-
-
-
-
-
-
-
-
-
-
-30
-26
-22
-10
9.6.6 Derating values [ps] for DDR3-800/1066/1333/1600 tDS/tDH - AC/DC based AC150 Threshold
AC150 Threshold -> VIH(ac) = VREF(dc) + 150mV, VIL(ac) = VREF(dc) - 150mV
DDR3
DQS, DQS# Differential Slew Rate
4.0V/ns
3.0V/ns
2.0V/ns
1.8V/ns
1.6V/ns
1.4V/ns
1.2V/ns
1.0V/ns
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
DQ Slew
Rate
V/ns
2
75
50
75
50
75
50
-
-
-
-
-
-
-
-
-
-
1.5
50
34
50
34
50
34
58
42
-
-
-
-
-
-
-
-
1
0
0
0
0
0
0
8
8
16
16
-
-
-
-
-
-
0.9
-
-
0
-4
0
-4
8
4
16
12
24
20
-
-
-
-
0.8
-
-
-
-
0
-10
8
-2
16
6
24
14
32
24
-
-
0.7
-
-
-
-
-
-
8
-8
16
0
24
8
32
18
40
34
0.6
-
-
-
-
-
-
-
-
15
-10
23
-2
31
8
39
24
0.5
-
-
-
-
-
-
-
-
-
-
14
-16
22
-6
30
10
0.4
-
-
-
-
-
-
-
-
-
-
-
-
7
-26
15
-10
9.6.7 Derating values [ps] for DDR3-1866/2133 tDS/tDH - AC/DC based AC135 Threshold
AC135 Threshold -> VIH(ac) = VREF(dc) + 135mV, VIL(ac) = VREF(dc) - 135mV
DC100 Threshold -> VIH(dc) = VREF(dc) + 100mV, VIL(dc) = VREF(dc) - 100mV
DDR3
DQS, DQS# Differential Slew Rate
8.0V/ns
7.0V/ns
6.0V/ns
5.0V/ns
4.0V/ns
3.0V/ns
2.0V/ns
1.8V/ns
1.6V/ns
1.4V/ns
1.2V/ns
1.0V/ns
ΔtD
S
ΔtD
H
ΔtD
S
ΔtD
H
ΔtD
S
ΔtD
H
ΔtD
S
ΔtD
H
ΔtD
S
ΔtD
H
ΔtD
S
ΔtD
H
ΔtD
S
ΔtD
H
ΔtD
S
ΔtD
H
ΔtD
S
ΔtD
H
ΔtD
S
ΔtD
H
ΔtD
S
ΔtD
H
ΔtD
S
ΔtD
H
DQ
Slew
Rate
V/ns
4
34
25
34
25
34
25
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3.5
29
21
29
21
29
21
29
21
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
23
17
23
17
23
17
23
17
23
17
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.5
-
-
14
10
14
10
14
10
14
10
14
10
-
-
-
-
-
-
-
-
-
-
-
-
2
-
-
-
-
0
0
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
-
-
1.5
-
-
-
-
-
-
-23
-17
-23
-17
-23
-17
-23
-17
-15
-9
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
-68
-50
-68
-50
-68
-50
-60
-42
-52
-34
-
-
-
-
-
-
0.9
-
-
-
-
-
-
-
-
-
-
-66
-54
-66
-54
-58
-46
-50
-38
-42
-30
-
-
-
-
0.8
-
-
-
-
-
-
-
-
-
-
-
-
-64
-60
-56
-52
-48
-44
-40
-36
-32
-26
-
-
0.7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-53
-59
-45
-51
-37
-43
-29
-33
-21
-17
0.6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-43
-61
-35
-53
-27
-43
-19
-27
0.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-39
-66
-31
-56
-23
-40
0.4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-36
-76
-30
-60
IS43/46TR16640ED
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Rev. B1
03/12/2018
9.6.8 Derating values [ps] for DDR3-800/1066/1333/1600 tDS/tDH - AC/DC based AC135 Threshold
AC135 Threshold -> VIH(ac) = VREF(dc) + 135mV, VIL(ac) = VREF(dc) - 135mV
DC100 Threshold -> VIH(dc) = VREF(dc) + 100mV, VIL(dc) = VREF(dc) - 100mV
DDR3
DQS, DQS# Differential Slew Rate
4.0V/ns
3.0V/ns
2.0V/ns
1.8V/ns
1.6V/ns
1.4V/ns
1.2V/ns
1.0V/ns
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
DQ Slew
Rate
V/ns
2
68
50
68
50
68
50
-
-
-
-
-
-
-
-
-
-
1.5
45
34
45
34
45
34
53
42
-
-
-
-
-
-
-
-
1
0
0
0
0
0
0
8
8
16
16
-
-
-
-
-
-
0.9
-
-
2
-4
2
-4
10
4
18
12
26
20
-
-
-
-
0.8
-
-
-
-
3
-10
11
-2
19
6
27
14
35
24
-
-
0.7
-
-
-
-
-
-
14
-8
22
0
30
8
38
18
46
34
0.6
-
-
-
-
-
-
-
-
25
-10
33
-2
41
8
49
24
0.5
-
-
-
-
-
-
-
-
-
-
29
-16
37
-6
45
10
0.4
-
-
-
-
-
-
-
-
-
-
-
-
30
-26
38
-10
9.6.9 Required minimum time tVAC [ps] above VIH(ac) {below VIL(ac)} for valid DQ transition
Slew
Rate
[V/ns]
DDR3
DDR3L
800/1066
800/1066/1333/1600
800/1066/1333/1600
1866
2133
800/1066
800/1066/1333/1600
1866
AC175
AC150
AC135
AC160
AC135
AC130
> 2.0
75
105
113
93
73
165
113
95
2
57
105
113
93
73
165
113
95
1.5
50
80
90
70
50
138
90
73
1
38
30
45
25
5
85
45
30
0.9
34
13
30
Note
Note
67
30
16
0.8
29
Note
11
Note
Note
45
11
Note
0.7
Note
Note
Note
-
-
16
Note
-
0.6
Note
Note
Note
-
-
Note
Note
-
0.5
Note
Note
Note
-
2
Note
Note
-
< 0.5
Note
Note
Note
-
-
Note
Note
-
Note:
The rising input signal shall become equal to or greater than VIH(ac) level; and the falling input signal shall become equal to or less than VIL(ac) level
IS43/46TR16640ED
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9.6.10 Data Setup, Hold and Slew Rate Derating
9.6.10.1 Nominal slew rate and tVAC for setup time tDS(left) and hold time t DH(right) - DQ with respect to strobe
9.6.10.2 Tangent line for setup time tDS(left) and hold time tDH(right) - DQ with respect to strobe
DQS
VDDQ
VIH(ac)MIN
VIH(dc)MIN
VREF(dc)
VIL(dc)MAX
VIL(ac)MAX
Nominal
slew rate
Nominal
slew rate
tDS
tDH
tVAC
tVAC
tDS
tDH
VSS
TF
TR
Setup slew Rate @
Falling signal
=
[VREF(dc)-VIL(ac)max]
/ ΔTF
Setup slew Rate @ Rising
signal
=
[VIH(ac)min-VREF(dc)]
/ ΔTR
DQS
VDDQ
VIH(ac)MIN
VIH(dc)MIN
VREF(dc)
VIL(dc)MAX
VIL(ac)MAX
Nominal
slew rate
Nominal
slew rate
tDS
tDH
tVAC
tDS
tDH
VSS
TR
TF
Hold slew Rate @
Rising signal
=
[VREF(dc)-VIL(dc)max]
/ ΔTR
Hold slew Rate @
Falling signal
=
[VIH(dc)min-VREF(dc)]
/ ΔTF
DQS#
DQS
VDDQ
VIH(ac)MIN
VIH(dc)MIN
VREF(dc)
VIL(dc)MAX
VIL(ac)MAX
Nominal
slew rate
Nominal
slew rate
tDS
tDH
tVAC
tVAC
tDS
tDH
VSS
TF
TR
Setup slew Rate @
Rising signal
= tangent line
[VIH(ac)min-VREF(dc)]
/ ΔTR
Setup slew Rate @
Falling signal
= tangent line
[VREF(dc)-VIL(ac)max]
/ ΔTF
tangent
line
tangent
line
DQS#
DQS
VDDQ
VIH(ac)MIN
VIH(dc)MIN
VREF(dc)
VIL(dc)MAX
VIL(ac)MAX
Nominal
slew rate
Nominal
slew rate
tDS
tDH
tDS
tDH
VSS
TR
Hold slew Rate @
Falling signal
= tangent line
[VIH(dc)min-VREF(dc)]
/ ΔTF
Hold slew Rate @
Rising signal
= tangent line
[VREF(dc)-VIL(dc)max]
/ ΔTR
tangent
line
tangent
line
TF
VREF to AC region
VREF to DC region
VREF to AC region
VREF to DC region
IS43/46TR16640ED
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Rev. B1
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ORDERING INFORMATION, 64MX16, 1.5V (DDR3)
64Mx16 - Industrial Range: (–40°C TC 95°C)
Data Rate
CL-tRCD-tRP
Order Part No.
Package
1333MT/s
9-9-9
IS43TR16640ED-15HBLI
96-ball BGA,Lead-free
1600MT/s
11-11-11
IS43TR16640ED-125KBLI
96-ball BGA,Lead-free
64Mx16 – Automotive, A1 Range: (–40°C TC 95°C)
Data Rate
CL-tRCD-tRP
Order Part No.
Package
1333MT/s
9-9-9
IS46TR16640ED-15HBLA1
96-ball BGA,Lead-free
1600MT/s
11-11-11
IS46TR16640ED-125KBLA1
96-ball BGA,Lead-free
64Mx16 – Automotive, A2 Range: (–40°C TC 105°C)
Data Rate
CL-tRCD-tRP
Order Part No.
Package
1333MT/s
9-9-9
IS46TR16640ED-15HBLA2
96-ball BGA,Lead-free
1600MT/s
11-11-11
IS46TR16640ED-125KBLA2
96-ball BGA,Lead-free
64Mx16 – Automotive, A3 Range: (–40°C TC 125°C)
Data Rate
CL-tRCD-tRP
Order Part No.
Package
1333MT/s
9-9-9
IS46TR16640ED-15HBLA3
96-ball BGA,Lead-free
1600MT/s
11-11-11
IS46TR16640ED-125KBLA3
96-ball BGA,Lead-free
Note: Contact ISSI for availability of options.
IS43/46TR16640ED
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Rev. B1
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ORDERING INFORMATION, 128MX8, 1.5V (DDR3)
128Mx8 - Industrial Range: (–40°C TC 95°C)
Data Rate
CL-tRCD-tRP
Order Part No.
Package
1333MT/s
9-9-9
IS43TR81280ED-15HBLI
78-ball BGA,Lead-free
1600MT/s
11-11-11
IS43TR81280ED-125KBLI
78-ball BGA,Lead-free
128Mx8 – Automotive, A1 Range: (–40°C TC 95°C)
Data Rate
CL-tRCD-tRP
Order Part No.
Package
1333MT/s
9-9-9
IS46TR81280ED-15HBLA1
78-ball BGA,Lead-free
1600MT/s
11-11-11
IS46TR81280ED-125KBLA1
78-ball BGA,Lead-free
128Mx8 – Automotive, A2 Range: (–40°C TC 105°C)
Data Rate
CL-tRCD-tRP
Order Part No.
Package
1333MT/s
9-9-9
IS46TR81280ED-15HBLA2
78-ball BGA,Lead-free
1600MT/s
11-11-11
IS46TR81280ED-125KBLA2
78-ball BGA,Lead-free
128Mx8 – Automotive, A3 Range: (–40°C TC 125°C)
Data Rate
CL-tRCD-tRP
Order Part No.
Package
1333MT/s
9-9-9
IS46TR81280ED-15HBLA3
78-ball BGA,Lead-free
1600MT/s
11-11-11
IS46TR81280ED-125KBLA3
78-ball BGA,Lead-free
Note: Contact ISSI for availability of options.
IS43/46TR16640ED
IS43/46TR81280ED
Integrated Silicon Solution, Inc. – www.issi.com – 74
Rev. B1
03/12/2018
PACKAGE OUTLINE DRAWING
IS43/46TR16640ED
IS43/46TR81280ED
Integrated Silicon Solution, Inc. – www.issi.com – 75
Rev. B1
03/12/2018
