74ACT373MSAX - Fairchild Semiconductor

November 1988

Revised November 1999

74AC373 • 74ACT373 Octal Transparent Latch with 3-STATE Outputs

74AC373 • 74ACT373

Octal Transparent Latch with 3-STATE Outputs

General Description

The AC/ACT373 consists of eight latches with 3-STATE

outputs for bus organized system applications. The flip-

flops appear transparent to the data when Latch Enable

(LE) is HIGH. When LE is LOW, the data that meets the

setup time is latched. Data appears on the bus when the

Output Enable (OE) is LOW. When OE is HIGH, the bus

output is in the high impedance state.

Features

■ICC and IOZ reduced by 50%

■Eight latches in a single package

■3-STATE outputs for bus interfacing

■Outputs source/sink 24 mA

■ACT373 has TTL-compatible inputs

Ordering Code:

Device a ls o av ailable in Tape and R eel. Specif y by append ing suffix lette r “X” to the ord ering inform ation

Logic Symbols

IEEE/IEC

Connection Diagram

Pin Descriptions

FACT is a trademark of Fairchild Semiconductor Corporation.

Order Number Package Number Package Description

74AC373SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body

74AC373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74AC373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74AC373PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

74ACT373SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body

74ACT373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74ACT373MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide

74ACT373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74ACT373PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Pin Names Description

D0–D7Data Inputs

LE Latch Enab le Input

OE Output Enable Input

O0–O73-STATE Latch Outputs

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74AC373 • 74ACT373

Functional Description

The AC/ACT373 contains eight D-type latches with 3-

STATE standard outputs. When the Latch Enable (LE)

input is HI GH, data on the Dn inpu ts enters t he latches. In

this c ondition the latches ar e transparen t, i.e., a latch out-

put will change state each time its D-type input changes.

When LE is LOW, the latches store the information that

was present on the D-type inputs a setup time preceding

the HI GH-to-LOW tr ansition of LE . The 3-STATE stan dard

outputs are controlled by the Output Enable (OE) input.

When OE is LOW, the standard outputs are in the 2-state

mode. When OE is HIGH, the standard outputs are in the

high impedance mode but this does not interfere with

entering new data into the latches.

Truth Table

H = HIGH Voltage Lev el

L = LOW Voltage Level

Z = High Impedance

X = Immaterial

O0 = Previous O0 before HIGH-t o-LOW tr ans it ion of Lat ch Enable

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagatio n delays.

Inputs Outputs

LE OE DnOn

XHX Z

HLL L

HLH H

LLX O

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74AC373 • 74ACT373

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absol ut e maximum ratings are those v alues beyond whic h damage

to the dev ice may occ ur. The databoo k specific ations sh ould be m et, with-

out exc eption, to e nsure that the system des ign is reliable over its power

supply, temperature, and output/input loading vari ables. Fairchild does not

recommend operation of FACT circuits outside da t abook spe c if ic at ions.

DC Electrical Characteristics for AC

Note 2: All outputs lo aded, thre sholds on input as s oc iated with outpu t un der test.

Note 3: Maximum test duration 2.0 ms, one output loaded at a time.

Note 4: IIN and ICC @ 3.0V are gu aranteed to be less t han or equa l t o th e respectiv e limit @ 5.5V VCC.

Supply Voltage (VCC)−0.5V to +7.0V

DC Input Diode Current (IIK)

VI = −0.5V −20 mA

VI = VCC + 0.5V +20 mA

DC Input Voltage (VI)−0.5V to VCC + 0.5V

DC Output Diode Current (IOK)

VO = −0.5V −20 mA

VO = VCC + 0.5V +20 mA

DC Output Voltage (VO)−0.5V to VCC + 0.5V

DC Output Source

or Sink Current (IO)± 50 mA

DC VCC or Ground Current

per Output Pin (ICC or IGND)± 50 mA

Storage Temperature (TSTG)−65°C to +150°C

Junction Temperature (TJ)

PDIP 140°C

Supply Voltage (VCC)

AC 2.0V to 6.0V

ACT 4.5V to 5.5V

Input Voltage (VI)0V to V

Output Voltage (VO)0V to V

Operating Temperature (TA)−40°C to +85°C

Minimum Input Edge Rate (∆V/∆t)

AC Devices

VIN from 30% to 70% of VCC

VCC @ 3.3V, 4.5V, 5.5 V 125 mV/ns

Minimum Input Edge Rate (∆V/∆t)

ACT Devices

VIN from 0.8V to 2.0V

VCC @ 4.5V, 5.5V 125 mV/ns

Symbol Parameter VCC

(V)

TA = +25°CT

A = −40°C to +85°CUnits Conditions

Typ Guaranteed Limits

VIH Minimum HIGH Level 3.0 1.5 2.1 2.1 VOUT = 0.1V

Input V oltag e 4.5 2.25 3.15 3.15 V or VCC − 0.1V

5.5 2.75 3.85 3.85

VIL Maximum LOW Level 3.0 1.5 0.9 0.9 VOUT = 0.1V

Input V oltag e 4.5 2.25 1.35 1.35 V or VCC − 0.1V

5.5 2.75 1.65 1.65

VOH Minimum HIGH Level 3.0 2.99 2.9 2.9

Output Voltage 4.5 4.49 4.4 4.4 V IOUT = −50 µA

5.5 5.49 5.4 5.4 VIN = VIL or VIH

3.0 2.56 2.46 IOH = −12 mA

4.5 3.86 3.76 V IOH = −24 mA

5.5 4.86 4.76 IOL = −24 mA (Note 2)

VOL Maximum LOW Level 3.0 0.002 0.1 0.1

Output Voltage 4.5 0.001 0.1 0.1 V IOUT = 50 µA

5.5 0.001 0.1 0.1 VIN = VIL or VIH

3.0 0.36 0.44 IOL = 12 mA

4.5 0.36 0.44 V IOL = 24 mA

5.5 0.36 0.44 IOL = 24 mA (Note 2)

IIN (Note 4) Maximum Input Leakage Current 5.5 ± 0.1 ± 1.0 µAV

I = VCC, GND

IOZ Maximum 3-STATE Current VI (OE) = VIL, VIH

5.5 ±0.25 ± 2.5 µAV

I = VCC, GND

VO = VCC, GND

IOLD Minimum Dynamic Output Current

(Note 3) 5.5 75 mA VOLD = 1.65V Max

IOHD 5.5 −75 mA VOHD = 3.85V Min

ICC (Note 4) Maximum Quiesce nt S upply Cur rent 5.5 4.0 40.0 µAV

IN = VCC or GND

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74AC373 • 74ACT373

DC Electrical Character istics for ACT

Note 5: All outputs loaded; th resholds on input associate d w it h output under tes t.

Note 6: Maximum test du ration 2.0 m s, one out put loaded a t a tim e.

AC Electrical Characteristics for AC

Note 7: Voltage Range 3.3 is 3.3V ± 0.3V

Voltage R ange 5.0 is 5. 0V ± 0.5V

Symbol Parameter VCC TA = +25°CT

A = −40°C to +85°Units Conditions

(V) Typ Guaranteed Limits

VIH Minimum HIGH Level 4.5 1.5 2.0 2.0 VVOUT = 0.1V

Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V

VIL Maximum LOW Level 4.5 1.5 0.8 0.8 VVOUT = 0.1V

Input Voltage 5.5 1.5 0.8 0.8 or VCC − 0.1V

VOH Minimum HIGH Level 4.5 4.49 4.4 4.4 VI

OUT = −50 µA

Output Voltage 5.5 5.49 5.4 5 .4 VIN = VIL or VIH

4.5 3.86 3.76 V IOH = −24 mA

5.5 4.86 4.76 IOH= −24 mA (Note 5)

VOL Maximum LOW Level 4.5 0.001 0.1 0.1 VI

OUT = 50 µA

Output Voltage 5.5 0.001 0.1 0.1 VIN = VIL or VIH

4.5 0.36 0.44 V IOL = 24 mA

5.5 0.36 0.44 IOL = 24 mA (Note 5)

IIN Maximum Input 5.5 ± 0.1 ± 1.0 µAV

I = VCC, GND

Leakage Current

IOZ Maximum 3-STATE 5.5 ± 0.25 ± 2.5 µAVI = VIL, VIH

Current VO = VCC, GND

ICCT Maximum ICC/Input 5.5 0.6 1.5 mA VI = VCC − 2.1V

IOLD Minimum Dynamic 5.5 75 mA VOLD =1.65V Max

IOHD Output Current (Note 6) 5.5 −75 mA VOHD =3.85V Min

ICC Maximum Quiescent 5.5 4.0 40.0 µAVIN = VCC

Supply Current or GND

VCC TA = +25°CT

A = −40°C to +85°C

Symbol Parameter (V) CL = 50 pF CL = 50 pF Units

(Note 7) Min Typ Max Min Max

tPLH Propagation Delay 3.3 1.5 10.0 13.5 1.5 15.0 ns

Dn to On5.0 1.5 7.0 9.5 1.5 10.5

tPHL Propagation Delay 3.3 1.5 9.5 13.0 1.5 14.5 ns

Dn to On5.0 1.5 7.0 9.5 1.5 10.5

tPLH Propagation Delay 3.3 1.5 10.0 13.5 1.5 15.0 ns

LE to On5.0 1.5 7.5 9.5 1.5 10.5

tPHL Propagation Delay 3.3 1.5 9.5 12.5 1.5 14.0 ns

LE to On5.0 1.5 7.0 9.5 1.5 10.5

tPZH Output Enable Time 3.3 1.5 9.0 11.5 1.0 13.0 ns

5.0 1.5 7.0 8.5 1.0 9.5

tPZL Output Enable Time 3.3 1.5 8.5 11.5 1.0 13.0 ns

5.0 1.5 6.5 8.5 1.0 9.5

tPHZ Output Disable Time 3.3 1.5 10.0 12.5 1.0 14.5 ns

5.0 1.5 8.0 11.0 1.0 12.5

tPLZ Output Disable Time 3.3 1.5 8.0 11.5 1.0 12.5 ns

5.0 1.5 6.5 8.5 1.0 10.0

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74AC373 • 74ACT373

AC Operating Requirements for AC

Note 8: Volt age Range 3.3 is 3.3V ± 0.3V

Voltage Range 5. 0 is 5. 0V ± 0.5V

AC Electrical Characteristics for ACT

Note 9: Volt age Range 5.0 is 5.0V ± 0.5V

AC Operating Requirements for ACT

Note 10: Voltage Range 5. 0 is 5.0V ± 0.5V

Capacitance

VCC TA = +25°CT

A = −40°C to +85°C

Symbol Parameter (V) CL = 50 pF CL = 50 pF Units

(Note 8) Typ Guaranteed Minimum

tSSetup T ime, HIGH or LOW 3.3 3.5 5.5 6.0 ns

Dn to LE 5.0 2.0 4.0 4.5

tHHold Time, HIGH or LOW 3.3 −3.0 1.0 1.0 ns

Dn to LE 5.0 −1.5 1.0 1.0

tWLE Pulse Width, 3.3 4.0 5.5 6.0 ns

HIGH 5.0 2.0 4.0 4.5

VCC TA = +25°CT

A = −40°C to +85°C

Symbol Parameter (V) CL = 50 pF CL = 50 pF Units

(Note 9) Min Typ Max Min Max

tPLH Propagation Delay 5.0 2.5 8.5 10.0 1.5 11.5 ns

Dn to On

tPHL Propagation Delay 5.0 2.0 8.0 10.0 1.5 11.5 ns

Dn to On

tPLH Propagation Delay 5.0 2.5 8.5 11.0 2.0 11.5 ns

LE to On

tPHL Propagation Delay 5.0 2.0 8.0 10.0 1.5 11.5 ns

LE to On

tPZH Output Enable Time 5.0 2.0 8.0 9.5 1.5 10.5 ns

tPZL Output Enable Time 5.0 2.0 7.5 9.0 1.5 10.5 ns

tPHZ Output Disable Time 5.0 2.5 9.0 11.0 2.5 12.5 ns

tPLZ Output Disable Time 5.0 1.5 7.5 8.5 1.0 10.0 ns

VCC TA = +25°CT

A = −40°C to +85°C

Symbol Parameter (V) CL = 50 pF CL = 50 pF Units

(Note 10) Typ Guaranteed Minimum

tSSetup Time, HIGH or LOW 5.0 0.8 2.5 3.5 ns

Dn to LE

tHHold Time, HIGH or LOW 5.0 0 0 1.0 ns

Dn to LE

tWLE Pulse Width, HIGH 5.0 2.0 7.0 8.0 ns

Symbol Parameter Typ Units Conditions

CIN Input Capacitance 4.5 pF VCC = OPEN

CPD Power Dissipation Capacitance 40.0 pF VCC = 5.0V

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74AC373 • 74ACT373

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Out line Integrated Circu it (SOIC), JEDEC MS-013, 0.300” Wide Body

Package Number M20B

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74AC373 • 74ACT373

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

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74AC373 • 74ACT373

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide

Packag e Num b er MSA2 0

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74AC373 • 74ACT373

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lea d Th in S hri n k Small Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 4.4mm Wide

Package Number MTC20

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74AC373 • 74ACT373 Octal Transparent Latch with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N20A

Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syste ms are devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent i n any compon ent of a lif e supp ort

device or system whose failure to perform can be rea-

sonabl y ex pect ed to ca use the fa ilu re of the li fe su pp ort

device or system, or to affect its safety or effectiveness.