HY62V8100A-(I)/HY62U8100A-(I) Series 128Kx8bit CMOS SRAM DESCRIPTION FEATURES The HY62V8100A-(I)/HY62U8100A-(I) is a high speed, low power and 1M bit CMOS SRAM organized as 131,072 words by 8bit. The HY62V8100A-(I) / HY62U8100A-(I) uses high performance CMOS process technology and designed for high speed low power circuit technology. It is particulary well suited for used in high density low power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 2.0V. * Fully static operation and Tri-state output * TTL compatible inputs and outputs * Battery backup(L/LL-part) - 2.0V(min) data retention * Standard pin configuration - 32pin 8x20mm/ 8x13.4mm Small TSOP-I (Standard and Reversed) Product Voltage Speed Operation Standby Current(uA) No. (V) (ns) Current(mA) L LL HY62V8100A 3.3 85/100/120 5 50 10 HY62V8100A-I 3.3 85/100/120 5 50 20 HY62U8100A 3.0 100/120/150 5 50 10 HY62U8100A-I 3.0 100/120/150 5 50 15 Note 1. E.T. : Extended Temperature, Normal : Normal Temperature 2. Current value is max. Temperature (C) 0~70(Normal) -40~85(E.T.) 0~70(Normal) -40~85(E.T.) PIN CONNECTION A4 A5 A6 A7 A12 A14 A16 NC Vcc A15 CS2 /WE A13 A8 A9 A11 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A3 A2 A1 A0 DQ1 DQ2 DQ3 Vss DQ4 DQ5 DQ6 DQ7 DQ8 /CS1 A10 /OE 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 TSOP-I/Small TSOP-I (Reversed) PIN DESCRIPTION ROW DECODER A0 ADD INPUT BUFFER Pin Function Chip Select 1 Chip Select 2 Write Enable Output Enable Address Input Data Input/Output Power(3.3V or 3.0V) Ground A16 /CS1 CS2 /OE /WE MEMORY ARRAY 1024x1024 I/O1 I/O8 CONTROL LOGIC Pin Name /CS1 CS2 /WE /OE A0 ~ A16 I/O1 ~ I/O8 Vcc Vss BLOCK DIAGRAM OUTPUT BUFFER TSOP-I/Small TSOP-I (Standard) /OE A10 /CS1 DQ8 DQ7 DQ6 DQ5 DQ4 Vss DQ3 DQ2 DQ1 A0 A1 A2 A3 SENSE AMP 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 WRITE DRIVER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 COLUMN DECODER A11 A9 A8 A13 /WE CS2 A15 Vcc NC A16 A14 A12 A7 A6 A5 A4 This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.06 /Jan.99 Hyundai Semiconductor HY62V8100A-(I)/HY62U8100A-(I) Series ORDERING INFORMATION Part No. HY62V8100ALT1 HY62V8100ALLT1 HY62V8100ALR1 HY62V8100ALLR1 HY62V8100ALST HY62V8100ALLST HY62V8100ALSR HY62V8100ALLSR HY62V8100ALT1-I HY62V8100ALLT1-I HY62V8100ALR1-I HY62V8100ALLR1-I HY62V8100ALST-I HY62V8100ALLST-I HY62V8100ALSR-I HY62V8100ALLSR-I HY62U8100ALT1 HY62U8100ALLT1 HY62U8100ALR1 HY62U8100ALLR1 HY62U8100ALST HY62U8100ALLST HY62U8100ALSR HY62U8100ALLSR HY62U8100ALT1-I HY62U8100ALLT1-I HY62U8100ALR1-I HY62U8100ALLR1-I HY62U8100ALST-I HY62U8100ALLST-I HY62U8100ALSR-I HY62U8100ALLSR-I Speed 85/100/120 85/100/120 85/100/120 85/100/120 85/100/120 85/100/120 85/100/120 85/100/120 85/100/120 85/100/120 85/100/120 85/100/120 85/100/120 85/100/120 85/100/120 85/100/120 100/120/150 100/120/150 100/120/150 100/120/150 100/120/150 100/120/150 100/120/150 100/120/150 100/120/150 100/120/150 100/120/150 100/120/150 100/120/150 100/120/150 100/120/150 100/120/150 Power L-part LL-part L-part LL-part L-part LL-part L-part LL-part L-part LL-part L-part LL-part L-part LL-part L-part LL-part L-part LL-part L-part LL-part L-part LL-part L-part LL-part L-part LL-part L-part LL-part L-part LL-part L-part LL-part Temp. E.T. E.T. E.T. E.T. E.T. E.T. E.T. E.T. E.T. E.T. E.T. E.T. E.T. E.T. E.T. E.T. Package TSOP-I(Standard) TSOP-I(Standard) TSOP-I(Reversed) TSOP-I(Reversed) Small TSOP-I(Standard) Small TSOP-I(Standard) Small TSOP-I(Reversed) Small TSOP-I(Reversed) TSOP-I(Standard) TSOP-I(Standard) TSOP-I(Reversed) TSOP-I(Reversed) Small TSOP-I(Standard) Small TSOP-I(Standard) Small TSOP-I(Reversed) Small TSOP-I(Reversed) TSOP-I(Standard) TSOP-I(Standard) TSOP-I(Reversed) TSOP-I(Reversed) Small TSOP-I(Standard) Small TSOP-I(Standard) Small TSOP-I(Reversed) Small TSOP-I(Reversed) TSOP-I(Standard) TSOP-I(Standard) TSOP-I(Reversed) TSOP-I(Reversed) Small TSOP-I(Standard) Small TSOP-I(Standard) Small TSOP-I(Reversed) Small TSOP-I(Reversed) Note 1. E.T. : Extended Temperature, Blank : Normal Temperature ABSOLUTE MAXIMUM RATING (1) Symbol Vcc, VIN, VOUT TA TSTG PD IOUT TSOLDER Parameter Power Supply, Input/Output Voltage Operating Temperature Storage Temperature Power Dissipation Data Output Current Lead Soldering Temperature & Time Rating -0.3 to 4.6 0 to 70 Unit V C -40 to 85 C -65 to 125 1.0 50 260 * 10 C W mA C*sec Remark HY62V8100A HY62U8100A HY62V8100A-I HY62U8100A-I Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability. Rev.06 /Jan.99 2 HY62V8100A-(I)/HY62U8100A-(I) Series RECOMMENDED DC OPERATING CONDITION Symbol Vcc Parameter Supply Voltage Vss Ground VIH Input High Voltage VIL Input Low Voltage Product HY62V8100A-(I) HY62U8100A-(I) HY62V8100A-(I) HY62U8100A-(I) HY62V8100A-(I) HY62U8100A-(I) HY62V8100A-(I) HY62U8100A-(I) Min. 3.0 2.7 0 Typ. 3.3 3.0 0 Max. 3.6 3.3 0 Unit V V V 2.2 - Vcc+0.3 V -0.3(1) - 0.6 V Note : 1. VIL = -1.5V for pulse width less than 30ns TRUTH TABLE /CS1 H X L L L CS2 X L H H H /WE X X H H L /OE X X H L X MODE Standby Output Disabled Read Write I/O OPERATION High-Z High-Z High-Z Data Out Data In Note : 1. H=VIH, L=VIL, X=don't care DC ELECTRICAL CHARACTERISTICS Vcc = 3.3V10%/3.0V10%, TA = 0C to 70C (Normal)/ -40C to 85C (E.T.), unless otherwise specified Symbol Parameter Test Condition Min. Typ. Max. Unit ILI Input Leakage Current Vss < VIN < Vcc -1 1 uA -1 1 uA ILO Output Leakage Current Vss <VOUT < Vcc, /CS1 = VIH or CS2 = VIL or /OE = VIH or /WE = VIL Icc Operating Power Supply /CS1 = VIL, CS2 = VIH, 3 5 mA Current VIN = VIH or VIL, II/O = 0mA ICC1 Average HY62V8100A-(I) /CS1 = VIL CS2 = VIH, 25 35 mA Operating HY62U8100A-(I) Min Duty Cycle = 100%, II/O = 0mA 20 30 mA Current ISB TTL Standby Current /CS1 = VIH or CS2 = VIL 0.5 mA (TTL Input) ISB1 Standby HY62V8100A /CS1 > Vcc - 0.2V L 1 50 uA Current CS2 < 0.2V or LL 0.5 10 uA (CMOS HY62V8100A-I CS2 > Vcc - 0.2V L 1 50 uA Input) LL 0.5 20 uA HY62U8100A L 1 50 uA LL 0.5 10 uA HY62U8100A-I L 1 50 uA LL 0.5 15 uA VOL Output Low Voltage IOL = 2.1mA 0.4 V VOH Output High Voltage IOH = -1mA 2.2 V Note : Typical values are at Vcc = 3.3V/3.0V, TA = 25C Rev.06 /Jan.99 3 HY62V8100A-(I)/HY62U8100A-(I) Series AC CHARACTERISTICS(I) Vcc = 3.3V10%, TA = 0C to 70C (Normal)/ -40C to 85C (E.T.), unless otherwise specified -85 -10 -12 # Symbol Parameter Min. Max. Min. Max. Min Max. READ CYCLE 1 tRC Read Cycle Time 85 100 120 2 tAA Address Access Time 85 100 120 3 tACS Chip Select Access Time 85 100 120 4 tOE Output Enable to Output Valid 45 50 60 5 tCLZ Chip Select to Output in Low Z 10 10 20 6 tOLZ Output Enable to Output in Low Z 5 5 10 7 tCHZ Chip Deselection to Output in High Z 0 30 0 30 0 40 8 tOHZ Out Disable to Output in High Z 0 30 0 30 0 40 9 tOH Output Hold from Address Change 10 10 20 WRITE CYCLE 10 tWC Write Cycle Time 85 100 120 11 tCW Chip Selection to End of Write 70 80 100 12 tAW Address Valid to End of Write 70 80 100 13 tAS Address Set-up Time 0 0 0 14 tWP Write Pulse Width 55 60 85 15 tWR Write Recovery Time 0 0 0 16 tWHZ Write to Output in High Z 0 30 0 30 0 50 17 tDW Data to Write Time Overlap 40 45 50 18 tDH Data Hold from Write Time 0 0 0 19 tOW Output Active from End of Write 5 5 5 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns AC CHARACTERISTICS(II) Vcc = 3.0V10%, TA = 0C to 70C (Normal)/ -40C to 85C (E.T.), unless otherwise specified -10 -12 -15 # Symbol Parameter Min. Max. Min. Max. Min Max. READ CYCLE 1 tRC Read Cycle Time 100 120 150 2 tAA Address Access Time 100 120 150 3 tACS Chip Select Access Time 100 120 150 4 tOE Output Enable to Output Valid 50 60 75 5 tCLZ Chip Select to Output in Low Z 20 20 20 6 tOLZ Output Enable to Output in Low Z 10 10 10 7 tCHZ Chip Deselection to Output in High Z 0 30 0 40 0 50 8 tOHZ Out Disable to Output in High Z 0 30 0 40 0 50 9 tOH Output Hold from Address Change 20 20 20 WRITE CYCLE 10 tWC Write Cycle Time 100 120 150 11 tCW Chip Selection to End of Write 80 100 120 12 tAW Address Valid to End of Write 80 100 120 13 tAS Address Set-up Time 0 0 0 14 tWP Write Pulse Width 75 85 100 15 tWR Write Recovery Time 0 0 0 16 tWHZ Write to Output in High Z 0 35 0 40 0 50 17 tDW Data to Write Time Overlap 45 50 60 18 tDH Data Hold from Write Time 0 0 0 19 tOW Output Active from End of Write 10 10 10 - Rev.06 /Jan.99 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4 HY62V8100A-(I)/HY62U8100A-(I) Series AC TEST CONDITIONS TA = 0C to 70C (Normal) / -40C to 85C (E.T.), unless otherwise specified PARAMETER Value Input Pulse Level 0.4V to 2.2V Input Rise and Fall Time 5ns Input and Output Timing Reference Level 1.5V Output Load CL = 100pF + 1TTL Load AC TEST LOADS TTL CL(1) Note : 1 Including jig and scope capacitance CAPACITANCE (Temp = 25C, f= 1.0MHz) Symbol Parameter CIN Input Capacitance COUT Output Capacitance Condition VIN = 0V VI/O = 0V Max. 6 8 Unit pF pF Note : These parameters are sampled and not 100% tested TIMING DIAGRAM READ CYCLE 1 tRC ADDR tAA OE tOE tOH tOLZ CS1 CS2 tACS tOHZ tCHZ tCLZ Data Out Rev.06 /Jan.99 High-Z Data Valid 5 HY62V8100A-(I)/HY62U8100A-(I) Series Note(READ CYCLE): 1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels 2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given device and from device to device. 3. /WE is high for the read cycle. READ CYCLE 2 tRC ADDR tAA tOH tOH Data Out Previous Data Data Valid Note(READ CYCLE): 1. /WE is high for the read cycle. 2. Device is continuously selected /CS1 = VIL, CS2 = VIH. 3. /OE =VIL. WRITE CYCLE 1(/WE Controlled) tWC ADDR tAW tWR tCW CS1 CS2 tWP tAS WE tDW Data In Data Valid tOHZ Data Out Rev.06 /Jan.99 tDH Data Undefined tOW High-Z 6 HY62V8100A-(I)/HY62U8100A-(I) Series WRITE CYCLE 2 (/CS1 Controlled) tWC ADDR tWR tAS tCW CS1 tAW CS2 tWP WE tDH tDW Data In Data Valid High-Z tCLZ tWHZ Data Out High-Z High-Z WRITE CYCLE 3 (CS2 Controlled) tWC ADDR tAS tWR tCW CS1 tAW CS2 tWP WE tDW Data In tDH Data Valid High-Z tCLZ tWHZ Data Out Rev.06 /Jan.99 High-Z High-Z 7 HY62V8100A-(I)/HY62U8100A-(I) Series Notes(WRITE CYCLE): 1. A write occurs during the overlap of a low /CS1, CS2 and low /WE. A write begines at the latest transition among /CS1 going low, CS2 going high and /WE going low: A write ends at the earliest transition among /CS1 going high, CS2 low and /WE going high. tWP is measured from the beginning of write to the end of write. . 2. tCW is measured from the later of /CS1 going low or CS2 going high to the end of write . 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends as /CS1, or /WE going high, and tWR is applied in case a write ends at CS2 going low. 5. If /OE, CS2 and /WE are in the read mode during this period, the I/O pins are in the output low-Z state, input of opposite phase of the output must not be applied because bus contention can occur. 6. If /CS1 goes low simultaneously with /WE going low, the outputs remain in high impedance state. 7. Dout is the read data of the new address. 8. When /CS1 is low and CS2 is high, I/O pins are in the output state. The input signals in the opposite phase leading to the outputs should not be applied. DATA RETENTION ELECTRIC CHARACTERISTIC TA=0C to 70C (Normal)/-40C to 85C (E.T.) Symbol Parameter VDR Vcc for Data Retention ICCDR Data Retention Current HY62V8100A HY62V8100A-I HY62U8100A Test Condition /CS1>Vcc-0.2V, CS2<0.2V or Vcc - 0.2V, Vss<VIN<Vcc Vcc=3.0V, /CS1>Vcc - 0.2V, CS2<0.2V or > Vcc - 0.2V, Vss< VIN <Vcc HY62U8100A-I tCDR tR Chip Deselect to Data Retention Time Operating Recovery Time See Data Retention Timing Diagram L LL L LL L LL L LL Min 2.0 Typ - Max - Unit V 0 tRC(2) 1 0.5 1 0.5 1 0.5 1 0.5 - 50 10 50 15 50 10 50 15 - uA uA uA uA uA uA uA uA ns ns Notes: 1. Typical values are under the condition of TA = 25C. 2. tRC is read cycle time. DATA RETENTION TIMING DIAGRAM 1 DATA RETENTION MODE VCC 3.0/2.7V tCDR tR 2.2V VDR CS1>VCC-0.2V CS1 VSS Rev.06 /Jan.99 8 HY62V8100A-(I)/HY62U8100A-(I) Series DATA RETENTION TIMING DIAGRAM 2 DATA RETENTION MODE VCC 3.0/2.7V tCDR tR CS2 VDR 0.4V CS2<0.2V VSS Note : 1. 3.0V : HY62V8100A and HY62V8100A-I 2.7V : HY62U8100A and HY62U8100A-I RELIABILITY SPEC. TEST MODE ESD HBM MM LATCH - UP Rev.06 /Jan.99 TEST SPEC. > 2000V > 250V < -100mA > 100mA 9 HY62V8100A-(I)/HY62U8100A-(I) Series PACKAGE INFORMATION 32pin 8x20mm Thin Small Outline Package Standard(T1) #1 #32 UNIT : INCH(mm) 0.319(8.103) 0.311(7.900) #17 #16 0.728(18.491) 0.720(18.288) 0.792(20.117) 0.784(19.914) 0.041(1.05) 0.037(0.95) 0.006(0.15) 0.002(0.05) 0.008(0.21) 0.004(0.10) 0.025(0.64) 0.021(0.54) 0.020(0.50) BSC 0.011(0.27) 0.007(0.17) 32pin 8x20mm Thin Small Outline Package Reversed(R1) #16 #17 UNIT : INCH(mm) 0.319(8.103) 0.311(7.900) #32 #1 0.728(18.491) 0.720(18.288) 0.792(20.117) 0.784(19.914) 0.041(1.05) 0.037(0.95) 0.006(0.15) 0.002(0.05) 0.025(0.64) 0.021(0.54) Rev.06 /Jan.99 0.008(0.21) 0.004(0.1) 0.020(0.50) BSC 0.011(0.27) 0.007(0.17) 10 HY62V8100A-(I)/HY62U8100A-(I) Series 32pin 8x13.4mm Thin Small Outline Package Standard(ST) #1 #32 UNIT : INCH(mm) 0.319(8.1) 0.311(7.9) #17 #16 0.468(11.9) 0.460(11.7) 0.536(13.6) 0.520(13.2) 0.041(1.05) 0.037(0.95) 0.008(0.20) 0.002(0.05) 0.008(0.2) 0.004(0.1) 0.024(0.6) 0.016(0.4) 0.020(0.50) 0.011(0.27) 0.007(0.17) 32pin 8x13.4mm Thin Small Outline Package Reversed(SR) #16 #17 UNIT : INCH(mm) 0.319(8.1) 0.311(7.9) #32 #1 0.468(11.9) 0.460(11.7) 0.536(13.6) 0.520(13.2) 0.041(1.05) 0.037(0.95) 0.008(0.20) 0.002(0.05) 0.024(0.6) 0.016(0.4) Rev.06 /Jan.99 0.008(0.2) 0.004(0.1) 0.020(0.50) 0.011(0.27) 0.007(0.17) 11