This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.06 /Jan.99 Hyundai Semiconductor
HY62V8100A-(I)/HY62U8100A-(I) Series
128Kx8bit CMOS SRAM
DESCRIPTION
The HY62V8100A-(I)/HY62U8100A-(I) is a high
speed, low power and 1M bit CMOS SRAM
organized as 131,072 words by 8bit. The
HY62V8100A-(I) / HY62U8100A-(I) uses high
performance CMOS process technology and
designed for high speed low power circuit
technology. It is particulary well suited for used in
high density low power system application. This
device has a data retention mode that guarantees
data to remain valid at a minimum power supply
voltage of 2.0V.
FEATURES
• Fully static operation and Tri-state output
• TTL compatible inputs and outputs
• Battery backup(L/LL-part)
- 2.0V(min) data retention
• Standard pin configuration
- 32pin 8x20mm/ 8x13.4mm Small TSOP-I
(Standard and Reversed)
Product Voltage Speed Operation Standby Current(uA) Temperature
No. (V) (ns) Current(mA) L LL (°C)
HY62V8100A 3.3 85/100/120 5 50 10 0~70(Normal)
HY62V8100A-I 3.3 85/100/120 5 50 20 -40~85(E.T.)
HY62U8100A 3.0 100/120/150 5 50 10 0~70(Normal)
HY62U8100A-I 3.0 100/120/150 5 50 15 -40~85(E.T.)
Note 1. E.T. : Extended Temperature, Normal : Normal Temperature
2. Current value is max.
PIN CONNECTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
/OE
A10
DQ8
DQ7
DQ6
DQ5
DQ4
Vss
DQ3
DQ2
DQ1
A0
A1
A2
A3
A11
A9
A8
A13
/WE
CS2
A15
Vcc
NC
A16
A14
A12
A7
A6
A5
A4
/CS1
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A3
A2
A0
DQ1
DQ2
DQ3
Vss
DQ4
DQ5
DQ6
DQ7
DQ8
/CS1
A10
/OE
A4
A5
A6
A7
A12
A14
A16
NC
Vcc
A15
CS2
/WE
A13
A8
A9
A11
A1
TSOP-I/Small TSOP-I TSOP-I/Small TSOP-I
(Standard) (Reversed)
PIN DESCRIPTION BLOCK DIAGRAM
Pin Name Pin Function
/CS1 Chip Select 1
CS2 Chip Select 2
/WE Write Enable
/OE Output Enable
A0 ~ A16 Address Input
I/O1 ~ I/O8 Data Input/Output
Vcc Power(3.3V or 3.0V)
Vss Ground
CS2
A16
COLUMN DECODER
A0 ROW DECODER
MEMORY ARRAY
1024x1024
SENSE AMP
OUTPUT BUFFER
I/O1
I/O8
ADD INPUT BUFFER
/CS1
/OE
/WE
WRITE DRIVER
CONTROL
LOGIC
HY62V8100A-(I)/HY62U8100A-(I) Series
Rev.06 /Jan.99
2
ORDERING INFORMATION
Part No. Speed Power Temp. Package
HY62V8100ALT1 85/100/120 L-part TSOP-I(Standard)
HY62V8100ALLT1 85/100/120 LL-part TSOP-I(Standard)
HY62V8100ALR1 85/100/120 L-part TSOP-I(Reversed)
HY62V8100ALLR1 85/100/120 LL-part TSOP-I(Reversed)
HY62V8100ALST 85/100/120 L-part Small TSOP-I(Standard)
HY62V8100ALLST 85/100/120 LL-part Small TSOP-I(Standard)
HY62V8100ALSR 85/100/120 L-part Small TSOP-I(Reversed)
HY62V8100ALLSR 85/100/120 LL-part Small TSOP-I(Reversed)
HY62V8100ALT1-I 85/100/120 L-part E.T. TSOP-I(Standard)
HY62V8100ALLT1-I 85/100/120 LL-part E.T. TSOP-I(Standard)
HY62V8100ALR1-I 85/100/120 L-part E.T. TSOP-I(Reversed)
HY62V8100ALLR1-I 85/100/120 LL-part E.T. TSOP-I(Reversed)
HY62V8100ALST-I 85/100/120 L-part E.T. Small TSOP-I(Standard)
HY62V8100ALLST-I 85/100/120 LL-part E.T. Small TSOP-I(Standard)
HY62V8100ALSR-I 85/100/120 L-part E.T. Small TSOP-I(Reversed)
HY62V8100ALLSR-I 85/100/120 LL-part E.T. Small TSOP-I(Reversed)
HY62U8100ALT1 100/120/150 L-part TSOP-I(Standard)
HY62U8100ALLT1 100/120/150 LL-part TSOP-I(Standard)
HY62U8100ALR1 100/120/150 L-part TSOP-I(Reversed)
HY62U8100ALLR1 100/120/150 LL-part TSOP-I(Reversed)
HY62U8100ALST 100/120/150 L-part Small TSOP-I(Standard)
HY62U8100ALLST 100/120/150 LL-part Small TSOP-I(Standard)
HY62U8100ALSR 100/120/150 L-part Small TSOP-I(Reversed)
HY62U8100ALLSR 100/120/150 LL-part Small TSOP-I(Reversed)
HY62U8100ALT1-I 100/120/150 L-part E.T. TSOP-I(Standard)
HY62U8100ALLT1-I 100/120/150 LL-part E.T. TSOP-I(Standard)
HY62U8100ALR1-I 100/120/150 L-part E.T. TSOP-I(Reversed)
HY62U8100ALLR1-I 100/120/150 LL-part E.T. TSOP-I(Reversed)
HY62U8100ALST-I 100/120/150 L-part E.T. Small TSOP-I(Standard)
HY62U8100ALLST-I 100/120/150 LL-part E.T. Small TSOP-I(Standard)
HY62U8100ALSR-I 100/120/150 L-part E.T. Small TSOP-I(Reversed)
HY62U8100ALLSR-I 100/120/150 LL-part E.T. Small TSOP-I(Reversed)
Note 1. E.T. : Extended Temperature, Blank : Normal Temperature
ABSOLUTE MAXIMUM RATING (1)
Symbol Parameter Rating Unit Remark
Vcc, VIN, VOUT Power Supply, Input/Output Voltage -0.3 to 4.6 V
TAOperating Temperature 0 to 70 °CHY62V8100A
HY62U8100A
-40 to 85 °CHY62V8100A-I
HY62U8100A-I
TSTG Storage Temperature -65 to 125 °C
PDPower Dissipation 1.0 W
IOUT Data Output Current 50 mA
TSOLDER Lead Soldering Temperature & Time 260 • 10 °C•sec
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
HY62V8100A-(I)/HY62U8100A-(I) Series
Rev.06 /Jan.99
3
RECOMMENDED DC OPERATING CONDITION
Symbol Parameter Product Min. Typ. Max. Unit
Vcc Supply Voltage HY62V8100A-(I) 3.0 3.3 3.6 V
HY62U8100A-(I) 2.7 3.0 3.3 V
Vss Ground HY62V8100A-(I) 0 0 0 V
HY62U8100A-(I)
VIH Input High Voltage HY62V8100A-(I) 2.2 -Vcc+0.3 V
HY62U8100A-(I)
VIL Input Low Voltage HY62V8100A-(I) -0.3(1) -0.6 V
HY62U8100A-(I)
Note :
1. VIL = -1.5V for pulse width less than 30ns
TRUTH TABLE
/CS1 CS2 /WE /OE MODE I/O OPERATION
HX X X Standby High-Z
XLX X High-Z
LH H H Output Disabled High-Z
LH H LRead Data Out
LHLXWrite Data In
Note :
1. H=VIH, L=VIL, X=don't care
DC ELECTRICAL CHARACTERISTICS
Vcc = 3.3V±10%/3.0V±10%, TA = 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.), unless otherwise specified
Symbol Parameter Test Condition Min. Typ. Max. Unit
ILI Input Leakage Current Vss < VIN < Vcc -1 -1uA
ILO Output Leakage Current Vss <VOUT < Vcc, /CS1 = VIH or
CS2 = VIL or /OE = VIH or /WE =
VIL
-1 -1uA
Icc Operating Power Supply
Current /CS1 = VIL, CS2 = VIH,
VIN = VIH or VIL, II/O = 0mA -3 5 mA
ICC1 Average HY62V8100A-(I) /CS1 = VIL CS2 = VIH, -25 35 mA
Operating HY62U8100A-(I) Min Duty Cycle = 100%, II/O = 0mA -20 30 mA
Current
ISB TTL Standby Current
(TTL Input) /CS1 = VIH or CS2 = VIL - - 0.5 mA
ISB1 Standby HY62V8100A /CS1 > Vcc - 0.2V L-1 50 uA
Current CS2 < 0.2V or LL -0.5 10 uA
(CMOS HY62V8100A-I CS2 > Vcc - 0.2V L-1 50 uA
Input) LL -0.5 20 uA
HY62U8100A L-1 50 uA
LL -0.5 10 uA
HY62U8100A-I L-1 50 uA
LL -0.5 15 uA
VOL Output Low Voltage IOL = 2.1mA - - 0.4 V
VOH Output High Voltage IOH = -1mA 2.2 - - V
Note : Typical values are at Vcc = 3.3V/3.0V, TA = 25°C
HY62V8100A-(I)/HY62U8100A-(I) Series
Rev.06 /Jan.99
4
AC CHARACTERISTICS(I)
Vcc = 3.3V±10%, TA = 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.), unless otherwise specified
-85 -10 -12
Min. Max. Min. Max. Min Max.
1tRC Read Cycle Time 85 -100 -120 -ns
2tAA Address Access Time -85 -100 -120 ns
3tACS Chip Select Access Time -85 -100 -120 ns
4tOE Output Enable to Output Valid -45 -50 -60 ns
5tCLZ Chip Select to Output in Low Z 10 -10 -20 -ns
6tOLZ Output Enable to Output in Low Z 5-5-10 -ns
7tCHZ Chip Deselection to Output in High Z 0 30 0 30 0 40 ns
8tOHZ Out Disable to Output in High Z 0 30 0 30 0 40 ns
9tOH Output Hold from Address Change 10 -10 -20 -ns
10 tWC Write Cycle Time 85 -100 -120 -ns
11 tCW Chip Selection to End of Write 70 -80 -100 -ns
12 tAW Address Valid to End of Write 70 -80 -100 -ns
13 tAS Address Set-up Time 0-0-0-ns
14 tWP Write Pulse Width 55 -60 -85 -ns
15 tWR Write Recovery Time 0-0-0-ns
16 tWHZ Write to Output in High Z 0 30 0 30 0 50 ns
17 tDW Data to Write Time Overlap 40 -45 -50 -ns
18 tDH Data Hold from Write Time 0-0-0-ns
19 tOW Output Active from End of Write 5-5-5-ns
AC CHARACTERISTICS(II)
Vcc = 3.0V±10%, TA = 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.), unless otherwise specified
-10 -12 -15
Min. Max. Min. Max. Min Max.
1tRC Read Cycle Time 100 -120 -150 -ns
2tAA Address Access Time -100 -120 -150 ns
3tACS Chip Select Access Time -100 -120 -150 ns
4tOE Output Enable to Output Valid -50 -60 -75 ns
5tCLZ Chip Select to Output in Low Z 20 -20 -20 -ns
6tOLZ Output Enable to Output in Low Z 10 -10 -10 -ns
7tCHZ Chip Deselection to Output in High Z 0 30 0 40 0 50 ns
8tOHZ Out Disable to Output in High Z 0 30 0 40 0 50 ns
9tOH Output Hold from Address Change 20 -20 -20 -ns
10 tWC Write Cycle Time 100 -120 -150 -ns
11 tCW Chip Selection to End of Write 80 -100 -120 -ns
12 tAW Address Valid to End of Write 80 -100 -120 -ns
13 tAS Address Set-up Time 0-0-0-ns
14 tWP Write Pulse Width 75 -85 -100 -ns
15 tWR Write Recovery Time 0-0-0-ns
16 tWHZ Write to Output in High Z 0 35 0 40 0 50 ns
17 tDW Data to Write Time Overlap 45 -50 -60 -ns
18 tDH Data Hold from Write Time 0-0-0-ns
19 tOW Output Active from End of Write 10 -10 -10 -ns
READ CYCLE
WRITE CYCLE
READ CYCLE
WRITE CYCLE
Symbol Parameter
#Unit
Symbol
Parameter
#Unit
HY62V8100A-(I)/HY62U8100A-(I) Series
Rev.06 /Jan.99
5
AC TEST CONDITIONS
TA = 0°C to 70°C (Normal) / -40°C to 85°C (E.T.), unless otherwise specified
PARAMETER Value
Input Pulse Level 0.4V to 2.2V
Input Rise and Fall Time 5ns
Input and Output Timing Reference Level 1.5V
Output Load CL = 100pF + 1TTL Load
AC TEST LOADS
CL(1)
TTL
Note : 1 Including jig and scope capacitance
CAPACITANCE
(Temp = 25°C, f= 1.0MHz)
Symbol Parameter Condition Max. Unit
CIN Input Capacitance VIN = 0V 6pF
COUT Output Capacitance VI/O = 0V 8pF
Note : These parameters are sampled and not 100% tested
TIMING DIAGRAM
READ CYCLE 1
ADDR
OE
CS1
CS2
Data
Out Data Valid
tRC
tACS
tCLZ
tOE
tOLZ
tAA
tOH
tOHZ
tCHZ
High-Z
HY62V8100A-(I)/HY62U8100A-(I) Series
Rev.06 /Jan.99
6
Note(READ CYCLE):
1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are
not referenced to output voltage levels
2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given
device and from device to device.
3. /WE is high for the read cycle.
READ CYCLE 2
tRC
tAA
Data ValidPrevious Data
tOH tOH
ADDR
Data
Out
Note(READ CYCLE):
1. /WE is high for the read cycle.
2. Device is continuously selected /CS1 = VIL, CS2 = VIH.
3. /OE =VIL.
WRITE CYCLE 1(/WE Controlled)
ADDR
CS1
CS2
Data
Out
Data Undefined
tWC
tDW
tOHZ
tAW
tOW
High-Z
WE
tCW
tWR
Data Valid
tDH
tWP
tAS
Data In
HY62V8100A-(I)/HY62U8100A-(I) Series
Rev.06 /Jan.99
7
WRITE CYCLE 2 (/CS1 Controlled)
ADDR
CS1
CS2
Data
Out
Data Valid
tWC
tWP
tCLZ
tCW
tAW
tAS
tDH
High-Z
tWR
tWHZ
tDW
High-Z
High-Z
Data In
WE
WRITE CYCLE 3 (CS2 Controlled)
ADDR
CS1
CS2
Data
Out
Data Valid
tWC
tWP
tCLZ
tCW
tAW
tAS
tDH
High-Z
tWR
tWHZ
tDW
High-Z
High-Z
Data In
WE
HY62V8100A-(I)/HY62U8100A-(I) Series
Rev.06 /Jan.99
8
Notes(WRITE CYCLE):
1. A write occurs during the overlap of a low /CS1, CS2 and low /WE. A write begines at the latest transition
among /CS1 going low, CS2 going high and /WE going low: A write ends at the earliest transition among
/CS1 going high, CS2 low and /WE going high. tWP is measured from the beginning of write to the end of
write. .
2. tCW is measured from the later of /CS1 going low or CS2 going high to the end of write .
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends as
/CS1, or /WE going high, and tWR is applied in case a write ends at CS2 going low.
5. If /OE, CS2 and /WE are in the read mode during this period, the I/O pins are in the output low-Z state,
input of opposite phase of the output must not be applied because bus contention can occur.
6. If /CS1 goes low simultaneously with /WE going low, the outputs remain in high impedance state.
7. Dout is the read data of the new address.
8. When /CS1 is low and CS2 is high, I/O pins are in the output state. The input signals in the opposite
phase leading to the outputs should not be applied.
DATA RETENTION ELECTRIC CHARACTERISTIC
TA=0°C to 70°C (Normal)/-40°C to 85°C (E.T.)
Symbol Parameter Test Condition Min Typ Max Unit
VDR Vcc for Data Retention /CS1>Vcc-0.2V, 2.0 - - V
CS2<0.2V or
Vcc – 0.2V,
Vss<VIN<Vcc
ICCDR Data Retention HY62V8100A Vcc=3.0V, L-1 50 uA
Current /CS1>Vcc - 0.2V, LL -0.5 10 uA
HY62V8100A-I CS2<0.2V or L-1 50 uA
> Vcc - 0.2V, LL -0.5 15 uA
HY62U8100A Vss< VIN <Vcc L-1 50 uA
LL -0.5 10 uA
HY62U8100A-I L-1 50 uA
LL -0.5 15 uA
tCDR Chip Deselect to Data Retention Time See Data Retention 0- - ns
tR Operating Recovery Time Timing Diagram tRC(2) - - ns
Notes:
1. Typical values are under the condition of TA = 25°C.
2. tRC is read cycle time.
DATA RETENTION TIMING DIAGRAM 1
CS1
VDR
CS1>VCC-0.2V
tCDR tR
VSS
VCC
3.0/2.7V
2.2V
DATA RETENTION MODE
HY62V8100A-(I)/HY62U8100A-(I) Series
Rev.06 /Jan.99
9
DATA RETENTION TIMING DIAGRAM 2
0.4V
VDR
tCDR tR
VSS
VCC
CS2
3.0/2.7V
DATA RETENTION MODE
CS2<0.2V
Note :
1. 3.0V : HY62V8100A and HY62V8100A-I
2.7V : HY62U8100A and HY62U8100A-I
RELIABILITY SPEC.
TEST MODE TEST SPEC.
ESD HBM > 2000V
MM > 250V
LATCH - UP < -100mA
> 100mA
HY62V8100A-(I)/HY62U8100A-(I) Series
Rev.06 /Jan.99
10
PACKAGE INFORMATION
32pin 8x20mm Thin Small Outline Package Standard(T1)
UNIT : INCH(mm)
0.319(8.103)
0.311(7.900)
0.728(18.491)
0.720(18.288)
0.792(20.117)
0.784(19.914)
0.025(0.64)
0.021(0.54)
0.008(0.21)
0.004(0.10) 0.020(0.50)
BSC 0.011(0.27)
0.041(1.05)
0.037(0.95)
0.006(0.15)
0.002(0.05)
#1
#32
#16
#17
0.007(0.17)
32pin 8x20mm Thin Small Outline Package Reversed(R1)
UNIT : INCH(mm)
0.319(8.103)
0.311(7.900)
0.728(18.491)
0.720(18.288)
0.792(20.117)
0.784(19.914)
0.025(0.64)
0.021(0.54)
0.008(0.21)
0.004(0.1) 0.020(0.50)
BSC 0.007(0.17)
0.041(1.05)
0.037(0.95)
0.006(0.15)
0.002(0.05)
#16
#17
#1
#32
0.011(0.27)
HY62V8100A-(I)/HY62U8100A-(I) Series
Rev.06 /Jan.99
11
32pin 8x13.4mm Thin Small Outline Package Standard(ST)
UNIT : INCH(mm)
0.319(8.1)
0.311(7.9)
0.468(11.9)
0.460(11.7)
0.536(13.6)
0.520(13.2)
0.024(0.6)
0.016(0.4)
0.008(0.2)
0.004(0.1) 0.020(0.50)
0.007(0.17)
0.041(1.05)
0.037(0.95)
0.008(0.20)
0.002(0.05)
#1
#32
#16
#17
0.011(0.27)
32pin 8x13.4mm Thin Small Outline Package Reversed(SR)
UNIT : INCH(mm)
0.319(8.1)
0.311(7.9)
0.468(11.9)
0.460(11.7)
0.536(13.6)
0.520(13.2)
0.024(0.6)
0.016(0.4)
0.008(0.2)
0.004(0.1) 0.020(0.50)
0.007(0.17)
0.041(1.05)
0.037(0.95)
0.008(0.20)
0.002(0.05)
#16
#17
#1
#32
0.011(0.27)
