Rev. 3.1_01
CMOS SERIAL E2PROM S-93C46B/56B/66B
Seiko Instruments Inc. 1
The S-93C46B/56B/66B is a high speed, low current
consumption, 1/2/4 K-bit serial E2PROM with a wide
operating voltage range. It is organized as 64-word
× 16-bit, 128-word × 16-bit, 256-word × 16-bit,
respectively. Each is capable of sequential read, at
which time addresses are automatically incremented
in 16-bit blocks. The instruction code is compatible
with the NM93CS46/56/66.
Features
• Low current consumption Standby: 1.5 µA Max. (VCC = 5.5 V)
Operating: 0.8 mA Max. (VCC = 5.5 V)
0.4 mA Max. (VCC = 2.5 V)
• Wide operating voltage range Read: 1.8 to 5.5 V (at −40 to +85°C)
Write: 2.7 to 5.5 V (at −40 to +85°C)
• Sequential read capable
• Write disable function when power supply voltage is low
• Function to protect against write due to erroneous instruction recognition
• Endurance: 107 cycles/word* (at +25°C) write capable,
106 cycles/word* (at +85°C)
3 × 105 cycles/word* (at +105°C)
* For each address (Word: 16 bits)
• Data retention: 10 years (after rewriting 106 cycles/word at +85°C)
• S-93C46B: 1 K-bit NM93CS46 instruction code compatible
• S-93C56B: 2 K-bit NM93CS56 instruction code compatible
• S-93C66B: 4 K-bit NM93CS66 instruction code compatible
• High-temperature operation: +105°C Max. supported
(Only S-93Cx6BD0H-J8T2, S-93Cx6BD0H-T8T2)
Packages
Package name Drawing code
Package Tape Reel
8-Pin DIP DP008-F
8-Pin SOP(JEDEC) FJ008-A FJ008-D FJ008-D
8-Pin TSSOP FT008-A FT008-E FT008-E
SNT-8A PH008-A PH008-A PH008-A
Caution This product is intended to use in general electronic devices such as consumer electronics,
office equipment, and communications devices. Before using the product in medical
equipment or automobile equipment including car audio, keyless entry and engine control
unit, contact to SII is indispensable.
CMOS SERIAL E2PROM
S-93C46B/56B/66B Rev.3.1_01
Seiko Instruments Inc.
2
Pin Assignment
8-Pin DIP
Top view
Table 1
Pin Number Pin Name Function
1 CS
Chip select input
2 SK
Serial clock input
3 DI
Serial data input
4 DO
Serial data output
5 GND
Ground
6 TEST*1 Test
7 NC No connection
8 VCC Power supply
*1. Connect to GND or VCC.
Even if this pin is not connected, performance is not affected
so long as the absolute maximum rating is not exceeded.
1
2
3
4
8
7
6
5
VCC
NC
TEST
GND
CS
SK
DO
DI
Figure 1
S-93C46BD0I-D8S1
S-93C56BD0I-D8S1
S-93C66BD0I-D8S1
Remark See Dimensions for details of the package drawings.
8-Pin SOP(JEDEC)
Top view
Table 2
Pin Number Pin Name Function
1 CS
Chip select input
2 SK
Serial clock input
3 DI
Serial data input
4 DO
Serial data output
5 GND
Ground
6 TEST*1 Test
7 NC No connection
8 VCC Power supply
*1. Connect to GND or VCC.
Even if this pin is not connected, performance is not affected
so long as the absolute maximum rating is not exceeded.
1
2
3
4
8
7
6
5
VCC
NC
TEST
GND
CS
SK
DO
DI
Figure 2
S-93C46BD0I-J8T1
S-93C46BD0H-J8T2
S-93C56BD0I-J8T1
S-93C56BD0H-J8T2
S-93C66BD0I-J8T1
S-93C66BD0H-J8T2
Remark See Dimensions for details of the package drawings.
CMOS SERIAL E2PROM
Rev.3.1_01 S-93C46B/56B/66B
Seiko Instruments Inc. 3
8-Pin SOP(JEDEC) (Rotated)
Top view
Table 3
Pin Number Pin Name Function
1 NC No connection
2 VCC Power supply
3 CS
Chip select input
4 SK
Serial clock input
5 DI
Serial data input
6 DO
Serial data output
7 GND
Ground
8 TEST*1 Test
*1. Connect to GND or VCC.
Even if this pin is not connected, performance is not affected
so long as the absolute maximum rating is not exceeded.
1
2
3
4
8
7
6
5
CS
SK
TEST
GND
DO
DI
VCC
NC
Figure 3
S-93C46BR0I-J8T1
S-93C56BR0I-J8T1
S-93C66BR0I-J8T1
Remark See Dimensions for details of the package drawings.
8-Pin TSSOP
Top view
Table 4
Pin Number Pin Name Function
1 CS
Chip select input
2 SK
Serial clock input
3 DI
Serial data input
4 DO
Serial data output
5 GND
Ground
6 TEST*1 Test
7 NC No connection
8 VCC Power supply
*1. Connect to GND or VCC.
Even if this pin is not connected, performance is not affected
so long as the absolute maximum rating is not exceeded.
1
2
3
4
8
7
6
5
VCC
NC
TEST
GND
CS
SK
DO
DI
Figure 4
S-93C46BD0I-T8T1
S-93C46BD0H-T8T2
S-93C56BD0I-T8T1
S-93C56BD0H-T8T2
S-93C66BD0I-T8T1
S-93C66BD0H-T8T2
Remark See Dimensions for details of the package drawings.
CMOS SERIAL E2PROM
S-93C46B/56B/66B Rev.3.1_01
Seiko Instruments Inc.
4
SNT-8A
Top view
Table 5
Pin Number Pin Name Function
1 CS
Chip select input
2 SK
Serial clock input
3 DI
Serial data input
4 DO
Serial data output
5 GND
Ground
6 TEST*1 Test
7 NC No connection
8 VCC Power supply
*1. Connect to GND or VCC.
Even if this pin is not connected, performance is not affected so
long as the absolute maximum rating is not exceeded.
1
2
3
4
8
7
6
5
VCC
NC
TEST
GND
CS
SK
DI
DO
Figure 5
S-93C46BD0I-I8T1G
S-93C56BD0I-I8T1G
S-93C66BD0I-I8T1G
Remark See Dimensions for details of the package drawings.
CMOS SERIAL E2PROM
Rev.3.1_01 S-93C46B/56B/66B
Seiko Instruments Inc. 5
Block Diagram
Memory array
Data register
Address
decoder
Mode decode logic
Clock pulse
monitoring circuit
Output buffer
VCC
GND
DO
DI
CS
Clock generator
Voltage detector
SK
Figure 6
Instruction Sets
1. S-93C46B
Table 6
Instruction Start Bit Operation
Code
Address Data
SK input clock 1 2 3 4 5 6 7 8 9 10 to 25
READ (Read data) 1 1 0 A5 A4 A3 A2 A1 A0
D15 to D0 Output*1
WRITE (Write data) 1 0 1 A5 A4 A3 A2 A1 A0
D15 to D0 Input
ERASE (Erase data) 1 1 1 A5 A4 A3 A2 A1 A0
WRAL (Write all) 1 0 0 0 1 x x x x
D15 to D0 Input
ERAL (Erase all) 1 0 0 1 0 x x x x
EWEN (Write enable) 1 0 0 1 1 x x x x
EWDS (Write disable) 1 0 0 0 0 x x x x
*1. When the 16-bit data in the specified address has been output, the data in the next address is output.
Remark x: Don’t care
CMOS SERIAL E2PROM
S-93C46B/56B/66B Rev.3.1_01
Seiko Instruments Inc.
6
2. S-93C56B
Table 7
Instruction Start Bit Operation
Code
Address Data
SK input clock 1 2 3 4 5 6 7 8 9 10 11 12 to 27
READ (Read data) 1 1 0 x A6 A5 A4 A3 A2 A1 A0
D15 to D0 Output*1
WRITE (Write data) 1 0 1 x A6 A5 A4 A3 A2 A1 A0
D15 to D0 Input
ERASE (Erase data) 1 1 1 x A6 A5 A4 A3 A2 A1 A0
WRAL (Write all) 1 0 0 0 1 x x x x x x
D15 to D0 Input
ERAL (Erase all) 1 0 0 1 0 x x x x x x
EWEN (Write enable) 1 0 0 1 1 x x x x x x
EWDS (Write disable) 1 0 0 0 0 x x x x x x
*1. When the 16-bit data in the specified address has been output, the data in the next address is output.
Remark x: Don’t care
3. S-93C66B
Table 8
Instruction Start Bit Operation
Code
Address Data
SK input clock 1 2 3 4 5 6 7 8 9 10 11 12 to 27
READ (Read data) 1 1 0 A7 A6 A5 A4 A3 A2 A1 A0 D15 to D0 Output*1
WRITE (Write data) 1 0 1 A7 A6 A5 A4 A3 A2 A1 A0 D15 to D0 Input
ERASE (Erase data) 1 1 1 A7 A6 A5 A4 A3 A2 A1 A0
WRAL (Write all) 1 0 0 0 1 x x x x x x
D15 to D0 Input
ERAL (Erase all) 1 0 0 1 0 x x x x x x
EWEN (Write enable) 1 0 0 1 1 x x x x x x
EWDS (Write disable) 1 0 0 0 0 x x x x x x
*1. When the 16-bit data in the specified address has been output, the data in the next address is output.
Remark x: Don’t care
CMOS SERIAL E2PROM
Rev.3.1_01 S-93C46B/56B/66B
Seiko Instruments Inc. 7
Absolute Maximum Ratings
Table 9
Parameter Symbol Ratings Unit
Power supply voltage VCC −0.3 to +7.0 V
Input voltage VIN −0.3 to VCC +0.3 V
Output voltage VOUT −0.3 to VCC V
Storage temperature Tstg −65 to +150 °C
Caution The absolute maximum ratings are rated values exceeding which the product could
suffer physical damage. These values must therefore not be exceeded under any
conditions.
Recommended Operating Conditions
Table 10
−
40 to
+
85
°
C
+
85 to
+
105
°
C
Parameter
Symbol
Conditions Min. Typ. Max. Min. Typ. Max. Unit
READ/EWDS 1.8
5.5 V
Power supply voltage V
CC
WRITE/ERASE/
WRAL/ERAL/EWEN 2.7
5.5 4.5
5.5 V
V
CC
=
4.5 to 5.5 V 2.0
V
CC
2.0
V
CC
V
V
CC
=
2.7 to 4.5 V 0.8
×
V
CC
V
CC
V
High level input voltage V
IH
V
CC
=
1.8 to 2.7 V 0.8
×
V
CC
V
CC
V
V
CC
=
4.5 to 5.5 V 0.0
0.8 0.0
0.8 V
V
CC
=
2.7 to 4.5 V 0.0
0.2
×
V
CC
V
Low level input voltage V
IL
V
CC
=
1.8 to 2.7 V 0.0
0.15
×
V
CC
V
Operating temperature T
opr
−
40
+
85
+
85
+
105
°
C
Pin Capacitance
Table 11
(Ta = 25°C, f = 1.0 MHz,
V
CC
= 5.0 V)
Parameter Symbol Conditions Min. Typ. Max. Unit
Input Capacitance CIN VIN = 0 V 8 pF
Output Capacitance COUT VOUT = 0 V 10 pF
Endurance
Table 12
Parameter Symbol
Operating
Temperature Min. Typ. Max. Unit
−40 to +85°C 106
Endurance NW
+
85
to +105°C 3 × 105 cycles/word*
* For each address (Word: 16 bits)
CMOS SERIAL E2PROM
S-93C46B/56B/66B Rev.3.1_01
Seiko Instruments Inc.
8
DC Electrical Characteristics
Table 13
−
40 to
+
85
°
C
+
85
to
+
105
°
C
V
CC
=
4.5 to 5.5 V V
CC
=
2.5 to 4.5 V V
CC
=
1.8 to 2.5 V V
CC
=
4.5 to 5.5 V
Parameter Symbol Conditions
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Unit
Current
consumption
(READ)
I
CC1
DO no load
0.8
0.5
0.4
0.8 mA
Table 14
−
40 to
+
85
°
C
+
85
to
+
105
°
C
V
CC
=
4.5 to 5.5 V V
CC
=
2.7 to 4.5 V V
CC
=
4.5 to 5.5 V
Parameter Symbol Conditions
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Unit
Current consumption
(WRITE) I
CC2
DO no load
2.0
1.5
2.0 mA
Table 15
−
40 to
+
85
°
C
+
85
to
+
105
°
C
V
CC
=
4.5 to 5.5 V V
CC
=
2.5 to 4.5 V V
CC
=
1.8 to 2.5 V V
CC
=
4.5 to 5.5 V
Parameter
Symbol
Conditions
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Unit
Standby current
consumption
I
SB
CS
=
GND, DO
=
Open, Other inputs
to V
CC
or GND
1.5
1.5
1.5
1.5
µ
A
Input leakage
current
I
LI
V
IN
=
GND to V
CC
0.1 1.0
0.1 1.0
0.1 1.0
0.1 1.0
µ
A
Output leakage
current
I
LO
V
OUT
=
GND to V
C
C
0.1 1.0
0.1 1.0
0.1 1.0
0.1 1.0
µ
A
I
OL
=
2.1 mA
0.4
0.4 V
Low level output
voltage
V
OL
I
OL
=
100
µ
A
0.1
0.1
0.1
0.1 V
I
OH
=
−
400
µ
A 2.4
2.4
V
I
OH
=
−
100
µ
A
V
CC
−
0.3
V
CC
−
0.3
V
CC
−
0.3
V
High level output
voltage
V
OH
I
OH
=
−
10
µ
A
V
CC
−
0.2
V
CC
−
0.2
V
CC
−
0.2
V
CC
−
0.2
V
Write enable latch
data hold voltage
V
DH
Only when write
disable mode 1.5
1.5
1.5
1.5
V
CMOS SERIAL E2PROM
Rev.3.1_01 S-93C46B/56B/66B
Seiko Instruments Inc. 9
AC Electrical Characteristics
Table 16 Measurement Conditions
Input pulse voltage 0.1 × VCC to 0.9 × VCC
Output reference voltage 0.5 × VCC
Output load 100 pF
Table 17
−40 to +85°C
+
85
to +105°C
VCC = 4.5 to 5.5 V VCC = 2.5 to 4.5 V VCC = 1.8 to 2.5 V VCC = 4.5 to 5.5 V
Parameter Symbol
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Unit
CS setup time tCSS 0.2 0.4 1.0 0.2 µs
CS hold time tCSH 0 0 0 0 µs
CS deselect time tCDS 0.2 0.2 0.4 0.2 µs
Data setup time tDS 0.1 0.2 0.4 0.1 µs
Data hold time tDH 0.1 0.2 0.4 0.1 µs
Output delay time tPD 0.4 0.8 2.0 0.6 µs
Clock frequency*1 f
SK 0 2.0 0 0.5 0 0.25 0 1.0 MHz
SK clock time “L” *1 t
SKL 0.1 0.5 1.0 0.25 µs
SK clock time “H” *1 t
SKH 0.1 0.5 1.0 0.25 µs
Output disable time tHZ1, tHZ2 0 0.15 0 0.5 0 1.0 0 0.15 µs
Output enable time tSV 0 0.15 0 0.5 0 1.0 0 0.15 µs
*1. The clock cycle of the SK clock (frequency: fSK) is 1/fSK µs. This clock cycle is determined by a combination
of several AC characteristics, so be aware that even if the SK clock cycle time is minimized, the clock cycle
(1/fSK) cannot be made equal to tSKL(Min.) + tSKH(Min.).
Table 18
−40 to +85°C
+
85
to +105°C
VCC = 2.7 to 5.5 V VCC = 4.5 to 5.5 V
Parameter Symbol
Min. Typ. Max. Min. Typ. Max.
Unit
Write time tPR 4.0 8.0 4.0 8.0 ms
CMOS SERIAL E2PROM
S-93C46B/56B/66B Rev.3.1_01
Seiko Instruments Inc.
10
t
SKH
t
CDS
tCSS
CS
Valid data
Valid data
DI
tSKL
SK
t
SV
t
HZ2
tCSH
t
HZ1
t
PD tPD
tDS tDH
t
DS t
DH
Hi-Z Hi-Z
Hi-Z
DO
DO
(READ)
(VERIFY)
Hi-Z
*1
1/fSK
*2
*1. Indicates high impedance.
*2. 1/fSK is the SK clock cycle. This clock cycle is determined by a combination of several AC
characteristics, so be aware that even if the SK clock cycle time is minimized, the clock cycle
(1/fSK) cannot be made equal to tSKL(Min.) + tSKH(Min.).
Figure 7 Timing Chart
CMOS SERIAL E2PROM
Rev.3.1_01 S-93C46B/56B/66B
Seiko Instruments Inc. 11
Operation
All instructions are executed by inputting DI in synchronization with the rising edge of SK after CS goes
high. An instruction set is input in the order of start bit, instruction, address, and data.
Instruction input finishes when CS goes low. A low level must be input to CS between commands during
tCDS. While a low level is being input to CS, the S-93C46B/56B/66B is in standby mode, so the SK and DI
inputs are invalid and no instructions are allowed.
Start Bit
A start bit is recognized when the DI pin goes high at the rise of SK after CS goes high. After CS goes high,
a start bit is not recognized even if the SK pulse is input as long as the DI pin is low.
1. Dummy clock
SK clocks input while the DI pin is low before a start bit is input are called dummy clocks. Dummy
clocks are effective when aligning the number of instruction sets (clocks) sent by the CPU with those
required for serial memory operation. For example, when a CPU instruction set is 16 bits, the number
of instruction set clocks can be adjusted by inserting a 7-bit dummy clock for the S-93C46B and a 5-bit
dummy clock for the S-93C56B/66B.
2. Start bit input failure
• When the output status of the DO pin is high during the verify period after a write operation, if a high
level is input to the DI pin at the rising edge of SK, the S-93C46B/56B/66B recognizes that a start bit
has been input. To prevent this failure, input a low level to the DI pin during the verify operation
period (refer to “4.1 Verify operation”).
• When a 3-wire interface is configured by connecting the DI input pin and DO output pin, a period in
which the data output from the CPU and the serial memory collide may be generated, preventing
successful input of the start bit. Take the measures described in “ 3-Wire Interface (Direct
Connection between DI and DO)”.
CMOS SERIAL E2PROM
S-93C46B/56B/66B Rev.3.1_01
Seiko Instruments Inc.
12
3. Reading (READ)
The READ instruction reads data from a specified address.
After CS has gone high, input an instruction in the order of the start bit, read instruction, and address.
Since the last input address (A0) has been latched, the output status of the DO pin changes from high
impedance (Hi-Z) to low, which is held until the next rise of SK. 16-bit data starts to be output in
synchronization with the next rise of SK.
3.1 Sequential read
After the 16-bit data at the specified address has been output, inputting SK while CS is high
automatically increments the address, and causes the 16-bit data at the next address to be output
sequentially. The above method makes it possible to read the data in the whole memory space.
The last address (An yyy A1 A0 = 1 yyy 1 1) rolls over to the top address (An yyy A1 A0 = 0 yyy 0 0).
D
15
D15 D14
D14 D13 D
14
D13
D0
D1
D2
D
15
0 D
0
D
1
D
2 D13
A
1
A
2
A3
A
4
A
5
0 1 <1> A
0
SK
DI
CS
DO
ADRINC
Hi-Z
282726252423121110 9 8 7 6 5 4 3 2 1 4443 42 41 40 39
ADRINC
Hi-Z
Figure 8 Read Timing (S-93C46B)
SK
D13
D
15
0 D14 D14 D13
D0
D1
D
2
D1
5
D
14
D
0
D
1
D
2
D
13
D
15
4140 43 44 42
2827262524
A3
A
4
A
5
A
0
A
1
A
2
DI
1311 10 9 8 7 6 5 4 3 2 1 12
CS
DO
A
6
45
29
14
Hi -Z
Hi-Z
0 1 <1>
ADRINC ADRINC
X: S-93C56B
A7: S-93C66B
Figure 9 Read Timing (S-93C56B, S-93C66B)
CMOS SERIAL E2PROM
Rev.3.1_01 S-93C46B/56B/66B
Seiko Instruments Inc. 13
4. Writing (WRITE, ERASE, WRAL, ERAL)
A write operation includes four write instructions: data write (WRITE), data erase (ERASE), chip write
(WRAL), and chip erase (ERAL).
A write instruction (WRITE, ERASE, WRAL, ERAL) starts a write operation to the memory cell when a
low level is input to CS after a specified number of clocks have been input. The SK and DI inputs are
invalid during the write period, so do not input an instruction.
Input an instruction while the output status of the DO pin is high or high impedance (Hi-Z).
A write operation is valid only in program enable mode (refer to “5. Write enable (EWEN) and write
disable (EWDS)”).
4.1 Verify operation
A write operation executed by any instruction is completed within 8 ms (write time tPR: typically 4
ms), so if the completion of the write operation is recognized, the write cycle can be minimized. A
sequential operation to confirm the status of a write operation is called a verify operation.
(1) Operation
After the write operation has started (CS = low), the status of the write operation can be verified
by confirming the output status of the DO pin by inputting a high level to CS again. This
sequence is called a verify operation, and the period that a high level is input to the CS pin after
the write operation has started is called the verify operation period.
The relationship between the output status of the DO pin and the write operation during the
verify operation period is as follows.
• DO pin = low: Writing in progress (busy)
• DO pin = high: Writing completed (ready)
(2) Operation example
There are two methods to perform a verify operation: Waiting for a change in the output status
of the DO pin while keeping CS high, or suspending the verify operation (CS = low) once and
then performing it again to verify the output status of the DO pin. The latter method allows the
CPU to perform other processing during the wait period, allowing an efficient system to be
designed.
Caution 1. Input a low level to the DI pin during a verify operation.
2. If a high level is input to the DI pin at the rise of SK when the output status of the DO
pin is high, the S-93C46B/56B/66B latches the instruction assuming that a start bit has
been input. In this case, note that the DO pin immediately enters a high-impedance
(Hi-Z) state.
CMOS SERIAL E2PROM
S-93C46B/56B/66B Rev.3.1_01
Seiko Instruments Inc.
14
4.2 Writing data (WRITE)
To write 16-bit data to a specified address, change CS to high and then input the WRITE
instruction, address, and 16-bit data following the start bit. The write operation starts when CS
goes low. There is no need to set the data to 1 before writing. If the clocks more than the specified
number have been input, the clock pulse monitoring circuit cancels the WRITE instruction. For
details of the clock pulse monitoring circuit, refer to “ Function to Protect Against Write due to
Erroneous Instruction Recognition”.
HZ1
A5 A3 A2 A1 A0 D15 A4
1 3 4 5 6 7 8 9 10 2
0 1
<1>
25
t
CDS
Verify
Busy
Standby
t
SV t
Ready
t PR Hi-Z
CS
SK
DI
DO Hi-Z
D0
Figure 10 Data Write Timing (S-93C46B)
<1>
R eady
Busy
t
PR
t
SV
t
CDS
27 1 2 3 4 5 6 7 8 9 10 11 12
0 1 D0 A6 A5 A4 A3 A2 A1 A0 D15
CS
SK
DI
DO Hi-Z
Verify Standby
Hi-Z t
HZ1
x : S-93C56B
A7: S-93C66B
Figure 11 Data Write Timing (S-93C56B, S-93C66B)
CMOS SERIAL E2PROM
Rev.3.1_01 S-93C46B/56B/66B
Seiko Instruments Inc. 15
4.3 Erasing data (ERASE)
To erase 16-bit data at a specified address, set all 16 bits of the data to 1, change CS to high, and
then input the ERASE instruction and address following the start bit. There is no need to input data.
The data erase operation starts when CS goes low. If the clocks more than the specified number
have been input, the clock pulse monitoring circuit cancels the ERASE instruction. For details of
the clock pulse monitoring circuit, refer to “ Function to Protect Against Write due to
Erroneous Instruction Recognition”.
Verify
t
SV
SK
DI A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9
CS
DO
t
CDS
t
PR
Busy
Hi-Z
Standby
Hi-Z t
HZ1
<1> 1 A0
Ready
1
Figure 12 Data Erase Timing (S-93C46B)
Ready
t
CDS
t
SV
Hi-Z
t
HZ1
t
PR
SK
DI <1> A6 A5 A4 A3 A2 A1 A0
1 2 3 4 5 6 7 8 9 10 11
CS
DO Busy
Verify Standby
Hi-Z
1 1
x : S-93C56B
A7: S-93C66B
Figure 13 Data Erase Timing (S-93C56B, S-93C66B)
CMOS SERIAL E2PROM
S-93C46B/56B/66B Rev.3.1_01
Seiko Instruments Inc.
16
4.4 Writing to chip (WRAL)
To write the same 16-bit data to the entire memory address space, change CS to high, and then
input the WRAL instruction, an address, and 16-bit data following the start bit. Any address can be
input. The write operation starts when CS goes low. There is no need to set the data to 1 before
writing. If the clocks more than the specified number have been input, the clock pulse monitoring
circuit cancels the WRAL instruction. For details of the clock pulse monitoring circuit, refer to “
Function to Protect Against Write due to Erroneous Instruction Recognition”.
2 3 4 5 6 7 8 9 10 1
SK
DI
t
CDS
t
SV t
HZ1
Hi-Z
t
PR
CS
DO B usy
Verify Standby
Hi-Z
25
<1> 0 D0
R eady
0 0 1
4Xs
D15
Figure 14 Chip Write Timing (S-93C46B)
Verify
2 3 4 5 6 7 8 9 10 1
SK
DI
t
CDS
t
SV t
HZ1
Hi-Z
t
PR
CS
DO B usy
Standby
Hi-Z
11 12 27
<1> 0 D0
R eady
0 0 1
6Xs
D15
Figure 15 Chip Write Timing (S-93C56B, S-93C66B)
CMOS SERIAL E2PROM
Rev.3.1_01 S-93C46B/56B/66B
Seiko Instruments Inc. 17
4.5 Erasing chip (ERAL)
To erase the data of the entire memory address space, set all the data to 1, change CS to high, and
then input the ERAL instruction and an address following the start bit. Any address can be input.
There is no need to input data. The chips erase operation starts when CS goes low. If the clocks
more than the specified number have been input, the clock pulse monitoring circuit cancels the
ERAL instruction. For details of the clock pulse monitoring circuit, refer to “ Function to Protect
Against Write due to Erroneous Instruction Recognition”.
t
CDS
4Xs
0 1 0
8 7 6 5 4 3 2 1
<1> 0
t
PR
Hi-Z
t
HZ1
R eady
B usy
t
SV
Standby
Verify
9
SK
DI
CS
DO
Figure 16 Chip Erase Timing (S-93C46B)
7 6 5 4 3 2 1 9 8
CS
SK
DI
DO
t
CDS
t
SV
R eady
B usy
t
HZ1
Hi-Z
t
PR
11
6Xs
0 1 0
<1> 0
Standby
Verify
10
Figure 17 Chip Erase Timing (S-93C56B, S-93C66B)
CMOS SERIAL E2PROM
S-93C46B/56B/66B Rev.3.1_01
Seiko Instruments Inc.
18
5. Write enable (EWEN) and write disable (EWDS)
The EWEN instruction is an instruction that enables a write operation. The status in which a write
operation is enabled is called the program enable mode.
The EWDS instruction is an instruction that disables a write operation. The status in which a write
operation is disabled is called the program disable mode.
After CS goes high, input an instruction in the order of the start bit, EWEN or EWDS instruction, and
address (optional). Each mode becomes valid by inputting a low level to CS after the last address
(optional) has been input.
5 4 3 2 1 9 8 7 6
SK
DI
CS
4Xs
11 = EWEN
00 =EWDS
0
<1> 0
Standby
Figure 18 Write Enable/Disable Timing (S-93C46B)
DI
SK 6 5 4 3 2 1 9 8 11 10
7
CS
6Xs
11 =EWEN
00 =EWDS
0
<1> 0
Standby
Figure 19 Write Enable/Disable Timing (S-93C56B, S-93C66B)
(1) Recommendation for write operation disable instruction
It is recommended to implement a design that prevents an incorrect write operation when a write
instruction is erroneously recognized by executing the write operation disable instruction when
executing instructions other than write instruction, and immediately after power-on and before
power off.
CMOS SERIAL E2PROM
Rev.3.1_01 S-93C46B/56B/66B
Seiko Instruments Inc. 19
Write Disable Function when Power Supply Voltage is Low
The S-93C46B/56B/66B provides a built-in detector to detect a low power supply voltage and disable
writing. When the power supply voltage is low or at power application, the write instructions (WRITE,
ERASE, WRAL, and ERAL) are cancelled, and the write disable state (EWDS) is automatically set. The
detection voltage is 1.75 V typ., the release voltage is 2.05 V typ., and there is a hysteresis of about 0.3 V
(refer to Figure 20). Therefore, when a write operation is performed after the power supply voltage has
dropped and then risen again up to the level at which writing is possible, a write enable instruction (EWEN)
must be sent before a write instruction (WRITE, ERASE, WRAL, or ERAL) is executed.
When the power supply voltage drops during a write operation, the data being written to an address at that
time is not guaranteed.
Release voltage (+VDET)
2.05 V Typ.
Power supply voltage
Hysteresis
A
bout 0.3 V
Detection voltage (−VDET)
1.75 V Typ.
Write instruction cancelled
Write disable state (EWDS) automatically set
Figure 20 Operation when Power Supply Voltage is Low
CMOS SERIAL E2PROM
S-93C46B/56B/66B Rev.3.1_01
Seiko Instruments Inc.
20
Function to Protect Against Write due to Erroneous Instruction Recognition
The S-93C46B/56B/66B provides a built-in clock pulse monitoring circuit which is used to prevent an
erroneous write operation by canceling write instructions (WRITE, ERASE, WRAL, and ERAL) recognized
erroneously due to an erroneous clock count caused by the application of noise pulses or double counting
of clocks.
Instructions are cancelled if a clock pulse more or less than specified number decided by each write
operation (WRITE, ERASE, WRAL, or ERAL) is detected.
<Example> Erroneous recognition of program disable instruction (EWDS) as erase instruction (ERASE)
1 3 4 5 6 7 2 8 9
CS
SK
DI
Input EWDS instruction
Erroneous recognition as
ERASE instruction due to
noise pulse
1 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 1 0
Noise pulse
Example of S-93C46B
1
In products that do not include a clock pulse monitoring circuit, FFFF is
mistakenly written on address 00h. However the S-93C46B detects the overcount
and cancels the instruction without performing a write operation.
Figure 21 Example of Clock Pulse Monitoring Circuit Operation
CMOS SERIAL E2PROM
Rev.3.1_01 S-93C46B/56B/66B
Seiko Instruments Inc. 21
3-Wire Interface (Direct Connection between DI and DO)
There are two types of serial interface configurations: a 4-wire interface configured using the CS, SK, DI,
and DO pins, and a 3-wire interface that connects the DI input pin and DO output pin.
When the 3-wire interface is employed, a period in which the data output from the CPU and the data output
from the serial memory collide may occur, causing a malfunction. To prevent such a malfunction, connect
the DI and DO pins of the S-93C46B/56B/66B via a resistor (10 kΩ to 100 kΩ) so that the data output from
the CPU takes precedence in being input to the DI pin (refer to “Figure 22 Connection of 3-Wire
Interface”).
CPU
DI
SIO
DO
S-93C46B/56B/66B
R: 10 kΩ to 100 kΩ
Figure 22 Connection of 3-Wire Interface
I/O Pins
1. Connection of input pins
All the input pins of the S-93C46B/56B/66B employ a CMOS structure, so design the equipment so that high
impedance will not be input while the S-93C46B/56B/66B is operating. Especially, deselect the CS input (a
low level) when turning on/off power and during standby. When the CS pin is deselected (a low level),
incorrect data writing will not occur. Connect the CS pin to GND via a resistor (10 kΩ to 100 kΩ pull-down
resistor). To prevent malfunction, it is recommended to use equivalent pull-down resistors for pins other
than the CS pin.
2. Input and output pin equivalent circuits
The following shows the equivalent circuits of input pins of the S-93C46B/56B/66B. None of the input pins
incorporate pull-up and pull-down elements, so special care must be taken when designing to prevent a
floating status.
Output pins are high-level/low-level/high-impedance tri-state outputs. The TEST pin is disconnected from
the internal circuit by a switching transistor during normal operation. As long as the absolute maximum
rating is satisfied, the TEST pin and internal circuit will never be connected.
CMOS SERIAL E2PROM
S-93C46B/56B/66B Rev.3.1_01
Seiko Instruments Inc.
22
2.1 Input pin
CS
Figure 23 CS Pin
SK, DI
Figure 24 SK, DI Pin
TEST
Figure 25 TEST Pin
CMOS SERIAL E2PROM
Rev.3.1_01 S-93C46B/56B/66B
Seiko Instruments Inc. 23
2.2 Output pin
DO
Vcc
Figure 26 DO Pin
3. Input pin noise elimination time
The S-93C46B/56B/66B include a built-in low-pass filter to eliminate noise at the SK, DI, and CS pins. This
means that if the supply voltage is 5.0 V (at room temperature), noise with a pulse width of 20 ns or less can
be eliminated.
Note, therefore, the noise with a pulse width of more than 20 ns will be recognized as a pulse if the voltage
exceeds VIH/VIL.
Precaution
• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in
electrostatic protection circuit.
• SII claims no responsibility for any and all disputes arising out of or in connection with any infringement by
products including this IC of patents owned by a third party.
CMOS SERIAL E2PROM
S-93C46B/56B/66B Rev.3.1_01
Seiko Instruments Inc.
24
Characteristics
1. DC Characteristics
1.1 Current consumption (READ) ICC1
vs. ambient temperature Ta
1.2 Current consumption (READ) ICC1
vs. ambient temperature Ta
Ta (°C)
0.4
0.2
VCC = 5.5 V
fSK
=
2 MHz
DATA
=
0101
0 −40 0 85
ICC1
(mA)
Ta (°C)
0.4
0.2
VCC = 3.3 V
fSK = 500 kHz
DATA = 0101
0 −40 0 85
ICC1
(mA)
1.3 Current consumption (READ) ICC1
vs. ambient temperature Ta
1.4 Current consumption (READ) ICC1
vs. power supply voltage VCC
ICC1
(mA)
Ta (°C)
0.4
0.2
VCC = 1.8 V
fSK
=
10 kHz
DATA
=
0101
0 −40 0 85
1 MHz
∼
500 kHz
ICC1
(mA)
0.4
0.2
0 2 3 4 5 6 7
Ta = 25°C
fSK = 1 MHz, 500 kHz
DATA = 0101
VCC (V)
1.5 Current consumption (READ) ICC1
vs. power supply voltage VCC
1.6 Current consumption (READ) ICC1
vs. Clock frequency fSK
100 kHz
10 kHz
ICC1
(mA)
0.4
0.2
0 2 3 4 5 67
VCC (V)
Ta = 25°C
fSK = 100 kHz, 10 kHz
DATA = 0101
ICC1
(
mA
)
0.4
0.2
0
VCC = 5.0 V
Ta = 25°C
1 M 2M 10M 10 k 100 k
fSK (Hz)
CMOS SERIAL E2PROM
Rev.3.1_01 S-93C46B/56B/66B
Seiko Instruments Inc. 25
1.7 Current consumption (WRITE) ICC2
vs. ambient temperature Ta
1.8 Current consumption (WRITE) ICC2
vs. ambient temperature Ta
Ta (°C)
1.0
0.5
VCC = 5.5 V
0 −40 0 85
ICC2
(mA)
ICC2
(mA)
Ta (°C)
1.0
0.5
VCC = 3.3 V
0 −40 0 85
1.9 Current consumption (WRITE) ICC2
vs. ambient temperature Ta
1.10 Current consumption (WRITE) ICC2
vs. power supply voltage VCC
Ta (°C)
1.0
0.5
VCC = 2.7 V
0 −40 0 85
ICC2
(mA)
1.0
0.5
02 3 4 5 6 7
Ta
=
25°C
VCC (V)
ICC2
(mA)
1.11 Current consumption in standby mode ISB
vs. ambient temperature Ta
1.12 Current consumption in standby mode ISB
vs. power supply voltage VCC
Ta (°C)
1.0
0.5
VCC = 5.5 V
CS = GND
0 −40 0 85
ISB
(µA)
ISB
(µA)
1.0
0.5
02 3 4 5 6 7
Ta = 25°C
CS = GND
VCC (V)
CMOS SERIAL E2PROM
S-93C46B/56B/66B Rev.3.1_01
Seiko Instruments Inc.
26
1.13 Input leakage current ILI
vs. ambient temperature Ta
1.14 Input leakage current IL1
vs. ambient temperature Ta
1.0
0.5
VCC=5.5 V
CS, SK, DI,
TEST=0 V
0 -40 0 85
lL1
(µA)
Ta (°C)
Ta (°C)
1.0
0.5
0−40 085
VCC = 5.5 V
CS, SK, DI,
TEST = 5.5 V
ILI
(µA)
1.15 Output leakage current ILO
vs. ambient temperature Ta
1.16 Output leakage current ILO
vs. ambient temperature Ta
Ta (°C)
1.0
0.5
VCC = 5.5 V
DO = 0 V
0 −40 0 85
ILO
(µA)
Ta (°C)
1.0
0.5
VCC = 5.5 V
DO = 5.5 V
0 −40 0 85
ILO
(µA)
1.17 High-level output voltage VOH
vs. ambient temperature Ta
1.18 High-level output voltage VOH
vs. ambient temperature Ta
Ta (°C)
4.6
4.4
VCC = 4.5 V
IOH = −400 µA
−40 0 85
V
OH
(V)
4.2
Ta (°C)
2.7
2.6
VCC = 2.7 V
IOH = −100
µ
A
−40 085
V
OH
(V)
2.5
CMOS SERIAL E2PROM
Rev.3.1_01 S-93C46B/56B/66B
Seiko Instruments Inc. 27
1.19 High-level output voltage VOH
vs. ambient temperature Ta
1.20 High-level output voltage VOH
vs. ambient temperature Ta
Ta (°C)
2.5
2.4
VCC = 2.5 V
IOH
=
−100
µ
A
−40 0 85
VOH
(V)
2.3
Ta (°C)
1.9
1.8
VCC = 1.8 V
IOH = −10 µA
−40 0 85
VOH
(V)
1.7
1.21 Low-level output voltage VOL
vs. ambient temperature Ta
1.22 Low-level output voltage VOL
vs. ambient temperature Ta
Ta (°C)
0.3
0.2
VCC = 4.5 V
IOL
=
2.1 mA
−40 0 85
V
OL
(V)
0.1
Ta (°C)
0.03
0.02
VCC = 1.8 V
IOL
=
100
µ
A
−40 085
V
OL
(V)
0.01
1.23 High-level output current IOH
vs. ambient temperature Ta
1.24 High-level output current IOH
vs. ambient temperature Ta
Ta (°C)
−20.0
−10.0
VCC = 4.5 V
VOH = 2.4 V
0 −40 0 85
IOH
(mA)
Ta (°C)
−2
−1
VCC = 2.7 V
VOH = 2.4 V
0−40 0 85
IOH
(mA)
CMOS SERIAL E2PROM
S-93C46B/56B/66B Rev.3.1_01
Seiko Instruments Inc.
28
1.25 High-level output current IOH
vs. ambient temperature Ta
1.26 High-level output current IOH
vs. ambient temperature Ta
Ta (°C)
−2
−1
VCC = 2.5 V
VOH = 2.2 V
0 −40 0 85
IOH
(mA)
Ta (°C)
−1.0
−0.5
VCC = 1.8 V
VOH = 1.6 V
0
−40 0 85
IOH
(mA)
1.27 Low-level output current IOL
vs. ambient temperature Ta
1.28 Low-level output current IOL
vs. ambient temperature Ta
Ta (°C)
20
10
VCC = 4.5 V
VOL = 0.4 V
0 −40 0 85
IOL
(mA)
Ta (°C)
1.0
0.5
VCC = 1.8 V
VOL = 0.1 V
0−40 085
IOL
(mA)
1.29 Input inverted voltage VINV
vs. power supply voltage VCC
1.30 Input inverted voltage VINV
vs. ambient temperature Ta
3.0
1.5
0 1 2 3 4 5 6
Ta
=
25°C
CS, SK, DI
VCC (V)
VINV
(V)
7
Ta (°C)
3.0
2.0
VCC = 5.0 V
CS, SK, DI
0−40 085
VINV
(V)
CMOS SERIAL E2PROM
Rev.3.1_01 S-93C46B/56B/66B
Seiko Instruments Inc. 29
1.31 Low supply voltage detection voltage −VDET
vs. ambient temperature Ta
1.32 Low supply voltage release voltage +VDET
vs. ambient temperature Ta
Ta (°C)
2.0
1.0
0 −40 0 85
−VDET
(V)
Ta (°C)
2.0
1.0
0−40 0 85
+VDET
(V)
2. AC Characteristics
2.1 Maximum operating frequency fmax
vs. power supply voltage VCC
2.2 Write time tPR
vs. power supply voltage VCC
10k
2 3 4 5
Ta = 25°C
VCC (V)
f
max.
(Hz)
1
100k
1M
2M
4
2
234 56 7
Ta = 25°C
VCC (V)
tPR
(ms)
1
2.3 Write time tPR
vs. ambient temperature Ta
2.4 Write time tPR
vs. ambient temperature Ta
Ta (°C)
6
4
VCC = 5.0 V
−40 0 85
2
t
PR
(ms)
Ta (°C)
6
4
VCC = 3.0 V
−40 0 85
2
t
PR
(ms)
CMOS SERIAL E2PROM
S-93C46B/56B/66B Rev.3.1_01
Seiko Instruments Inc.
30
2.5 Write time tPR
vs. ambient temperature Ta
2.6 Data output delay time tPD
vs. ambient temperature Ta
Ta (°C)
6
4
VCC = 2.7 V
−40 0 85
2
t
PR
(ms)
Ta (°C)
0.3
0.2
VCC = 4.5 V
−40 0 85
0.1
tPD
(µs)
2.7 Data output delay time tPD
vs. ambient temperature Ta
2.8 Data output delay time tPD
vs. ambient temperature Ta
Ta (°C)
0.6
0.4
VCC = 2.7 V
−40 0 85
0.2
tPD
(µs)
Ta (°C)
1.5
1.0
VCC = 1.8 V
−40 085
0.5
tPD
(µs)
CMOS SERIAL E2PROM
Rev.3.1_01 S-93C46B/56B/66B
Seiko Instruments Inc. 31
Product Code Structure
1. 8-Pin DIP, 8-Pin SOP(JEDEC), 8-Pin TSSOP package
Package name (abbreviation) and IC packing specifications
D8S1: 8-Pin DIP, Tube
J8T1: 8-Pin SOP(JEDEC), Tape
J8T2: 8-Pin SOP(JEDEC), Tape, +105°C Max.supported
T8T1: 8-Pin TSSOP, Tape
T8T2: 8-Pin TSSOP, Tape, +105°C Max. supported
Operation temperature
I: −40 to +85°C
H: −40 to +105°C (Only 8-Pin SOP(JEDEC) , 8-Pin TSSOP)
Fixed
Pin assignment
D: 8-Pin DIP
8-Pin SOP(JEDEC)
8-Pin TSSOP
R: 8-Pin SOP(JEDEC) (Rotated)
Product name
S-93C46B : 1 K-bit
S-93C56B : 2 K-bit
S-93C66B : 4 K-bit
S-93CxxB x 0 x - xxxx
2. SNT-8A package
Fixed
Package name (abbreviation) and IC packing specifications
I8T1：SNT-8A, Tape
Fixed
Product name
S-93C46B：1 K-bit
S-93C56B：2 K-bit
S-93C66B：4 K-bit
S-93CxxB D0I - I8T1 G
No.
TITLE
SCALE
UNIT mm
Seiko Instruments Inc.
DIP8-F-PKG Dimensions
No. DP008-F-P-SD-3.0
DP008-F-P-SD-3.0
0.48±0.1
2.54
0.89 1.3
0° to 15°
0.25+0.11
-0.05
7.62
9.6(10.6max.)
14
5
8
No. FJ008-A-P-SD-2.1
No.
TITLE
SCALE
UNIT mm
SOP8J-D-PKG Dimensions
Seiko Instruments Inc.
FJ008-A-P-SD-2.1
0.4±0.05
1.27
0.20±0.05
5.02±0.2
14
85
No.
TITLE
SCALE
UNIT mm
5
8
1
4
ø2.0±0.05
ø1.55±0.05 0.3±0.05
2.1±0.1
8.0±0.1
5°max.
6.7±0.1
2.0±0.05
Seiko Instruments Inc.
Feed direction
4.0±0.1(10 pitches:40.0±0.2)
SOP8J-D-Carrier Tape
No. FJ008-D-C-SD-1.1
FJ008-D-C-SD-1.1
No.
TITLE
SCALE
UNIT mm
QTY. 2,000
2±0.5
13.5±0.5
60°
2±0.5
ø13±0.2
ø21±0.8
Seiko Instruments Inc.
Enlarged drawing in the central part
SOP8J-D-Reel
No. FJ008-D-R-SD-1.1
FJ008-D-R-SD-1.1
No.
TITLE
SCALE
UNIT mm
Seiko Instruments Inc.
TSSOP8-E-PKG Dimensions
No. FT008-A-P-SD-1.1
FT008-A-P-SD-1.1
0.17±0.05
3.00 +0.3
-0.2
0.65
0.2±0.1
14
5
8
No.
TITLE
SCALE
UNIT mm
Seiko Instruments Inc.
ø1.55±0.05
2.0±0.05
8.0±0.1 ø1.55 +0.1
-0.05
(4.4)
0.3±0.05
1
45
8
4.0±0.1
Feed direction
TSSOP8-E-Carrier Tape
No. FT008-E-C-SD-1.0
FT008-E-C-SD-1.0
+0.4
-0.2
6.6
No.
TITLE
SCALE
UNIT mm
Seiko Instruments Inc.
Enlarged drawing in the central part
No. FT008-E-R-SD-1.0
2±0.5
ø13±0.5
ø21±0.8
13.4±1.0
17.5±1.0
3,000
QTY.
TSSOP8-E-Reel
FT008-E-R-SD-1.0
1.97±0.03
0.2±0.05
0.48±0.02
0.08
No.
TITLE
SCALE
UNIT mm
Seiko Instruments Inc.
SNT-8A-A-PKG Dimensions
PH008-A-P-SD-1.0
No. PH008-A-P-SD-1.0
0.5
+0.05
-0.02
123 4
56
78
No.
TITLE
SCALE
UNIT mm
Seiko Instruments Inc.
PH008-A-C-SD-1.0
SNT-8A-A-Carrier Tape
No. PH008-A-C-SD-1.0
Feed direction
4.0±0.1
2.0±0.05
4.0±0.1
ø1.5 +0.1
-0
ø0.5±0.1
2.25±0.05
0.65±0.05
0.25±0.05
2134
7865
5°
12.5max.
9.0±0.3
ø13±0.2
(60°) (60°)
Enlarged drawing in the central part
QTY.
PH008-A-R-SD-1.0
No.
TITLE
SCALE
UNIT mm
Seiko Instruments Inc.
SNT-8A-A-Reel
No. PH008-A-R-SD-1.0
5,000
•
The information described herein is subject to change without notice.
• Seiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein
whose related industrial properties, patents, or other rights belong to third parties. The application circuit
examples explain typical applications of the products, and do not guarantee the success of any specific
mass-production design.
• When the products described herein are regulated products subject to the Wassenaar Arrangement or other
agreements, they may not be exported without authorization from the appropriate governmental authority.
• Use of the information described herein for other purposes and/or reproduction or copying without the
express permission of Seiko Instruments Inc. is strictly prohibited.
• The products described herein cannot be used as part of any device or equipment affecting the human
body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus
installed in airplanes and other vehicles, without prior written permission of Seiko Instruments Inc.
• Although Seiko Instruments Inc. exerts the greatest possible effort to ensure high quality and reliability, the
failure or malfunction of semiconductor products may occur. The user of these products should therefore
give thorough consideration to safety design, including redundancy, fire-prevention measures, and
malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.
