July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Am29LV065D
Data Sheet
Publication Number 23544 Revision BAmendment 0 Issue Date January 10, 2002
Publication# 23544 Rev: BAmendment/0
Issue Date: J anuar y 10, 2002
Refer to AMD
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sWebs
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te (www.amd.com) for the latest
i
nformat
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on.
Am29LV065D
64 Megabit (8 M x 8-Bit) CMOS 3.0 Volt-only
Uniform Sector Flash Memory w i th VersatileIOTM Control
DISTINCTIVE CHARACTERISTICS
■Single power supply operation
— 3.0 to 3.6 volt read, erase, and program operatio ns
■VersatileIOTM control
— Device generates output voltages and tolerates input
voltages on the DQ I/Os as determined by the voltage
on VIO input
■High performance
— Access times as fast as 90 ns
■Manufactured on 0.23 µm process technology
■CFI (Common F lash Interface) compliant
—Prov ides devic e -specific i nformation to the system,
allowing host software to easily rec onfigure for
different Flash devices
■SecSi (Secured Silicon) Sector region
—256-byte sector for permanent, secure identification
through an 16-byte random Electronic Serial Number
—May be programmed and locked at the factory or by
the customer
—Accessible through a command sequence
■Ultra low power consumption (typical values at 3.0 V ,
5 MHz)
—9 mA typical active read current
—26 mA typical er ase/program current
—200 nA typical standby mode current
■Flexible sector architecture
—One hundred twenty-eight 64 Kby te sectors
■Sector Protection
—A hardware method to lock a sector to prevent
program or erase operations within that sector
—Sectors can be locked in-system or via programming
equipment
—Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■Embedded Algorithms
—Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
—Embedded Program algorithm automatically writes
and verifies data at speci fied addresses
■Compatibility with JEDEC standards
—Pinout and software compatible with single-power
supply Flash
—Sup e rior inadvertent write protection
■Minimum 1 million erase cycle guarantee per secto r
■Package optio ns
—48-pin TSOP (standard or r e verse pinout)
—63-ball FBGA
■Erase Suspend/Erase Resume
—Suspends an erase operation to read data from, or
program data to, a sector that is not being erased,
then resumes the erase operation
■Data# Polling and toggle bits
—Provides a softw are method of detecting program or
erase operation completion
■Unlock Bypass Program command
—Reduces overall programming time when issuing
multiple program command sequences
■Ready/Busy# pin (RY/BY#)
—Provides a hardware method of detecting program or
erase cycle completion
■Hardware reset pin (RESET#)
—Hardware method to reset the device for reading array
data
■ACC pin
—Accelerates programming time for higher throughput
during system production
■Program and Erase Performance (VHH not applied to
the ACC in put pi n)
—Byte program time: 5 µs typical
—Sector erase time: 0.9 s typ ical for each 64 Kbyte
sector
■20-year data retention at 125°C
—Reliable operation for the life of the system
2 Am29LV065D January 10, 2002
GENERAL DESCRIPTION
The Am29LV065D is a 64 Mbit, 3.0 Volt (3.0 V to 3.6
V) single power supply flash memory dev ices orga-
nized as 8,388, 608 by tes. Data appears on DQ 0- DQ7.
The device is designed to be programmed in-system
with the standard system 3.0 volt VCC supply. A 12. 0
volt VPP is not required for program or erase opera-
tions. The device c an als o be programmed in standard
EPROM programmers.
The device off ers access times of 90, 100, and 120 ns.
The device is offered i n standar d or rever se 48-pi n
TSOP and 63-ball FBGA packages. To eliminate bus
contention each device has separate chip enable
(CE#), write enable (WE#) and output enable (OE#)
controls.
Each device requires on ly a single 3.0 Volt power
supply (3.0 V to 3.6 V) for both read and write func-
tions. Internally gene rated and regulated v oltages are
provided fo r the program and erase operations.
The devic e is entirely command set compatible with
th e JEDEC single-power-supply Flash standard.
Commands are written to the c ommand register using
standard microprocessor write timing. Register con-
tents serve as inputs to an internal state-machine that
controls the er ase and programming circuitry. Write
cycles also internally latch addresses and data
needed for the progr amming an d erase operations.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
Device programming occ ur s by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matica lly time s the p rogra m puls e widt hs a nd verif ies
proper cell m argin. Th e Unlock Bypass m ode facili-
tates faste r programmin g times by requiring on ly two
write cycles to program data instead of four.
Device erasure occurs by executing the erase com-
man d se quen ce. This ini tia tes t he Embedded E rase
algorithm—an i nternal algorithm that a utoma tically
preprograms the array (if it is not already pro-
grammed) befor e executing the er ase operation. Dur-
ing erase, the devic e automatical ly times the er ase
pulse widths and verifies proper cell margin.
The VersatileIO™ (VIO) control allows the host system
to set the voltage levels that the device generates and
tolerates on CE# and DQ I/Os to the same voltage
level that is asserted on VIO. VIO is ava ilable in two
configurations (1.8–2.9 V and 3.0–5.0 V) for operation
in various syst em e nvir on men ts .
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, by reading the DQ 7 (Data# Polling), o r DQ6 (tog-
gle) status bits. After a program or erase cycle has
been complet ed, the dev ic e is ready to read ar r ay dat a
or accept another command.
The sector erase architecture allows memory se c-
tors to be erased and reprogrammed without affecting
the data co ntents of ot her sector s. Th e devi ce is fu lly
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both progr am and erase
operations in any combination of sectors of memory.
This can be achieved in-syste m or vi a programm ing
equipment.
The Erase Suspend/Erase Resume fea ture enables
the user to put erase on hold for any period of time to
read data fro m, or progra m dat a to, any se ctor that is
not selected for erasure. True background erase can
thus be achieved.
The hardware RE SET# pin terminates any opera tion
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to
the system reset circuitry. A system reset would thus
also reset the device, enabling the system micropro-
cessor to read boot-up firmware from the Flash m em-
ory device.
The device offers a standby mode as a power-saving
feature. Once the system places the device into the
standby mode power consumption is greatly reduced.
The SecSiTM (Secu red Silicon) Sector provides an
minimum 256-byte area for code or data t hat can be
perm anently protec ted. Onc e th is sector is pro tected,
no further programming or erasing within the sector
can occur.
The accelerated program (ACC) feature allows the
system to program the device at a much faster rate.
When ACC is pulled high to VHH, the device enters the
Unlock Bypass mode, enabling the user to reduce the
time needed to do the program operation. This feature
is intend ed to inc rease fact ory throughpu t during sys-
tem production, but may also be used in the field if de-
sired.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunnelling.
The data is progr amm ed using hot electro n injection.
January 10, 2002 Am29LV065D 3
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Am29LV065D Device Bus Operations ................................9
VersatileIOTM (VIO) Control ........................................................ 9
Requirements for Reading Array Data ..................................... 9
Writing Commands/Command Sequences ............................ 10
Accelerated Program Operation ............................................. 10
Autoselect Functions .............................................................. 10
Standby Mode ........................................................................ 10
Automatic Sleep Mode ........................................................... 10
RESET#: Hardware Reset Pin ............................................... 10
Output Disable Mode .............................................................. 11
Table 2. Sector Address Table ........................................................11
Autoselect Mode ..................................................................... 15
Table 3. Am29LV065D Autoselect Codes, (High Voltage Method) 15
Sector Group Protection and Unprotection ............................. 16
Table 4. Sector Group Protection/Unprotection Address Table .....16
Temporary Sector Group Unprotect ....................................... 17
Figure 1. Temporary Sector Group Unprotect Operation................ 17
Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 18
SecSi (Secured Silicon) Sector Flash Memory Region .......... 19
Table 5. SecSi Sector Contents ......................................................19
Hardware Data Protection ......................................................19
Low VCC Write Inhibit ............................................................ 19
Write Pulse “Glitch” Protection ............................................... 20
Logical Inhibit .......................................................................... 20
Power-Up Write Inhibit ............................................................ 20
Common Flash Memory Interface (CFI). . . . . . . 20
Table 6. CFI Query Identification String.......................................... 20
System Interface String................................................................... 21
Table 8. Device Geometry Definition .............................................. 21
Table 9. Primary Vendor-Specific Extended Query ........................ 22
Command Definitions . . . . . . . . . . . . . . . . . . . . . 22
Reading Array Data ................................................................ 22
Reset Command ..................................................................... 23
Autoselect Command Sequence ............................................ 23
Enter SecSi Sector/Exit SecSi Sector
Command Sequence .............................................................. 23
Byte Program Command Sequence ....................................... 23
Unlock Bypass Command Sequence ..................................... 24
Figure 3. Program Operation .......................................................... 24
Chip Erase Command Sequence ........................................... 24
Sector Erase Command Sequence ........................................ 25
Erase Suspend/Erase Resume Commands ........................... 25
Figure 4. Erase Operation............................................................... 26
Command Definitions ............................................................. 27
Table 10. Am29LV065D Command Definitions ..............................27
Wri t e Op e ra tion S ta t u s . . . . . . . . . . . . . . . . . . . . . 2 8
DQ7: Data# Polling ................................................................. 28
Figure 5. Data# Polling Algorithm ................................................... 28
RY/BY#: Ready/Busy# ........................................................... 29
DQ6: Toggle Bit I .................................................................... 29
Figure 6. Toggle Bit Algorithm........................................................ 29
DQ2: Toggle Bit II ................................................................... 30
Reading Toggle Bits DQ6/DQ2 ............................................... 30
DQ5: Exceeded Timing Limits ................................................ 30
DQ3: Sector Erase Timer .......................................................30
Table 11. Write Operation Status ................................................... 31
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 3 2
Figure 7. Maximum Negative Overshoot Waveform ..................... 32
Figure 8. Maximum Positive Overshoot Waveform....................... 32
Operati ng Ran ge s . . . . . . . . . . . . . . . . . . . . . . . . 32
DC Cha ra c teristi c s . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 9. ICC1 Current vs. Time (Showing Active and
Automatic Sleep Currents)............................................................. 34
Figure 10. Typical ICC1 vs. Frequency............................................ 34
Test C onditions . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 11. Test Setup.................................................................... 35
Table 12. Test Specifications ......................................................... 35
Figure 12. Input Waveforms and Measurement Levels ................. 35
Key to Switching Waveforms. . . . . . . . . . . . . . . . 35
AC Cha ra c teristi c s . . . . . . . . . . . . . . . . . . . . . . . . 36
Read-Only Operations ...........................................................36
Figure 13. Read Operation Timings............................................... 36
Hardware Reset (RESET#) .................................................... 37
Figure 14. Reset Timings............................................................... 37
Erase and Program Operations .............................................. 38
Figure 15. Program Operation Timings.......................................... 39
Figure 16. Accelerated Program Timing Diagram.......................... 39
Figure 17. Chip/Sector Erase Operation Timings .......................... 40
Figure 18. Data# Polling Timings (During Embedded Algorithms). 41
Figure 19. Toggle Bit Timings (During Embedded Algorithms)...... 42
Figure 20. DQ2 vs. DQ6................................................................. 42
Temporary Sector Unprotect .................................................. 43
Figure 21. Temporary Sector Group Unprotect Timing Diagram ... 43
Figure 22. Sector Group Protect and Unprotect Timing Diagram .. 44
Figure 23. Alternate CE# Controlled Write
(Erase/Program) Operation Timings .............................................. 46
Erase And Programming Performance . . . . . . . 47
La t c h up Cha r a c te r is t i c s. . . . . . . . . . . . . . . . . . . . 47
TS O P Pin Ca pa c i t a nc e . . . . . . . . . . . . . . . . . . . . . 4 7
Dat a Ret e nti on. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 48
TS 048—48-Pin Standard Pinout Thin Small Outline
Package (TSOP) ..................................................................... 48
TSR048—48-Pin Reverse Pinout Thin Small Outline
Package (TSOP) ..................................................................... 49
FBE063—63-Ball Fine-Pitch Ball Grid Array (FBGA)
11 x 12 mm package .............................................................. 50
Revis ion Summary . . . . . . . . . . . . . . . . . . . . . . . . 51
Revision A (July 27, 2000) ...................................................... 51
Revision A+1 (August 4, 2000) ............................................... 51
Revision A+2 (August 14, 2000) ............................................. 51
Revision A+3 (August 25, 2000) ............................................. 51
Revision A+4 (October 19, 2000) ........................................... 51
Revision A+5 (November 7, 2000) ......................................... 51
Revision A+6 (November 27, 2000) ....................................... 51
Revision A+7 (March 8, 2001) ................................................ 51
Revision B (January 10, 2002) ............................................... 51
4 Am29LV065D January 10, 2002
PRODUCT SELECTOR GUIDE
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
Part Number Am29LV065D
Sp eed Option VCC = 3.0–3.6 V, VIO = 3.0–5.0 V 90R 120R
VCC = 3.0–3.6 V, VIO = 1.8–2.9 V 101R 121R
Max Access Time (ns) 90 100 120
CE# Access Time (ns) 90 100 120
OE# Access Time (ns) 35 35 50
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
VCC Detector
State
Control
Command
Register
VCC
VSS
WE#
ACC
CE#
OE#
STB
STB
DQ0–DQ7
Sector Switches
RY/BY#
RESET#
Data
Latch
Y-Gating
Cell Matrix
Address Latch
A0–A22
VIO
January 10, 2002 Am29LV065D 5
CONNECTION DIAGRAMS
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
40
25
39
38
37
36
35
34
33
32
31
48
47
46
45
44
43
42
41
30
29
28
27
26
A16
A5
A15
NC
A22
A14
A13
A12
A11
A9
A8
WE#
RESET#
ACC
RY/BY#
A18
A7
A6
A4
A3
A2
A1
NC
NC
A17
DQ0
VSS
NC
NC
NC
NC
A20
A19
A10
DQ7
DQ6
DQ5
OE#
VSS
CE#
A0
DQ4
VCC
VIO
A21
DQ3
DQ2
DQ1
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
40
25
39
38
37
36
35
34
33
32
31
48
47
46
45
44
43
42
41
30
29
28
27
26
A16
A5
A15
NC
A22
A14
A13
A12
A11
A9
A8
WE#
RESET#
ACC
RY/BY#
A18
A7
A6
A4
A3
A2
A1
NC
NC
A17
DQ0
VSS
NC
NC
NC
NC
A20
A19
A10
DQ7
DQ6
DQ5
OE#
VSS
CE#
A0
DQ4
VCC
VIO
A21
DQ3
DQ2
DQ1
48-Pin Standard TSOP
48-Pin Reverse TSOP
6 Am29LV065D January 10, 2002
CONNECTION DIAGRAMS
Special Hand lin g Instruc tio ns for FBGA
Package
Special handling is required f or Flash Memory products
in FBGA packages.
Flash memory devices in FBGA packages may be
damaged if exposed to ultrasonic cleaning methods.
The p ac kage an d /or da ta i nte gr i ty m ay be c omp ro mi sed
if the package body is exposed to temperatures above
150°C for prolonged per iods of tim e.
C2 D2
C3 D3
E2
E3
F2
F3
G2
G3
H2
H3
J2
J3
K2
A3 A4 A2 A1 A0 CE# OE# V
SS
A7 A18 A6 A5 DQ0 NC NC DQ1
RY/BY# ACC NC NC DQ2 DQ3 V
IO
A21
WE# RESET# A22 NC DQ5 NC V
CC
DQ4
A9 A8 A11 A12 A19 A10 DQ6 DQ7
A14 A13 A15 A16 A17 NC A20 V
SS
C4 D4 E4
A1 B1
A2
NC* NC*
NC*
F4 G4 H4 J4 K4
C5 D5 E5 F5 G5 H5 J5 K5
C6 D6 E6 F6 G6 H6 J6 K6
C7 D7 E7
NC*NC*
NC* NC*
A7 B7
A8 B8
F7 G7 H7 J7 K7
NC* NC*
NC* NC*
L7 M7
L8 M8
K3
L1
L2
M1
NC* NC*
NC* NC*
M2
* Balls are shorted together via the substrate but not connected to the die.
63-Ball FBGA
Top View, Balls Facing
Down
January 10, 2002 Am29LV065D 7
PIN DESCRIPTION
A0–A22 = 23 Addresses inputs
DQ0–DQ7 = 8 Data inputs/outputs
CE# = Chip Enable input
OE# = Output Enable input
WE# = Write Enable input
ACC = Acceleration In put
RESET# = Hardware Reset Pin input
RY/BY# = Ready/Busy output
VCC = 3.0 volt-only single power supply
(see Product Selector Guide for
speed options and voltage
supply tolerances)
VIO = Output Buffer power
VSS = Device Ground
NC = Pin Not Connected Internally
LOGIC SYMBOL
23 8
DQ0–DQ7
A0–A22
CE#
OE#
WE#
RESET#
RY/BY#
ACC
VIO
8 Am29LV065D January 10, 2002
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
offic e to confirm availabili ty of specific valid combinations and
to check on ne wly released combinations.
Am29LV065D U 90R WH I N OPTIONAL PROCESSING
Blank = Standard Processing
N = 16-byte ESN devices
(Contact an AMD repres entat i ve for more infor mati on)
TEM PERATU RE R A NGE
I = Industrial (–40°C to + 85 °C)
E = Extended (–55°C to +125°C)
PACKA GE TYPE
E = 48-Pin Standard Pinout Thin Small Outline Package (TS 048)
F = 48-Pin Reverse Pino ut Thin Small Outli ne Package (T SR0 48)
WH = 63-Ball Fine-Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 11 x 12 mm package (FBE063)
SPEED OPTION
See Product Selector Guide and Valid Combinations
SECTOR ARCHITECTURE
U = Uniform sector device
DEVI CE NUMBER/DESCRIPTION
Am29LV065D
64 Megabit (8 M x 8-Bit) CMOS Uniform Sector Flash Memory wi th VersatileIO Cont rol
3.0 Volt-only Read, Program, and E rase
Valid Combinations for TSOP
Packages Speed/VIO Range
AM29LV065DU90R,
AM29LV065DU90R EI, FI
90ns,
VIO = 3.0 V – 5.0 V
AM29LV065DU101R,
AM29LV065DU101R 100 ns,
VIO = 1.8 V – 2.9 V
AM29LV065DU120R,
AM29LV065DU120R EI, EE,
FI, FE
120 ns,
VIO = 3.0 V – 5.0 V
AM29LV065DU121R,
AM29LV065DU121R 120 ns,
VIO = 1.8 V – 2.9 V
Valid Combinations for FBGA Packages Speed/
VIO RangeOrder Number Package
Marking
AM29LV065DU90R WHI L065DU90R I
90 ns, VIO =
3.0 V – 5.0 V
AM29LV065DU101R L065DU01R 100 ns, VIO =
1.8 V – 2.9 V
AM29LV065DU120R WHI,
WHE
L065DU12R I,
E
120 ns, VIO =
3.0 V – 5.0 V
AM29LV065DU121R L065DU21R 120 ns, VIO =
1.8 V – 2.9 V
January 10, 2002 Am29LV065D 9
DEVICE BUS OPERATIONS
This section describes the r equirements and use of
the device bus operation s, which are initiated through
the internal command register. The command register
itself does not occupy any addressable m emory loca -
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
regis ter serve as inputs to t he intern al state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts an d cont rol levels they requir e, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Am29LV065D Device Bus Operations
Legend: L = Logic Low = V IL, H = Logic High = VIH, VID = 8. 5 –12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address,
AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addres ses are A22:A0. Sector addresses are A22:A16.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group
Protection and Unprotec tion” section.
3. All sectors are unprotected when shipped from the factory (The SecSi Sector may be factory protected depending on version
ordered.)
4. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
VersatileIOTM (VIO) Control
The VersatileIO ™ (VIO) control allows the host system
to set the voltage levels that the device generates and
tolerates on CE# and DQ I/Os to the same voltage
level that is asserted on VIO. VIO is ava ilable in two
configurations (1.8–2.9 V and 3.0–5.0 V) for operation
in various syst em e nvir on men ts .
For example, a VI/O of 4.5–5.0 volts allows for I/O at
the 5 volt level, driving and receiving signals to and
from other 5 V devices on the same data bus.
Requirements for Reading Array Data
To r ead arra y data from the outpu ts, the s ystem mus t
drive the CE# and OE# pins to VIL. CE# is th e power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH.
The internal stat e machine is set for reading ar ray data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
ma nd is nec ess ary in this mode to obta in array dat a.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
Operation CE# OE# WE# RESET# ACC Addresses
(Note 2) DQ0–
DQ7
Read L L H H XAIN DOUT
Wri te (Program /Era se) L H L H XAIN (Note 4)
Acce lera ted Pro g r a m L H L H VHH AIN (Note 4)
Standby VCC ±
0.3 V XXVCC ±
0.3 V HX High-Z
Output Disable L H H H XX High-Z
Reset X X X L XX High-Z
Sector Group Protect (Note 2) L H L VID XSA , A6 = L,
A1 = H, A0 = L (Note 4)
Sector Group Unprotect
(Note 2) LHL V
ID XSA, A6 = H,
A1 = H, A0 = L (Note 4)
Tem porary Sector Group
Unprotect XXX V
ID XAIN (Note 4)
10 Am29LV065D January 10, 2002
enabled for read access until the command register
contents are altered.
See “VersatileIOTM (VIO) Contro l” for more information.
Refer to the AC Read-Only Operations table for timing
specifications and to F igure 13 for the timing diagram.
ICC1 in the DC Characteristics table represents the ac-
tive current specifi ca tion for reading ar ra y data.
W ritin g Commands/Command Seque nces
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sec tors of m emo ry) , th e sys te m mus t d rive WE # an d
CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facil-
itate fast er progr amm ing. Once the device en ters th e
Unlock Bypass mode, only two write cycles are re-
quired to program a byte, instead of four. The “Byte
Program Command Sequence” section has details on
programming data to the device using both standard
and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple s ec-
tors , or the entire device. Table 2 indicat es the address
space that each sector occupies.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The AC
Characteristics section contains timing specification
tables and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This function is primarily in-
tended to allow faster manufacturing throughput dur-
ing system production.
If the system asserts VHH on this pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and us es the hi gher vo ltage o n the pi n to reduc e the
time required for program operations. The system
would use a two-c ycle program command sequence
as required by the Unlock Bypass mode. Removing
VHH from the ACC pin returns the device to normal op-
eration. Note that the A CC pin m ust not be at V HH for
operatio ns other t han acceler ated programming, or
device damage may result.
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from t he inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standar d read cycle timings apply in
this mode. Ref er to the A utoselect Mo de and Autos e-
lect Command Sequence sections for more informa-
tion.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby m ode when the
CE# and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more r estricted voltage range than
VIH. ) If CE# and RESET# are held at VIH, but n ot within
VCC ± 0.3 V, the device will be in the standby mode,
but the standby current will be greater. The device re-
quires standard access time (tCE) for read access
whe n th e dev ice is in eit her o f th ese st andb y m odes ,
before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
ICC3 in th e DC C haracteristics table represents the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode mi nimizes Flash device en-
ergy consumption. The device automatically enables
this m ode when addre sses remain sta ble for tACC +
30 ns. The automatic sleep m ode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and a lways available t o the system.
ICC4 in th e DC C haracteristics table represents the
automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting t he dev ice to reading array data. When t he RE -
SE T# pin is dr iven l ow fo r at le ast a p eriod of t RP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/wr ite comm ands for the du ration of t he RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.3 V, the device
draws CMOS s t andby c ur r ent (I CC4). If RESET# is held
at VIL but not within VSS±0.3 V, t he standby current will
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would t hus also reset t he Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
January 10, 2002 Am29LV065D 11
If RESE T# is as serted during a progr am or erase op -
eration, the RY/BY# p in remains a “0” (bu s y ) un ti l th e
internal reset o perat ion is complet e, whic h req uires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is
asserted when a program or er ase operation is not ex-
ecuting ( RY/BY# pin is “1”), the reset operation is com-
pleted within a time of tREADY (not during Embedded
Algorithms). The system can read data tRH after the
RESET# pin returns to VIH.
Refer to the AC Charac teristics tables for RESET# pa-
rameters and to Figure 14 for the timing diagr am.
Output Disable Mode
When the OE# in put is at VIH, output from the de vi ce is
disabled. The output pins are placed in the high
impedance state.
Table 2. Sector Address Table
Sector A22 A21 A20 A19 A18 A17 A16 8-bit Address Range
(in hexadecimal)
SA0 0 0 0 0 0 0 0 000000–00FFFF
SA1 0 0 0 0 0 0 1 010000–01FFFF
SA2 0 0 0 0 0 1 0 020000–02FFFF
SA3 0 0 0 0 0 1 1 030000–03FFFF
SA4 0 0 0 0 1 0 0 040000–04FFFF
SA5 0 0 0 0 1 0 1 050000–05FFFF
SA6 0 0 0 0 1 1 0 060000–06FFFF
SA7 0 0 0 0 1 1 1 070000–07FFFF
SA8 0 0 0 1 0 0 0 080000–08FFFF
SA9 0 0 0 1 0 0 1 090000–09FFFF
SA10 0 0 0 1 0 1 0 0A0000–0AFFFF
SA11 0001011 0B0000–0BFFFF
SA12 0 0 0 1 1 0 0 0C0000–0CFFFF
SA13 0 0 0 1 1 0 1 0D0000–0DFFFF
SA14 0 0 0 1 1 1 0 0E0000–0EFFFF
SA15 0001111 0F0000–0FFFFF
SA16 0 0 1 0 0 0 0 100000–10FFFF
SA17 0010001 110000–11FFFF
SA18 0 0 1 0 0 1 0 120000–12FFFF
SA19 0 0 1 0 0 1 1 130000–13FFFF
SA20 0 0 1 0 1 0 0 140000–14FFFF
SA21 0 0 1 0 1 0 1 150000–15FFFF
SA22 0 0 1 0 1 1 0 160000–16FFFF
SA23 0 0 1 0 1 1 1 170000–17FFFF
SA24 0 0 1 1 0 0 0 180000–18FFFF
SA25 0 0 1 1 0 0 1 190000–19FFFF
SA26 0 0 1 1 0 1 0 1A0000–1AFFFF
12 Am29LV065D January 10, 2002
SA27 0 0 1 1 0 1 1 1B0000–1BFFFF
SA28 0 0 1 1 1 0 0 1C0000–1CFFFF
SA29 0 0 1 1 1 0 1 1D0000–1DFFFF
SA30 0 0 1 1 1 1 0 1E0000–1EFFFF
SA31 0011111 1F0000–1FFFFF
SA32 0 1 0 0 0 0 0 200000–20FFFF
SA33 0 1 0 0 0 0 1 210000–21FFFF
SA34 0 1 0 0 0 1 0 220000–22FFFF
SA35 0 1 0 0 0 1 1 230000–23FFFF
SA36 0 1 0 0 1 0 0 240000–24FFFF
SA37 0 1 0 0 1 0 1 250000–25FFFF
SA38 0 1 0 0 1 1 0 260000–26FFFF
SA39 0 1 0 0 1 1 1 270000–27FFFF
SA40 0 1 0 1 0 0 0 280000–28FFFF
SA41 0 1 0 1 0 0 1 290000–29FFFF
SA42 0 1 0 1 0 1 0 2A0000–2AFFFF
SA43 0 1 0 1 0 1 1 2B0000–2BFFFF
SA44 0 1 0 1 1 0 0 2C0000–2CFFFF
SA45 0 1 0 1 1 0 1 2D0000–2DFFFF
SA46 0 1 0 1 1 1 0 2E0000–2EFFFF
SA47 0101111 2F0000–2FFFFF
SA48 0 1 1 0 0 0 0 300000–30FFFF
SA49 0 1 1 0 0 0 1 310000–31FFFF
SA50 0 1 1 0 0 1 0 320000–32FFFF
SA51 0 1 1 0 0 1 1 330000–33FFFF
SA52 0 1 1 0 1 0 0 340000–34FFFF
SA53 0 1 1 0 1 0 1 350000–35FFFF
SA54 0 1 1 0 1 1 0 360000–36FFFF
SA55 0 1 1 0 1 1 1 370000–37FFFF
SA56 0 1 1 1 0 0 0 380000–38FFFF
SA57 0 1 1 1 0 0 1 390000–39FFFF
SA58 0 1 1 1 0 1 0 3A0000–3AFFFF
SA59 0 1 1 1 0 1 1 3B0000–3BFFFF
SA60 0 1 1 1 1 0 0 3C0000–3CFFFF
SA61 0 1 1 1 1 0 1 3D0000–3DFFFF
Table 2. Sector Address Table (Continued)
Sector A22 A21 A20 A19 A18 A17 A16 8-bit Address Range
(in hexadecimal)
January 10, 2002 Am29LV065D 13
SA62 0 1 1 1 1 1 0 3E0000–3EFFFF
SA63 0111111 3F0000–3FFFFF
SA64 1 0 0 0 0 0 0 400000–40FFFF
SA65 1 0 0 0 0 0 1 410000–41FFFF
SA66 1 0 0 0 0 1 0 420000–42FFFF
SA67 1 0 0 0 0 1 1 430000–43FFFF
SA68 1 0 0 0 1 0 0 440000–44FFFF
SA69 1 0 0 0 1 0 1 450000–45FFFF
SA70 1 0 0 0 1 1 0 460000–46FFFF
SA71 1 0 0 0 1 1 1 470000–47FFFF
SA72 1 0 0 1 0 0 0 480000–48FFFF
SA73 1 0 0 1 0 0 1 490000–49FFFF
SA74 1 0 0 1 0 1 0 4A0000–4AFFFF
SA75 1 0 0 1 0 1 1 4B0000–4BFFFF
SA76 1 0 0 1 1 0 0 4C0000–4CFFFF
SA77 1 0 0 1 1 0 1 4D0000–4DFFFF
SA78 1 0 0 1 1 1 0 4E0000–4EFFFF
SA79 1001111 4F0000–4FFFFF
SA80 1 0 1 0 0 0 0 500000–50FFFF
SA81 1 0 1 0 0 0 1 510000–51FFFF
SA82 1 0 1 0 0 1 0 520000–52FFFF
SA83 1 0 1 0 0 1 1 530000–53FFFF
SA84 1 0 1 0 1 0 0 540000–54FFFF
SA85 1 0 1 0 1 0 1 550000–55FFFF
SA86 1 0 1 0 1 1 0 560000–56FFFF
SA87 1 0 1 0 1 1 1 570000–57FFFF
SA88 1 0 1 1 0 0 0 580000–58FFFF
SA89 1 0 1 1 0 0 1 590000–59FFFF
SA90 1 0 1 1 0 1 0 5A0000–5AFFFF
SA91 1 0 1 1 0 1 1 5B0000–5BFFFF
SA92 1 0 1 1 1 0 0 5C0000–5CFFFF
SA93 1 0 1 1 1 0 1 5D0000–5DFFFF
SA94 1 0 1 1 1 1 0 5E0000–5EFFFF
SA95 1011111 5F0000–5FFFFF
SA96 1 1 0 0 0 0 0 600000–60FFFF
Table 2. Sector Address Table (Continued)
Sector A22 A21 A20 A19 A18 A17 A16 8-bit Address Range
(in hexadecimal)
14 Am29LV065D January 10, 2002
Note: All sectors are 64 Kbytes in size.
SA97 1 1 0 0 0 0 1 610000–61FFFF
SA98 1 1 0 0 0 1 0 620000–62FFFF
SA99 1 1 0 0 0 1 1 630000–63FFFF
SA100 1 1 0 0 1 0 0 640000–64FFFF
SA101 1 1 0 0 1 0 1 650000–65FFFF
SA102 1 1 0 0 1 1 0 660000–66FFFF
SA103 1 1 0 0 1 1 1 670000–67FFFF
SA104 1 1 0 1 0 0 0 680000–68FFFF
SA105 1 1 0 1 0 0 1 690000–69FFFF
SA106 1 1 0 1 0 1 0 6A0000–6AFFFF
SA107 1 1 0 1 0 1 1 6B0000–6BFFFF
SA108 1 1 0 1 1 0 0 6C0000–6CFFFF
SA109 1 1 0 1 1 0 1 6D0000–6DFFFF
SA110 1 1 0 1 1 1 0 6E0000–6EFFFF
SA111 1101111 6F0000–6FFFFF
SA112 1 1 1 0 0 0 0 700000–70FFFF
SA113 1 1 1 0 0 0 1 710000–71FFFF
SA114 1 1 1 0 0 1 0 720000–72FFFF
SA115 1 1 1 0 0 1 1 730000–73FFFF
SA116 1 1 1 0 1 0 0 740000–74FFFF
SA117 1 1 1 0 1 0 1 750000–75FFFF
SA118 1 1 1 0 1 1 0 760000–76FFFF
SA119 1 1 1 0 1 1 1 770000–77FFFF
SA120 1 1 1 1 0 0 0 780000–78FFFF
SA121 1 1 1 1 0 0 1 790000–79FFFF
SA122 1 1 1 1 0 1 0 7A0000–7AFFFF
SA123 1 1 1 1 0 1 1 7B0000–7BFFFF
SA124 1 1 1 1 1 0 0 7C0000–7CFFFF
SA125 1 1 1 1 1 0 1 7D0000–7DFFFF
SA126 1 1 1 1 1 1 0 7E0000–7EFFFF
SA127 1111111 7F0000–7FFFFF
Table 2. Sector Address Table (Continued)
Sector A22 A21 A20 A19 A18 A17 A16 8-bit Address Range
(in hexadecimal)
January 10, 2002 Am29LV065D 15
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equip-
ment to automatically match a device to be pro-
grammed with its corresponding programming
algorithm. However, the autoselect codes can also be
accessed in-system through the command register.
When using programming equipment, the autoselect
mode requires VID ( 8.5 V t o 12.5 V) on addr es s pin A9.
Address pins A6, A1, and A0 must be as shown in
Table 3. In additio n, w hen v erifyi ng se ctor protec tion ,
the sector ad dress mus t appear on the appropriate
highest order address bits (see Table 2). Table 3
show s the rem aining ad dress bit s that are don’t care.
When all necessary bits have been set as required,
the programming equipment may then read the corre-
sponding identifier c ode on DQ7–DQ0.
To ac cess the au toselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Ta bl e 10. This method
does not require VID. Refer to the Autoselect Com-
mand Sequence section for more information.
Table 3. Am29LV065D Autoselect Codes, (High Voltage Method)
Legend: L = Logic Low = VIL, H = Logic H igh = VIH, SA = Sector Address, X = Don’t ca re.
Description CE# OE# WE#
A22
to
A16
A15
to
A10 A9
A8
to
A7 A6
A5
to
A2 A1 A0 DQ7 to DQ0
Manufacturer ID: AMD L L H X X VID XLXLL 01h
Device ID: Am29LV065D L L H X X VID XLXLH 93h
Sector Protection
Verification LLHSAXV
ID XLXHL 80h (protected),
00h (unprotected)
SecSi Sector Indicator Bit
(DQ7) LLH X XV
ID XLXHH 90h (factory lock ed),
10h (not factory locked)
16 Am29LV065D January 10, 2002
Sector Group Protection and
Unprotection
The hardware sector group pr otection feature disables
both program and erase operations in any sector
group. In this device, a sector group consists of four
adjac ent se ctor s tha t ar e pr otec ted or unpr otecte d at
the same time (see Table 4). The hardware sector
group unprotection feature re- enables both program
and erase operations in previously protected sector
groups. Sector group protection/unprotection can be
implemented via two methods.
Sector protection and unprotection requires VID on t he
RESET# pin only, and can be implemented either
in-system or via programming equipment. Figure 2
shows the algor ithms and Figure 2 2 shows the timing
diagram. This method uses standard microprocessor
bus cycle timing. For sector group unprotect, all unpro-
tected sector groups must first be protected prior to
the first sector group unprotect write cycle.
The device is shipped with all sector gro ups unpro -
tected. AMD offers the option of programming and
protecting sector groups at its factory prior to shipping
the device through AMD’s ExpressFlas h™ Servic e.
Contact an AMD representative for detail s.
It is possible to determine whether a sector group is
protected or unpr otected. See the A utoselect Mode
section for details.
Table 4. Sector Group Protection/Unprotection
Address Table
Note: All sector groups are 256 Kbytes in size.
Sector Group A22–A18
SA0–SA3 00000
SA4–SA7 00001
SA8–SA11 00010
SA12–SA15 00011
SA16–SA19 00100
SA20–SA23 00101
SA24–SA27 00110
SA28–SA31 00111
SA32–SA35 01000
SA36–SA39 01001
SA40–SA43 01010
SA44–SA47 01011
SA48–SA51 01100
SA52–SA55 01101
SA56–SA59 01110
SA60–SA63 01111
SA64–SA67 10000
SA68–SA71 10001
SA72–SA75 10010
SA76–SA79 10011
SA80–SA83 10100
SA84–SA87 10101
SA88–SA91 10110
SA92–SA95 10111
SA96–SA99 11000
SA100–SA103 11001
SA104–SA107 11010
SA108–SA111 11011
SA112–SA115 11100
SA116–SA119 11101
SA120–SA123 11110
SA124–SA127 11111
January 10, 2002 Am29LV065D 17
Temporary Sect or Group Unprotect
(Note: In this device, a sector gr oup consists of four adjacent
sectors that are protected or unprotected at the same time
(see Table 4)).
This feature allows temporary unprotection of previ-
ously protected sector groups to change data in-sys-
tem. The Sector Group Unprotect mode is activated by
setting the RESET# pin to VID (8.5 V – 12.5 V). During
this mode, f ormerly protec ted sector gr oups can be
prog ram med or era sed by sele cting th e se ctor gr oup
addre sses . Once V ID is removed from the RESET#
pin, all the previously protected sector groups are
protected again . Figure 1 shows th e algorithm, and
Figure 21 shows the timing diagrams, for this feature.
Figure 1. Temporary Sector Group
Unprotect Operation
START
Perfor m Erase or
Program Operations
RESET# = VIH
Temporar y Sector
Group Unprotect
Completed (Note 2)
RESET# = VID
(Note 1)
Notes:
1. All protected sector groups unprotected.
2. All previously protected sector groups are protected
once again.
18 Am29LV065D January 10, 2002
Figure 2. In-System Sector Group Protect/Unprotect Algorithms
Sector Group Protect:
Write 60h to sector
group address with
A6 = 0, A1 = 1,
A0 = 0
Set up sector
group address
Wait 150 µs
Verify Sector Group
Protect: Write 40h
to sector group
address twith A6 = 0,
A1 = 1, A0 = 0
Read from
sector group address
with A6 = 0,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = VID
Wait 1 µs
First Write
Cycle = 60h?
Data = 01h?
Remove VID
from RESET#
Write reset
command
Sector Group
Protect complete
Yes
Yes
No
PLSCNT
= 25?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Group Unprotect
Mode
No
Sector Group
Unprotect:
Write 60h to sector
group address with
A6 = 1, A1 = 1,
A0 = 0
Set up first sector
group address
Wait 15 ms
Verify Sector Group
Unprotect: Write
40h to sector group
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector group
address with A6 = 1,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = VID
Wait 1 µs
Data = 00h?
Last sector
group
verified?
Remove VID
from RESET#
Write reset
command
Sector Group
Unprotect complete
Yes
No
PLSCNT
= 1000?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Group Unprotect
Mode
No All sector
groups
protected?
Yes
Protect all sector
groups: The indicated
portion of the sector
group protect algorithm
must be performed for all
unprotected sector
groups prior to issuing
the first sector group
unprotect address
Set up
next sector group
address
No
Yes
No
Yes
No
No
Yes
No
Sector Group
Protect
Algorithm
Sector Group
Unprotect
Algorithm
First Write
Cycle = 60h?
Protect
another
sector group?
Reset
PLSCNT = 1
January 10, 2002 Am29LV065D 19
SecSi (Secured Silicon) Sector Flash
Memory Region
The SecSi (Secured Sili con) Sector feature provides a
Flash memory region that enables permanent part
identification through an Electronic Serial Number
(ESN). The SecSi Sector is 256 bytes in length, and
uses a SecSi Sec tor Indicator Bit (DQ7) to indicate
whether or not the SecSi Sector is locked when
shipped from the factory. This bit is permanently set at
the factory and cann ot be chang ed, which prevents
cloning of a fact ory locked part. Thi s ensures the secu-
rity of the ESN once t he product i s shipped t o the fiel d.
AMD offers th e device with the SecSi Sector either
factory locked or customer lockable. The fac-
tory-locked version is always protected when shipped
from the f actor y, and h as the S ecSi (Se cured Silic on)
Sector Indicator Bit permanently set to a “1.” The cus-
tomer-lockable version is shipped with the SecSi Sec-
tor unprotected, allowing customers to utilize that
sector in any manner they choose. T he customer-lock-
able version als o has the SecSi Sector Indicator Bit
permanently set to a “0.” Thus, the SecSi Sector In di-
cator Bit prevents customer-lockable devices from
being used to replace devices that are factory locked.
The SecSi sector address space in this device is allo-
cated as follows:
The system accesses the SecSi Sector through a
command sequence (see “Enter SecSi Sector/Exit
SecSi Sector Command Sequence”). Aft er t h e sys tem
has written the Enter SecSi Sector command se-
quence, it may read the SecSi Sector by using the ad-
dr ess es no rmal ly occ upie d by th e first sector ( SA0).
This m ode of ope ration cont inues until t he sys tem is -
sues the E xit SecSi S ector co mman d sequence, or
until power is removed from the device. On power-up,
or followin g a hardware reset, the d evice rev erts to
sendin g commands to sector SA0.
Factory Locked: SecSi Sector Programmed and
Protected At the Factory
In devices with an ESN, the SecSi Sector is protected
when the device is shipped from the fa cto ry. The Sec Si
Sector cannot be modified in any way. A factory locked
device has an 16-byte random ESN at addresses
000000h–00000Fh.
Customers may opt to have their code programmed by
AMD through the AMD ExpressFlash service. The de-
vices are the n shipped from AMD’s factor y with the
SecSi Sector permanently locked. Contact an A MD
representative for details on using AMD’s Express-
Flash service.
Customer Lockable: SecSi Sector NOT
Programmed or Protected At t he Factory
As an alternative to the factory-locked version, the de-
vice may be ordered such that the customer may pro-
gram and protect the 256-byte SecSi sector. The
SecSi Sector is one-time programmable, may not be
erased, and can be locked only once. Note that the ac-
celerated programming (ACC) and unlock bypass
functions are not available when programming the
SecSi Sector.
The SecSi Sector area can be pro tected using one of
the following procedures:
■Write the three-cycle Enter SecSi Sector Region
command sequence, and then follow the in-system
sector protect algorithm as shown in Figure 2, ex-
cept that RE SET# may be at either VIH or V ID. Thi s
allows in-system protection of the SecSi Sector
without raising any device pin to a high voltage.
Note that this method is only applicable to the SecSi
Sector.
■Write the three-cycle Enter SecSi Sector Region
command sequence, and then use the method of
sector protection described in the “Sector Group
Protection and Unprotection” section.
The SecSi Sector is one-tim e programmable . Once
the Sec Si Sector is pr ogrammed, locked and ver ified,
the system must write the Exit SecSi Sector Region
command sequence to return to reading and writing
the remainder of the array.
The SecS i Sector protection must be used with cau-
tion since, once pr otected, there is no pr oc edur e ava il-
able for unpr otecting the SecSi S ector area and none
of the bits in the SecSi Sector memory space can be
modified in any way.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 10 for com-
man d def initio ns). I n ad ditio n, th e follow ing hard ware
dat a pr otec tion mea sur es pre vent ac ciden tal er asu re
or programming, which mi ght otherwise be caused by
spurious system level signals during VCC power-up
and power-down transitions, or from system noise.
Low VCC W r ite Inhi bit
When VCC is less than VLKO, the d evic e does no t ac -
cept any write cycles. This protects data during VCC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to the read mode. Subsequent
Table 5. SecSi Sector Contents
SecSi Sector
Address Range Standard
Factory Loc ked ExpressFlash
Factory Locked Customer
Lockable
000000h–00000Fh ESN ESN or
determined by
customer Determined by
customer
000010h–00007Fh,
000400h–00047Fh Unavailable Determined by
customer
20 Am29LV065D January 10, 2002
writes are ig nored unti l VCC is greate r t han VLKO. Th e
system m ust prov ide the pr oper sig nals to t he contr ol
pins to prevent unintentional writes when VCC is
greater than VLKO.
Write Pulse “Glitch” Protectio n
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiat e a wr ite cy cle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up,
the device does not accept commands on the rising
edge of WE#. The intern al state machine is aut omati-
cally reset to the read m ode on power-up.
COMMON FLASH MEMORY INTERFACE (CF I )
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-indepe ndent, and forwar d- and
backward- compa tible fo r the specified flash devic e
families . Flas h vendo rs can s tand ardize t heir existin g
interfaces for long-term compatibility.
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, any time the
device is r eady to read array data (addr esses are don’t
care). The system can read CFI information at the ad-
dresses given in Tables 6–9. To terminate reading CFI
data, the s ystem must write the reset command.
The system can als o write the CFI qu ery command
when the device is in the autoselect mode. The device
ent ers the CFI qu ery mode , and the syst em ca n read
CFI data at the addresses given in Tables 6–9. The
system must write the reset c ommand to return the de-
vice to the autoselect mode.
For further information, pleas e refer to the CFI Specifi-
cation and CFI Publication 100, available via the
World Wide Web at http://www.amd.com/prod-
ucts/n vd/overview/cfi.html. Alternatively, c ontact an
AMD representative for copies of these documents.
Table 6. CFI Query Identification String
Addresses (x8) Data Description
10h
11h
12h
51h
52h
59h Query Unique ASCII string “QRY”
13h
14h 02h
00h Primary OEM Command Set
15h
16h 40h
00h Address for Primary Extended Table
17h
18h 00h
00h Alternate OEM Command Set (00h = none exists)
19h
1Ah 00h
00h Address for Alternate OEM Extended Table (00h = none exists)
January 10, 2002 Am29LV065D 21
Table 7. System Interface String
Table 8. Device Geometry Definition
Addresses (x8) Data Description
1Bh 27h VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch 36h VCC Max. (write/erase )
D7–D4: volt, D3–D0: 100 millivolt
1Dh 00h VPP Min. voltage (00h = no VPP pin present)
1Eh 00h VPP Max. voltage (00h = no VPP pi n present)
1Fh 04h Typical timeout per single byte write 2N µs
20h 00h Typical timeout for Min. size buffer wri te 2 N µs (00h = not supported)
21h 0Ah Typical timeout per individual block erase 2N ms
22h 00h Typical timeout for full chip erase 2N ms (00h = not suppo rted)
23h 05h Max. timeout for byte write 2N times typical
24h 00h Max. timeout for buffer write 2N times typical
25h 04h Max. timeout per individual block erase 2N times typical
26h 00h Max. timeout for full chip erase 2N times typical (00h = not supported)
Addresses (x8) Data Description
27h 17h Device Size = 2N byte
28h
29h 00h
00h Flash Device Interface descr iption (refer to CFI publication 100)
2Ah
2Bh 00h
00h Max. number of bytes in mul ti-byte write = 2N
(00h = not supported)
2Ch 01h Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
7Fh
00h
00h
01h
Eras e Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
00h
00h
00h
00h
Eras e Block Region 2 Information (refer to CFI publication 100)
35h
36h
37h
38h
00h
00h
00h
00h
Eras e Block Region 3 Information (refer to CFI publication 100)
39h
3Ah
3Bh
3Ch
00h
00h
00h
00h
Eras e Block Region 4 Information (refer to CFI publication 100)
22 Am29LV065D January 10, 2002
Table 9. Primary Vendor-Specific Extended Query
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences int o the command register initi ates device op-
erations. Table 10 defines the valid register command
sequenc es. Writing incorrect add ress an d data val -
ues or writing them in the improper sequence re sets
the device to reading array data.
All a ddre sses are l atc hed o n th e falli ng edge of WE#
or CE#, whichever happens later. All data is lat ched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the AC Characteristics section for timing
diagrams.
Reading Array Data
The device is automatically set to reading array data
after device pow er-up. No co mma nds are requir ed t o
retrieve data. The device is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
After the dev ic e ac c epts an Erase Suspend command,
the device enters the er ase-suspend-read mode, after
which the system can read data from any
non -era se- suspe nde d se ctor. Aft er co m pleting a pro -
gramming operatio n in the Erase Suspe nd mode, the
system may once again read array data with the same
exception. See the Erase Suspend/Erase Resume
Commands section for more information.
The system must issue the reset command to re turn
the device t o the re ad (or erase-s uspend -read) m ode
if DQ5 goes high during an active program or erase
operation, or if the device is in the autoselect mode.
See the next sect ion, Reset Command, for more i nfor-
mation.
Addresses (x8) Data Description
40h
41h
42h
50h
52h
49h Query-u n ique ASCII string “PRI”
43h 31h Major version number, ASCII
44h 31h Minor version number, ASCII
45h 01h Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
Silicon Revision Number (Bits 7-2)
46h 02h Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h 04h Sector Protect
0 = Not Supported, X = Number of sectors in per group
48h 01h Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h 04h Sector Protect/Unprotect scheme
04 = 29LV800 mode
4Ah 00h Simultaneous Operation
00 = Not Supported, X = Number of Sectors in Bank
4Bh 000h Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch 00h Page Mode Type
00 = Not Su pported
4Dh B5h ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
4Eh C5h ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
4Fh 00h Top/Bottom Boot Sector Flag
02h = Bottom Boot Device, 03h = Top Boot Device
January 10, 2002 Am29LV065D 23
See also “VersatileIOTM (VIO) C ontro l” in the De vice
Bus Operations section for more information. The
Read-Only O perations table provides the read param-
eters , and Figure 13 shows the timing diagram.
Reset Command
Writing the reset comm and resets the device to th e
read or erase-suspend-read mode. A ddress bits are
don’t cares for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to the read
mode. Once erasure begins, however, the device ig-
nores reset commands until t he operation is complet e.
The reset command may be written between the
seque nce cycles in a pro gram com mand sequenc e
before programming b egins. This resets the dev ice to
the read m ode. If th e program c omman d sequence is
writte n while the device is in t he Erase Suspend mode,
writing the reset command returns the device to the
erase-sus pend-rea d mode. Onc e prog ram ming be -
gins, however, the device ignores reset commands
until th e operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be w ritten to retu rn to the rea d mode. If the de-
vice entered the autoselect mode while in the Erase
Suspend mode, writing the r es et com man d re turns the
device to the erase-suspend-read mode .
If DQ5 goes high during a pr ogr am or erase oper ation,
writing the reset command returns the device to the
read mode (or erase-suspend-read mode if the device
was in Erase Suspend).
Autoselect Command Sequence
The autoselect comm and sequence allows the h ost
system to read severa l identifier codes at specific ad -
dresses:
Table 10 shows the address and data requirements.
The command sequence is an alternative to the high
voltage method sh own in Table 3. The autoselect com-
man d s equen ce may b e writte n to an ad dress that is
either in the read or erase-suspend-read mode. The
autoselect command may not be written while the de-
vice is actively programming or erasing.
The autoselect command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write c y cle that c ontains the autos elec t com mand. The
device then enters t he autoselect mode. The system
may read at any address any number of times without
initiating another aut oselect command sequence.
The system must write the reset command to ret ur n to
the read mode ( or er as e- s uspen d-read mode if the de-
vice was previously in Erase Suspend).
Enter SecSi Sector/Exit SecSi Sector
Command Sequence
The SecSi Sector regi on pr ovi des a secured dat a ar ea
con tainin g an 16 -byte r andom Elect ronic Se rial Nu m-
ber (ESN). The system can access the SecSi Sector
region by issuing the three-cycle Enter SecSi Sector
com mand seq uence. The dev ice c ontinues to ac cess
the Sec Si Sector region until the system issues the
four-cycle Exit SecSi Sector command sequence. The
Exit SecSi Sector command sequence returns the de-
vic e to nor mal op eration . Tabl e 10 shows the address
and data requirements for both command sequenc es.
See also “SecSi (Secured Silicon) Sector Flash
Memory Region” for further information.
Byte Program Command Sequenc e
Programming is a four-bus-cycle operation. The pro-
gram com mand sequence is initiated b y writing two
unlock w rite cycles, followed by the program set-up
command. The program addre ss and data are w ritten
next, which in turn initiate the E mbedded Pro gram al-
go rith m. The sy stem is not required to pr ovide further
controls or timings. The device automatically provides
internally generated program pulses and verifies the
pro gramm ed cell m argin. Table 10 shows the address
and data requirements for the byte program command
sequence.
Wh en the Em bedde d Prog ram algor ithm is c omple te,
the device then returns to the read mode and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using
DQ7, DQ6, or RY/BY#. Refer to the Write Operation
Status section for information on these status bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
ha rdw are r eset imm edia tely ter mina tes th e prog ram
operation. The program command sequence should
be reinitiated once the device has returned to the read
mode, to ensure data integrity.
Pr ogramm ing is allowe d in any seque nce an d acros s
sector boundaries. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may
cause the device to set DQ5 = 1, or cause the DQ7
and DQ6 status bits to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0.” Only erase operations can convert a
“0” to a “1.”
Identifier Code Address
Manufacturer ID 00h
Device ID 01h
SecSi Sector Factory Prot ect 03h
Sector Group Protect Verify (SA)02h
24 Am29LV065D January 10, 2002
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to p ro-
gram bytes to the dev ice faster than using the stan-
dard program command sequence. The unlock
bypass com mand sequenc e is initiated b y first writing
two unlock cycles. This is followed by a third write
cycle con taining the un lock bypass comm and, 20h.
The device then enters t he unlock by pass mode. A
two-cycle unlock bypass program command seq uence
is all that is required to program in this mode. The first
cycle in thi s sequence contains the unlock bypass pro-
gram command, A0h; the se cond cycle contains the
program address and data. Additional data is pro-
grammed in the same manner. This mode dispenses
with the in itial two unloc k cyc les requ ired i n the s tan-
dard p rogra m comm and s equenc e, res ulting in faster
total programming time. Table 10 shows the require-
ments for the command sequence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must is sue the two- cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h. The second cy cl e must contain the data 00h. The
device then returns to the read mode.
The device offers accelerated program operations
through the ACC pin. When the system asserts VHH on
the ACC pin, the device automatically enters the Un-
lock Bypass mode. The system may then write the
two-cycle Unlock Bypass program command se-
quenc e. The de vice u ses the h igher volta ge on th e
ACC pin to accelerate the operation. Note that the
ACC pin m ust not be at VHH for operations other than
accele rated pr ogrammin g, or device da mage m ay re -
sult.
Figure 3 illustrates the algorithm for the program oper-
ation. Refer to the Erase and Program Operations
table in the AC Characteristics section for parameters,
and Figure 15 for timing diagrams.
Figure 3. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algo rith m. The de vic e does not requir e the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 10
shows the address and data requirements for the chip
erase command sequence.
START
Write Program
Command Sequence
Data Poll
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
Note: See Table 10 for program command sequence.
January 10, 2002 Am29LV065D 25
When the Embedded Erase algorithm is complete, the
device ret ur ns to the read m ode and addr es s es are no
longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY# . Refer to the Write Opera tion S tatus se ction
for information on these status bits.
Any commands writt en during the chip erase oper ation
are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that oc-
curs, the c hip erase command se quence should b e
rein itiated once th e devic e has return ed to readin g
array dat a, to ensure dat a integrity.
Figure 4 illus trates the algor ithm fo r th e era se op era-
tion. Refer to the Erase and Program O perations ta-
bles in the AC Charact eristics section for parameters,
and Figure 17 section for timing diagrams .
Sector Erase Command Sequen ce
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a s et-up com man d. Two ad-
ditional unlock cycles are w ritten, and are then fo l-
lowed b y t he add ress of the s ect or to b e eras ed, an d
the sector erase command. Table 10 shows the ad-
dress and data requirements for the sect or erase com-
mand sequence.
The devic e does not requir e the system to pr epr ogram
prior to erase. The Embedded Erase algorithm auto-
matically progra ms and verifies the entire m emory for
an al l zer o data patt ern pr ior to el ectri cal er ase . The
syst em i s not requ ired to p rovide an y cont rols o r tim-
ings during these operati ons.
After the command sequence is writ ten, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addre sses and sector erase com -
mands may be written. Loa ding the sect or er as e buffer
may be done i n any sequenc e, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise era sure may begin. Any s ector erase
address and command following the exceeded
time-out may or may not be accepted. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector
Erase c om mand is wr itten. An y command other than
Sector Erase or Erase Suspend during the
time-out period resets the device to the read
mode. The system must rewrite the command se-
quence and any additional addresses and commands.
The sys tem can monitor D Q3 to deter mine if t he sec-
tor erase timer has timed out (S ee the section on DQ3:
Sector Erase Timer.). T he time-out begins f r om the ris-
ing edge of the final WE# pulse in the command
sequence.
When the Embedded Erase algorithm is complete, the
device returns to rea ding array data and add resses
are no lon ger la tch ed. Not e that while the Embedd ed
Erase operation is in progress, the system can r ead
data from the non-erasing sector. The system can de-
termine the status of the erase operation by reading
DQ7, DQ6, DQ2, or RY/BY# in the erasing sector.
Refer to the Write Operation Status section for infor-
mation on these status bits.
On ce th e sec tor e rase oper ati on ha s beg un, only the
Erase Suspend command is valid. All other com-
mands are ignored. However, note that a hardware
reset immediately terminates the erase operation. If
that occurs, the sector erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
Fi gure 4 illus trates the algori thm f or the eras e ope ra-
tion. Refer to the Erase and Program Operations ta-
bles in the AC Ch aracteristics section for para meters,
and Figure 17 section for timing diagram s.
Erase Suspend/Erase Resume
Commands
The Erase Suspend command, B0h, allows the sys-
tem to interrupt a sector er ase operation and then r ead
data from, or program data to, any sector not selected
for er asure. Thi s com man d is va lid only during the
sector erase operation, including the 50 µs time-out
period during the sector erase command sequence.
The Erase Suspend command is ignored if written dur-
ing the chip erase operation or Embedded Program
algorithm.
W hen the Er ase S usp end c omman d is writ ten d uring
the sector erase operation, the device requires a max-
imu m o f 20 µs to su spen d t he er ase oper at ion. H ow -
ever, when the Erase Suspend command i s written
during the sector erase time-out, the device immedi-
ately terminates the time-out period and suspends the
erase operation.
After the erase o peration has b een suspen ded, the
device enters the erase-suspend- r ead mode. The sys-
tem can read data from or program data to any sector
not selected for erasure. (The device “erase sus-
pends” all sectors selected for erasure.) Reading at
any address within erase-suspended sectors pro-
duces status information on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
Refer to the Write Operation Status section for infor-
mation on these status bits.
Aft er an erase-s uspen ded pr ogram oper ation is com-
plete, the device returns to the erase-suspend-read
mo de. T he sy stem can determine the status of the
prog ram o peration using the D Q7 or D Q6 s tatus bit s,
just as in the standard byte program operation.
26 Am29LV065D January 10, 2002
Refer to the Write Operation Status section for more
information.
In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. Refer to the
Autosel ect Mode and Autosele ct Command Sequence
sections for details.
To resume the sector erase operation, the system
must write the Erase Resume command. The address
of th e er ase- suspe nd ed s ector is req ui red w hen writ -
ing this command. Further writes of the Resume com-
mand are ignored. Anot her Erase Suspend com mand
can be written after the chip has resumed erasing.
Figure 4. Erase Operation
START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
Data = FFh?
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
Notes:
1. See Tabl e 10 for erase command sequence.
2. See th e section on DQ3 for information on the sector
erase timer.
January 10, 2002 Am29LV065D 27
Co mmand Definitions
Table 10. Am29LV065D Command Definitions
Legend:
X = Don’t care
RA = Address of the m em ory loca ti on to be re ad.
RD = Data read from locati on RA during read oper ation.
PA = A ddres s of the memory locatio n to be progr amme d. Address e s
latch on the falling edge of the WE# or CE# pulse, whichever happens
later.
PD = Data to be programmed at location PA. Data latches on t he ri sing
edge of WE# or CE# puls e, whichever ha ppens first.
SA = Addres s of the sector to be v erified (in autoselect mo de) or
erased. Address bi ts A22–A16 uniquely select any sector.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the four th cycle of the autoselect
command sequence, all bus cycl es are write cycles.
4. Unless otherwise noted, address bits A22–A12 are don’t cares.
5. No unlock or command cycles required when device is in read
mode.
6. The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when the device is in the autosel ect mode, or if DQ5 goes high
(while the device is providing status information).
7. The fourth cycle of the autoselect command sequence is a read
cycle. See the Autoselect Command Sequence section for more
information.
8. The data is 80h for fact ory locked and 00h for not fact ory l ocked.
9. The data is 00h for an unprotected sector group and 01h for a
protected sector group.
10. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
11. The Unlock Bypass Reset command is required to return to the
read mode when the device is in the unl ock bypass mode.
12. The system may read and program in non-erasing sector s, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.
13. The Erase Resume command is valid only during the Erase
Suspend mode.
14. Command is valid when device is ready to read array data or when
device is in autoselect mode.
Command
Sequence
(Note 1)
Cycles
Bus Cycles (Notes 2–4)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXX F0
Autoselect (Note 7)
Manufacturer ID 4 XXX AA XXX 55 XXX 90 X00 01
Device ID 4 XXX AA XXX 55 XXX 90 X01 93
SecSi Sector Factory
Protect (Note 8) 4 XXX AA XXX 55 XXX 90 X03 80/00
Sector Group Protect Verify
(Note 9) 4 XXX AA XXX 55 XXX 90 (SA)X02 00/01
Enter SecSi Sector Region 3 XXX AA XXX 55 XXX 88
Exit SecSi Sector Region 4 XXX AA XXX 55 XXX 90 XXX 00
Program 4 XXX AA XXX 55 XXX A0 PA PD
Unlock Bypass 3XXX AA XXX 55 XXX 20
Unlock Bypass Progr am (Note 10) 2XXX A0 PA PD
Unlock Bypass Reset (Note 11) 2XXX 90 XXX 00
Chip Erase 6 XXX AA XXX 55 XXX 80 XXX AA X XX 55 XXX 10
Sector Erase 6 XXX AA XXX 55 XXX 80 XXX AA XXX 55 SA 30
Erase Suspend (Note 12) 1 BA B0
Erase Resume (Note 13) 1 BA 30
CFI Query (Note 14) 1 XX 98
28 Am29LV065D January 10, 2002
WRITE OPERATION STATUS
The device provides several bits to determine the status of
a program or erase operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 11 and th e fol lowing s ubsections descr ibe the
funct ion of thes e bits. DQ7 and DQ6 each offer a method
for determining whether a progr am or erase opera tion is
complete or in progress. The device also provides a hard-
war e-based output signal, RY/ B Y# , t o determine whether
an Embedded Pr ogram or Erase operation is in progress or
has been completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system
whether an Em bedded Prog ram or Erase alg orit hm is in
prog re ss or completed, or whether the device is in Erase
Suspend. Data# Polling is valid after the rising edge of the
final WE# pulse in the command sequence.
Dur ing the Embedded Prog r am algori thm, th e device out -
puts on DQ7 the complement of the datum progr ammed to
DQ7. This DQ7 status also applies t o programming during
Erase Suspend. When the Embedded Program algorithm is
comp lete, the devic e o ut puts t he d at um pr og ram m ed to
DQ7 . T he sy s tem m us t pr ov ide the progr am address to
read valid status information on DQ7. If a pr ogram address
falls within a protected sector , Data# Polling on DQ7 is ac-
tive for approximately 1 µs, then the device returns to t he
read mode.
During the Embe dded E rase al gorithm, D ata# P olling
produces a “0” on DQ7. When the Embedded Erase
algor ithm is complet e, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the
sectors selected for er asure to read valid stat us infor-
mation on DQ 7.
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Poll-
ing on DQ7 is active for approximately 100 µs, then
the device returns to the read mode. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores t he se-
lected sectors tha t are protected. However, if the sys-
tem reads DQ7 at an address within a protected
secto r, the st atus may n ot be vali d.
Just prior to the completion of an Embedded Program
or Erase operation, DQ7 may change asynchronously
with DQ0–DQ6 while Output Enable (OE#) is asserted
low. That is, the device ma y chan ge from providin g
status information t o va lid dat a on DQ7. Depending on
when the sy stem samples the DQ 7 output , it may read
the status or valid data. Even if the device has com-
pleted the program or eras e operation and DQ7 has
valid data, the data outputs on DQ0–DQ6 may be still
invalid. Valid data on DQ0–DQ7 will appear on suc-
cess iv e read cy cles.
Table 1 1 s hows the outputs for Data# Polling on DQ7.
Figure 5 shows the Data# Polling algorithm. Figure 18
in the AC Characteristics section shows the Data#
Polling timing diagram.
Figure 5. Da t a # Polling Alg orithm
DQ7 = Data? Yes
No
No
DQ5 = 1?
No
Yes
Yes
FAIL PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
START
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
January 10, 2002 Am29LV065D 29
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin
which indicates whether an Embedded Algorithm is in
progress or complet e. T he RY /BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output , sev-
eral RY/BY# pins c an be tied together in parallel with a
pull-up resistor to VCC.
If the output is low (Bus y), the device is actively eras -
ing or program ming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Rea dy) , th e dev ice is in the rea d mode , th e sta ndby
mode, or the device is in the erase-suspend-read
mode.
Table 11 shows the out puts for RY/BY #.
DQ6: Toggle Bit I
Togg le B it I on DQ6 in dica tes w het her an E mb edde d
Program or Erase algorithm is in progress or com-
plete, or w hether th e device has entered the Eras e
Suspend mode. Toggle Bit I may be read at any ad-
dress, and is vali d afte r the r ising edge o f the fina l
WE# pulse in the command sequence (prior to the
program or er ase operat ion), and during the sector
erase time-out .
During an Embedded Program or Erase algorithm op-
eration, successive r ead cycles to any address cause
DQ6 to toggle. The system may use either OE# or
CE# to control the read cycles. When the operation is
complet e, DQ6 stops toggling.
A fter an er as e command sequence is wri tten, if al l sectors
selected for erasing are protected, DQ6 toggles for approxi-
mately 100 µs, then returns to reading ar ray data. If not all
selected sectors are protected, the Embedded Erase algo-
ri t hm er ases the un pr ot ected sect or s, and ignores the se-
lected sector s that are protected.
The system ca n use DQ6 and DQ2 to gether t o dete r m ine
whether a sector is actively erasing or i s erase-suspended.
When the device is actively erasi ng (that is, the Embedded
Erase algorithm is in progress), DQ6 toggles. When the de-
vice enters the Erase Suspend mode, DQ6 stops toggling.
Howev er, the system mu st also use DQ2 to determin e
which se ctors are er as ing or er as e- su sp ended. Alt er na -
tively, the system can use DQ7 (see the subsection on
DQ7: Data# P olling).
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs af ter the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, an d stops to ggling once the Em bedded Pro -
gram algorithm is complete.
Table 11 s hows the outputs for Toggle Bit I on DQ6.
Figure 6 shows the toggle bit algorithm. Fi gure 19 in
the “AC Characteristics” section shows the toggle bit
timing d iagrams . Figur e 20 sho ws th e d iffere nce s b e-
tween DQ2 and DQ6 in graphical form. See also the
subsection on DQ2: Toggle Bit II.
Figure 6. To ggle B it A lgor it h m
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
= Toggle? No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Read DQ7–DQ0
Toggle Bit
= Toggle?
Read DQ7–DQ0
Twice
Read DQ7–DQ0
Note: The system should recheck the toggle bit even if
DQ5 = “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more information.
30 Am29LV065D January 10, 2002
DQ2: Toggle Bit II
The “Toggle Bit I I” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase- suspended. Tog gle Bit
II is valid after the risi ng edge of t he final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is er ase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguis h which se ctors are selected for era-
sure. Thus, both s tat us bits ar e r equired for secto r and
mode information. Refer to Table 11 to compare out-
puts for DQ2 and DQ6.
Figure 6 shows the t oggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains t he
algorithm . See a lso th e DQ6: Toggle Bit I sub secti on.
Fig u re 1 9 shows the toggle bit timing diagra m. Figure
20 shows the differences between DQ2 and DQ6 in
graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figur e 6 for t he follo wing disc ussio n. W hen -
ever the system init ially beg ins reading t oggle bit s ta-
tus, it must read DQ7–DQ0 at least twice in a row to
determine whet her a toggle bit is toggling. Typically,
the system wo uld note and store the va lue of the tog-
gle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the fir st. If the toggle bit is not tog gling, the device
has completed the pr ogram or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still tog gling, the s ys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then dete rmi ne agai n whether the to ggle bit is tog-
gling , s ince the t oggl e bit ma y ha ve s toppe d to gglin g
just as DQ5 w ent high. If the t oggle bit is no longer
toggling, the device has successfully completed the
program or erase operati on. If it is s til l toggling, the de-
vice did not completed the operation successfully, and
the system must write the reset command to return to
reading array data.
The remain ing scenario is that the sy stem initially de -
termines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor
the toggle bit and DQ5 through successive read cy-
cles, determining the status as described in the previ-
ous paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of Figure 6).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time h as
exceeded a speci fied internal pulse count limit. Under these
conditions DQ5 produces a “1,” indic ating that the program
or erase cycle was not successfully completed.
The devic e may output a “1” on DQ5 if the system tries
to program a “1” to a location that was previously pro-
grammed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit
has been exceeded, DQ5 prod uces a “1.”
Under both these conditions, the system must write
the reset command to return to the read mode (or to
the erase-suspend-read mode if the device was previ-
ously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to deter mine whe ther or no t
era sure has b egun. ( The secto r era se tim er do es no t
apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out
also applies after each additional sector erase com-
mand. When the time-out period is complete, DQ3
switches from a “0” to a “1.” If the time b etween addi-
tional sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the Sec tor Erase Command
Sequence section.
After t he sector erase command is writ ten, the syst em
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all fur-
ther command s (exce pt Eras e Susp end) are ig nored
until the erase operation is complete. If DQ3 is “0,” the
devic e will accept additional sec tor erase com mands.
To en sure the c omman d has bee n accepted , the sys-
tem software should check the status of DQ3 prior to
and following each subsequent sector erase com-
mand. I f DQ3 is high o n the s econd status check, the
last command might not have been accepted.
Table 11 shows the status of DQ3 relative to the other
status bits.
January 10, 2002 Am29LV065D 31
Table 11. Write Operation Status
Notes:
1. DQ5 switches t o ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
Status DQ7
(Note 2) DQ6 DQ5
(N ote 1) DQ3 DQ2
(N ote 2) RY/BY#
Standard
Mode Embedded Program A lgorithm DQ7# Toggle 0 N/A No toggle 0
Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0
Erase
Suspend
Mode
Erase-Suspend-
Read
Erase
Suspended Sec tor 1 No toggle 0 N/A Toggle 1
Non-Erase
Suspended Sec tor Data Data Data Data Data 1
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0
32 Am29LV065D January 10, 2002
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plast ic Packages . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Powe r Ap p l i e d . . . . . . . . . . . . . –65°C to +125°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
VIO. . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +5.5 V
A9, OE#, ACC, and RESET#
(No te 2 ). . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V
All other pins (Note 1). . . . . . –0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V.
During voltage transitions, input or I/O pins may
overshoot VSS to –2.0 V for periods of up to 20 ns.
Maximu m DC volta ge on input or I/O pins is VCC +0.5 V.
See Figure 7. During voltage transitions, inpu t or I/O pins
may overshoot to VCC +2.0 V for periods up to 20 ns. See
Figure 8.
2. Minimum DC input voltage on pins A9, OE#, ACC, and
RE SET # is –0.5 V. During voltage transitions, A9, OE#,
ACC, and RESET# may overshoot VSS to –2.0 V for
periods of up to 20 ns. See Figure 7. Maximu m DC input
voltage on pin A9, OE#, ACC, and RESET# is +12.5 V
which may overshoot to +14.0 V for periods up to 20 ns.
3. No more than one outp ut may be shorted to gr ound at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed unde r “Absolute Maximum
Ratings” m ay caus e perman ent da mage to the dev ice. Th is
is a s tress rating only; func tional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
OPERATING RANGES
Industri al (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . –55°C to +125°C
Supply Voltages
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 –3.6 V
VIO . . . . . . . . . . . . . . . . .ei the r 1. 8 –2.9 V or 3.0–5.0 V
(see Ordering Information section)
Operating ranges define those limits between which the
functionality of the device is guaranteed.
20 ns
20 ns
+0.8 V
–0.5 V
20 ns
–2.0 V
Figur e 7 . Maximum Negative
Overshoot Waveform
20 ns
20 ns
VCC
+2.0 V
VCC
+0.5 V
20 ns
2.0 V
Figure 8. Maximum Positive
Overshoot Waveform
January 10, 2002 Am29LV065D 33
DC CHARACTERISTICS
CMOS Compatible
Notes:
1. The ICC current listed is typically less than 2 mA/MH z, with OE# at VIH.
2. Maximum ICC specifications are tested with VCC = V CCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. T ypical sleep mode current is
200 nA.
5. If VIO < V CC, maximum VIL for CE# and DQ I/Os is 0.3 VIO. If VIO < V CC, mi nimu m VIH for CE# and DQ I/Os is 0.7 VIO. Max imu m VIH
for these connections is VIO + 0.3 V.
6. Not 100% tested.
Parameter
Symbol Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC,
VCC = VCC max ±1.0 µA
ILIT A9, ACC Input Load Current VCC = VCC max; A9 = 12.5 V 35 µA
ILO Output Leakage Current VOUT = VSS to VCC,
VCC = VCC max ±1.0 µA
ICC1 VCC Active Read Current
(Notes 1, 2) CE# = VIL, OE# = VIH 5 MHz 9 16 mA
1 MHz 2 4
ICC2 VCC Active Write Current (Notes 2, 3) CE# = VIL, OE# = VIH 26 30 mA
ICC3 VCC Standby Current (Note 2) CE#, RESET# = VCC ± 0.3 V 0.2 5 µA
ICC4 VCC Reset Current (Note 2) RESET# = VSS ± 0.3 V 0.2 5 µA
ICC5 Auto matic Sleep Mode (Notes 2, 4) VIH = VCC ± 0.3 V ; VIL = VSS ± 0. 3 V 0.2 5 µA
IACC ACC Accelerated Program Current CE# = VIL, OE# = VIH ACC pin 5 10 mA
VCC pin 15 30 mA
VIL Input Low Voltage (Note 5) –0.5 0.8 V
VIH Input High Voltage (Note 5) 0.7 x VCC VCC + 0.3 V
VHH Voltage for ACC Program
Acceleration VCC = 3.0 V ± 10% 11.5 12.5 V
VID Voltage for Autoselect and
Temporary Sector Unprotect VCC = 3.0 V ± 10% 8.5 12.5 V
VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45 V
VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.8 VIO V
VOH2 IOH = –100 µA, VCC = VCC min V
IO–0.4 V
VLKO Low VCC Lock-Out Voltage (Note 6) 2.3 2.5 V
34 Am29LV065D January 10, 2002
DC CHARACTERISTICS
Zero-Power Flash
Note: Addresses are switching at 1 MHz
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
25
20
15
10
5
00 500 1000 1500 2000 2500 3000 3500 4000
Supply Current in mA
Time in ns
10
8
2
0
12345
Frequency in MHz
Suppl y Current in mA
Note: T = 25 °C
Figure 10. Typical ICC1 vs. Frequency
4
6
12
3.0 V
3.6 V
January 10, 2002 Am29LV065D 35
TEST CONDITIONS
Table 12. Test Specifications
Note: If VIO < VCC, the reference lev el is 0.5 VIO.
KEY TO SWITCHING WAVEFORMS
2.7 kΩ
CL6.2 kΩ
3.3 V
Device
Under
Test
Note: Diodes are IN3064 or equivalent
Figure 11. Test Setup
Test Condition 90R,
101R 120R,
121R Unit
Output Load 1 TTL gate
Output Load Capacitance, CL
(including jig cap acitance) 30 100 pF
Input Rise and Fall Times 5 ns
Input P u lse Levels 0.0–3.0 V
Input timing measurement
refer ence levels (See Note) 1.5 V
Output timing measurement
reference levels 0.5 VIO V
3.0 V
0.0 V 1.5 V 0.5 VIO V OutputMeasurement LevelInput
Note: If VIO < VCC, the input measuremen t reference level is 0.5 VIO.
Figure 12. Input Waveform s and Measurement Levels
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
36 Am29LV065D January 10, 2002
AC CHARACTERISTICS
Read-Only Operations
Notes:
1. All test setups assume VIO = VCC.
2. Not 100% tested.
3. See Figure 1 1 and Table 12 for test specifications.
Parameter
Description Test Setup
(N ote 1)
Speed Options
JEDEC Std. 90R 101R 120R,
121R Unit
tAVAV tRC Read Cycle Time (Note 2) Min 90 100 120 ns
tAVQV tACC Address to Output Delay CE#, OE# = VIL Max 90 100 120 ns
tELQV tCE Chip Enable to Output Del a y OE# = VIL Max 90 100 120 ns
tGLQV tOE Output Enable to O utput Delay Max 35 35 50 ns
tEHQZ tDF Chip Enable to Output High Z (Note 2) Max 30 30 30 ns
tGHQZ tDF Output Enable to O utput High Z
(Note 2) Max 30 30 30 ns
tAXQX tOH Output Hold Time From Addresses,
CE# or OE#, Whichever Occurs First Min 0 ns
tOEH Output Enable
Hol d Time (Note 2)
Read Min 0 ns
Togg le and
Data# Polling Min 10 ns
tOH
tCE
Outputs
WE#
Addresses
CE#
OE#
HIGH Z
Output V alid
HIGH Z
Addresses Stable
tRC
tACC
tOEH
tRH
tOE
tRH
0 V
RY/BY#
RESET#
tDF
Figure 13. Read Operation Timings
January 10, 2002 Am29LV065D 37
AC CHARACTERISTICS
Hardware Reset (RESET#)
Note: Not 100% tested.
Parameter
Description All Speed Options UnitJEDEC Std
tReady RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note) Max 20 µs
tReady RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note) Max 500 ns
tRP RESET# Pulse Width Min 500 ns
tRH Reset High Time Before Read (See Note) Min 50 ns
tRPD RESET# Low to Standby Mode Min 20 µs
tRB RY/BY# Recovery Time Min 0 ns
RESET#
RY/BY#
RY/BY#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
tReady
CE#, OE#
tRH
CE#, OE#
Reset Timings during Embedded Algorithms
RESET#
tRP
tRB
Figure 14. Reset Timings
38 Am29LV065D January 10, 2002
AC CHARACTERISTICS
Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase And Programmi ng Performance” section for more information.
Parameter Speed Options
JEDEC Std. Description 90R 101R 120R,
121R Unit
tAVAV tWC Write Cycle Time (Note 1) Min 90 100 120 ns
tAVWL tAS Address Setup Time Min 0 ns
tASO Address Setup Time to O E# low during toggle bi t polling Min 15 ns
tWLAX tAH Address Hold Time Min 45 45 50 ns
tAHT Address Hold Time From C E# or OE# high
during toggle bit polling Min 0 ns
tDVWH tDS Data Setup Time Min 45 45 50 ns
tWHDX tDH Data Hold Time Min 0 ns
tOEPH Output Enable High during toggle bit polling Mi n 20 ns
tGHWL tGHWL Read Recovery Time Before Write
(OE# High to WE# Low) Min 0 ns
tELWL tCS CE# Setup Time Min 0 ns
tWHEH tCH CE# Hold Time Min 0 ns
tWLWH tWP Write Pulse Width Min 35 35 50 ns
tWHDL tWPH Write Pulse Width High Min 30 ns
tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ 5 µs
tWHWH1 tWHWH1 Accelerated Byte Programming Operati on (Note 2) Typ 4 µs
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.9 sec
tVHH VHH Rise and Fall Time (Note 1) Min 250 ns
tVCS VCC Setup Time (Note 1) Min 50 µs
tRB Write Recovery Time from RY/BY# Min 0 ns
tBUSY Program/Erase Valid to RY/BY# Delay Max 90 ns
January 10, 2002 Am29LV065D 39
AC CHARACTERISTICS
OE#
WE#
CE#
VCC
Data
Addresses
t
DS
tAH
tDH
tWP
PD
tWHWH1
tWC tAS
tWPH
tVCS
XXXh PA PA
Read Status Data (last two cycles)
A0h
tCS
Status DOUT
Program Command Sequence (last two cycles)
RY/BY#
t
RB
tBUSY
tCH
PA
N
ote: PA = program address, PD = program data, DOUT is the true data at the program address .
Figure 15. Program Operation Timings
ACC tVHH
VHH
VIL or VIH VIL or VIH
tVHH
Figure 16. Accel erated Program Timing Diagram
40 Am29LV065D January 10, 2002
AC CHARACTERISTICS
OE#
CE#
Addresses
VCC
WE#
Data
XXXh SA
tAH
tWP
tWC tAS
tWPH
XXXh for chip erase
10 for Chip Erase
30h
tDS
tVCS
tCS
tDH
55h
tCH
In
Progress Complete
tWHWH2
VA
VA
Erase Command Sequence (last two cycles) Read Status Data
RY/BY#
tRB
tBUSY
Note: SA = sector address (for Sector Erase), VA = V alid Address for reading status data (see “Write Operation Status”..
Figure 17. Chip/Sector Erase Operation T imi ngs
January 10, 2002 Am29LV065D 41
AC CHARACTERISTICS
WE#
CE#
OE#
High Z
tOE
High Z
DQ7
DQ0–DQ6
RY/BY#
tBUSY
Complement True
Addresses VA
tOEH
tCE
tCH
tOH
tDF
VA VA
Status Data
Complement
Status Data True
Valid Data
Valid Data
tACC
tRC
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 18 . Data# Poll ing Timings (D uring Embed de d Algorithm s )
42 Am29LV065D January 10, 2002
AC CHARACTERISTICS
OE#
CE#
WE#
Addresses
tOEH
tDH
tAHT
tASO
tOEPH
tOE
Valid Data
(first read) (second read) (stops toggling)
tCEPH
tAHT
tAS
DQ6/DQ2 Valid Data
Valid
Status Valid
Status Valid
Status
RY/BY#
Note: VA = Valid address; not requi red for D Q6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle
Figure 19 . Toggle B it Timing s (During Embed de d Algorithm s )
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle
DQ2 and DQ6.
Figure 20. DQ2 vs. DQ6
Enter
Erase
Erase
Erase
Enter Erase
Suspend Program
Erase Suspend
Read Erase Su spend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing
January 10, 2002 Am29LV065D 43
AC CHARACTERISTICS
Temporary Sector Unprotect
Note: Not 100% tested.
Parameter
All S pe e d Op t ion sJEDEC Std Description Unit
tVIDR VID Rise and Fall Time (See Note) Min 500 ns
tRSP RESET# Setup Time for Temporary Sector
Unprotect Min 4 µs
tRRB RESET# Hold Time from RY/BY# High for
Temporary Sector Group Unprotect Min 4 µs
RESET#
tVIDR
VID
VSS, VIL,
or VIH
VID
VSS, VIL,
or VIH
CE#
WE#
RY/BY#
tVIDR
tRSP
Program or Erase Command Sequence
tRRB
Figure 21. Temporary Sector Group Unprotect Timin g Diagram
44 Am29LV065D January 10, 2002
AC CHARACTERISTICS
Sector Group Protect: 150 µs,
Sector Group Unprotect: 15 ms
1 µs
RESET#
SA, A6,
A1, A0
Data
CE#
WE#
OE#
60h 60h 40h
Valid* Valid* Valid*
Status
Sector Group Protect or Unprotect Verify
VID
VIH
* For sec tor group protect, A6 = 0, A1 = 1, A0 = 0. For sector group unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 22. Sector Group Protect and Unprotect Timing Diagram
January 10, 2002 Am29LV065D 45
AC CHARACTERISTICS
Alternate CE# Controlled Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase And Programmi ng Performance” section for more information.
Parameter Speed Options
JEDEC Std Description 90R 101R 120R Unit
tAVAV tWC Write Cycle Time (Note 1) Min 90 100 120 ns
tAVWL tAS Addr ess Setup Tim e Min 0 ns
tELAX tAH Address Hold Ti me Min 45 45 50 ns
tDVEH tDS Data Setup Time Min 45 45 50 ns
tEHDX tDH Data Hold Time Min 0 ns
tGHEL tGHEL Read Recovery Time Before Write
(OE# High to WE# Low) Min 0 ns
tWLEL tWS WE# Setup Time Min 0 ns
tEHWH tWH WE# Hold Time Min 0 ns
tELEH tCP CE# P ulse Width Min 45 45 50 ns
tEHEL tCPH CE# Pulse Width High Min 30 ns
tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ 11 µs
tWHWH1 tWHWH1 Accelerated Byte Programming Operation (Note 2) Typ 7 µs
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.9 sec
46 Am29LV065D January 10, 2002
AC CHARACTERISTICS
tGHEL
tWS
OE#
CE#
WE#
RESET#
tDS
Data
tAH
Addresses
tDH
tCP
DQ7# D
OUT
tWC tAS
tCPH
PA
Data# Polling
A0 for program
55 for erase
tRH
tWHWH1 or 2
RY/BY#
tWH
PD for program
30 for sector erase
10 for chip erase
XXX for program
XXX for erase PA for program
SA for sector erase
XXX for chip erase
tBUSY
Notes:
1. Figure indicates last two bus cycles of a p rogram or erase operation.
2. PA = pr og r a m a dd re s s, SA = se c t or address, PD = p ro gr am da t a.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
Figure 23. Alternate CE# Con tr ol led Wri t e (Erase/ Program) Operati on Ti min gs
January 10, 2002 Am29LV065D 47
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical p rogram and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000 ,000 cycl es. Additiona lly,
programming typicals assume checkerboard pattern.
2. Under worst case conditio ns of 90°C, VCC = 3.0 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algori thm, all bits are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table
10 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycl es.
LATCHUP CHARACTERISTICS
Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
TSOP PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter Typ (Note 1) Max (Not e 2) Unit Comments
Sector Erase Time 0.9 15 sec E xcludes 00h programmi ng
prior to erasure (Note 4)
Chip Erase Time 115 sec
Byte Program Time 5 150 µs Excludes system level
overhead (Note 5)
Accelerated Byte Program Time 4 120 µs
Chip Program Time (Note 3) 42 126 sec
Description Min Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#) –1.0 V 12.5 V
Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V
VCC Curre nt –100 mA +100 mA
Parameter
Symbol Parameter Description Test Setup Typ Max Unit
CIN Input Capac itanc e V IN = 0 6 7.5 pF
COUT Output Cap ac itanc e VOUT = 0 8.5 12 pF
CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF
Parameter Description Test Conditions Min Unit
Minimum Pattern Data Retention Time 150°C10Years
125°C20Years
48 Am29LV065D January 10, 2002
PHYSICAL DIMENSIONS
TS 048—48-Pin Standard Pinout Thin Small Outline Package (TSOP)
Dwg rev AA; 10/99
January 10, 2002 Am29LV065D 49
PHYSICAL DIMENSIONS
TSR048—48-Pin Reverse Pinout Thin Small Outline Package (TSOP)
Dwg rev AA; 10/99
50 Am29LV065D January 10, 2002
PHYSICAL DIMENSIONS
FBE063—63-Ball Fine-Pitch Ball Grid Array (FBGA)
11 x 12 mm package
Dwg rev AF; 10/99
January 10, 2002 Am29LV065D 51
REVISION SUMMARY
Revision A (July 27, 2000)
Init ial r eleas e.
Revision A+1 (August 4, 2000)
Global
Deleted references to the 48-pin reverse TSOP.
Connection Diagrams
Corrected pin 36 on TSOP package to VIO.
Accelerated Program Operation, Unlock Bypass
Co m m a nd Sequence
Modified cau tion not e regarding ACC input.
Revision A+2 (August 14, 2000)
Ordering Information
Corrected 90 ns entry in VIO colu m n fo r FBGA .
Revision A+3 (August 25, 2000)
Table 3, Am29LV065D Autoselect Codes,
(High Voltage Method)
Corrected the SecSI Sector Indicator Bit codes from
80h/00h to 90h/10h.
Revision A+4 (October 19, 2000)
Global
Changed data sheet status to “Preliminary.”
Revision A+5 (November 7, 2000)
Ordering Information
Deleted burn-in option.
Revision A+6 (November 27, 2000)
Pin D e scr iption, an d Table 11, Write Operation
Status
Deleted references to RY/BY# being available only on
the FBGA package. RY/BY# is also available on the
TSOP package.
Revision A+7 (March 8, 2001)
Global
Deleted “Preliminary” status from document.
Table 4, Sector Group Protection/Unprotection
Address Table
Corr ected the sector group a ddress bits for s ectors
64–127.
Revision B (January 10, 2002)
Global
Add ed TSR0 48 package. Clar ified des criptio n of Ver-
satileIO (VIO) in the following sections: Distinctive
Characteristics; General Description; VersatileIO (VIO)
Control; Operating Ranges; DC Characteristics;
CMOS compatible.
Reduced typical sector erase time from 1.6 s to 0.9 s.
Table 3, Am29LV065D Au toselect Codes,
(High Voltage Method)
Corr ected the aut oselect code for sec tor protection
verification.
Sector Group Protection and Unprotection
Deleted reference to previous method of sector pro-
tection and unprotection.
Autoselect Command Sequence
Clarified descript ion of funct ion.
SecSi (Secured Silicon) Sector Flash
Memory Region
Clar ified the customer lo ckable ve rsio n of t his device
can be programmed and protected only once. In Table
5, changed addr ess range in second row.
DC Characteristics
Changed minimum VOH1 fr om 0. 85VIO to 0.8VIO. De-
leted reference to Note 6 for both VOH1 and VOH2.
Erase and Program Oper ation s table
Corrected to indicate tBUSY specification is a maximum
value.
Erase and Program Performance table
Chang ed typ ical sector erase tim e from 1 .6 s to 0.9 s
and typical chip erase time from 205 s to 115 s.
Copyright © 2002 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered tradem arks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
