CLC420AJE-TR13 - Texas Instruments High-Performance Analog

CLC420

CLC420 High Speed, Voltage Feedback Op Amp

Literature Number: SNOS857F

CLC420

July 15, 2009

High Speed, Voltage Feedback Op Amp

General Description

The CLC420 is an operational amplifier designed for applica-

tions requiring matched inputs, integration or transimpedance

amplification. Utilizing voltage feedback architecture, the

CLC420 offers a 300MHz bandwidth, a 1100V/µs slew rate

and a 4mA supply current (power consumption of 40mW,±5V

supplies).

Applications such as differential amplifiers will benefit from

70dB common mode rejection ratio and an input offset current

of 0.2µA. With its unity-gain stability, 2pA/ current noise

and 3µA of input bias current, the CLC420 is designed to meet

the needs of filter applications and log amplifiers. The low in-

put offset current and current noise, combined with a settling

time of 18ns to 0.01% make the CLC420 ideal for D/A con-

verters, pin diode receivers and photo multipliers amplifiers.

All applications will find 70dB power supply rejection ratio at-

tractive.

Features

■300MHz small signal bandwidth

■1100V/µs slew rate

■Unity-gain stability

■Low distortion, -60dBc at 20MHz

■0.01% settling in 18ns

■0.2µA input offset current

■2pA current noise

Applications

■Active filters/integrators

■Differential amplifiers

■Pin diode receivers

■Log amplifiers

■D/A converters

■Photo multiplier amplifiers

Non-Inverting Frequency Response

1275219

Connection Diagram

1275218

Pinout

DIP & SOIC

1275220

2nd and 3rd Harmonic Distortion

CLC420 High Speed, Voltage Feedback Op Amp

Ordering Information

Package Temperature Range

Industrial

Part Number Package Marking NSC Drawing

8-pin plastic DIP −40°C to +85°C CLC420AJP CLC420AJP N08E

8-pin plastic SOIC −40°C to +85°C CLC420AJE CLC420AJE M08A

CLC420AJE-TR13 CLC420AJE

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CLC420

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (VCC)±7V

IOUT

(is short circuit protected to ground,

but maximum reliability will be

maintained if IOUT does not exceed

70mA, except A8D, B8D which should

not exceed 35mA over the military

temperature range)..

70mA

Common Mode Input Voltage ±VCC

Differential Input Voltage 10V

Junction Temperature +150°C

Operating Temperature Range −40°C to +85°C

Storage Temperature Range −65°C to +150°C

Lead Solder Duration (+300°C) 10 sec

Operating Ratings

Thermal Resistance

Package (θJC) (θJA)

MDIP 65°C/W 120°C/W

SOIC 60°C/W 140°C/W

Electrical Characteristics

AV = +1, VCC = ±5V, RL = 100Ω, Rf = 0Ω; unless specified

Symbol Parameter Conditions Typ Max/Min (Note 2) Units

Ambient Temperature CLC420AJ +25°C −40°C +25°C +85°C

Frequency Domain Response

SSBW -3dB Bandwidth VOUT <0.4VPP 300 >200 >200 >130 MHz

LSBW VOUT<5VPP 40 >20 >25 >20 MHz

SSBWI AV =−1, Rf = 500Ω VOUT <0.4VPP 100 >65 >65 >45 MHz

LSBWI AV = −1, Rf = 500Ω VOUT <5VPP 60 >30 >35 >30 MHz

Gain Flatness VOUT< 0.4VPP

GFPL Peaking 0.1MHz to 100MHz 0 <1 <0.6 <0.6 dB

GFPH Peaking >100MHz 0 <5 <3 <3 dB

GFR Rolloff 0.1MHz to 100MHz 0.2 <1 <1 <2 dB

GFRI Rolloff, AV = −1, Rf = 500Ω 0.1MHz to 30MHz 0.2 <1.4 <1.4 <1.6 dB

LPD Linear Phase Deviation 0.1MHz to 100MHz 0.9 <1.8 <1.8 <2.5 deg

Time Domain Response

TRS Rise and Fall Time 0.4V Step 1.2 <2 <2 <3 ns

TRL 5V Step 1.4 <25 <20 <20 ns

TRSI Rise and Fall Time,

AV = −1, Rf = 500Ω

0.4V Step 3.5 <5.5 <5.5 <7.8 ns

TRLI 5V Step 6 <10 <9.5 <10 ns

TSS Settling Time to ±0.1% 2V Step 12 <18 <18 <18 ns

TSP ±0.01% 2V Step 18 <25 <25 <25 ns

OS Overshoot 0.4V Step 8 <35 <25 <25 %

SR Slew Rate, AV = +2 5V Step 1100 >600 >750 >600 V/µs

SRI Slew Rate, AV = −1, Rf = 500Ω 5V Step 750 >430 >500 >430 V/µs

Distortion And Noise Response

HD2 2nd Harmonic Distortion 2VPP, 20MHz −50 <−40 <−40 <−40 dBc

HD3 3rd Harmonic Distortion 2VPP, 20MHz −53 <−45 <−45 <−40 dBc

HD2 2nd Harmonic Distortion AV = −1 2VPP, 20MHz, Rf =

500Ω

−51 <−40 <−40 <−40 dBc

HD3 3rd harmonic distortion AV = −1, Rf = 500Ω

2VPP, 20MHz, Rf = 500Ω

−51 <−40 <−40 <−35 dBc

Input Referred Noise

VN Voltage 1MHz to 200MHz 4.2 <5.3 <5.3 <6 nV/

ICN Current 1MHz to 200MHz 2 <2.9 <2.6 <2.3 pA/

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CLC420

Symbol Parameter Conditions Typ Max/Min (Note 2) Units

Static DC Performance

VIO Input Offset Voltage (Note 3) 1 <3.2 <2 <3.5 mV

DVIO Average Temperature Coefficient 8 <15 - <15 µV/°C

IB Input Bias Current (Note 3) 3 <20 <10 <10 µA

DIB Average Temperature Coefficient 45 <120 - <60 nA/°C

IIO Input Offset Current (Note 3) 0.2 <2.6 <1 <2 µA

DIIO Average Temperature Coefficient 2 <20 - <10 nA/°C

AOL Open Loop Gain (Note 3) 65 >52 >56 >56 µA

PSRR Power Supply Rejection Ratio 70 >55 >60 >60 dB

CMRR Common Mode Rejection Ratio 80 >60 >65 >65 dB

ICC Supply Current (Note 3) No Load, Quiescent 4 <5 <5 <5 mA

Miscellaneous Performance

RIND Differential Mode Input Resistance 2 >0.5 >1 >1 MΩ

CIND Capacitance 1 <2 <2 <2 pF

RINC Common Mode Input Resistance 1 >0.25 >0.5 >0.5 MΩ

CINC Capacitance 1 <2 <2 <2 pF

RO Output Impedence At DC 0.02 <0.3 <0.2 <0.2 Ω

VO Output Voltage Range No Load ±3.6 ±2.8 ±3 ±3 V

VOL Output Voltage Range RL = 100Ω±2.9 ±2.5 ±2.5 ±2.5 V

CMIR Common Mode Input Range For Rated Performance ±3.2 ±2.5 ±2.8 ±2.8 V

IO Output Current ±60 ±30 ±50 ±50 mA

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices

should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.

Note 2: Max/min ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined

from tested parameters.

Note 3: AJ-level: spec. is 100% tested at +25°C.

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CLC420

Typical Performance Characteristics

Non-Inverting Frequency Response

1275201

Inverting Frequency Response

1275202

Frequency Response for Various RLS

1275203

Open Loop Gain and Phase

1275204

Bandwidth vs. Gain, Transimpedance Configuration

1275205

2nd and 3rd Harmonic Distortion

1275206

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CLC420

2-Tone, 3rd Order Intermodulation Intercept

1275207

Equivalent Input Noise

1275208

PSRR, CMRR, and Closed Loop RO

1275209

Pulse Response

1275210

Settling Time

1275211

Long-Term Settling Time

1275212

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CLC420

Settling Time vs. Capacitive Load

1275213

Settling Time vs. Gain

1275214

IB and IOS vs. Common-Mode Voltage

1275215

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CLC420

Application Division

1275216

FIGURE 1. Recommended Non-Inverting Gain Circuit

1275217

FIGURE 2. Recommended Inverting Gain Circuit

Description

The CLC420 is a high speed, slew boosted, voltage feedback

amplifier with unity-gain stability. These features along with

matched inputs, low input bias and noise currents, and ex-

cellent CMRR render the CLC420 very attractive for active

filters, differential amplifiers, log amplifiers, and tran-

simpedance amplifiers.

DC accuracy

Unlike current feedback amplifiers, voltage-feedback ampli-

fiers have matched inputs. This means that the non inverting

and inverting input bias current are well matched and track

over temperature, etc. As a result, by matching the resistance

looking out of the two inputs, these errors can be reduced to

a small offset current term.

Gain bandwidth product

Since the CLC420 is a voltage feedback op amp, closed loop

bandwidth is approximately equal to the gain bandwidth prod-

uct (typically 100MHz) divided by the noise gain of the circuit

(for noise gains greater than 5). At lower noise gains, higher

order amplifier poles contribute to higher closed loop band-

width. At low gains use the frequency response performance

plots given in the data sheet.

Another point to remember is that the closed loop bandwidth

is determined by the noise gain, not the signal gain of the

circuit. Noise gain is the reciprocal of the attenuation in the

feedback network enclosing the op amp. For example, a

CLC420 setup as a non-inverting amplifier with a closed loop

gain of +1 (a noise gain of 1) has a 300MHz bandwidth. When

used as an inverting amplifier with a gain of −1 (a noise gain

of 2), the bandwidth is less, typically only 100MHz.

Full-power bandwidth, and slew-rate

The CLC420 combines exceptional full power bandwidths

(40MHz, V0 = 5Vpp, AV = +1) and slew rates (1100V/µs, AV =

+1) with low (40mW) power consumption. These attractive

results are achieved by using slew boosting circuitry to keep

the slew rates high while consuming very little power.

In non slew boosted amplifiers, full power bandwidth can be

easily determined from slew rate measurements, but in slew

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CLC420

boosting amplifiers, such as the CLC420, you can't. For this

reason we provide data for both.

Slew rate is also different for inverting and non-inverting con-

figurations. This occurs because common-mode signal volt-

ages are present in non-inverting circuits but absent in

inverting circuits. Once again data is provided for both.

Transimpedance amplifier circuits

Low inverting, input current noise (2pA/ ) makes the

CLC420 ideal for high sensitivity transimpedance amplifier

circuits for applications such as pin diode optical receivers,

and detectors in receiver IFs. However, feedback resistors

4kΩ or greater are required if feedback resistor noise current

is going to be less than the input current noise contribution of

the op amp.

With feedback resistors this large, shunt capacitance on the

inverting input of the op amp (from the pin diode, etc.) will

unacceptably degrade phase margin causing frequency re-

sponse peaking or oscillations a small valued capacitor shunt-

ing the feedback resistor solves this problem (Note: This

approach does not work for a current-feedback op amp con-

figured for transimpedance applications). To determine the

value of this capacitor, refer to the “Transimpedance BW vs.

Rf and Ci” plot.

For example, let's assume an optical transimpedance receiv-

er is being developed. Total capacitance from the inverting

input to ground, including the photodiode and strays is 5pF.

A 5kΩ feedback resistor value has been determined to pro-

vide best dynamic range based on the response of the pho-

todiode and the range of incident optical powers, etc. From

the “Transimpedance BW vs. Rf and Ci” plot, using Ci= 5pF it

is determined from the two curves labeled Ci = 5pF, that Cf =

1.5pF provides optimal compensation (no more than 0.5dB

frequency response peaking) and a −3dB bandwidth of ap-

proximately 27MHz.

Printed circuit layout

As with any high frequency device, a good PCB layout will

enhance performance. Ground plane construction and good

power supply bypassing close to the package are critical to

achieving full performance. The amplifier is sensitive to stray

capacitance to ground at the output and inverting input: Node

connections should be small with minimal coupling to the

ground plane.

Parasitic or load capacitance directly on the output (pin 6) will

introduce additional phase shift in the loop degrading the loop

phase margin and leading to frequency response peaking. A

small series resistor before this capacitance, if present, ef-

fectively decouples this effect. The graphs on the preceding

page, “ Settling Time vs. CL”, illustrates the required resistor

value and resulting performance vs. capacitance.

Evaluation PC boards (part no. 730013 for through-hole and

CLC730027 for SOIC) are available for the CLC420.

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CLC420

Physical Dimensions inches (millimeters) unless otherwise noted

8-Pin MDIP

NS Package Number N08E

8-Pin SOIC

NS Package Number M08A

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CLC420

Notes

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CLC420

Notes

CLC420 High Speed, Voltage Feedback Op Amp

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