DS123 (v2.4) July 20, 2004 www.xilinx.com 1
Preliminary Product Specification 1-800-255-7778
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Features
• In-System Programmable PROMs for Configuration of
Xilinx FPGAs
• Low-Power Advanced CMOS FLASH Process
• Endurance of 20,000 Program/Erase Cycles
• Operation over Full Industrial Temperature Range
(–40°C to +85°C)
• IEEE Standard 1149.1/1532 Boundary-Scan (JTAG)
Support for Programming, Prototyping, and Testing
• JTAG Command Initiation of Standard FPGA
Configuration
• Cascadable for Storing Longer or Multiple Bitstreams
• Dedicated Boundary-Scan (JTAG) I/O Power Supply
(VCCJ)
• I/O Pins Compatible with Voltage Levels Ranging From
1.5V to 3.3V
• Design Support Using the Xilinx Alliance ISE and
Foundation ISE Series Software Packages
• XCF01S/XCF02S/XCF04S
- 3.3V supply voltage
- Serial FPGA configuration interface (up to 33 MHz)
- Available in small-footprint VO20 and VOG20
packages.
• XCF08P/XCF16P/XCF32P
- 1.8V supply voltage
- Serial or parallel FPGA configuration interface
(upto33MHz)
- Available in small-footprint VO48, VOG48, FS48,
and FSG48 packages
- Design revision technology enables storing and
accessing multiple design revisions for
configuration
- Built-in data decompressor compatible with Xilinx
advanced compression technology
Description
Xilinx introduces the Platform Flash series of in-system pro-
grammable configuration PROMs. Available in 1 to 32
Megabit (Mbit) densities, these PROMs provide an
easy-to-use, cost-effective, and reprogrammable method
for storing large Xilinx FPGA configuration bitstreams. The
Platform Flash PROM series includes both the 3.3V
XCFxxS PROM and the 1.8V XCFxxP PROM. The XCFxxS
version includes 4-Mbit, 2-Mbit, and 1-Mbit PROMs that
support Master Serial and Slave Serial FPGA configuration
modes (Figure 1). The XCFxxP version includes 32-Mbit,
16-Mbit, and 8-Mbit PROMs that support Master Serial,
Slave Serial, Master SelectMAP, and Slave SelectMAP
FPGA configuration modes (Figure 2). A summary of the
Platform Flash PROM family members and supported fea-
tures is shown in Ta bl e 1 .
3
9Platform Flash In-System Programmable
Configuration PROMS
DS123 (v2.4) July 20, 2004 0Preliminary Product Specification
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Tabl e 1 : Platform Flash PROM Features
Density VCCINT
VCCO / VCCJ
Range Packages
JTAG ISP
Programming
Serial
Configuration
Parallel
Configuration
Design
Revisioning Compression
XCF01S 1 Mbit 3.3V 1.8V - 3.3V VO20/VOG28 √√
XCF02S 2 Mbit 3.3V 1.8V - 3.3V VO20/VOG28 √√
XCF04S 4 Mbit 3.3V 1.8V - 3.3V VO20/VOG28 √√
XCF08P 8 Mbit 1.8V 1.5V - 3.3V VO48/VOG48
FS48/FSG48 √√√√√
XCF16P 16 Mbit 1.8V 1.5V - 3.3V VO48/VOG48
FS48/FSG48 √√√√√
XCF32P 32 Mbit 1.8V 1.5V - 3.3V VO48/VOG48
FS48/FSG48 √√√√√
Platform Flash In-System Programmable Configuration PROMS
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Preliminary Product Specification 1-800-255-7778
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When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. With CF High, a
short access time after CE and OE are enabled, data is
available on the PROM DATA (D0) pin that is connected to
the FPGA DIN pin. New data is available a short access
time after each rising clock edge. The FPGA generates the
appropriate number of clock pulses to complete the config-
uration.
When the FPGA is in Slave Serial mode, the PROM and the
FPGA are both clocked by an external clock source, or
optionally, for the XCFxxP PROM only, the PROM can be
used to drive the FPGA’s configuration clock.
The XCFxxP version of the Platform Flash PROM also sup-
ports Master SelectMAP and Slave SelectMAP (or Slave
Parallel) FPGA configuration modes. When the FPGA is in
Master SelectMAP mode, the FPGA generates a configura-
tion clock that drives the PROM. When the FPGA is in Slave
SelectMAP Mode, either an external oscillator generates
the configuration clock that drives the PROM and the
FPGA, or optionally, the XCFxxP PROM can be used to
drive the FPGA’s configuration clock. With BUSY Low and
CF High, after CE and OE are enabled, data is available on
the PROMs DATA (D0-D7) pins. New data is available a
short access time after each rising clock edge. The data is
clocked into the FPGA on the following rising edge of the
CCLK. A free-running oscillator can be used in the Slave
Parallel /Slave SelecMAP mode.
The XCFxxP version of the Platform Flash PROM provides
additional advanced features. A built-in data decompressor
supports utilizing compressed PROM files, and design revi-
sioning allows multiple design revisions to be stored on a
single PROM or stored across several PROMs. For design
revisioning, external pins or internal control bits are used to
select the active design revision.
Multiple Platform Flash PROM devices can be cascaded to
support the larger configuration files required when target-
ing larger FPGA devices or targeting multiple FPGAs daisy
chained together. When utilizing the advanced features for
the XCFxxP Platform Flash PROM, such as design revi-
sioning, programming files which span cascaded PROM
devices can only be created for cascaded chains containing
only XCFxxP PROMs. If the advanced XCFxxP features are
Figure 1: XCFxxS Platform Flash PROM Block Diagram
Control
and
JTAG
Interface
Memory Serial
Interface
DATA (D0)
Serial Mode
Data
Address
CLK CE
TCK
TMS
TDI
TDO
OE/RESET
CEO
Data
ds123_01_30603
CF
FI
Figure 2: XCFxxP Platform Flash PROM Block Diagram
CLKOUT
CEO
DATA (D0)
(Serial/Parallel Mode)
D[1:7]
(Parallel Mode)
TCK
TMS
TDI
TDO
CLK CE EN_EXT_SEL OE/RESET BUSY
Data
Data
Address
REV_SEL [1:0]
CF
Control
and
JTAG
Interface
Memory
OSC Serial
or
Parallel
Interface
Decompressor
ds123_19_050604
Platform Flash In-System Programmable Configuration PROMS
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Preliminary Product Specification 1-800-255-7778
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not enabled, then the cascaded chain can include both
XCFxxP and XCFxxS PROMs.
The Platform Flash PROMs are compatible with all of the
existing FPGA device families. A reference list of Xilinx
FPGAs and the respective compatible Platform Flash
PROMs is given in Ta b l e 2 . A list of Platform Flash PROMs
and their capacities is given in Ta ble 3.
Tabl e 2 : Xilinx FPGAs and Compatible Platform Flash
PROMs
FPGA
Configuration
Bitstream
Platform Flash
PROM(1)
Virtex-II Pro
XC2VP2 1,305,440 XCF02S
XC2VP4 3,006,560 XCF04S
XC2VP7 4,485,472 XCF08P
XC2VP20 8,214,624 XCF08P
XC2VP30 11,589,984 XCF16P
XC2VP40 15,868,256 XCF16P
XC2VP50 19,021,408 XCF32P
XC2VP70 26,099,040 XCF32P
XC2VP100 34,292,832 XCF32P(2)
Virtex-II
XC2V40 338,976 XCF01S
XC2V80 598,816 XCF01S
XC2V250 1,593,632 XCF02S
XC2V500 2,560,544 XCF04S
XC2V1000 4,082,592 XCF04S
XC2V1500 5,170,208 XCF08P
XC2V2000 6,812,960 XCF08P
XC2V3000 10,494,368 XCF16P
XC2V4000 15,659,936 XCF16P
XC2V6000 21,849,504 XCF32P
XC2V8000 26,194,208 XCF32P
Virtex-E
XCV50E 630,048 XCF01S
XCV100E 863,840 XCF01S
XCV200E 1,442,016 XCF02S
XCV300E 1,875,648 XCF02S
XCV400E 2,693,440 XCF04S
XCV405E 3,430,400 XCF04S
XCV600E 3,961,632 XCF04S
XCV812E 6,519,648 XCF08P
XCV1000E 6,587,520 XCF08P
XCV1600E 8,308,992 XCF08P
XCV2000E 10,159,648 XCF16P
XCV2600E 12,922,336 XCF16P
XCV3200E 16,283,712 XCF16P
Virtex
XCV50 559,200 XCF01S
XCV100 781,216 XCF01S
XCV150 1,040,096 XCF01S
XCV200 1,335,840 XCF02S
XCV300 1,751,808 XCF02S
XCV400 2,546,048 XCF04S
XCV600 3,607,968 XCF04S
XCV800 4,715,616 XCF08P
XCV1000 6,127,744 XCF08P
Spartan-3
XC3S50 439,264 XCF01S
XC3S200 1,047,616 XCF01S
XC3S400 1,699,136 XCF02S
XC3S1000 3,223,488 XCF04S
XC3S1500 5,214,784 XCF08P
XC3S2000 7,673,024 XCF08P
XC3S4000 11,316,864 XCF16P
XC3S5000 13,271,936 XCF16P
Spartan-IIE
XC2S50E 630,048 XCF01S
XC2S100E 863,840 XCF01S
XC2S150E 1,134,496 XCF02S
XC2S200E 1,442,016 XCF02S
XC2S300E 1,875,648 XCF02S
XC2S400E 2,693,440 XCF04S
XC2S600E 3,961,632 XCF04S
Spartan-II
XC2S15 197,696 XCF01S
XC2S30 336,768 XCF01S
XC2S50 559,200 XCF01S
XC2S100 781,216 XCF01S
XC2S150 1,040,096 XCF01S
XC2S200 1,335,840 XCF02S
Notes:
1. If design revisioning or other advanced feature support is required,
the XCFxxP can be used as an alternative to the XCF01S, XCF02S,
or XCF04S.
2. Assumes compression used.
Tabl e 3 : Platform Flash PROM Capacity
Platform
Flash PROM
Configuration
Bits
Platform Flash
PROM
Configuration
Bits
XCF01S 1,048,576 XCF08P 8,388,608
XCF02S 2,097,152 XCF16P 16,777,216
XCF04S 4,194,304 XCF32P 33,554,432
Tabl e 2 : Xilinx FPGAs and Compatible Platform Flash
PROMs (Continued)
FPGA
Configuration
Bitstream
Platform Flash
PROM(1)
Platform Flash In-System Programmable Configuration PROMS
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Preliminary Product Specification 1-800-255-7778
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Programming
In-System Programming
In-System Programmable PROMs can be programmed indi-
vidually, or two or more can be daisy-chained together and
programmed in-system via the standard 4-pin JTAG proto-
col as shown in Figure 3. In-system programming offers
quick and efficient design iterations and eliminates unnec-
essary package handling or socketing of devices. The pro-
gramming data sequence is delivered to the device using
either Xilinx iMPACT software and a Xilinx download cable,
a third-party JTAG development system, a JTAG-compatible
board tester, or a simple microprocessor interface that emu-
lates the JTAG instruction sequence. The iMPACT software
also outputs serial vector format (SVF) files for use with any
tools that accept SVF format, including automatic test
equipment. During in-system programming, the CEO output
is driven High. All other outputs are held in a high-imped-
ance state or held at clamp levels during in-system pro-
gramming. In-system programming is fully supported
across the recommended operating voltage and tempera-
ture ranges.
OE/RESET
The 1/2/4 Mbit XCFxxS Platform Flash PROMs in-system
programming algorithm requires issuance of a reset that
causes OE/RESET to pulse Low.
External Programming
Xilinx reprogrammable PROMs can also be programmed by
the Xilinx MultiPRO Desktop Tool or a third-party device
programmer. This provides the added flexibility of using
pre-programmed devices with an in-system programmable
option for future enhancements and design changes.
Reliability and Endurance
Xilinx in-system programmable products provide a guaran-
teed endurance level of 20,000 in-system program/erase
cycles and a minimum data retention of 20 years. Each
device meets all functional, performance, and data retention
specifications within this endurance limit.
Design Security
The Xilinx in-system programmable Platform Flash PROM
devices incorporate advanced data security features to fully
protect the FPGA programming data against unauthorized
reading via JTAG. The XCFxxP PROMs can also be pro-
grammed to prevent inadvertent writing via JTAG. Tabl e 4
and Ta b le 5 show the security settings available for the
XCFxxS PROM and XCFxxP PROM, respectively.
Read Protection
The read protect security bit can be set by the user to pre-
vent the internal programming pattern from being read or
copied via JTAG. Read protection does not prevent write
operations. For the XCFxxS PROM, the read protect secu-
rity bit is set for the entire device, and resetting the read pro-
tect security bit requires erasing the entire device. For the
XCFxxP PROM the read protect security bit can be set for
individual design revisions, and resetting the read protect bit
requires erasing the particular design revision.
Write Protection
The XCFxxP PROM device also allows the user to write
protect (or lock) a particular design revision to prevent inad-
vertent erase or program operations. Once set, the write
protect security bit for an individual design revision must be
reset (using the UNLOCK command followed by
ISC_ERASE command) before an erase or program opera-
tion can be performed.
Figure 3: JTAG In-System Programming Operation
(a) Solder Device to PCB
(b) Program Using Download Cable
DS026_02_082703
GND
V
CC
(a) (b)
Tabl e 4 : XCFxxS Device Data Security Options
Read Protect
Read/Verify
Inhibited
Program
Inhibited
Erase
Inhibited
Reset (default)
Set √
Platform Flash In-System Programmable Configuration PROMS
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Preliminary Product Specification 1-800-255-7778
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IEEE 1149.1 Boundary-Scan (JTAG)
The Platform Flash PROM family is IEEE Standard 1532
in-system programming compatible, and is fully compliant
with the IEEE Std. 1149.1 Boundary-Scan, also known as
JTAG, which is a subset of IEEE Std. 1532 Boundary-Scan.
A Test Access Port (TAP) and registers are provided to sup-
port all required boundary scan instructions, as well as
many of the optional instructions specified by IEEE Std.
1149.1. In addition, the JTAG interface is used to implement
in-system programming (ISP) to facilitate configuration, era-
sure, and verification operations on the Platform Flash
PROM device. Tab l e 6 lists the required and optional
boundary-scan instructions supported in the Platform Flash
PROMs. Refer to the IEEE Std. 1149.1 specification for a
complete description of boundary-scan architecture and the
required and optional instructions.
Instruction Register
The Instruction Register (IR) for the Platform Flash PROM
is connected between TDI and TDO during an instruction
scan sequence. In preparation for an instruction scan
sequence, the instruction register is parallel loaded with a
fixed instruction capture pattern. This pattern is shifted out
onto TDO (LSB first), while an instruction is shifted into the
instruction register from TDI.
XCFxxS Instruction Register (8 bits wide)
The Instruction Register (IR) for the XCFxxS PROM is eight
bits wide and is connected between TDI and TDO during an
instruction scan sequence. The detailed composition of the
instruction capture pattern is illustrated in Figure 4.
The instruction capture pattern shifted out of the XCFxxS
device includes IR[7:0]. IR[7:5] are reserved bits and are set
to a logic "0". The ISC Status field, IR[4], contains logic "1"
if the device is currently in In-System Configuration (ISC)
mode; otherwise, it contains logic "0". The Security field,
IR[3], contains logic "1" if the device has been programmed
with the security option turned on; otherwise, it contains
logic "0". IR[2] is unused, and is set to '0'. The remaining bits
IR[1:0] are set to '01' as defined by IEEE Std. 1149.1.
XCFxxP Instruction Register (16 bits wide)
The Instruction Register (IR) for the XCFxxP PROM is six-
teen bits wide and is connected between TDI and TDO dur-
ing an instruction scan sequence. The detailed composition
of the instruction capture pattern is illustrated in Figure 5.
The instruction capture pattern shifted out of the XCFxxP
device includes IR[15:0]. IR[15:9] are reserved bits and are
set to a logic "0". The ISC Error field, IR[8:7], contains a "10"
when an ISC operation is a success, otherwise a "01" when
an In-System Configuration (ISC) operation fails The
Erase/Program (ER/PROG) Error field, IR[6:5], contains a
"10" when an erase or program operation is a success, oth-
erwise a "01" when an erase or program operation fails. The
Erase/Program (ER/PROG) Status field, IR[4], contains a
logic "1" when the device is busy performing an erase or
programming operation, otherwise, it contains a logic "0".
The ISC Status field, IR[3], contains logic "1" if the device is
currently in In-System Configuration (ISC) mode; otherwise,
it contains logic "0". The DONE field, IR[2], contains logic
"1" if the sampled design revision has been successfully
programmed; otherwise, a logic "0" indicates incomplete
programming. The remaining bits IR[1:0] are set to '01' as
defined by IEEE Std. 1149.1.
Tabl e 5 : XCFxxP Design Revision Data Security Options
Read Protect Write Protect
Read/Verify
Inhibited
Program
Inhibited Erase Inhibited
Reset (default) Reset (default)
Reset (default) Set √√
Set Reset (default) √
Set Set √√√
Platform Flash In-System Programmable Configuration PROMS
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Preliminary Product Specification 1-800-255-7778
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Boundary Scan Register
The boundary-scan register is used to control and observe
the state of the device pins during the EXTEST, SAM-
PLE/PRELOAD, and CLAMP instructions. Each output pin
on the Platform Flash PROM has two register stages which
contribute to the boundary-scan register, while each input
pin has only one register stage. The bidirectional pins have
a total of three register stages which contribute to the
boundary-scan register. For each output pin, the register
stage nearest to TDI controls and observes the output state,
and the second stage closest to TDO controls and observes
the High-Z enable state of the output pin. For each input pin,
a single register stage controls and observes the input state
of the pin. The bidirectional pin combines the three bits, the
input stage bit is first, followed by the output stage bit and
finally the output enable stage bit. The output enable stage
bit is closest to TDO.
See the XCFxxS/XCFxxP Pin Names and Descriptions
Tabl e s in t he Pinouts and Pin Descriptions section for the
boundary-scan bit order for all connected device pins, or
see the appropriate BSDL file for the complete bound-
ary-scan bit order description under the "attribute
BOUNDARY_REGISTER" section in the BSDL file. The bit
assigned to boundary-scan cell "0" is the LSB in the bound-
ary-scan register, and is the register bit closest to TDO.
Tabl e 6 : Platform Flash PROM Boundary Scan Instructions
Boundary-Scan Command
XCFxxS IR[7:0]
(hex)
XCFxxP IR[15:0]
(hex) Instruction Description
Required Instructions
BYPASS FF FFFF Enables BYPASS
SAMPLE/PRELOAD 01 0001 Enables boundary-scan SAMPLE/PRELOAD operation
EXTEST 00 0000 Enables boundary-scan EXTEST operation
Optional Instructions
CLAMP FA 00FA Enables boundary-scan CLAMP operation
HIGHZ FC 00FC Places all outputs in high-impedance state
simultaneously
IDCODE FE 00FE Enables shifting out 32-bit IDCODE
USERCODE FD 00FD Enables shifting out 32-bit USERCODE
Platform Flash PROM Specific
Instructions
CONFIG EE 00EE
Initiates FPGA configuration by pulsing CF pin Low
once. (For the XCFxxP this command also resets the
selected design revision based on either the external
REV_SEL[1:0] pins or on the internal design revision
selection bits.)(1)
Notes:
1. For more information see Initiating FPGA Configuration.
TDI → IR[7:5] IR[4] IR[3] IR[2] IR[1:0] → TDO
Reserved ISC Status Security 0 0 1
Figure 4: XCFxxS Instruction Capture Values Loaded into IR as part of an Instruction Scan Sequence
TDI →
IR[15:9] IR[8:7] IR[6:5] IR[4] IR[3] IR[2] IR[1:0]
→ TDO
Reserved ISC Error ER/PROG
Error
ER/PROG
Status ISC Status DONE 0 1
Figure 5: XCFxxP Instruction Capture Values Loaded into IR as part of an Instruction Scan Sequence
Platform Flash In-System Programmable Configuration PROMS
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Preliminary Product Specification 1-800-255-7778
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Identification Registers
IDCODE Register
The IDCODE is a fixed, vendor-assigned value that is used
to electrically identify the manufacturer and type of the
device being addressed. The IDCODE register is 32 bits
wide. The IDCODE register can be shifted out for examina-
tion by using the IDCODE instruction. The IDCODE is avail-
able to any other system component via JTAG. Ta b l e 7 lists
the IDCODE register values for the Platform Flash PROMs.
The IDCODE register has the following binary format:
vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1
where
v = the die version number
f = the PROM family code
a = the specific Platform Flash PROM product ID
c = the Xilinx manufacture's ID
The LSB of the IDCODE register is always read as logic "1"
as defined by IEEE Std. 1149.1.
USERCODE Register
The USERCODE instruction gives access to a 32-bit user
programmable scratch pad typically used to supply informa-
tion about the device's programmed contents. By using the
USERCODE instruction, a user-programmable identifica-
tion code can be shifted out for examination. This code is
loaded into the USERCODE register during programming of
the Platform Flash PROM. If the device is blank or was not
loaded during programming, the USERCODE register con-
tains FFFFFFFFh.
Customer Code Register
For the XCFxxP Platform Flash PROM, in addition to the
USERCODE, a unique 32-byte Customer Code can be
assigned to each design revision enabled for the PROM.
The Customer Code is set during programming, and is typ-
ically used to supply information about the design revision
contents. A private JTAG instruction is required to read the
Customer Code. If the PROM is blank, or the Customer
Code for the selected design revision was not loaded during
programming, or if the particular design revision is erased,
the Customer Code will contain all ones.
Platform Flash PROM TAP
Characteristics
The Platform Flash PROM family performs both in-system
programming and IEEE 1149.1 boundary-scan (JTAG) test-
ing via a single 4-wire Test Access Port (TAP). This simpli-
fies system designs and allows standard Automatic Test
Equipment to perform both functions. The AC characteris-
tics of the Platform Flash PROM TAP are described as fol-
lows.
TAP Timing
Figure 6 shows the timing relationships of the TAP signals.
These TAP timing characteristics are identical for both
boundary-scan and ISP operations.
Tabl e 7 : IDCODES Assigned to Platform Flash PROMs
Device IDCODE(1) (hex)
XCF01S 05044093
XCF02S 05045093
XCF04S 05046093
XCF08P 05057093
XCF16P 05058093
XCF32P 05059093
Notes:
1. The first four bits indicate the die version number, and may
vary.
Figure 6: Test Access Port Timing
TCK
T
CKMIN
T
MSS
TMS
TDI
TDO
T
MSH
T
DIH
T
DOV
T
DIS
DS026_04_020300
Platform Flash In-System Programmable Configuration PROMS
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Preliminary Product Specification 1-800-255-7778
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TAP AC Parameters
Ta bl e 8 shows the timing parameters for the TAP waveforms shown in Figure 6.
Additional Features for the XCFxxP
Internal Oscillator
The 8/16/32 Mbit XCFxxP Platform Flash PROMs include
an optional internal oscillator which can be used to drive the
CLKOUT and DATA pins on FPGA configuration interface.
The internal oscillator can be enabled during device pro-
gramming, and can be set to either the default frequency or
to a slower frequency (AC Characteristics Over Operat-
ing Conditions When Cascading).
CLKOUT
The 8/16/32 Mbit XCFxxP Platform Flash PROMs include
the programmable option to enable the CLKOUT signal
which allows the PROM to provide a source synchronous
clock aligned to the data on the configuration interface. The
CLKOUT signal is derived from one of two clock sources:
the CLK input pin or the internal oscillator. The input clock
source is selected during the PROM programming
sequence. Output data is available on the rising edge of
CLKOUT.
The CLKOUT signal is enabled during programming, and is
active when CE is Low and OE/RESET is High. When dis-
abled, the CLKOUT pin is put into a high-impedance state
and should be pulled High externally to provide a known
state.
When cascading Platform Flash PROMs with CLKOUT
enabled, after completing it's data transfer, the first PROM
disables CLKOUT and releases the CEO pin enabling the
next PROM in the PROM chain. The next PROM will begin
driving the CLKOUT signal once that PROM is enabled and
data is available for transfer.
During high-speed parallel configuration without compres-
sion, the FPGA drives the BUSY signal on the configuration
interface. When BUSY is asserted High, the PROMs inter-
nal address counter stops incrementing, and the current
data value is held on the data outputs. While BUSY is High,
the PROM will continue driving the CLKOUT signal to the
FPGA, clocking the FPGA’s configuration logic. When the
FPGA deasserts BUSY, indicating that it is ready to receive
additional configuration data, the PROM will begin driving
new data onto the configuration interface.
Decompression
The 8/16/32 Mbit XCFxxP Platform Flash PROMs include a
built-in data decompressor compatible with Xilinx advanced
compression technology. Compressed Platform Flash
PROM files are created from the target FPGA bitstream(s)
using the iMPACT software. Only Slave Serial and Slave
SelectMAP (parallel) configuration modes are supported for
FPGA configuration when using a XCFxxP PROM pro-
grammed with a compressed bitstream. Compression rates
will vary depending on several factors, including the target
device family and the target design contents.
The decompression option is enabled during the PROM
programming sequence. The PROM decompresses the
stored data before driving both clock and data onto the
FPGA's configuration interface. If Decompression is
enabled, then the Platform Flash clock output pin (CLK-
OUT) must be used as the clock signal for the configuration
interface, driving the target FPGA's configuration clock input
pin (CCLK). Either the PROM's CLK input pin or the internal
oscillator must be selected as the source for CLKOUT. Any
target FPGA connected to the PROM must operate as slave
in the configuration chain, with the configuration mode set to
Slave Serial mode or Slave SelectMap (parallel) mode.
When decompression is enabled, the CLKOUT signal
becomes a controlled clock output with a reduced maximum
frequency and remains Low when decompressed data is
not ready.
The BUSY input is automatically disabled when decompres-
sion is enabled.
Tabl e 8 : Test Access Port Timing Parameters
Symbol Parameter Min Max Units
TCKMIN1 TCK minimum clock period when VCCJ = 2.5V or 3.3V 100 - ns
TCKMIN2 TCK minimum clock period, Bypass Mode, when VCCJ = 2.5V or 3.3V 50 - ns
TMSS TMS setup time when VCCJ = 2.5V or 3.3V 10 - ns
TMSH TMS hold time when VCCJ = 2.5V or 3.3V 25 - ns
TDIS TDI setup time when VCCJ = 2.5V or 3.3V 10 - ns
TDIH TDI hold time when VCCJ = 2.5V or 3.3V 25 - ns
TDOV TDO valid delay when VCCJ = 2.5V or 3.3V - 30 ns
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.4) July 20, 2004 www.xilinx.com 9
Preliminary Product Specification 1-800-255-7778
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Design Revisioning
Design Revisioning allows the user to create up to four
unique design revisions on a single PROM or stored across
multiple cascaded PROMs. Design Revisioning is sup-
ported for the 8/16/32 Mbit XCFxxP Platform Flash PROMs
in both serial and parallel modes. Design Revisioning can
be used with compressed PROM files, and also when the
CLKOUT feature is enabled. The PROM programming files
along with the revision information files (.cfi) are created
using the iMPACT software. The .cfi file is required to enable
design revision programming in iMPACT.
A single design revision is composed of from 1 to n 8-Mbit
memory blocks. If a single design revision contains less
than 8 Mbits of data, then the remaining space is padded
with all ones. A larger design revision can span several
8-Mbit memory blocks, and any space remaining in the last
8-Mbit memory block is padded with all ones.
• A single 32-Mbit PROM contains four 8-Mbit memory
blocks, and can therefore store up to four separate
design revisions: one 32-Mbit design revision, two
16-Mbit design revisions, three 8-Mbit design revisions,
four 8-Mbit design revisions, and so on.
• Because of the 8-Mbit minimum size requirement for
each revision, a single 16-Mbit PROM can only store
up to two separate design revisions: one 16-Mbit
design revision, one 8-Mbit design revision, or two
8-Mbit design revisions.
• A single 8-Mbit PROM can store only one 8-Mbit
design revision.
Larger design revisions can be split over several cascaded
PROMs. For example, two 32-Mbit PROMs can store up to
four separate design revisions: one 64-Mbit design revision,
two 32-Mbit design revisions, three 16-Mbit design revi-
sions, four 16-Mbit design revisions, and so on. When cas-
cading one 16-Mbit PROM and one 8-Mbit PROM, there are
24 Mbits of available space, and therefore up to three sepa-
rate design revisions can be stored: one 24-Mbit design
revision, two 8-Mbit design revisions, or three 8-Mbit design
revisions.
See Figure 7 for a few basic examples of how multiple revi-
sions can be stored. The design revision partitioning is han-
dled automatically during file generation in iMPACT.
During the PROM file creation, each design revision is
assigned a revision number:
Revision 0 = '00'
Revision 1 = '01'
Revision 2 = '10'
Revision 3 = '11'
After programming the Platform Flash PROM, a particular
design revision can be selected using the external
REV_SEL[1:0] pins or using the internal programmable
design revision control bits. The EN_EXT_SEL pin deter-
mines if the external pins or internal bits are used to select
the design revision. When EN_EXT_SEL is Low, design
revision selection is controlled by the external Revision
Select pins, REV_SEL[1:0]. When EN_EXT_SEL is High,
design revision selection is controlled by the internal pro-
grammable Revision Select control bits. During power up,
the design revision selection inputs (pins or control bits) are
sampled internally. After power up, when CE is asserted
(Low) enabling the PROM inputs, the design revision selec-
tion inputs are sampled again after the rising edge of the CF
pulse. The data from the selected design revision is then
presented on the FPGA configuration interface.
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.4) July 20, 2004 www.xilinx.com 10
Preliminary Product Specification 1-800-255-7778
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PROM to FPGA Configuration Mode and Connections Summary
The FPGA's I/O, logical functions, and internal interconnec-
tions are established by the configuration data contained in
the FPGA’s bitstream. The bitstream is loaded into the
FPGA either automatically upon power up, or on command,
depending on the state of the FPGA's mode pins. Xilinx
Platform Flash PROMs are designed to download directly to
the FPGA configuration interface. FPGA configuration
modes which are supported by the XCFxxS Platform Flash
PROMs include: Master Serial and Slave Serial. FPGA con-
figuration modes which are supported by the XCFxxP Plat-
form Flash PROMs include: Master Serial, Slave Serial,
Master SelectMAP, and Slave SelectMAP. Below is a short
summary of the supported FPGA configuration modes. See
the respective FPGA data sheet for device configuration
details, including which configuration modes are supported
by the targeted FPGA device.
FPGA Master Serial Mode
In Master Serial mode, the FPGA automatically loads the
configuration bitstream in bit-serial form from external mem-
ory synchronized by the configuration clock (CCLK) gener-
ated by the FPGA. Upon power-up or reconfiguration, the
FPGA's mode select pins are used to select the Master
Serial configuration mode. Master Serial Mode provides a
simple configuration interface. Only a serial data line, a
clock line, and two control lines (INIT and DONE) are
required to configure an FPGA. Data from the PROM is
read out sequentially on a single data line (DIN), accessed
via the PROM's internal address counter which is incre-
mented on every valid rising edge of CCLK. The serial bit-
stream data must be set up at the FPGA’s DIN input pin a
short time before each rising edge of the FPGA's internally
generated CCLK signal.
Figure 7: Design Revision Storage Examples
REV 0
(8 Mbits)
REV 1
(8 Mbits)
REV 2
(8 Mbits)
REV 3
(8 Mbits)
REV 0
(8 Mbits)
REV 1
(8 Mbits)
REV 2
(16 Mbits)
REV 0
(16 Mbits)
REV 1
(16 Mbits)
REV 0
(8 Mbits)
REV 1
(24 Mbits)
REV 0
(32 Mbits)
4 Design Revisions 3 Design Revisions 2 Design Revisions 1 Design Revision
(a) Design Revision storage examples for a single XCF32P PROM
REV 0
(16 Mbits)
REV 1
(16 Mbits)
REV 2
(16 Mbits)
REV 3
(16 Mbits)
REV 0
(16 Mbits)
REV 1
(16 Mbits)
REV 2
(32 Mbits)
REV 0
(32 Mbits)
REV 1
(32 Mbits)
REV 0
(16 Mbits)
REV 1
(16 Mbits)
REV 0
(32 Mbits)
4 Design Revisions 3 Design Revisions 2 Design Revisions 1 Design Revision
(b) Design Revision storage examples spanning two XCF32P PROMs
PROM 0 PROM 0 PROM 0 PROM 0 PROM 0
PROM 0 PROM 0 PROM 0 PROM 0 PROM 0
REV 0
(32 Mbits)
REV 1
(32 Mbits)
PROM 1 PROM 1 PROM 1 PROM 1 PROM 1
ds123_20_102103
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.4) July 20, 2004 www.xilinx.com 11
Preliminary Product Specification 1-800-255-7778
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Typically, a wide range of frequencies can be selected for
the FPGA’s internally generated CCLK which always starts
at a slow default frequency. The FPGA’s bitstream contains
configuration bits which can switch CCLK to a higher fre-
quency for the remainder of the Master Serial configuration
sequence. The desired CCLK frequency is selected during
bitstream generation.
Connecting the FPGA device to the configuration PROM for
Master Serial Configuration Mode (Figure 8):
• The DATA output of the PROM(s) drive the DIN input of
the lead FPGA device.
• The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s)
•The CEO
output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
• The OE/RESET pins of all PROMs are connected to
the INIT_B pins of all FPGA devices. This connection
assures that the PROM address counter is reset before
the start of any (re)configuration.
•The PROM CE
input can be driven from the DONE pin.
The CE input of the first (or only) PROM can be driven
by the DONE output of all target FPGA devices,
provided that DONE is not permanently grounded. CE
can also be permanently tied Low, but this keeps the
DATA output active and causes an unnecessary ICC
active supply current (DC Characteristics Over
Operating Conditions).
•The PROM CF pin is typically connected to the FPGA's
PROG_B (or PROGRAM) input. For the XCFxxP only,
the CF pin is a bidirectional pin. If the XCFxxP CF pin is
not connected to the FPGA's PROG_B (or PROGRAM)
input, then the pin should be tied High.
FPGA Slave Serial Mode
In Slave Serial mode, the FPGA loads the configuration bit-
stream in bit-serial form from external memory synchro-
nized by an externally supplied clock. Upon power-up or
reconfiguration, the FPGA's mode select pins are used to
select the Slave Serial configuration mode. Slave Serial
Mode provides a simple configuration interface. Only a
serial data line, a clock line, and two control lines (INIT and
DONE) are required to configure an FPGA. Data from the
PROM is read out sequentially on a single data line (DIN),
accessed via the PROM's internal address counter which is
incremented on every valid rising edge of CCLK. The serial
bitstream data must be set up at the FPGA’s DIN input pin a
short time before each rising edge of the externally provided
CCLK.
Connecting the FPGA device to the configuration PROM for
Slave Serial Configuration Mode (Figure 9):
• The DATA output of the PROM(s) drive the DIN input of
the lead FPGA device.
• The PROM CLKOUT (for XCFxxP only) or an external
clock source drives the FPGA's CCLK input.
•The CEO
output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
• The OE/RESET pins of all PROMs are connected to
the INIT_B (or INIT) pins of all FPGA devices. This
connection assures that the PROM address counter is
reset before the start of any (re)configuration.
•The PROM CE
input can be driven from the DONE pin.
The CE input of the first (or only) PROM can be driven
by the DONE output of all target FPGA devices,
provided that DONE is not permanently grounded. CE
can also be permanently tied Low, but this keeps the
DATA output active and causes an unnecessary ICC
active supply current (DC Characteristics Over
Operating Conditions).
•The PROM CF pin is typically connected to the FPGA's
PROG_B (or PROGRAM) input. For the XCFxxP only,
the CF pin is a bidirectional pin. If the XCFxxP CF pin is
not connected to the FPGA's PROG_B (or PROGRAM)
input, then the pin should be tied High.
Serial Daisy Chain
Multiple FPGAs can be daisy-chained for serial configura-
tion from a single source. After a particular FPGA has been
configured, the data for the next device is routed internally
to the FPGA’s DOUT pin. Typically the data on the DOUT
pin changes on the falling edge of CCLK, although for some
devices the DOUT pin changes on the rising edge of CCLK.
Consult the respective device data sheets for detailed infor-
mation on a particular FPGA device. For clocking the
daisy-chained configuration, either the first FPGA in the
chain can be set to Master Serial, generating the CCLK,
with the remaining devices set to Slave Serial (Figure 10),
or all the FPGA devices can be set to Slave Serial and an
externally generated clock can be used to drive the FPGA's
configuration interface.
FPGA Master SelectMAP (Parallel) Mode(1)
In Master SelectMAP mode, byte-wide data is written into
the FPGA, typically with a BUSY flag controlling the flow of
data, synchronized by the configuration clock (CCLK) gen-
erated by the FPGA. Upon power-up or reconfiguration, the
FPGA's mode select pins are used to select the Master
SelectMAP configuration mode. The configuration interface
typically requires a parallel data bus, a clock line, and two
control lines (INIT and DONE). In addition, the FPGA’s Chip
Select, Write, and BUSY pins must be correctly controlled to
enable SelectMAP configuration. The configuration data is
read from the PROM byte by byte on pins [D0..D7],
accessed via the PROM's internal address counter which is
incremented on every valid rising edge of CCLK. The bit-
1. The Master SelectMAP (Parallel) FPGA configuration mode is sup-
ported only by the XCFxxP Platform Flash PROM. This mode is not
supported by the XCFxxS Platform Flash PROM.
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.4) July 20, 2004 www.xilinx.com 12
Preliminary Product Specification 1-800-255-7778
R
stream data must be set up at the FPGA’s [D0..D7] input
pins a short time before each rising edge of the FPGA's
internally generated CCLK signal. If BUSY is asserted
(High) by the FPGA, the configuration data must be held
until BUSY goes Low. An external data source or external
pull-down resistors must be used to enable the FPGA's
active Low Chip Select (CS or CS_B) and Write (WRITE or
RDWR_B) signals to enable the FPGA's SelectMAP config-
uration process.
The Master SelectMAP configuration interface is clocked by
the FPGA’s internal oscillator. Typically, a wide range of fre-
quencies can be selected for the internally generated CCLK
which always starts at a slow default frequency. The FPGA’s
bitstream contains configuration bits which can switch
CCLK to a higher frequency for the remainder of the Master
SelectMAP configuration sequence. The desired CCLK fre-
quency is selected during bitstream generation.
Connecting the FPGA device to the configuration PROM for
Master SelectMAP (Parallel) Configuration Mode
(Figure 11):
• The DATA outputs of the PROM(s) drive the [D0..D7]
input of the lead FPGA device.
• The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s)
•The CEO
output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
• The OE/RESET pins of all PROMs are connected to
the INIT_B pins of all FPGA devices. This connection
assures that the PROM address counter is reset before
the start of any (re)configuration.
•The PROM CE
input can be driven from the DONE pin.
The CE input of the first (or only) PROM can be driven
by the DONE output of all target FPGA devices,
provided that DONE is not permanently grounded. CE
can also be permanently tied Low, but this keeps the
DATA output active and causes an unnecessary ICC
active supply current (DC Characteristics Over
Operating Conditions).
• For high-frequency parallel configuration, the BUSY
pins of all PROMs are connected to the FPGA's BUSY
output. This connection assures that the next data
transition for the PROM is delayed until the FPGA is
ready for the next configuration data byte.
•The PROM CF
pin is typically connected to the FPGA's
PROG_B (or PROGRAM) input. For the XCFxxP only,
the CF pin is a bidirectional pin. If the XCFxxP CF pin is
not connected to the FPGA's PROG_B (or PROGRAM)
input, then the pin should be tied High.
FPGA Slave SelectMAP (Parallel) Mode(1)
In Slave SelectMAP mode, byte-wide data is written into the
FPGA, typically with a BUSY flag controlling the flow of
data, synchronized by an externally supplied configuration
clock (CCLK). Upon power-up or reconfiguration, the
FPGA's mode select pins are used to select the Slave
SelectMAP configuration mode. The configuration interface
typically requires a parallel data bus, a clock line, and two
control lines (INIT and DONE). In addition, the FPGA’s Chip
Select, Write, and BUSY pins must be correctly controlled to
enable SelectMAP configuration. The configuration data is
read from the PROM byte by byte on pins [D0..D7],
accessed via the PROM's internal address counter which is
incremented on every valid rising edge of CCLK. The bit-
stream data must be set up at the FPGA’s [D0..D7] input
pins a short time before each rising edge of the provided
CCLK. If BUSY is asserted (High) by the FPGA, the config-
uration data must be held until BUSY goes Low. An external
data source or external pull-down resistors must be used to
enable the FPGA's active Low Chip Select (CS or CS_B)
and Write (WRITE or RDWR_B) signals to enable the
FPGA's SelectMAP configuration process.
After configuration, the pins of the SelectMAP port can be
used as additional user I/O. Alternatively, the port can be
retained using the persist option.
Connecting the FPGA device to the configuration PROM for
Slave SelectMAP (Parallel) Configuration Mode (Figure 12):
• The DATA outputs of the PROM(s) drives the [D0..D7]
inputs of the lead FPGA device.
• The PROM CLKOUT (for XCFxxP only) or an external
clock source drives the FPGA's CCLK input
•The CEO
output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
• The OE/RESET pins of all PROMs are connected to
the INIT_B pins of all FPGA devices. This connection
assures that the PROM address counter is reset before
the start of any (re)configuration.
•The PROM CE
input can be driven from the DONE pin.
The CE input of the first (or only) PROM can be driven
by the DONE output of all target FPGA devices,
provided that DONE is not permanently grounded. CE
can also be permanently tied Low, but this keeps the
DATA output active and causes an unnecessary ICC
active supply current (DC Characteristics Over
Operating Conditions).
• For high-frequency parallel configuration, the BUSY
pins of all PROMs are connected to the FPGA's BUSY
output. This connection assures that the next data
transition for the PROM is delayed until the FPGA is
ready for the next configuration data byte.
•The PROM CF
pin is typically connected to the FPGA's
PROG_B (or PROGRAM) input. For the XCFxxP only,
the CF pin is a bidirectional pin. If the XCFxxP CF pin is
not connected to the FPGA's PROG_B (or PROGRAM)
1. The Slave SelectMAP (Parallel) FPGA configuration mode is sup-
ported only by the XCFxxP Platform Flash PROMs.This mode is
not supported by the XCFxxS Platform Flash PROM.
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.4) July 20, 2004 www.xilinx.com 13
Preliminary Product Specification 1-800-255-7778
R
input, then the pin should be tied High.
FPGA SelectMAP (Parallel) Device Chaining(1)
Multiple Virtex-II FPGAs can be configured using the
SelectMAP mode, and be made to start up simultaneously.
To configure multiple devices in this way, wire the individual
CCLK, DONE, INIT, Data ([D0..D7]), Write (WRITE or
RDWR_B), and BUSY pins of all the devices in parallel. If all
devices are to be configured with the same bitstream, read-
back is not being used, and the CCLK frequency selected
does not require the use of the BUSY signal, the CS_B pins
can be connected to a common line so all of the devices are
configured simultaneously (Figure 13).
With additional control logic, the individual devices can be
loaded separately by asserting the CS_B pin of each device
in turn and then enabling the appropriate configuration data.
The PROM can also store the individual bitstreams for each
FPGA for SelectMAP configuration in separate design revi-
sions. When design revisioning is utilized, additional control
logic can be used to select the appropriate bitstream by
asserting the EN_EXT_SEL pin, and using the
REV_SEL[1:0] pins to select the required bitstream, while
asserting the CS_B pin for the FPGA the bitstream is target-
ing (Figure 14).
For clocking the parallel configuration chain, either the first
FPGA in the chain can be set to Master SelectMAP, gener-
ating the CCLK, with the remaining devices set to Slave
SelectMAP, or all the FPGA devices can be set to Slave
SelectMAP and an externally generated clock can be used
to drive the configuration interface. Again, the respective
device data sheets should be consulted for detailed infor-
mation on a particular FPGA device, including which config-
uration modes are supported by the targeted FPGA device.
Cascading Configuration PROMs
When configuring multiple FPGAs in a serial daisy chain,
configuring multiple FPGAs in a SelectMAP parallel chain,
or configuring a single FPGA requiring a larger configura-
tion bitstream, cascaded PROMs provide additional mem-
ory (Figure 10, Figure 13, Figure 14, and Figure 15).
Multiple Platform Flash PROMs can be concatenated by
using the CEO output to drive the CE input of the down-
stream device. The clock signal and the data outputs of all
Platform Flash PROMs in the chain are interconnected.
After the last data from the first PROM is read, the first
PROM asserts its CEO output Low and drives its outputs to
a high-impedance state. The second PROM recognizes the
Low level on its CE input and immediately enables its out-
puts.
After configuration is complete, address counters of all cas-
caded PROMs are reset if the PROM OE/RESET pin goes
Low or CE goes High.
When utilizing the advanced features for the XCFxxP Plat-
form Flash PROM, including the clock output (CLKOUT)
option, decompression option, or design revisioning, pro-
gramming files which span cascaded PROM devices can
only be created for cascaded chains containing only
XCFxxP PROMs. If the advanced features are not used,
then cascaded PROM chains can contain both XCFxxP and
XCFxxS PROMs.
Initiating FPGA Configuration
The options for initiating FPGA configuration via the Plat-
form Flash PROM include:
1. Automatic configuration on power up
2. Applying an external PROG_B (or PROGRAM) pulse
3. Applying the JTAG CONFIG instruction
Following the FPGA’s power-on sequence or the assertion
of the PROG_B (or PROGRAM) pin the FPGA’s configura-
tion memory is cleared, the configuration mode is selected,
and the FPGA is ready to accept a new configuration bit-
stream. The FPGA’s PROG_B pin can be controlled by an
external source, or alternatively, the Platform Flash PROMs
incorporate a CF pin that can be tied to the FPGA’s
PROG_B pin. Executing the CONFIG instruction through
JTAG pulses the CF output Low once for 300-500 ns, reset-
ting the FPGA and initiating configuration. The iMPACT soft-
ware can issue the JTAG CONFIG command to initiate
FPGA configuration by setting the "Load FPGA" option.
When using the XCFxxP Platform Flash PROM with design
revisioning enabled, the CF pin should always be connected
to the PROG_B (or PROGRAM) pin on the FPGA to ensure
that the current design revision selection is sampled when
the FPGA is reset. The XCFxxP PROM samples the current
design revision selection from the external REV_SEL pins
or the internal programmable Revision Select bits on the ris-
ing edge of CF
. When the JTAG CONFIG command is exe-
cuted, the XCFxxP will sample the new design revision
before initiating the FPGA configuration sequence. When
using the XCFxxP Platform Flash PROM without design
revisioning, if the CF pin is not connected to the FPGA
PROG_B (or PROGRAM) pin, then the XCFxxP CF pin
should be tied High.
1. The SelectMAP (Parallel) FPGA configuration modes are sup-
ported only by the XCFxxP Platform Flash PROM.These modes
are not supported by the XCFxxS Platform Flash PROM.
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.4) July 20, 2004 www.xilinx.com 14
Preliminary Product Specification 1-800-255-7778
R
Configuration PROM to FPGA Device Interface Connection Diagrams
Figure 8: Configuring in Master Serial Mode
Xilinx FPGA
Master Serial
DIN
CCLK
DONE
INIT_B
PROG_B
TDI
TMS
TCK
GND
MODE PINS(1)
DOUT
TDO
VCCJ VCCO VCCINT
DIN
CCLK
DONE
INIT_B
PROG_B
DIN
CCLK
DONE
INIT_B
PROG_B
4.7 kΩ
4.7 kΩ
(1)
VCCO(2)
...OPTIONAL
Daisy-chained
Slave FPGAs
with
different
configurations
...OPTIONAL
Slave FPGAs
with
identical
configurations
TDI
TMS
TCK
TDO
Notes:
1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet.
2 For compatible voltages, refer to the appropriate data sheet.
3 For the XCFxxS the CF pin is an output pin. For the XCFxxP the CF pin is a bidirectional pin.
Platform Flash
PROM
VCCINT
VCCO(2)
VCCJ(2)
TDI
TMS
TCK
GND
D0
CLK
CE
CEO
OE/RESET
CF(3)
TDO
ds123_11_071304
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.4) July 20, 2004 www.xilinx.com 15
Preliminary Product Specification 1-800-255-7778
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Figure 9: Configuring in Slave Serial Mode
Xilinx FPGA
Slave Serial
DIN
CCLK
DONE
INIT_B
PROG_B
TDI
TMS
TCK
GND
MODE PINS(1)
DOUT
TDO
VCCJ VCCO VCCINT
DIN
CCLK
DONE
INIT_B
PROG_B
DIN
CCLK
DONE
INIT_B
PROG_B
4.7 kΩ
4.7 kΩ
(1)
VCCO(2)
...OPTIONAL
Daisy-chained
Slave FPGAs
with
different
configurations
...OPTIONAL
Slave FPGAs
with
identical
configurations
TDI
TMS
TCK
TDO
Notes:
1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet.
2 For compatible voltages, refer to the appropriate data sheet.
3 In Slave Serial mode, the configuration interface can be clocked by an external oscillator, or
optionally—for the XCFxxP Platform Flash PROM only—the CLKOUT signal can be used to drive
the FPGA's configuration clock (CCLK). If the XCFxxP PROM's CLKOUT signal is used, then it
must be tied to a 4.7KΩ resistor pulled up to VCCO.
4 For the XCFxxS the CF pin is an output pin. For the XCFxxP the CF pin is a bidirectional pin.
Platform Flash
PROM
VCCINT
VCCO(2)
VCCJ(2)
TDI
TMS
TCK
GND
D0
CLK(3)
CE
CEO
OE/RESET
CF(4)
TDO
ds123_12_071304
External (3)
Oscillator
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.4) July 20, 2004 www.xilinx.com 16
Preliminary Product Specification 1-800-255-7778
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Figure 10: Configuring Multiple Devices Master/Slave Serial Mode
Platform Flash
PROM
First
PROM
(PROM 0)
VCCINT
VCCO(2)
VCCJ(2)
TDI
TMS
TCK
D0
CLK
CE
CEO
OE/RESET
CF(3)
TDO
Xilinx FPGA
Master Serial
DIN
CCLK
DONE
INIT_B
PROG_B
TDI
TMS
TCK
MODE PINS(1)
DOUT
TDO
VCCJ VCCO VCCINT
4.7 kΩ
4.7 kΩ
(1)
VCCO(2)
TDI
TMS
TCK
TDO
Notes:
1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet.
2 For compatible voltages, refer to the appropriate data sheet.
3 For the XCFxxS the CF pin is an output pin. For the XCFxxP the CF pin is a bidirectional pin.
Xilinx FPGA
Slave Serial
DIN
CCLK
DONE
INIT_B
PROG_B
TDI
TMS
TCK
Platform Flash
PROM
Cascaded
PROM
(PROM 1)
VCCINT
VCCO(2)
VCCJ(2)
TDI
TMS
TCK
D0
CLK
CE
CEO
OE/RESET
CF(3)
TDO
VCCJ VCCO VCCINT
MODE PINS(1)
TDO
ds123_13_031804
GND
GNDGND
GND
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.4) July 20, 2004 www.xilinx.com 17
Preliminary Product Specification 1-800-255-7778
R
Figure 11: Configuring in Master SelectMAP Mode
XCFxxP
Platform Flash
PROM
VCCINT
VCCO(2)
VCCJ(2)
TDI
TMS
TCK
GND
D[0:7]
CLK
CE
CEO
OE/RESET
CF(5)
BUSY(4)
TDO
Xilinx FPGA
Master SelectMAP
D[0:7]
CCLK
DONE
INIT_B
PROG_B
BUSY(4)
TDI
TMS
TCK
GND
MODE PINS(1)
RDWR_B
CS_B
TDO
VCCJ VCCO VCCINT
D[0:7]
CCLK
DONE
INIT_B
PROG_B
BUSY(4)
4.7 kΩ
4.7 kΩ
(1)
VCCO(2)
...OPTIONAL
Slave FPGAs
with
identical
configurations
TDI
TMS
TCK
TDO
Notes:
1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet.
2 For compatible voltages, refer to the appropriate data sheet.
3 CS_B (or CS) and RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown.
4 The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only required for
high-frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet.
5 For the XCFxxP the CF pin is a bidirectional pin.
1KΩ
1KΩ
I/O(3)
I/O(3)
ds123_14_031804
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.4) July 20, 2004 www.xilinx.com 18
Preliminary Product Specification 1-800-255-7778
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Figure 12: Configuring in Slave SelectMAP Mode
XCFxxP
Platform Flash
PROM
VCCINT
VCCO(2)
VCCJ(2)
TDI
TMS
TCK
GND
D[0:7]
CLK(5)
CE
CEO
OE/RESET
CF(6)
BUSY(4)
TDO
Xilinx FPGA
Slave SelectMAP
D[0:7]
CCLK
DONE
INIT_B
PROG_B
BUSY(4)
TDI
TMS
TCK
GND
MODE PINS(1)
RDWR_B
CS_B
TDO
VCCJ VCCO VCCINT
D[0:7]
CCLK
DONE
INIT_B
PROG_B
BUSY(4)
4.7 kΩ
4.7 kΩ
(1)
VCCO(2)
...OPTIONAL
Slave FPGAs
with
identical
configurations
TDI
TMS
TCK
TDO
Notes:
1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet.
2 For compatible voltages, refer to the appropriate data sheet.
3 CS_B (or CS) and RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown.
4 The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only required for
high-frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet.
5 If the XCFxxP Platform Flash PROM is not used with CLKOUT enabled to drive CCLK, then an external clock is required
for Slave SelectMAP (or Slave Parallel) modes. If CLKOUT is used, then it must be tied to a 4.7KΩ resistor pulled up
to VCCO.
6 For the XCFxxP the CF pin is a bidirectional pin.
1KΩ
1KΩ
I/O(3)
I/O(3)
ds123_15_031804
External (5)
Oscillator
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.4) July 20, 2004 www.xilinx.com 19
Preliminary Product Specification 1-800-255-7778
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Figure 13: Configuring Multiple Devices with Identical Patterns in Master/Slave SelectMAP Mode
XCFxxP
Platform Flash
PROM
First
PROM
(PROM 0)
VCCINT
VCCO(2)
VCCJ(2)
TDI
TMS
TCK
GND
D[0:7]
CLK
CE
CEO
OE/RESET
CF(5)
BUSY(4)
TDO
Xilinx FPGA
Master SelectMAP
D[0:7]
CCLK
DONE
INIT_B
PROG_B
BUSY(4)
TDI
TMS
TCK
GND
MODE PINS(1)
TDO
VCCJ VCCO VCCINT
4.7 kΩ
4.7 kΩ
(1)
VCCO(2)
TDI
T
MS
TCK
T
DO
Notes:
1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet.
2 For compatible voltages, refer to the appropriate data sheet.
3 CS_B (or CS) and RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown.
4 The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only required for
high-frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet.
5 For the XCFxxP the CF pin is a bidirectional pin.
Xilinx FPGA
Slave SelectMAP
D[0:7]
CCLK
DONE
INIT_B
PROG_B
BUSY(4)
TDI
TMS
TCK
GND
XCFxxP
Platform Flash
PROM
Cascaded
PROM
(PROM 1)
VCCINT
VCCO(2)
VCCJ(2)
TDI
TMS
TCK
GND
D[0:7]
CLK
CE
CEO
OE/RESET
CF(5)
BUSY(4)
TDO
VCCJ VCCO VCCINT
MODE PINS(1)
TDO
ds123_16_031804
1KΩ
1KΩ
I/O(3)
I/O(3)
1KΩ
1KΩ
I/O(3)
I/O(3)
RDWR_B
CS_B
RDWR_B
CS_B
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.4) July 20, 2004 www.xilinx.com 20
Preliminary Product Specification 1-800-255-7778
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Figure 14: Configuring Multiple Devices with Design Revisioning in Slave Serial Mode
XCFxxP
Platform Flash
PROM
First
PROM
(PROM 0)
VCCINT
VCCO(2)
VCCJ(2)
TDI
TMS
TCK
EN_EX_SEL
REV_SEL[1:0]
D0
CLK(3)
CE
CEO
OE/RESET
CF(4)
TDO
Xilinx FPGA
Slave Serial
DIN
CCLK
DONE
INIT_B
PROG_B
TDI
TMS
TCK
VCCJ VCCO VCCINT
4.7 kΩ
4.7 kΩ
(1)
VCCO(2)
TDI
TMS
TCK
TDO
2 For compatible voltages, refer to the appropriate data sheet.
3 In Slave Serial mode, the configuration interface can be clocked by an external oscillator, or
optionally the CLKOUT signal can be used to drive the FPGA's configuration clock (CCLK).
If the XCFxxP PROM's CLKOUT signal is used, then it must be tied to a 4.7KΩ resistor pulled
up to VCCO.
4 For the XCFxxP the CF pin is a bidirectional pin.
XCFxxP
Platform Flash
PROM
Cascaded
PROM
(PROM 1)
VCCINT
VCCO(2)
VCCJ(2)
TDI
TMS
TCK
EN_EX_SEL
REV_SEL[1:0]
D0
CLK(3)
CE
CEO
OE/RESET
CF(4)
TDO
VCCJ VCCO VCCINT
ds123_17_031804
Design
Revision
Control
Logic
EN_EXT_SEL
REV_SEL[1:0]
DONE
CF / PROG_B
Xilinx FPGA
Slave Serial
DIN
CCLK
DONE
INIT_B
PROG_B
TDI
TMS
TCK
MODE PINS(1)
TDO
GNDGND
GND
DOUT
MODE PINS(1)
GND
External (3)
Oscillator
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.4) July 20, 2004 www.xilinx.com 21
Preliminary Product Specification 1-800-255-7778
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Figure 15: Configuring Multiple Devices with Design Revisioning in Slave SelectMAP Mode
XCFxxP
Platform Flash
PROM
First
PROM
(PROM 0)
VCCINT
VCCO(2)
VCCJ(2)
TDI
TMS
TCK
EN_EX_SEL
REV_SEL[1:0]
GND
D[0:7]
CLK(5)
CE
CEO
OE/RESET
CF(6)
BUSY(4)
TDO
Xilinx FPGA
Slave SelectMAP
D[0:7]
CCLK
DONE
INIT_B
PROG_B
BUSY(4)
TDI
TMS
TCK
MODE PINS(1)
RDWR_B
CS_B
TDO
VCCJ VCCO VCCINT
4.7 kΩ
4.7 kΩ
(1)
VCCO(2)
TDI
TMS
TCK
TDO
Notes:
1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet.
2 For compatible voltages, refer to the appropriate data sheet.
3 RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown.
4 The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only
required for high frequency SelectMAP mode configuration. For BUSY pin requirements, refer to
the appropriate FPGA data sheet.
5 In Slave SelectMAP mode, the configuration interface can be clocked by an external oscillator, or
optionally the CLKOUT signal can be used to drive the FPGA's configuration clock (CCLK).
If the XCFxxP PROM's CLKOUT signal is used, then it must be tied to a 4.7KΩ resistor pulled
up to VCCO.
6 For the XCFxxP the CF pin is a bidirectional pin.
Xilinx FPGA
Slave SelectMAP
D[0:7]
CCLK
DONE
INIT_B
PROG_B
BUSY(4)
TDI
TMS
TCK
MODE PINS(1)
RDWR_B
CS_B
TDO
XCFxxP
Platform Flash
PROM
Cascaded
PROM
(PROM 1)
VCCINT
VCCO(2)
VCCJ(2)
TDI
TMS
TCK
EN_EX_SEL
REV_SEL[1:0]
GND
D[0:7]
CLK(5)
CE
CEO
OE/RESET
CF(6)
BUSY(4)
TDO
VCCJ VCCO VCCINT
1KΩ
I/O(3)
1KΩ
I/O(3)
EN_EXT_SEL
REV_SEL[1:0]
CF
DONE
PROG_B
CS_B[1:0]
Design
Revision
Control
Logic
GND GND
ds123_18_031804
External (5)
Oscillator
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.4) July 20, 2004 www.xilinx.com 22
Preliminary Product Specification 1-800-255-7778
R
Reset and Power-On Reset Activation
At power up, the device requires the VCCINT power supply to
monotonically rise to the nominal operating voltage within
the specified VCCINT rise time. If the power supply cannot
meet this requirement, then the device might not perform
power-on reset properly. During the power-up sequence,
OE/RESET is held Low by the PROM. Once the required
supplies have reached their respective POR (Power On
Reset) thresholds, the OE/RESET release is delayed (TOER
minimum) to allow more margin for the power supplies to
stabilize before initiating configuration. The OE/RESET pin
is connected to an external 4.7kΩ pull-up resistor and also
to the target FPGA's INIT pin. For systems utilizing slow-ris-
ing power supplies, an additional power monitoring circuit
can be used to delay the target configuration until the sys-
tem power reaches minimum operating voltages by holding
the OE/RESET pin Low. When OE/RESET is released, the
FPGA’s INIT pin is pulled High allowing the FPGA's config-
uration sequence to begin. If the power drops below the
power-down threshold (VCCPD), the PROM resets and
OE/RESET is again held Low until the after the POR thresh-
old is reached. OE/RESET polarity is not programmable.
These power-up requirements are shown graphically in
Figure 16.
For a fully powered Platform Flash PROM, a reset occurs
whenever OE/RESET is asserted (Low) or CE is deas-
serted (High). The address counter is reset, CEO is driven
High, and the remaining outputs are placed in a high-imped-
ance state.
Notes:
1. The XCFxxS PROM only requires VCCINT to rise above
its POR threshold before releasing OE/RESET.
2. The XCFxxP PROM requires both VCCINT to rise above
its POR threshold and for VCCO to reach the
recommended operating voltage level before releasing
OE/RESET
.
I/O Input Voltage Tolerance and Power
Sequencing
The I/Os on each re-programmable Platform Flash PROM
are fully 3.3V-tolerant. This allows 3V CMOS signals to con-
nect directly to the inputs without damage. The core power
supply (VCCINT), JTAG pin power supply (VCCJ), output
power supply (VCCO), and external 3V CMOS I/O signals
can be applied in any order.
Additionally, for the XCFxxS PROM only, when VCCO is sup-
plied at 2.5V or 3.3V and VCCINT is supplied at 3.3V, the I/Os
are 5V-tolerant. This allows 5V CMOS signals to connect
directly to the inputs on a powered XCFxxS PROM without
damage. Failure to power the PROM correctly while supply-
ing a 5V input signal may result in damage to the XCFxxS
device.
Standby Mode
The PROM enters a low-power standby mode whenever CE
is deasserted (High). In standby mode, the address counter
is reset, CEO is driven High, and the remaining outputs are
placed in a high-impedance state regardless of the state of
the OE/RESET input. For the device to remain in the
low-power standby mode, the JTAG pins TMS, TDI, and
TDO must not be pulled Low, and TCK must be stopped
(High or Low).
When using the FPGA DONE signal to drive the PROM CE
pin High to reduce standby power after configuration, an
external pull-up resistor should be used. Typically a 330Ω
pull-up resistor is used, but refer to the appropriate FPGA
data sheet for the recommended DONE pin pull-up value. If
the DONE circuit is connected to an LED to indicate FPGA
Figure 16: Platform Flash PROM Power-Up Requirements
TOER
VCCINT
VCCPOR
VCCPD
200 µs ramp 50 ms ramp
TOER TRST
TIME (ms)
A slow-ramping VCCINT supply may still
be below the minimum operating
voltage when OE/RESET is released.
In this case, the configuration
sequence must be delayed until both
VCCINT and VCCO have reached their
recommended operating conditions.
Recommended Operating Range
Delay or Restart
Configuration
ds123_21_103103
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.4) July 20, 2004 www.xilinx.com 23
Preliminary Product Specification 1-800-255-7778
R
configuration is complete, and is also connected to the
PROM CE pin to enable low-power standby mode, then an
external buffer should be used to drive the LED circuit to
ensure valid transitions on the PROM’s CE pin. If low-power
standby mode is not required for the PROM, then the CE pin
should be connected to ground.
DC Electrical Characteristics
•Absolute Maximum Ratings, page 24
•Supply Voltage Requirements for Power-On Reset and Power-Down, page 24
•Recommended Operating Conditions, page 25
•Quality and Reliability Characteristics, page 25
•DC Characteristics Over Operating Conditions, page 26
AC Electrical Characteristics
•AC Characteristics Over Operating Conditions, page 27
•AC Characteristics Over Operating Conditions When Cascading, page 30
Tabl e 9 : Truth Table for XCFxxS PROM Control Inputs
Control Inputs
Internal Address
Outputs
OE/RESET CE DATA CEO ICC
High Low If address < TC(2) : increment Active High Active
If address = TC(2) : don't change High-Z Low Reduced
Low Low Held reset High-Z High Active
X(1) High Held reset High-Z High Standby
Notes:
1. X = don’t care.
2. TC = Terminal Count = highest address value. TC + 1 = address 0.
Tabl e 1 0 : Truth Table for XCFxxP PROM Control Inputs
Control Inputs
Internal Address
Outputs
OE/RESET CE CF BUSY DATA CEO CLKOUT ICC
High Low High Low
If address < TC(2) and
address < EA(3) : increment Active High Active Active
If address < TC(2) and
address = EA(3) : don't change High-Z High High-Z Reduced
Else
If address = TC(2) : don't change High-Z Low High-Z Reduced
High Low High High Unchanged Active and
Unchanged High Active Active
High Low Low X(1) Held reset(4) Active High Active Active
Low Low X X Held reset(4) High-Z High High-Z Active
XHighXXHeld reset
(4) High-Z High High-Z Standby
Notes:
1. X = don’t care.
2. TC = Terminal Count = highest address value. TC + 1 = address 0.
3. For the XCFxxP with Design Revisioning enabled, EA = end address (last address in the selected design revision).
4. For the XCFxxP with Design Revisioning enabled, Held Reset = address reset to the beginning address of the selected bank. If Design Revisioning
is not enabled, then Held Reset = address reset to address 0.
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.4) July 20, 2004 www.xilinx.com 24
Preliminary Product Specification 1-800-255-7778
R
Absolute Maximum Ratings
Supply Voltage Requirements for Power-On Reset and Power-Down
Symbol Description
XCF01S, XCF02S,
XCF04S
XCF08P, XCF16P,
XCF32P Units
VCCINT Internal supply voltage relative to GND –0.5 to +4.0 –0.5 to +2.7 V
VCCO I/O supply voltage relative to GND –0.5 to +4.0 –0.5 to +4.0 V
VCCJ JTAG I/O supply voltage relative to GND –0.5 to +4.0 –0.5 to +4.0 V
VIN Input voltage with respect to GND VCCO < 2.5V –0.5 to +3.6 –0.5 to +3.6 V
VCCO ≥ 2.5V –0.5 to +5.5 –0.5 to +3.6 V
VTS Voltage applied to High-Z output VCCO < 2.5V –0.5 to +3.6 –0.5 to +3.6 V
VCCO ≥ 2.5V –0.5 to +5.5 –0.5 to +3.6 V
TSTG Storage temperature (ambient) –65 to +150 –65 to +150 °C
TJJunction temperature +125 +125 °C
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins can
undershoot to –2.0V or overshoot to +7.0V, provided this over- or undershoot lasts less then 10 ns and with the forcing current being limited to
200 mA.
2. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to
Absolute Maximum Ratings conditions for extended periods of time adversely affects device reliability.
3. For soldering guidelines, see the information on "Packaging and Thermal Characteristics" at www.xilinx.com.
Symbol Description
XCF01S, XCF02S,
XCF04S
XCF08P, XCF16P,
XCF32P
UnitsMin Max Min Max
TVCC VCCINT rise time from 0V to nominal voltage(2) 0.2500.250ms
VCCPOR POR threshold for the VCCINT supply 1 - TBD - V
TOER OE/RESET release delay following POR(3) 010TBDms
VCCPD Power-down threshold for VCCINT supply - 1 - TBD V
TRST
Time required to trigger a device reset when the VCCINT
supply drops below the maximum VCCPD threshold 10 - 10 - ms
Notes:
1. VCCINT
, VCCO, and VCCJ supplies may be applied in any order.
2. At power up, the device requires the VCCINT power supply to monotonically rise to the nominal operating voltage within the specified TVCC rise time.
If the power supply cannot meet this requirement, then the device might not perform power-on-reset properly. See Figure 16, page 22.
3. If the VCCINT and VCCO supplies do not reach their respective recommended operating conditions before the OE/RESET pin is released, then the
configuration data from the PROM will not be available at the recommended threshold levels. The configuration sequence must be delayed until both
VCCINT and VCCO have reached their recommended operating conditions.
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.4) July 20, 2004 www.xilinx.com 25
Preliminary Product Specification 1-800-255-7778
R
Recommended Operating Conditions
Quality and Reliability Characteristics
Symbol Description
XCF01S, XCF02S, XCF04S XCF08P, XCF16P, XCF32P
UnitsMin Typ Max Min Typ Max
VCCINT Internal voltage supply 3.0 3.3 3.6 1.65 1.8 2.0 V
VCCO/VCCJ
Supply
voltage for
output
drivers
3.3V Operation 3.0 3.3 3.6 3.0 3.3 3.6 V
2.5V Operation 2.3 2.5 2.7 2.3 2.5 2.7 V
1.8V Operation 1.7 1.8 2.0 1.7 1.8 2.0 V
1.5V Operation - - - TBD 1.5 TBD V
VIL
Low-level
input
voltage
3.3V Operation 0 - 0.8 0 - 0.8 V
2.5V Operation 0 - 0.8 0 - 0.8 V
1.8V Operation - - 20% VCCO - - 20% VCCO V
1.5V Operation - - - - - TBD V
VIH
High-level
input
voltage
3.3V Operation 2.0 - 5.5 2.0 - 3.6 V
2.5V Operation 1.7 - 5.5 1.7 - 3.6 V
1.8V Operation 70% VCCO -3.670% V
CCO -3.6V
1.5V Operation - - - TBD - 3.6 V
TIN Input signal transition time(1) - - 500 - - 500 ns
VOOutput voltage 0 - VCCO 0-V
CCO V
TAOperating ambient temperature –40 - 85 –40 - 85 °C
Notes:
1. Input signal transition time measured between 10% VCCO and 90% VCCO.
Symbol Description Min Max Units
TDR Data retention 20 - Years
NPE Program/erase cycles (Endurance) 20,000 - Cycles
VESD Electrostatic discharge (ESD) 2,000 - Volts
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.4) July 20, 2004 www.xilinx.com 26
Preliminary Product Specification 1-800-255-7778
R
DC Characteristics Over Operating Conditions
Symbol Description
XCF01S, XCF02S,
XCF04S
XCF08P, XCF16P,
XCF32P
Units
Test
Conditions Min Max
Test
Conditions Min Max
VOH
High-level output voltage for 3.3V outputs IOH = –4 mA 2.4 - IOH = TBD TBD - V
High-level output voltage for 2.5V outputs IOH = –500 µA VCCO
– 0.4 -IOH = TBD TBD - V
High-level output voltage for 1.8V outputs IOH = –50 µA VCCO
– 0.4 -IOH = TBD TBD - V
High-level output voltage for 1.5V outputs - - - IOH = TBD TBD - V
VOL
Low-level output voltage for 3.3V outputs IOL = 8 mA -0.4IOL = TBD -TBD V
Low-level output voltage for 2.5V outputs IOL = 500 µA -0.4IOL = TBD -TBD V
Low-level output voltage for 1.8V outputs IOL = 50 µA - 0.4 IOL = TBD - TBD V
Low-level output voltage for 1.5V outputs ---I
OL = TBD - TBD V
ICCINT Internal voltage supply current, active mode 33 MHz - 10 33 MHz - 10 mA
ICCO
Output driver supply current, active serial mode 33 MHz - 5 33 MHz - 5 mA
Output driver supply current, active parallel mode ---33MHz-20mA
ICCJ JTAG supply current, active mode Note (1) - 5 Note (1) - 5 mA
ICCINTS Internal voltage supply current, standby mode Note (2) - 1 Note (2) - 1 mA
ICCOS Output driver supply current, standby mode Note (2) - 1 Note (2) - 1 mA
ICCJS JTAG supply current, standby mode Note (2) - 1 Note (2) - 1 mA
IILJ JTAG pins TMS, TDI, and TDO pull-up current VCCJ = max
VIN = GND -100
VCCJ = max
VIN = GND -TBDµA
IIL Input leakage current
VCCINT = max
VIN = GND or
VCCINT
–10 10
VCCINT = max
VIN = GND or
VCCINT
TBD TBD µA
IIH Input and output High-Z leakage current
VCCINT = max
VIN = GND or
VCCINT
–10 10
VCCINT = max
VIN = GND or
VCCINT
TBD TBD µA
CIN Input capacitance VIN = GND
f = 1.0 MHz -8
VIN = GND
f = 1.0 MHz -TBDpF
COUT Output capacitance VIN = GND
f = 1.0 MHz -14
VIN = GND
f = 1.0 MHz -TBDpF
Notes:
1. TDI/TMS/TCK non-static (active).
2. CE High, OE Low, and TMS/TDI/TCK static.
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.4) July 20, 2004 www.xilinx.com 27
Preliminary Product Specification 1-800-255-7778
R
AC Characteristics Over Operating Conditions
Symbol Description
XCF01S, XCF02S,
XCF04S
XCF08P, XCF16P,
XCF32P
UnitsMin Max Min Max
TOE
OE/RESET to data delay(6) when VCCO = 3.3V or 2.5V -10TBDTBDns
OE/RESET to data delay(6) when VCCO = 1.8V -30TBDTBDns
TCE
CE to data delay(5) when VCCO = 3.3V or 2.5V -15TBDTBDns
CE to data delay(5) when VCCO = 1.8V -30TBDTBDns
TCAC
CLK to data delay when VCCO = 3.3V or 2.5V -15TBDTBDns
CLK to data delay when VCCO = 1.8V -30TBDTBDns
TOH
Data hold from CE, OE/RESET, or CLK
when VCCO = 3.3V or 2.5V 0-TBDTBDns
Data hold from CE, OE/RESET, or CLK
when VCCO = 1.8V 0-TBDTBDns
TDF
CE or OE/RESET to data float delay(2)
when VCCO = 3.3V or 2.5V -25TBDTBDns
CE or OE/RESET to data float delay(2)
when VCCO = 1.8V -30TBDTBDns
TCYC
Clock period(7) when VCCO = 3.3V or 2.5V 30 - TBD TBD ns
Clock period(7) when VCCO = 1.8V 67 - TBD TBD ns
TLC
CLK Low time(3) when VCCO = 3.3V or 2.5V 10 - TBD TBD ns
CLK Low time(3) when VCCO = 1.8V 15 - TBD TBD ns
CE
OE/RESET
CLK
CLKOUT
(optional)
BUSY
(optional)
DATA
TCE
TLC THC
TSCE
TOE TCAC
THCE
THOE
TCYC
TOH
TDF
TOH
THB
TSB
TOEC
TCEC
TCLKO
TCOH
TCDD
CF
EN_EXT_SEL
REV_SEL[1:0]
TSXT THXT
TSRV THRV
ds123_22_110403
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.4) July 20, 2004 www.xilinx.com 28
Preliminary Product Specification 1-800-255-7778
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THC
CLK High time(3) when VCCO = 3.3V or 2.5V 10 - TBD TBD ns
CLK High time(3) when VCCO = 1.8V 15 - TBD TBD ns
TSCE
CE setup time to CLK (guarantees proper counting)(3)
when VCCO = 3.3V or 2.5V 20 - TBD TBD ns
CE setup time to CLK (guarantees proper counting)(3)
when VCCO = 1.8V 30 TBD TBD ns
THCE
CE hold time (guarantees counters are reset)(5)
when VCCO = 3.3V or 2.5V 250 - TBD TBD ns
CE hold time (guarantees counters are reset)(5)
when VCCO = 1.8V 250 - TBD TBD ns
THOE
OE/RESET hold time (guarantees counters are reset)(6)
when VCCO = 3.3V or 2.5V 250 - TBD TBD ns
OE/RESET hold time (guarantees counters are reset)(6)
when VCCO = 1.8V 250 - TBD TBD ns
TSB
BUSY setup time to CLK when VCCO = 3.3V or 2.5V --TBDTBDns
BUSY setup time to CLK when VCCO = 1.8V --TBDTBDns
THB
BUSY hold time to CLK when VCCO = 3.3V or 2.5V --TBDTBDns
BUSY hold time to CLK when VCCO = 1.8V --TBDTBDns
TCLKO
CLK input to CLKOUT output delay
when VCCO = 3.3V or 2.5V --TBDTBDns
CLK input to CLKOUT output delay when VCCO = 1.8V --TBDTBDns
TCEC
CE to CLKOUT delay when VCCO = 3.3V or 2.5V --TBDTBDns
CE to CLKOUT delay when VCCO = 1.8V --TBDTBDns
TOEC
OE/RESET to CLKOUT delay
when VCCO = 3.3V or 2.5V --TBDTBDns
OE/RESET to CLKOUT delay when VCCO = 1.8V --TBDTBDns
TCDD
CLKOUT to data delay when VCCO = 3.3V or 2.5V --TBDTBDns
CLKOUT to data delay when VCCO = 1.8V --TBDTBDns
TCOH
Data hold from CLKOUT when VCCO = 3.3V or 2.5V --TBDTBDns
Data hold from CLKOUT when VCCO = 1.8V --TBDTBDns
TSXT
EN_EXT_SEL setup time to CF (rising edge)
when VCCO = 3.3V or 2.5V --TBDTBDns
EN_EXT_SEL setup time to CF (rising edge)
when VCCO = 1.8V --TBDTBDns
THXT
EN_EXT_SEL hold time from CF (rising edge)
when VCCO = 3.3V or 2.5V --TBDTBDns
EN_EXT_SEL hold time from CF (rising edge)
when VCCO = 1.8V --TBDTBDns
TSRV
REV_SEL setup time to CF (rising edge)
when VCCO = 3.3V or 2.5V --TBDTBDns
REV_SEL setup time to CF (rising edge)
when VCCO = 1.8V --TBDTBDns
Symbol Description
XCF01S, XCF02S,
XCF04S
XCF08P, XCF16P,
XCF32P
UnitsMin Max Min Max
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.4) July 20, 2004 www.xilinx.com 29
Preliminary Product Specification 1-800-255-7778
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THRV
REV_SEL hold time from CF (rising edge)
when VCCO = 3.3V or 2.5V --TBDTBDns
REV_SEL hold time from CF (rising edge)
when VCCO = 1.8V --TBDTBDns
TFF
CLKOUT default (fast) frequency --TBDTBDns
CLKOUT default (fast) frequency with compression --TBDTBDns
TSF
CLKOUT alternate (slower) frequency --TBDTBDns
CLKOUT alternate (slower) frequency with
compression --TBDTBDns
Notes:
1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
5. If THCE High < 2 µs, TCE = 2 µs.
6. If THOE Low < 2 µs, TOE = 2 µs.
7. Minimum possible TCYC. Actual TCYC = TCAC + FPGA data setup time. With VCCO = 3.3V, if FPGA data setup time = 15 ns,
actual TCYC = 15 ns + 15 ns = 30 ns.
Symbol Description
XCF01S, XCF02S,
XCF04S
XCF08P, XCF16P,
XCF32P
UnitsMin Max Min Max
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.4) July 20, 2004 www.xilinx.com 30
Preliminary Product Specification 1-800-255-7778
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AC Characteristics Over Operating Conditions When Cascading
Symbol Description
XCF01S, XCF02S,
XCF04S
XCF08P, XCF16P,
XCF32P
UnitsMin Max Min Max
TCDF
CLK to output float delay(2,3)
when VCCO = 2.5V or 3.3V -25TBDTBDns
CLK to output float delay(2,3) when VCCO = 1.8V -35TBDTBDns
TOCK
CLK to CEO delay(3,5) when VCCO = 2.5V or 3.3V -20TBDTBDns
CLK to CEO delay(3,5) when VCCO = 1.8V -35TBDTBDns
TOCE
CE to CEO delay(3) when VCCO = 2.5V or 3.3V -20TBDTBDns
CE to CEO delay(3) when VCCO = 1.8V -35TBDTBDns
TOOE
OE/RESET to CEO delay(3) when VCCO = 2.5V or 3.3V -20TBDTBDns
OE/RESET to CEO delay(3) when VCCO = 1.8V -35TBDTBDns
TCOCE
CLKOUT to CEO delay when VCCO = 2.5V or 3.3V --TBDTBDns
CLKOUT to CEO delay when VCCO = 1.8V --TBDTBDns
TCODF
CLKOUT to output float delay
when VCCO = 2.5V or 3.3V --TBDTBDns
CLKOUT to output float delay when VCCO = 1.8V --TBDTBDns
Notes:
1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
5. For cascaded PROMs:
-T
CYC min = TOCK + TCE + FPGA data setup time
-T
CAC min = TOCK + TCE
OE/RESET
CE
CLK
CLKOUT
(optional)
DATA
CEO
TOCE
TOOE
First BitLast Bit
TCDF
TCODF
TOCK
TCOCE
ds123_23_102203
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.4) July 20, 2004 www.xilinx.com 31
Preliminary Product Specification 1-800-255-7778
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Pinouts and Pin Descriptions
The XCFxxS Platform Flash PROM is available in the VO20 and VOG20 packages. The XCFxxP Platform Flash PROM is
available in the VO48, VOG48, FS48, and FSG48 packages. This section includes:
•Ta b le 1 1 , XCFxxS Pin Names and Descriptions, page 31
•Figure 17, VO20/VOG20 Pinout Diagram (Top View) with Pin Names, page 32
•Ta b le 1 2 , XCFxxP Pin Names and Descriptions, page 33
•Figure 18, VO48/VOG48 Pinout Diagram (Top View) with Pin Names, page 35
•Ta b le 1 3 , FS48/FSG48 Pin Number/Name Reference, page 36
•Figure 19, FS48/FSG48 Pinout Diagram (Top View), page 36
Notes:
1. VO20/VOG20 denotes a 20-pin (TSSOP) Plastic Thin Shrink Small Outline Package
2. VO48/VOG48 denotes a 48-pin (TSOP) Plastic Thin Small Outline Package.
3. FS48/FSG48 denotes a 48-pin (TFBGA) Plastic Thin Fine Pitch Ball Grid Array (0.8 mm pitch).
XCFxxS Pinouts and Pin Descriptions
Ta bl e 1 1 provides a list of the pin names and descriptions for the XCFxxS 20-pin VO20/VOG20 package.
Tabl e 1 1 : XCFxxS Pin Names and Descriptions
Pin Name
Boundary
Scan Order
Boundary
Scan Function Pin Description
20-pin TSSOP
(VO20/VOG20)
D0
4Data Out
D0 is the DATA output pin to provide data for configuring an
FPGA in serial mode. The D0 output is set to a
high-impedance state during ISPEN (when not clamped).
1
3 Output Enable
CLK 0Data In
Configuration Clock Input. Each rising edge on the CLK input
increments the internal address counter if the CLK input is
selected, CE is Low, and OE/RESET is High.
3
OE/RESET
20 Data In Output Enable/Reset (Open-Drain I/O). When Low, this input
holds the address counter reset and the DATA output is in a
high-impedance state. This is a bidirectional open-drain pin
that is held Low while the PROM is reset. Polarity is not
programmable.
819 Data Out
18 Output Enable
CE 15 Data In
Chip Enable Input. When CE is High, the device is put into
low-power standby mode, the address counter is reset, and
the DATA pins are put in a high-impedance state.
10
CF
22 Data Out Configuration Pulse (Open-Drain Output). Allows JTAG
CONFIG instruction to initiate FPGA configuration without
powering down FPGA. This is an open-drain output that is
pulsed Low by the JTAG CONFIG command.
7
21 Output Enable
CEO
12 Data Out Chip Enable Output. Chip Enable Output (CEO) is connected
to the CE input of the next PROM in the chain. This output is
Low when CE is Low and OE/RESET input is High, AND the
internal address counter has been incremented beyond its
Terminal Count (TC) value. CEO returns to High when
OE/RESET goes Low or CE goes High.
13
11 Output Enable
TMS Mode Select
JTAG Mode Select Input. The state of TMS on the rising edge
of TCK determines the state transitions at the Test Access
Port (TAP) controller. TMS has an internal 50KΩ resistive
pull-up to VCCJ to provide a logic "1" to the device if the pin is
not driven.
5
TCK Clock
JTAG Clock Input. This pin is the JTAG test clock. It
sequences the TAP controller and all the JTAG test and
programming electronics.
6
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.4) July 20, 2004 www.xilinx.com 32
Preliminary Product Specification 1-800-255-7778
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XCFxxS Pinout Diagram
TDI Data In
JTAG Serial Data Input. This pin is the serial input to all JTAG
instruction and data registers. TDI has an internal 50KΩ
resistive pull-up to VCCJ to provide a logic "1" to the device if
the pin is not driven.
4
TDO Data Out
JTAG Serial Data Output. This pin is the serial output for all
JTAG instruction and data registers. TDO has an internal
50KΩ resistive pull-up to VCCJ to provide a logic "1" to the
system if the pin is not driven.
17
VCCINT +3.3V Supply. Positive 3.3V supply voltage for internal logic. 18
VCCO
+3.3V, 2.5V, or 1.8V I/O Supply. Positive 3.3V, 2.5V, or 1.8V
supply voltage connected to the output voltage drivers and
input buffers.
19
VCCJ
+3.3V, 2.5V, or 1.8V JTAG I/O Supply. Positive 3.3V, 2.5V, or
1.8V supply voltage connected to the TDO output voltage
driver and TCK, TMS, and TDI input buffers.
20
GND Ground 11
DNC Do not connect. (These pins must be left unconnected.) 2, 9, 12, 14, 15, 16
Figure 17: VO20/VOG20 Pinout Diagram (Top View)
with Pin Names
Tabl e 1 1 : XCFxxS Pin Names and Descriptions (Continued)
Pin Name
Boundary
Scan Order
Boundary
Scan Function Pin Description
20-pin TSSOP
(VO20/VOG20)
VO20/VOG20
Top View
ds123_02_071304
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
D0
(DNC)
CLK
TDI
TMS
TCK
CF
OE/RESET
(DNC)
CE
VCCJ
VCCO
VCCINT
TDO
(DNC)
(DNC)
CEO
(DNC)
GND
(DNC)
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.4) July 20, 2004 www.xilinx.com 33
Preliminary Product Specification 1-800-255-7778
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XCFxxP Pinouts and Pin Descriptions
Ta bl e 1 2 provides a list of the pin names and descriptions for the XCFxxP 48-pin VO48/VOG48 and 48-pin FS48/FSG48
packages.
Tabl e 1 2 : XCFxxP Pin Names and Descriptions
Pin Name
Boundary
Scan
Order
Boundary
Scan
Function Pin Description
48-pin
TSOP
(VO48/
VOG48)
48-pin
TFBGA
(FS48/
FSG48)
D0
28 Data Out
D0 is the DATA output pin to provide data for configuring an
FPGA in serial mode.
D0-D7 are the DATA output pins to provide parallel data for
configuring a Xilinx FPGA in SelectMap (parallel) mode.
The D0 output is set to a high-impedance state during ISPEN
(when not clamped).
The D1-D7 outputs are set to a high-impedance state during
ISPEN (when not clamped) and when serial mode is selected
for configuration. The D1-D7 pins can be left unconnected
when the PROM is used in serial mode.
28 H6
27 Output Enable
D1
26 Data Out
29 H5
25 Output Enable
D2
24 Data Out
32 E5
23 Output Enable
D3
22 Data Out
33 D5
21 Output Enable
D4
20 Data Out
43 C5
19 Output Enable
D5
18 Data Out
44 B5
17 Output Enable
D6
16 Data Out
47 A5
15 Output Enable
D7
14 Data Out
48 A6
13 Output Enable
CLK 01 Data In
Configuration Clock Input. An internal programmable control
bit selects between the internal oscillator and the CLK input
pin as the clock source to control the configuration sequence.
Each rising edge on the CLK input increments the internal
address counter if the CLK input is selected, CE is Low,
OE/RESET is High, BUSY is Low (parallel mode only), and
CF is High.
12 B3
OE/RESET
04 Data In Output Enable/Reset (Open-Drain I/O).
When Low, this input holds the address counter reset and the
DATA and CLKOUT outputs are placed in a high-impedance
state. This is a bidirectional open-drain pin that is held Low
while the PROM is reset. Polarity is not programmable.
11 A303 Data Out
02 Output Enable
CE 00 Data In
Chip Enable Input. When CE is High, the device is put into
low-power standby mode, the address counter is reset, and
the DATA and CLKOUT outputs are placed in a
high-impedance state.
13 B4
CF
11 Data In Configuration Pulse (Open-Drain I/O). As an output, this pin
allows JTAG CONFIG instruction to initiate FPGA
configuration without powering down the FPGA. This is an
open-drain signal that is pulsed Low by the JTAG CONFIG
command. As an input, when Low, this signal resets the
internal address counter. The current design revision
selection is sampled on the rising edge of CF
.
6D110 Data Out
09 Output Enable
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.4) July 20, 2004 www.xilinx.com 34
Preliminary Product Specification 1-800-255-7778
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CEO
06 Data Out Chip Enable Output. Chip Enable Output (CEO) is connected
to the CE input of the next PROM in the chain. This output is
Low when CE is Low and OE/RESET input is High, AND the
internal address counter has been incremented beyond its
Terminal Count (TC) value. CEO returns to High when
OE/RESET goes Low or CE goes High.
10 D2
05 Output Enable
EN_EXT_SEL 31 Data In
Enable External Selection Input. When this pin is Low, design
revision selection is controlled by the Revision Select pins.
When this pin is High, design revision selection is controlled
by the internal programmable Revision Select control bits.
EN_EXT_SEL has an internal 50KΩ resistive pull-up to VCCO
to provide a logic "1" to the device if the pin is not driven.
25 H4
REV_SEL0 30 Data In Revision Select[1:0] Inputs. When the EN_EXT_SEL is Low,
the Revision Select pins are used to select the design
revision to be enabled, overriding the internal programmable
Revision Select control bits. The Revision Select[1:0] inputs
have an internal 50KΩ resistive pull-up to VCCO to provide a
logic "1" to the device if the pins are not driven.
26 G3
REV_SEL1 29 Data In 27 G4
BUSY 12 Data In
Busy Input. The BUSY input is enabled when parallel mode
is selected for configuration. When BUSY is High, the internal
address counter stops incrementing and the current data
remains on the data pins. On the first rising edge of CLK after
BUSY transitions from High to Low, the data for the next
address is driven on the data pins. When serial mode or
decompression is enabled during device programming, the
BUSY input is disabled. BUSY has an internal 50KΩ resistive
pull-down to GND to provide a logic "0" to the device if the pin
is not driven.
5C1
CLKOUT
08 Data Out
Configuration Clock Output. An internal Programmable
control bit enables the CLKOUT signal which is sourced from
either the internal oscillator or the CLK input pin. Each rising
edge on the selected clock source increments the internal
address counter if data is available, CE is Low, and
OE/RESET is High. Output data is available on the rising
edge of CLKOUT. CLKOUT remains Low when data is not
ready. When CLKOUT is not enabled , the CLKOUT pin is put
into a high-impedance state.
9C2
07 Output Enable
TMS Mode Select
JTAG Mode Select Input. The state of TMS on the rising edge
of TCK determines the state transitions at the Test Access
Port (TAP) controller. TMS has an internal 50KΩ resistive
pull-up to VCCJ to provide a logic "1" to the device if the pin is
not driven.
21 E2
TCK Clock
JTAG Clock Input. This pin is the JTAG test clock. It
sequences the TAP controller and all the JTAG test and
programming electronics.
20 H3
TDI Data In
JTAG Serial Data Input. This pin is the serial input to all JTAG
instruction and data registers. TDI has an internal 50KΩ
resistive pull-up to VCCJ to provide a logic "1" to the device if
the pin is not driven.
19 G1
TDO Data Out
JTAG Serial Data Output. This pin is the serial output for all
JTAG instruction and data registers. TDO has an internal
50KΩ resistive pull-up to VCCJ to provide a logic "1" to the
system if the pin is not driven.
22 E6
Tabl e 1 2 : XCFxxP Pin Names and Descriptions (Continued)
Pin Name
Boundary
Scan
Order
Boundary
Scan
Function Pin Description
48-pin
TSOP
(VO48/
VOG48)
48-pin
TFBGA
(FS48/
FSG48)
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.4) July 20, 2004 www.xilinx.com 35
Preliminary Product Specification 1-800-255-7778
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XCFxxP Pinout Diagrams
VCCINT +1.8V Supply. Positive 1.8V supply voltage for internal logic. 4, 15,
34
B1, E1,
G6
VCCO
+3.3V, 2.5V, or 1.8V I/O Supply. Positive 3.3V, 2.5V, or 1.8V
supply voltage connected to the output voltage drivers and
input buffers.
8, 30,
38, 45
B2, C6,
D6, G5
VCCJ
+3.3V, 2.5V, or 1.8V JTAG I/O Supply. Positive 3.3V, 2.5V, or
1.8V supply voltage connected to the TDO output voltage
driver and TCK, TMS, and TDI input buffers.
24 H2
GND Ground
2, 7,
17, 23,
31, 36,
46
A1, A2,
B6, F1,
F5, F6,
H1
DNC Do Not Connect. (These pins must be left unconnected.)
1, 3,
14, 16,
18, 35,
37, 39,
40, 41,
42
A4, C3,
C4, D3,
D4, E3,
E4, F2,
F3, F4,
G2
Tabl e 1 2 : XCFxxP Pin Names and Descriptions (Continued)
Pin Name
Boundary
Scan
Order
Boundary
Scan
Function Pin Description
48-pin
TSOP
(VO48/
VOG48)
48-pin
TFBGA
(FS48/
FSG48)
Figure 18: VO48/VOG48 Pinout Diagram (Top View)
with Pin Names
ds123_24_071304
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DNC
GND
DNC
VCCINT
BUSY
CF
GND
VCCO
CLKOUT
CEO
OE/RESET
CLK
CE
DNC
VCCINT
DNC
GND
DNC
TDI
TCK
TMS
TDO
GND
VCCJ
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
D7
D6
GND
VCCO
D5
D4
DNC
DNC
DNC
DNC
VCCO
DNC
GND
DNC
VCCINT
D3
D2
GND
VCCO
D1
D0
REV_SEL1
REV_SEL0
EN_EXT_SEL
VO48/VOG48
Top
View
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.4) July 20, 2004 www.xilinx.com 36
Preliminary Product Specification 1-800-255-7778
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Tabl e 1 3 : FS48/FSG48 Pin Number/Name Reference
Pin
Number Pin Name
Pin
Number Pin Name
A1 GND E1 VCCINT
A2 GND E2 TMS
A3 OE/RESET E3 DNC
A4 DNC E4 DNC
A5 D6 E5 D2
A6 D7 E6 TDO
B1 VCCINT F1 GND
B2 VCCO F2 DNC
B3 CLK F3 DNC
B4 CE F4 DNC
B5 D5 F5 GND
B6 GND F6 GND
C1 BUSY G1 TDI
C2 CLKOUT G2 DNC
C3 DNC G3 REV_SEL0
C4 DNC G4 REV_SEL1
C5 D4 G5 VCCO
C6 VCCO G6 VCCINT
D1 CF H1 GND
D2 CEO H2 VCCJ
D3 DNC H3 TCK
D4 DNC H4 EN_EXT_SEL
D5 D3 H5 D1
D6 VCCO H6 D0
Figure 19: FS48/FSG48 Pinout Diagram (Top View)
123456
ds121_01_071604
A
B
C
D
E
F
G
H
FS48/FSG48
Top View
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.4) July 20, 2004 www.xilinx.com 37
Preliminary Product Specification 1-800-255-7778
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Ordering Information
Valid Ordering Combinations
Marking Information
XCF01SVO20 C XCF08PVO48 C XCF08PFS48 C XCF01SVOG20 C XCF08PVOG48 C XCF08PFSG48 C
XCF02SVO20 C XCF16PVO48 C XCF16PFS48 C XCF02SVOG20 C XCF16PVOG48 C XCF16PFSG48 C
XCF04SVO20 C XCF32PVO48 C XCF32PFS48 C XCF04SVOG20 C XCF32PVOG48 C XCF32PFSG48 C
XCF04S VO20 C
Operating Range/Processing
C = (TA = –40°C to +85°C)
Package Type
VO20 = 20-pin TSSOP Package
VOG20 = 20-pin TSSOP Package, Pb-free
Device Number
XCF01S
XCF02S
XCF04S
XCF32P FS48 C
Operating Range/Processing
C = (TA = –40°C to +85°C)
Package Type
VO48 = 48-pin TSOP Package
VOG48 = 48-pin TSOP Package, Pb-free
FS48 = 48-pin TFBGA Package
FSG48 = 48-pin TFBGA Package, Pb-free
Device Number
XCF08P
XCF16P
XCF32P
XCF04S-V
Operating Range/Processing
C = (TA = –40°C to +85°C)
Package Type
V = 20-pin TSSOP Package (VO20)
VG = 20-pin TSSOP Package, Pb-free (VOG20)
VO48 = 48-pin TSOP Package (VO48)
VOG48 = 48-pin TSOP Package, Pb-free (VOG48)
F48 = 48-pin TFBGA Package (FS48)
FG48 = 48-pin TFBGA Package, Pb-free (FSG48)
Device Number
XCF01S
XCF02S
XCF04S
XCF08P
XCF16P
XCF32P
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.4) July 20, 2004 www.xilinx.com 38
Preliminary Product Specification 1-800-255-7778
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Revision History
The following table shows the revision history for this document.
Date Version Revision
04/29/03 1.0 Xilinx Initial Release.
06/03/03 1.1 Made edits to all pages.
11/05/03 2.0 Major revision.
11/18/03 2.1 Pinout corrections as follows:
•Ta b le 1 2 :
- For VO48 package, removed 38 from VCCINT and added it to VCCO.
- For FS48 package, removed pin D6 from VCCINT and added it to VCCO.
•Ta b le 1 3 (FS48 package):
- For pin D6, changed name from VCCINT to VCCO.
- For pin A4, changed name from GND to DNC.
•Figure 18 (VO48 package): For pin 38, changed name from VCCINT to VCCO.
12/15/03 2.2 • Added specification (4.7kΩ) for recommended pull-up resistor on OE/RESET pin to
section Reset and Power-On Reset Activation, page 22.
• Added paragraph to section Standby Mode, page 22, concerning use of a pull-up
resistor and/or buffer on the DONE pin.
05/07/04 2.3 • Section Features, page 1: Added package styles and 33 MHz configuration speed
limit to itemized features.
•Section Description, page 1 and following: Added state conditions for CF and
BUSY to the descriptive text.
•Table 2, page 3: Updated Virtex-II configuration bitstream sizes.
•Section Design Revisioning, page 9: Rewritten.
•Section PROM to FPGA Configuration Mode and Connections Summary,
page 10 and following, five instances: Added instruction to tie CF High if it is not tied
to the FPGA’s PROG_B (PROGRAM) input.
•Figure 8, page 14, through Figure 15, page 21: Added footnote indicating the
directionality of the CF pin in each configuration.
•Section I/O Input Voltage Tolerance and Power Sequencing, page 22: Rewritten.
•Table 10, page 23: Added CF column to truth table, and added an additional row to
document the Low state of CF
.
•Section Absolute Maximum Ratings, page 24: Revised VIN and VTS for ’P’
devices.
•Section Supply Voltage Requirements for Power-On Reset and Power-Down,
page 24:
- Revised footnote callout number on TOER from Footnote (4) to Footnote (3).
- Added Footnote (2) callout to TVCC.
•Section Recommended Operating Conditions, page 25:
- Added Typical (Typ) parameter columns and parameters for VCCINT and
VCCO/VCCJ.
- Added 1.5V operation parameter row to VIL and VIH, ’P’ devices.
-Revised V
IH Min, 2.5V operation, from 2.0V to 1.7V.
- Added parameter row TIN and Max parameters
• (Continued on next page)
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.4) July 20, 2004 www.xilinx.com 39
Preliminary Product Specification 1-800-255-7778
R
05/07/04
(cont’d)
2.3
(cont’d)
•Section DC Characteristics Over Operating Conditions, page 26:
- Added parameter row and parameters for parallel configuration mode, ’P’
devices, to ICCO.
- Added Footnote (1) and Footnote (2) with callouts in the Test Conditions column
for ICCJ, ICCINTS, ICCOS, and ICCJS, to define active and standby mode
requirements.
•Section AC Characteristics Over Operating Conditions, page 27:
- Corrected description for second TCAC parameter line to show parameters for
1.8V VCCO.
- Revised Footnote (7) to indicate VCCO = 3.3V.
- Applied Footnote (7) to second TCYC parameter line.
•Section AC Characteristics Over Operating Conditions When Cascading,
page 30: Revised Footnote (5)TCYC Min and TCAC Min formulas.
•Table 12, page 33:
- Added additional state conditions to CLK description.
- Added function of resetting the internal address counter to CF description.
07/20/04 2.4 • Added Pb-free package options VOG20, FSG48, and VOG48.
•Figure 8, page 14, and Figure 9, page 15: Corrected connection name for FPGA
DOUT (OPTIONAL Daisy-chained Slave FPGAs with different configurations) from
DOUT to DIN.
•Section Absolute Maximum Ratings, page 24: Removed parameter TSOL from
table. (TSOL information can be found in Package User Guide.)
•Table 2, page 3: Removed reference to XC2VP125 FPGA.
Design Enhancement for the
Platform Flash Family of PROMs
Manufactured at STMicroelectronics
PCN2004-18 (v1.0) August 9, 2004 Product/Process Change Notice
Overview
This notification describes a design enhancement to the commercial members of the Platform FlashTM family of
In-System Programmable Configuration PROMs manufactured at STMicroelectronics in Catania, Italy.
Description
This design enhancement addresses the intermittent sync word issue detailed in Customer Advisory CA2003-07
and the errata items detailed in DS123-E02. (NOTE: To view errata, you must be a registered user with the
Xilinx MySupport web site.)
The new STMicroelectronics offerings are form, fit, and function compatible with the current product.
Products Affected
This notification only applies to the following part numbers manufactured at STMicroelectronics. Reference the
Traceability section for further information on identifying these products.
XCF01SVO20C XCF02SVO20C XCF04SVO20C
XCF01SVOG20C XCF02SVOG20C XCF04SVOG20C
Table 1: Products Affected
Key Dates
Xilinx will begin shipping production devices manufactured at STMicroelectronics with this design
enhancement starting November 9, 2004. After this date, customers ordering the standard part number may
receive product manufactured with or without the design enhancement.
Qualification samples for product manufactured at STMicroelectronics with the design enhancement are now
available. Use the sample ordering code ES when placing orders for these sample units. To use sample ordering
code ES, append "ES" to the end of the standard ordering part number (e.g., XCF04SVO20CES). The sample
ordering code ES will be marked on the package topmark.
Customers who would like to receive only the enhanced product manufactured at STMicroelectronics beyond
the onset of device cross-shipment (November 9, 2004) should use special ordering code SCD0936. To use
SCD0936, append "0936" to the end of the standard ordering part number (e.g., XCF04SVO20C0936). The
ordering code 0936 will not be marked on the package topmark. Only product manufactured at
STMicroelectronics with this design enhancement will be us ed to fulfill SCD0936 orders .
Customers who need devices without the design enhancement beyond the onset of device cross-shipment
(November 9, 2004) may do so on a short-term basis only by using special ordering code SCD0901. To use
SCD0901, append “0901” to the end of the standard part ordering number (e.g., XCF04SVO20C0901). Only
product manufactured without the design enhancement will be used to fulfill SCD0901 orders. SCD0901 is
currently available for use and will be discontinued after March 1, 2005. The ordering code 0901 will not be
marked on the package topmark.
© 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
PCN2004-18 (v1.0) August 9, 2004 www.xilinx.com 1 of 3
Traceability
The devices manufactured at STMicroelectronics with the design enhancement can be distinguished both
visually and electrically.
Visually: The devices can be distinguished visually by the STMicroelectronics traceability code located on
line 2 of the package topmark. Line 2 will be changed from a 4-digit alphanumeric code to a 5-digit
alphanumeric code. Also, a 3-digit code will be added to line 3 for additional traceability information. See the
example below.
Sample Topmark for 20-Pin TSSOP Package
XCF04S ™ V
B352
XCF04S
™
V
HP421
AAB
Figure 1: Without Design Enhancement Figure 2: With Design Enhancement
Sample Topmark for 20-Pin TSSOP Package (Pb-Free)
XCF04S ™ VG
B352
XCF04S
™
VG
HP421
AAB
Figure 3: Without Design Enhancement Figure 4: With Design Enhancement
Electrically: The devices can be distinguished electrically by the IDCODE:
Device STMicroelectronics
IDCODE without
Design Enhancement
STMicroelectronics
IDCODE with Design
Enhancement
XCF01S 05044093h F5044093h
XCF02S 05045093h F5045093h
XCF04S 05046093h F5046093h
Table 2: IDCODEs
The current version of the programming algorithm ignores this revision field (1st character in bold above), so
customers need not update their programming algorithms.
© 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
PCN2004-18 (v1.0) August 9, 2004 www.xilinx.com 2 of 3
© 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
PCN2004-18 (v1.0) August 9, 2004 www.xilinx.com 3 of 3
Qualification Data
Part Test Sample Hours/Cycles Fails Status
XCF04S HTOL @140°C 77 1000 0 Pass
XCF04S Temp Cycle, Condition C
-65°C to 150°C 76 1000 0 Pass
XCF04S HTS, 150°C 77 1000 0 Pass
XCF04S Temperature/Humidity
Bias Test - Hast 130°C/85%RH 77 96 0 Pass
XCF04S ESD - HBM JESD22-A-114 12 2000 volts 0 Pass
XCF04S Latchup – EIA/JESD78 6 200 mA 0 Pass
Table 3: Reliability Qualification Data
Recommendation
No response is required to this PCN. Contact your Xilinx Sales Representative for assistance in obtaining
sample or production devices. For additional information or questions, contact Xilinx Technical Support .
Important Notice: Xilinx Customer Notifications (PCN, PDN, and Quality Alerts) can be delivered via e-mail
alerts sent by the MySupport website (http://www.xilinx.com/support). Register today and personalize your
"MyAlerts" to include Customer Notifications. This change provides many benefits, including the ability to
receive alerts for new and updated information about specific products, as well as alerts for other publications,
such as data sheets, errata, application notes, and so forth. For instructions on how to sign up, refer to Xilinx
Answer Record 18683.
Revision History
The following table shows the revision history for this document.
Date Version Revision
8/9/04 1.0 Initial Xilinx release.
