19-1388; Rev 0; 11/98 General Description The MAX157/MAX159 low-power, 10-bit analog-to-digi- tal converters (ADCs) are available in 8-pin pMAX and DIP packages. Both devices operate with a single +2.7V to +5.25V supply and feature a 7.4us succes- sive-approximation ADC, automatic power-down, fast wake-up (2.5us), an on-chip clock, and a high-speed, 3-wire serial interface. Power consumption is only 3.2mW (Vop = +3.6V) at the maximum sampling rate of 108ksps. At slower through- put rates, the 0.2uA automatic shutdown further reduces power consumption. The MAX157 provides 2-channel, single-ended opera- tion and accepts input signals from 0 to VREF. The MAX159 accepts pseudo-differential inputs ranging from O to Vref. An external clock accesses data through the 3-wire serial interface, which is SPI, QSPI, and MICROWIRE compatible. Excellent dynamic performance and low power, com- bined with ease of use and a small package size, make these converters ideal for battery-powered and data acquisition applications, or for other circuits with demanding power-consumption and space require- ments. For pin-compatible 12-bit upgrades, see the MAX1 44/MAX1 45 data sheet. Applications Instrumentation Test Equipment Medical Instruments System Supervision Battery-Powered Systems Portable Data Logging Isolated Data Acquisition Process-Control Monitoring Pin Configuration TOP VIEW wr Voo [1 | 8 | SCLK CHO (CH4) [2 | mam 7] pour MAX159 6 | CSYSHDN 5 | REF cHt (cH-) [3] eno [4 | WMAX/DIP MA AXILM +2./V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin uMAX Features @ Single-Supply Operation (+2.7V to +5.25V) # Two Single-Ended Channels (MAX157) Single Pseudo-Differential Channel (MAX159) Low Power 0.9mA (at 108ksps, +3V) 100p/A (at 10ksps, +3V) 10pA (at 1ksps, +3V) <0.2UA (power-down mode) Internal Track/Hold # 108ksps Sampling Rate @ SPI/QSPI/MICROWIRE-Compatible 3-Wire Serial Interface # Space-Saving 8-Pin pMAX Package @ Pin-Compatible 12-Bit Upgrades Available Ordering Information () ABE FOR MAX159 ONLY. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. MAXIMA TEMP. PIN- INL PART RANGE PACKAGE (LSB) MAX157ACUA 0C to+70C 8 pMAX +0.5 MAX157BCUA 0C to +70C 8 pMAX +1 MAXI57ACGPA0Cto+70C @Plastic DIP. 40.5 MAX157BCPA 0Cto+70C Plastic DIP +1 MAXI57AEUA -40C to +85C 8 pMAX +0.5 MAX157BEUA -40C to+85C 8 pMAX +1 MAXi57AEPA -40C to+85C @Plastic DIP. 40.5 MAX157BEPA -40Cto+85C Plastic DIP +1 MAX157AMJA -55C to+125C 8CERDIP* +0.5 MAX157BMJA -55C to+125C 8CERDIP* +1 MAX159ACUA 0C to+70C 8 MAX +0.5 MAX159BCUA 0C to+70C 8 MAX +1 MAXiS9ACPA 0Cto+70C @Plastic DIP. 40.5 MAXi59BCPA 0Cto+70C Plastic DIP +1 MAXI59AEUA -40C 0 +85C 8 pMAX +0.5 MAXI59BEUA -40C to +85C 8 pMAX +1 MAXIS59AEPA -40C to+85C 8Plastic DIP. 40.5 MAXiS59BEPA -40C to+85C @Plastic DIP +1 MAXI59AMJA -55C to+125C 8CERDIP* +0.5 MAXI59BMJA -55C to+125C 8CERDIP* +1 *Contact factory for availability. Maxim Integrated Products 1 For free samples & the latest literature: http:/1vwww.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. 6SLXVW/ZSLXVWMAX157/MAX159 +2./V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin uUMAX ABSOLUTE MAXIMUM RATINGS VDD to GND. occ eee neeennneeeeeneneneeanee -0.3V to +6V Operating Temperature Ranges CHO, CH1 (CH+, CH-) to GND... -0.3V to (VoD + 0.3V) MAX157/MAX159_C_A occ cece een nena 0C to +70C REF to GND... eee erence eenneeneee -0.3V to (VoD + 0.3V) MAX157/MAX159_ EA wees ee eee eee -40C to +85C Digital Inputs to GND.... -0.3V to +6V MAX157/MAX159_ MJA wa 55C to +125C DOUT to GND... tenner eenneeneee -0.3V to (VoD + 0.3V) Storage Temperature Range... cece scree -60C to +150C DOUT Sink CUITeNt occ cease eeeneeneeneneee ene 25mA Lead Temperature (soldering, 10S@C) occ see eens +300C Continuous Power Dissipation (Ta = +70C) MAX (derate 4.1MW/C above +70C) oo. eeees 330mW Plastic DIP (derate 9.09mW/C above +70C) ....... 727mW CERDIP (derate 8.00mW/C above +70C) ee 640mW Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Vpp = +2.7V to +5.25V, VREF = 2.5V, 0.1pF capacitor at REF, fsck = 2.17MHz, 16 clocks/conversion cycle (108ksps), CH- = GND for MAX159, Ta = TIN to TMAX, Unless otherwise noted. Typical values are at TA = +25C.) PARAMETER | SYMBOL | CONDITIONS | MIN TYP MAX | UNITS DC ACCURACY (Note 1) Resolution RES 10 Bits ; MAX15 A +0.5 Relative Accuracy (Note 2) INL LSB MAX15 B +1 Differential Nonlinearity DNL No missing codes over temperature +0.5 LSB Offset Error +2 LSB Gain Error (Note 3) +2 LSB Gain Temperature Coefficient External reference, VREF = 2.5V +0.8 ppm/C Channel-to-Channel Offset +0.02 LSB Matching Channel-to-Channel Gain Matching DYNAMIC SPECIFICATIONS (f/x (sine wave) = 10kKHz, Vin = 2.5Vp-p, 108ksps, external fscLk = 2.17MHz, CH- = GND for MAX159) +0.02 LSB Signal-to-Noise Ratio plus Distortion SINAD 66 dB (including Sthorder harmonic) | THO 70 0B Spurious-Free Dynamic Range SFDR 70 dB Channel-to-Channel Crosstalk fIN = 65kHZz, VIN = 2.5Vp-p (Note 4) -75 dB Small-Signal Bandwidth -3dB rolloff 2.25 MHz Full-Power Bandwidth 1.0 MHz 2 MA AXIAA+2./V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin uMAX ELECTRICAL CHARACTERISTICS (continued) (Vpp = +2.7V to +5.25V, VREF = 2.5V, 0.1pF capacitor at REF, fsck = 2.17MHz, 16 clocks/conversion cycle (108ksps), CH- = GND for MAX159, Ta = TIN to TMAX, Unless otherwise noted. Typical values are at TA = +25C.) PARAMETER | SYMBOL | CONDITIONS | MIN TYP MAX | UNITS CONVERSION RATE External clock, fSCLK = 2.17MHz, 16 clock 74 Conversion Time (Note 5) tCONV cycles per conversion ps Internal clock 5 7 T/H Acquisition Time tacQ 2.5 ps Aperture Delay 25 ns Aperture Jitter <50 ps External clock mode 0.1 2.17 Serial Clock Frequency fSCLK MHz Internal clock mode, for data transfer only 0 5 ANALOG INPUTS Notes neat Voltage Range VIN 0 VREF Vv Multiplexer Leakage Current On/off-leakage current, Vin = 0 to Vpp +0.01 +1 HA Input Capacitance CIN 16 HA EXTERNAL REFERENCE Input Voltage Range (Note 7) VREF 0 Vpp + 50mV Vv Input Current VREF = 2.5V 100 140 HA Input Resistance 18 25 kQ Shutdown REF Input Current 0.01 10 HA DIGITAL INPUTS (CS/SHDN, SCLK) AND DIGITAL OUTPUT (DOUT) Input High Voltage ViH Vo < 3.6V 20 V Vpbp > 3.6V 3.0 Input Low Voltage VIL 0.8 Vv Input Hysteresis Vuys 0.2 Vv Input Leakage Current lIN Vin = 0 or Vpp +1 HA Input Capacitance CIN (Note 8) 15 pF ISINK = mA 0.4 Output Low Voltage VoL Vv ISINK = 16mA 0.5 Output High Voltage VOH ISOURCE = 0.5mA Vpp - 0.5 Vv arree Slate Output Leakage CS/SHDN = Vpp +10 yA Three-State Output Capacitance] Cout | CS/SHDN = Vpp (Note 8) 15 pF MAAXIAA 3 6SLXVW/ZSLXVWMAX157/MAX159 +2./V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin uUMAX ELECTRICAL CHARACTERISTICS (continued) (Vpp = +2.7V to +5.25V, VREF = 2.5V, 0.1pF capacitor at REF, fsck = 2.17MHz, 16 clocks/conversion cycle (108ksps), CH- = GND for MAX159, Ta = TIN to TMAX, Unless otherwise noted. Typical values are at TA = +25C.) PARAMETER | SYMBOL | CONDITIONS | MIN TYP MAX | UNITS POWER REQUIREMENTS Positive Supply Voltage Vppb +2.7 +5.25 Vv Positive Supply Current IDD Operating mode 0.9 2.0 mA Positive Supply Current IDD Shutdown, CS/SHDN = GND 0.2 5 pA (Notes) Rejection PSR | Vpp = 2.7V to 5.25V, full-scale input +0.15 mV TIMING CHARACTERISTICS (Figure 7) (Vpp = +2.7V to +5.25V, VREF = 2.5V, 0.1pF capacitor at REF, fsck = 2.17MHz, 16 clocks/conversion cycle (108ksps), CH- = GND for MAX159, Ta = TIN to TMAX, Unless otherwise noted. Typical values are at Ta = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX | UNITS Wake-Up Time tWAKE 2.5 ps CS/SHDN Fall to Output Enable tov CL = 100pF (Figure 1) 120 ns CS/SHDN Rise to Output _ . Disable tTR C_= 100pF (Figure 1) 120 ns SCLK Fall to Output Data Valid tbo CL = 100pF 20 120 ns External clock 0.1 2.17 SCLK Clock Frequency fScLk MHz Internal clock, SCLK for data transfer only 0 5 External clock 215 SCLK Pulse Width High tCH Internal clock, SCLK for data transfer only 50 ns (Note 8) External clock 215 SCLK Pulse Width Low tCL Internal clock, SCLK for data transfer only 50 ns (Note 8) SCLK to CS/SHDN Setup tScLKS 60 ns CS/SHDN Pulse Width tcs 60 ns Note 1: Tested at Vpp = +2.7V. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after full-scale range has been calibrated. Note 3: Offset nulled. Note 4: The on channel is grounded; the sine wave is applied to off channel (MAX157 only). Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle. Note 6: The common-mode range for the analog inputs is from GND to Vpp (MAX159 only). Note 7: ADC performance is limited by the converters noise floor, typically 300pVp-p. Note 8: Guaranteed by design. Not subject to production testing. Note 9: Measured as Vrs(2.7V) - Ves(5.25V). MAXUM108ksps, Serial 10-Bit ADCs In 8-Pin pUMAX Typical Operating Characteristics +2./V, Low-Power, 2-Channel, (VDD = +3.0V, VREF = 2.5V, 0.1pF capacitor at REF, fscLk = 2.17MHz, 16 clocks/conversion cycle (108ksps); CH- = GND for MAX159; Ta = +25C, unless otherwise noted.) 1500 1300 1100 SUPPLY CURRENT (1A) co 8 ~ 3S S wn oS S SUPPLY CURRENT vs. SUPPLY VOLTAGE Ss UPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT vs. SAMPLING RATE T 5 1500 TT g 10,000 Vper = Vop 8 Vper = Vp g i 5 = 5 FC. =50pF ys _ | CL =50pF s 1000 E CODE = 1010101000 Ll 1250 FT cope=1010101000 = lL = LE "1 f fg 100 | 3 1000 s a a > a & ze 10 2 w 750 1 500 04 25 30 35 40 45 50 55 -60 -40 -20 0 20 40 60 80 100 120 140 O11) 10100 tk~S10K~100k Vpp (V) TEMPERATURE (C) SAMPLING RATE (sps) SHUTDOWN CURRENT SHUTDOWN CURRENT vs. SUPPLY VOLTAGE vs. TEMPERATURE 1000 4 1000 2 Vper = Vop 5 VpeF = Vop 2 z w ~ 80 g Ee Ee f 600 2 eo 2 2 g LY g =z 5 va 5 / 400 > 400 aa aa w 2 A 200 20 = ee J Le 0 0 25 30 35 40 45 50 55 -60 -40 -20 0 20 40 60 80 100 120 140 Vpp (V) TEMPERATURE (C) OFFSET ERROR vs. SUPPLY VOLTAGE OFFSET ERROR vs. TEMPERATURE 0.20 2 0.20 5 5 _ 0.45 = = o's = ca oc | Boo |p ee 5 0.10 fi 0.10 L F 4 r a 5 5 S 0.05 0.05 0 0 25 30 35 40 45 50 55 60 -35 -10 15 40 65 9 115 140 TEMPERATURE (C) MA AXIAMA Vpp (V) 6SLXVW/ZSLXVWMAX157/MAX159 +2./V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin uUMAX Typical Operating Characteristics (continued) (VDD = +3.0V, VREF = 2.5V, 0.1pF capacitor at REF, fscLk = 2.17MHz, 16 clocks/conversion cycle (108ksps); CH- = GND for MAX159; Ta = +25C, unless otherwise noted.) GAIN ERROR GAIN ERROR INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE vs. TEMPERATURE vs. OUTPUT CODE 0.2 8 0.2 @ 0.03 s Z Z 0.02 & 0.1 = 04 3 8 0.01 5 B E 0 & 0 2 Zz z = 3 3 -0.01 04 0.1 -0.02 -0.2 -0.2 -0.03 25 30 35 40 45 50 55 60 -35 -10 15 40 65 90 115 140 0 250 500 750 4000 Vpp (V) TEMPERATURE (C) OUTPUT CODE INTEGRAL NONLINEARITY INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE vs. TEMPERATURE 0.20 = 0.20 % 0.15 = 0.15 = B B = 010 = 0.10 Zz = el _, 0.05 0.05 0 0 25 30 35 40 45 50 55 -60 -35 -10 15 40 65 90 115 140 Vpp (V) TEMPERATURE (C) 6 MAXUM108ksps, Serial 10-Bit ADCs In 8-Pin pUMAX +2./V, Low-Power, 2-Channel, Pin Description PIN NAME FUNCTION 1 Vpb Positive Supply Voltage, +2.7V to +5.25V 2 CHO (CH+) Analog Input, MAX157: Single-Ended (CHO); MAX159: Differential (CH+). 3 CH1 (CH-) Analog Input, MAX157: Single-Ended (CH1); MAX159: Differential (CH-). 4 GND Analog and Digital Ground 5 REE external Reference Voltage Input. Sets analog voltage range. Bypass with a 100nF capacitor close to the part. 6 CS/SHDN Active-Low Chip-Select Input, Active-High Shutdown Input. Pulling CS/SHDN high puts chip into shutdown with a maximum current of 5pA. 7 DOUT Serial Data Output. Data changes state at SCLKs falling edge. High impedance when CS/SHDN is high. 8 SCLK Serial Clock Input. DOUT changes on the falling edge of SCLK. Vpp DOUT 6k DOUT 6k CL CL = GND = = GND a) HIGH-ZTO Von, VoL TO Von, AND Voy TO HIGH-Z b) HIGH-Z TO VoL, You TO VoL, AND VoL TO HIGH-Z Figure 1. Load Circuits for Enable and Disable Time Detailed Description The MAX157/MAX159 analog-to-digital converters (ADCs) use a successive-approximation conversion (SAR) technique and on-chip track/hold (T/H) structure to convert an analog signal to a serial, 10-bit digital out- put data stream. This flexible serial interface provides easy interface to microprocessors (uPs). Figure 2 shows a simplified functional diagram of the internal architecture for both the MAX157 (2 channels, single-ended) and the MAX159 (1 channel, pseudo-differential). Single-Ended (MAX157) and Pseudo- Differential (MAX159) Analog Inputs The sampling architecture of the ADCs analog com- parator is illustrated in the equivalent input circuit in Figure 3. In single-ended mode (MAX157), both chan- nels CHO and CH1 are referred to GND and can be connected to two different signal sources. Following the power-on reset, the ADC is set to convert CHO. After CHO has been converted, CH1 will be converted, and the conversions will continue to alternate between channels. Channel switching is performed by toggling the CS/SHDN pin. Conversions can be performed on MA AXLMA the same channel by toggling CS/SHDN twice between conversions. If only one channel is required, CHO and CH1 may be connected together; however the output data will still contain the channel identification bit (before the MSB). For the MAX159, the input channels form a single differ- ential channel pair (CH+, CH-). This configuration is pseudo-differential to the effect that only the signal at IN+ is sampled. The return side IN- must remain stable within +0.5LSB (+0.1LSB for optimum results) with respect to GND during a conversion. To accomplish this, connect a 0.1pF capacitor from IN- to GND. During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor CHoLp. The acquisition interval spans from when CS/SHDN falls to the falling edge of the second clock cycle (external clock mode) or from when CS/SHDN falls to the first falling edge of SCLK (internal clock mode). At the end of the acquisition interval, the T/H switch opens, retain- ing charge on CHoOLD as a sample of the signal at IN+. The conversion interval begins with the input multiplex- er switching CHOLD from the positive input (IN+) to the negative input (IN-). This unbalances node ZERO at the comparators positive input. 6SLXVW/ZSLXVWMAX157/MAX159 +2./V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin uUMAX The capacitive digital-to-analog converter (DAC) adjusts during the remainder of the conversion cycle to restore node ZERO to OV within the limits of 10-bit resolution. This action is equivalent to transferring a 16pF - [(VIN+) - (VIN-)] charge from CHoLp to the bina- ry-weighted capacitive DAC, which in turn forms a digi- tal representation of the analog input signal. Track/Hold The ADCs T/H stage enters its tracking mode on the falling edge of CS/SHDN. For the MAX157 (single- ended inputs), IN- is connected to GND and the con- verter samples the positive (+) input. For the MAX159 (pseudo-differential inputs), IN- connects to the nega- tive input (-"), and the difference of [(VIN+) - (VIN-)] is sampled. At the end of the conversion, the positive input connects back to IN+ and CHoLp charges to the input signal. The time required for the T/H stage to acquire an input signal is a function of how fast its input capacitance is charged. If the input signals source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. The acquisition time, taca, is the maximum time the device takes to acquire the signal, and is also the minimum time required for the signal to be acquired. Calculate this with the follow- ing equation: taca = 7(Rs + RIN)CIN where Rg is the source impedance of the input signal, RIN (9kQ) is the input resistance, and Cjn (16pF) is the input capacitance of the ADC. Source impedances below 4kQ have no significant impact on the AC perfor- mance of the MAX157/MAX159. Higher source impedances can be used if a 0.01pF capacitor is connected to the individual analog inputs. Together with the input impedance, this capacitor forms an RC filter, limiting the ADCs signal bandwidth. Input Bandwidth The MAX157/MAX159 T/H stage offers both a 2.25MHz small-signal and a 1MHz full-power bandwidth, which makes it possible to use the parts for digitizing high- speed transients and measuring periodic signals with bandwidths exceeding the ADCs sampling rate by using undersampling techniques. To avoid high-fre- quency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. Most aliasing problems can be fixed easily with an external resistor and a capacitor. However, if DC precision is required, it is usually best to choose a continuous or switched-capacitor filter, such as the MAX7410/ MAX7414 (Figure 4). Their Butterworth characteristic generally provides the best compromise (with regard to rolloff and attenuation) in filter configurations, is easy to design, and provides a maximally flat passband re- sponse. Analog Input Protection Internal protection diodes, which clamp the analog input to Vpp and GND, allow each input channel to swing within GND - 300mV to Vpp + 300mV without damage. However, for accurate conversions both inputs must not exceed Vpp + 50mV or be less than GND - 50mvV. If an off-channel analog input voltage exceeds the supplies, limit the input current to 4mA. CB/SHON ; SCLK . INTERNAL CLOCK VY DOUT CONTROL OUTPUT Loaic rd Reisen | CHO (CHs) SCLK T) MER Ffiepoln "Sor Marae IN SAR OUT Ct MUX out MAX157 (CH) | (2 CHANNEL) MAX159 per } ( ) ARE FORMAX159 CAPACITIVE DAC REF ---- INPUT COMPARATOR MUX CH o9 = | CH- (CH) CHoLD CHO 16pF TOSAR (CH+) CowitcH HOLD CONTROL GND LOGIC SINGLE-ENDED MODE: CHO, CH1 = IN+; GND = IN- DIFFERENTIAL MODE: CH+ = IN+; CH- = IN- ( ) ARE FOR MAX159 Figure 2. MAX157/MAX159 Simplified Functional Diagram Figure 3. Analog Input Channel Structure MAXUM+2./V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin uMAX Selecting Clock Mode To start the conversion process on the MAX157/ MAX159, pull CS/SHDN low. At CS/SHDNs falling edge, the part wakes up, the internal T/H enters track mode, and a conversion begins. In addition, the state of SCLK at CS/SHDNs falling edge selects internal (SCLK = high) or external (SCLK = low) clock mode. Internal Clock (fscLk < 100kHz or fscLk > 2.17MHz) In internal clock mode, the MAX157/MAX159 run from an internal, laser-trimmed oscillator to within 20% of the 2MHz specified clock rate. This releases the system microprocessor from running the SAR conversion clock and allows the conversion results to be read back at the processors convenience, at any clock rate from 0 to 5MHz. Operating the MAX157/MAX159 in internal clock mode is necessary for serial interfaces operating with clock frequencies lower than 100kHz or greater than 2.17MHz. Select internal clock mode (Figure 5) by hold- ing SCLK high during a high/low transition of CS/SHDN. The first SCLK falling edge samples the data and initi- ates a conversion using the integrated on-chip oscilla- tor. After the conversion, the oscillator shuts off and DOUT goes high, signaling the end of conversion (EOC). Data can then be read out with SCLK. External Clock (fscLK = 100kHz to 2.17MHz) External clock mode (Figure 6) is selected by transition- ing CS/SHDN from high to low while SCLK is low. The external clock signal not only shifts data out, but also drives the analog-to-digital conversion. The input is sampled and conversion begins on the falling edge of the second clock pulse. Conversion must be completed within 140ys to prevent degradation in the conversion results caused by droop on the T/H capacitors. External clock mode provides the best throughput for clock fre- quencies between 100kHz and 2.17MHz. Vbp Vp aN Vpp 5 EXTERNAL SHON CHO REF et PeFEENCE MAXLAA MAXUM MAX7410 OUT MAX157 21 MAX7414 yy 18 CHt rel fooRNER = 15kHz 8 x 6 we] SCLK CSYSHDN | uP/pC COM Os GND GND 1 6 3 |4 0.01 pF = 1.5MHz = a CLOCK Figure 4. Analog Input with Anti-Aliasing Filter Structure ACTIVE POWER ACTIVE DOWN +t t WA | otc _ cs pat (taco) a > CS/SHDN 3) 14) 75] ey [7] 18] yO] fio) ptt] pre] M3) ft4) [toy 16 SCLK 1] [2 SAMPLING INSTANT DOUT 7 HIGHZ FOC 1 1 \CHIDYWSEX De X D7 Xs Ds Xba KOs Ke KOrKooXs Yeo AS Figure 5. Internal Clock Mode Timing MA AXIAMA 6SLXVW/ZSLXVWMAX157/MAX159 +2./V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin uUMAX Output Data Format Table 1 illustrates the 16-bit, serial data-stream output format for both the MAX157 and MAX159. The first three bits are always logic high (including the EOC bit for internal clock mode), followed by the channel identifica- tion (CHID = 0 for CHO, CHID = 1 for CH1, CHID = 1 for MAX159), the 10 bits of data in MSB first format, and two sub-LSB bits (S1 and SO). After the last bit has been read out, additional SCLK pulses will clock out trailing zeros. DOUT transitions on the falling edge of SCLK. The output remains high impedance when CS/SHDN is high. External Reference An external reference is required for both the MAX157 and MAX159. At REF, the DC input resistance is a mini- mum of 18kQ. During a conversion, a reference must be able to deliver 250yA of DC load current and have an output impedance of 10 or less. Use a 0.1pF bypass capacitor for best performance. The reference input structure allows a voltage range of 0 to (Vpp + 50mV) although noise levels will decrease effective res- olution at lower reference voltages. Automatic Power-Down Mode Whenever the MAX157/MAX159 are not selected (CS/SHDN = Vpp), the parts enter their shutdown mode. In shutdown all internal circuitry is turned off, which reduces the supply current to typically less than 0.2pA. With an external reference stable to within 1LSB, the wake-up time is 2.5us. If the external reference is not sta- ble within 1LSB, the wake-up time must be increased to allow the reference to stabilize. Applications Information Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, SNR is the ratio of full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADCs resolution (N bits): SNR(MAX) = (6.02: N + 1.76)dB In reality, there are other noise sources besides quanti- zation noise: thermal noise, reference noise, clock jitter, ACTVE POWER ACTIVE SAMPLING INSTANT DOWN c tcs yt al (taca) tWAKE CS/SHDN v SCLK 1] [2] [3] [4] fs] fe] [7] a] fo] fol fa) fre] fal fa) fa) fre bout \cHID\iuse\(be X G7 X b6X os XDA DaXDXOI Koo Ks Yeo AS Figure 6. External Clock Mode Timing CSYSHDN \ | Figure 7. Detailed Serial-Interface Timing Sequence 10 MAXUM+2./V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin uMAX Table 1. Serial Output Data Stream for Internal and External Clock Mode SCLK CYCLE 1 2 3 4 5 6 7 8 9 10 ; 11 | 12 | 13 | 14 | 15 | 16 DOUT (Internal Clock) EOC} 1 1 |CHID] D9 | D8 | D7 | D6 | DS | D4} D3} D2} D1 |} DO] Si | SO DOUT (External Clock) 1 1 1 |CHID] D9 | D8 | D7 | D6 | DS | D4} D3} D2} D1 |} DO] Si | SO etc. Therefore, SNR is computed by taking the ratio of the RMS signal to the RMS noise (which includes all spectral components minus the fundamental), the first five harmonics, and the DC offset. Signal-to-Noise Plus Distortion (SINAD) Signal-to-noise plus distortion is the ratio of the funda- mental input frequencys RMS amplitude to RMS equiv- alent of all other ADC output signals: = 20- ____Signalams SINAD(AB) = 20 * log loses Distortion)aus Effective Number of Bits (ENOB) ENOB indicates the global accuracy of an ADC ata specific input frequency and sampling rate. An ideal ADCs error consists of quantization noise only. With an input range equal to the full-scale range of the ADC, calculate the effective number of bits as follows: ENOB = (SINAD - 1.76) /6.02 Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of the first five harmon- ics of the input signal to the fundamental itself. This is expressed as: (Vo2 + Vg2 + V2 + V52} v2 THD = 20: log where Vj is the fundamental amplitude and Ve through V5 are the amplitudes of the 2nd through 5th-order har- monics. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. Connection to Standard Interfaces The MAX157/MAX159 interface is fully compatible with SPI/QSPI and MICROWIRE standard serial interfaces. lf a serial interface is available, establish the CPU's seri- al interface as master so that the CPU generates the MA AXIAMA serial clock for the MAX157/MAX159. Select a clock fre- quency from 100kHz to 2.17MHz (external clock mode). 1) Use a general-purpose |/O line on the CPU to pull CS/SHDN low while SCLK is low. 2) Wait for the minimum wake-up time (tWAKE) speci- fied before activating SCLK. 3) Activate SCLK for a minimum of 16 clock cycles. The first falling clock edge will generate a serial data- stream of three leading ones, followed by the chan- nel identification, the MSB of the digitized input signal, and two sub-bits. DOUT transitions on SCLKs falling edge and is available in MSB-first for- mat. Observe the SCLK to DOUT valid timing char- acteristic. Data should be clocked into the uP on SCLKs rising edge. 4) Pull CS/SHDN high at or after the 16th falling clock edge. If CS/SHDN remains low, trailing zeros will be clocked out after the sub-bits. 5) With CS/SHDN high, wait at least 6Ons (tcs), before starting a new conversion by pulling CS/SHDN low. A conversion can be aborted by pulling CS/SHDN high before the conversion ends; wait at least 60ns before starting a new conversion. Data can be output either in two 8-bit sequences or continuously. The bytes will contain the result of the conversion padded with three leading ones, the chan- nel identification before the MSB, and two trailing sub- bits. If the serial clock hasn't been idled after the last sub-bit (SO) and CS/SHDN is kept low, DOUT sends trailing zeros. SPI and MICROWIRE Interface When using SPI (Figure 8a) or MICROWIRE (Figure 8b) interfaces, set CPOL = 0 and CPHA = 0. Conversion begins with a falling edge on CS/SHDN (Figure 8c). Two consecutive 8-bit readings are necessary to obtain the entire 10-bit result from the ADC. DOUT data transitions on the serial clocks falling edge and is clocked into the UP on SCLKs rising edge. The first 8-bit data stream contains three leading ones, followed by channel identi- fication and the first four data bits starting with the MSB. The second 8-bit data stream contains the remaining bits, D5 through DO, and the sub-bits S1 and SO. 11 6SLXVW/ZSLXVWMAX157/MAX159 +2./V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin uUMAX V0 w-1 CSSHDN SCK we] SCLK MISO |-} DOUT Vi SPI m0 MAXIMA ss MAX159 vO w-| CS/SHDN SK b-1 SCLK S| |< DOuT MICROWIRE MAAXILAA MAX157 MAX159 MAX157 Figure 8a. SPI Connections Figure 8b. MICROWIRE Connections |-<_ 1ST BYTE READ > | |< 2ND BYTE READ | SAMPLING MSB INSTANT *WHEN CS/SHDN IS HIGH, DOUT = HIGH -Z POLE MELEE ELT viviviviy : vivivivivivivivy, ..., DUT ~~ .CS;;C+ <CHIDK D9 X D8 X D7 X D6 D5 _Xb4 XD3 X D2 Di COOK SEX SY _ Figure 8c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0) QSPI Interface Using the high-speed QSPI interface with CPOL = 0 and CPHA = 0, the MAX157/MAX159 supports a maxi- mum fscLk of 2.17MHz. The QSPI circuit in Figure 9a can be programmed to perform a conversion on each of the two channels for the MAX157. Figure 9b shows the QSPI interface timing. PIC16 with SSP Module and PIC17 Interface The MAX157/MAX159 are compatible with a PIC16/ PIC17 microcontroller (uC), using the synchronous seri- al port (SSP) module. To establish SPI communication, connect the controller as shown in Figure 10a and configure the PIC16/PIC17 as system master by initializing its synchronous serial port control register (SSPCON) and synchronous serial port status register (SSPSTAT) to the bit patterns shown in Tables 2 and 3. In SPI mode, the PIC16/PIC17 pCs allow eight bits of data to be synchronously transmitted and received simultaneously. Two consecutive 8-bit readings (Figure 10b) are necessary to obtain the entire 10-bit result from the ADC. DOUT data transitions on the serial clocks falling edge and is clocked into the pC on SCLKs rising edge. The first 8-bit data stream contains 12 | CS/SHDN SCK wm] SCLK MISO. |<] DouT MAXISA MAX157 MAX159 al QSPI Figure 9a. QSPI Connections three leading ones, the channel identification, and the first four data bits starting with the MSB. The second 8- bit data stream contains the remaining bits, D5 through DO, and the two sub-bits S1 and SO. Layout, Grounding, and Bypassing For best performance use printed circuit boards (PCBs), wire-wrap configurations are not recommend- ed, since the layout should ensure proper separation of analog and digital traces. Run analog and digital lines anti-parallel to each other, and dont layout digital sig- nal paths underneath the ADC package. Use separate analog and digital PCB ground sections with only one MAXUM+2./V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin uMAX SCLK 1\#2\ 3 Lila Lats ate a7 us Lao atoh ae ash ath dish die} SISHON | A TUTTE ET ET Yiyyivivivivivivielviviv iy] naz pout KCHIDK D9 X D8 K D7 X DS K 05 D4 K D3 K D2 K D1 X DO X Si X 80 ry SAMPLING INSTANT MSB LSB *WHEN CS/SHDN IS HIGH, DOUT = HIGH - Z Figure 9b. QSPI Interface Timing Sequence (CPOL = CPHA = 0) star-point (Figure 11) connecting the two ground sys- Vop Vop tems (analog and digital). For lowest-noise operation, ensure the ground return to the star grounds power SCLK beg SCK supply is low impedance and as short as possible. pour we! 801 Route dig ital signals far away from sensitive analog and reference inputs. CS/SHDN |-t VO __, High-frequency noise in the power supply (VppD) could MAXIM influence the proper operation of the ADCs fast com- MAX157 PICI6/PIC17 parator. Bypass Vpp to the star ground with a network MAX159 of two parallel capacitors, 0.1uF and 1pF, located as I Lo close as possible to the power supply pin of the = GND = GND MAX157/MAX159. Minimize capacitor lead length for best supply-noise rejection and add an attenuation Figure 10a. SPI Interface Connection for a PIC16/PIC 17 resistor (10Q) if the power supply is extremely noisy. Controller |< 1ST BYTE READ | |-<__2ND BYTE READ | SCLK 1 2 3 4 5 6 7 8 A SSO" eT r viviviviy Hi-Z pour KCHID D9 K_D8_K_D7_K_D6 la SAMPLING INSTANT MgB *WHEN CS/SHDN IS HIGH, DOUT = HIGH - Z Figure 10b. SPI Interface Timing Sequence with PIC16/17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3-SSPMO0 = 0001) POWER SUPPLIES 43V +3V. GND Rt =10Q +p iM 0.1pF Vop GND +3V. DGND MAXIMA DIGITAL MAX157 CIRCUITRY MAX159 * OPTIONAL FILTER RESISTOR Figure 11. Power-Supply Bypassing and Grounding MAXIM 13 6SLXVW/ZSLXVWMAX157/MAX159 +2./V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin uUMAX Table 2. Detailed SSPCON Register Content CONTROL BIT ee 59 SYNCHRONOUS SERIAL PORT CONTROL REGISTER (SSPCON) WCOL Bit 7 X Write Collision Detection Bit SSPOV Bit 6 X Receive Overflow Detect Bit Synchronous Serial Port Enable Bit SSPEN Bit 5 1 0: Disables serial port and configures these pins as I/O port pins. 1: Enables serial port and configures SCK, SDO and SCI pins as serial port pins. CKP Bit 4 0 Clock Polarity Select Bit. CKP = 0 for SPI master mode selection. SSPM3 Bit 3 0 SSPM2 Bit 2 Q Synchronous Serial Port Mode Select Bit. Sets SPI master mode and selects SSPM1 Bit 1 0 fcLK = fosc / 16. SSPMO Bit 0 1 X = Dont care Table 3. Detailed SSPSTAT Register Content CONTROL BIT es 59 SYNCHRONOUS SERIAL STATUS REGISTER (SSPSTAT) SMP Bit 7 0 hoe Input Sample Phase. Input data is sampled at the middle of the data output CKE Bit 6 1 SPI Clock Edge Select Bit. Data will be transmitted on the rising edge of the serial clock. D/A Bit 5 X Data Address Bit P Bit 4 X Stop Bit $s Bit 3 X Start Bit RAW Bit 2 X Read/Write Bit Information UA Bit 1 X Update Address BF Bit 0 X Buffer Full Status Bit X = Dont care 14 MAXUM+2./V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin uMAX Chip Information TRANSISTOR COUNT: 2,058 SUBSTRATE CONNECTED TO GND Package Information ; ff Q JEDEC 3 _T INCHES MILLIMETERS | INCHES MILLIMETERS a MIN MAX MIN | MAX | MIN MAX MIN | MAX A [0.037 |0.043 [0.94 110 [--- |0.043 [--- |1,10 Al |0.002 |0.006 |0.05 0.15 [0.002 | 0.006 [0.05 | 015 B |o.oi10 [0.014 [0.25 0.36 |o010 |oo16 [025 | 0.40 EH c_|0.005 |0.007_ [0.13 0.18 [0.005 | 0.009 | 0.13 0.23 D jo16 jo120 [2.95 3.05 [014 |o122 [29 3.1 e | 0.0256 BSC 0.65 BSC 0.0256 BSC 0.64 BSC E [ou6 [o120 [2.95 3.05 [o1u4 loize [29 [31 H {0.188 [0198 | 4.78 5.03 | 0193 BSC 4.9 BSC L_[o.016 [0.026 [0.41 0.66 [0016 [0027 [040 0.70 a LS Tf 4. Hk nares: SVIAAIL/WVI 1. D&E DO NOT INCLUDE MOLD FLASH. PROPRIETARY INFORMATION 2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15mm<.0067>. TITLE: 3. CONTROLLING DIMENSION: INCHES. 8LD uMAX PACKAGE DUTLINE DWG. 4. MEETS JEDEC MO-187. APPROVAL DOCUMENT CONTROL NO rev VY, 21-0036 E 1 MA AXIAMA 15 6SLXVW/ZSLXVWMAX157/MAX159 +2./V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin uUMAX Package Information (continued) PDIPN EPS: EAH D \ P= EL L_f ~wiL- o-15+ ff ~a A\ m| eB* INCHES MILLIMETERS INCHES MILLIMETERS MIN | MAX | MIN | MAX MIN | MAX | MIN | MAX [_N_|MS00l A | --- |0e00 | --- |5.08 0.348 [0.390 | 8.84 | 9.91 |8 |AB A1|0.015 |--- |0.38 | --- 0.735 |0.765 |18.67 |19.43 [14 |AC A2|0.1eS (0.175 |3.18 [4.45 A3/0,055 (0.080 |1.40 [2.03 B|0.016 0.022 |0.41 0.56 B1/0.045 {0.065 [1.14 [1.65 C 0.008 |0.01e (0.20 (0.30 D1 0.005 {0.080 [0.13 [2.03 0.745 [0.765 [18.92 |19.43 [16 |AA 0.885 |0.915 |22,.48]23.24/18 |AD LQ1S [1.045 |25.78/26.54|/20|AE 114, [1.265 [28.96]32.13 [24 |AF 1.360 [1.380 |34.54]35,05 [28/*S OOO HO|o|o|o E {0.300 |0.325|7,.6e |8.2e6 NOTES: F110.240 [0.310 [6.10 17.87 3, MELD FLASH CIR PROTRUSTIINS. NOT e {0.100 |--~ [254 | ~- CONTROLLING DIMENSIEN MILLIMETER 3. co eAl0.300 |--- |7.62 | --- 4. MEETS JEDEC MS001-xx AS SHOWN eBl --- 10.400 | --- 11016 IN ABOVE TABLE L 0.115 [0.150 [2.92 13.81 oN NUMBER GE BINS ee LVIAXI ZVI) PACKAGE FAMILY OUTLINE: PDIP 300 (4) 21-0043 A PROPRIE TARY_INFORMATION TITLE DOCUMENT CONTROL NUNEER REV Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 1998 Maxim Integrated Products Printed USA MAXIMA is a registered trademark of Maxim Integrated Products.