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FEATURES
DESCRIPTION/ORDERING INFORMATION
J
H
G
F
E
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8
2
3 4 5 6
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ZAHPACKAGE
(BOTTOMVIEW)
TS2PCIE2212PCI Express™ SIGNAL SWITCH
SCDS209 – JUNE 2006
•Offers Bandwidth Allocation of PCI Express™ •Excellent Differential Skew (5 ps Max)Signal Using Two-Lane 1:2
•Minimal Propagation DelayMultiplexer/Demultiplexer
•ESD Performance Tested Per JESD 22•Vcc Operating Range From 1.7 V to 1.9 V
– 2000-V Human-Body Model•Supports Data Rates of 2.5 Gbps
(A114-B, Class II)•Port-Port Crosstalk (–39 dB at 1.25 GHz)
– 1000-V Charged-Device Model (C101)•OFF Port Isolation (–38 dB at 1.25 GHz)•Low ON-State Resistance (10 ΩTyp)•Low Input/Output Capacitance (3.5 pF Typ)
The TS2PCIE2212 can be used to muxltiplex/demultiplex two PCI Express™ lanes, each representingdifferential pairs of receive (RX) and transmit (TX) signals. The switch operates at the PCI Express bandwidthstandard of 2.5-Gbps signal-processing speed. The device is composed of two banks, with each bankaccommodating two sources (source A and source B) and two destinations (destination A and destination B).
When a logic-level low is applied to the control (CTRL) pin, source A is connected to destination A and source Bis connected to destination B. When a logic-level high is applied to CTRL, source A is connected to destinationB, while source B and destination A are open.
ORDERING INFORMATION
T
A
PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING
0°C to 85 °C BGA – ZAH Tape and reel TS2PCIE2212ZAHR
TERMINAL ASSIGNMENTS
123456789
ACTRL0 TxSB:0P TxSA:0P GND TxDA:0P TxDB:0P NC
BRxSA:0P GND TxSB:0N TxSA:0N VDD TxDA:0N TxDB:0N GND RxDA:0P
CRxSA:0N RxDA:0N
DRxSB:0P RxSB:0N RxDB:0N RxDB:0P
EGND VDD VDD GND
FTxSA:1P TxSA:1N TxDA:1N TxDA:1P
GTxSB:1N TxDB:1N
HTxSB:1P GND RxSA:1N RxSB:1N VDD RxDB:1N RxDA:1N GND TxDB:1P
JNC RxSA:1P RXSB:1P GND RXDB:1P RxDA:1P CTRL1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PCI Express is a trademark of PCI-SIG.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
TxDA:0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
TxDB:0
RxDA:0
RxDB:0
TxDA:1
TxDB:1
RxDA:1
RxDB:1
TxSA:0
TxSB:0
RxSA:0
RxSB:0
TxSA:1
TxSB:1
RxSA:1
RxSB:1
CTRL1
CTRL0
TS2PCIE2212
PCI Express™ SIGNAL SWITCH
SCDS209 – JUNE 2006
PIN DESCRIPTION
NAME FUNCTION
TxSA:nP, TxSA:nN Source A transmit pairRxSA:nP, RxSA:nN Source A receive pairTxSB:nP, TxSB:nN Source B transmit pairRxSB:nP, RxSB:nN Source B receive pairTxDA:nP, TxDA:nN Destination A transmit pairRxDA:nP, RxDA:nN Destination A receive pairTxDB:nP, TxDB:nN Destination B transmit pairRxDB:nP, RxDB:nN Destination B receive pairCTRL0 Control signal for bank 0CTRL1 Control signal for bank 1V
DD
Positive supply voltageGND Ground (0 V)NC No internal connection
LOGIC DIAGRAM
2
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Absolute Maximum Ratings
(1)
Recommended Operating Conditions
TS2PCIE2212PCI Express™ SIGNAL SWITCH
SCDS209 – JUNE 2006
FUNCTION TABLE
CTRLn FUNCTION
L SA:n = DA:n, SB:n = DB:nH SA:n = DB:n, DA:n = open, SBin = open
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
DD
Supply voltage range –0.5 2.5 VV
IN
Control input voltage range
(2) (3)
–0.5 2.5 VV
I/O
Switch I/O voltage range
(2) (3) (4)
–0.5 2.5 VI
IK
Control input clamp current V
IN
< 0 and V
I/O
< 0 50 mAI
I/OK
I/O port clamp current V
IN
< 0 and V
I/O
< 0 50 mAI
I/O
ON-state switch current
(5)
±100 mAContinuous current through V
DD
or GND ±100 mAθ
JA
Package thermal impedance
(6)
TBD °C/WT
stg
Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltages are with respect to ground, unless otherwise specified.(3) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.(4) V
I
and V
O
are used to denote specific conditions for V
I/O
.(5) I
I
and I
O
are used to denote specific conditions for I
I/O
.(6) The package thermal impedance is calculated in accordance with JESD 51-7.
MIN TYP MAX UNIT
V
DD
Supply voltage 1.7 1.8 1.9 VV
IH
High-level control input voltage CTRL 0.65 V
DD
VV
IL
Low-level control input voltage CTRL 0.35 V
DD
VV
IO
Data input/output voltage 0 V
DD
VT
A
Operating free-air temperature 0 85 °C
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Electrical Characteristics
Switching Characteristics
TS2PCIE2212
PCI Express™ SIGNAL SWITCH
SCDS209 – JUNE 2006
over recommended operating free-air temperature range (unless otherwise noted)
T
A
= 0 °C to 85 °CPARAMETER TEST CONDITIONS UNITMIN TYP MAX
V
IK
Control inputs V
DD
= 1.7 V, I
IN
= –18 mA –1.8 VI
IN
Control inputs V
DD
= 1.9 V, V
IN
= V
DD
or GND ±1µAV
O
= 0 to 1.9 V,I
OZ
V
DD
= 1.9 V, Switch OFF ±5µAV
I
= 0,V
DD
= 1.9 V,I
CC
I
I/O
= 0, Switch ON or OFF 160 300 µAV
IN
= V
DD
or GND,C
in
Control inputs V
DD
= 1.9 V, V
IN
= V
DD
or GND 0.5 1.0 pFC
IO(OFF)
SB or DA port V
I/O
= 0 V, Switch OFF 1.4 1.5 pFC
IO(ON)
V
I/O
= 0 V, Switch ON 3.5 4 pFV
DD
= 1.7 V, V
I
= 0 V, I
O
= 10 mA 10 14r
on
ΩV
DD
= 1.7 V, V
I
= 1.5 V, I
O
= –10 mA 12 17∆r
on(flat)
V
DD
= 1.7 V, I
O
= 10 mA, V
I
= 1.5 V ±0.4 V 2.5 5 Ω
over recommended operating free-air temperature range (unless otherwise noted)
T
A
= 0 °C to 85 °CPARAMETER DESCRIPTION TEST CONDITIONS UNITMIN TYP MAX
DR Data rate per TX or RX pair 2.5 Gbpst
pd
Propagation delay, Sx to Dx See Figure 7 250 pst
sk
Intra-pair skew f =1.25 GHz, See Figure 7 5 pst
en
(t
PZL
, t
PZH
) Switch turn-on delay, CTRL to DA See Figure 6 5 nst
dis
(t
PLZ
, t
PHZ
) Switch turn-off delay, CTRL to DA See Figure 6 2.5 nsf =1.25 GHz, R
LOAD
= 50 Ω,I
LOSS
Differential insertion loss –2.5 –3.2 dBSee Figure 1f =1.25 GHz, R
LOAD
= 50 Ω,R
LOSS
Differential return loss –7.2 –9.5 dBSee Figure 2f =1.25 GHz, R
LOAD
= 50 Ω,I
LOSS(CM)
Common-mode insertion loss –2 dBSee Figure 3f =1.25 GHz, R
LOAD
= 50 Ω,O
IFF
Differential OFF isolation –33 –38 dBSee Figure 4f =1.25 GHz, R
LOAD
= 50 Ω,X
TALK
Differential crosstalk –33 –39 dBSee Figure 5
4
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OPERATING CHARACTERISTICS
Frequency (GHz)
−6
−5
−4
−3
−2
−1
0
0.01 0.10 1.00 10.00
Decibel (dB)
Frequency (GHz)
−25
−20
−15
−10
−5
0
0.01 0.10 1.00 10.00
Decibel (dB)
Frequency (GHz)
−12
−10
−8
−6
−4
−2
0
0.01 0.10 1.00 10.00
Decibel (dB)
Frequency (GHz)
−80
−60
−40
−20
0
0.01 0.10 1.00 10.00
Decibel (dB)
Frequency (GHz)
−80
−60
−40
−20
0
0.01 0.10 1.00 10.00
Decibel (dB)
TS2PCIE2212PCI Express™ SIGNAL SWITCH
SCDS209 – JUNE 2006
Figure 1. Differential Insertion Loss vs Frequency Figure 2. Differential Return Loss vs Frequency
Figure 3. Common-Mode Insertion Loss vs Frequency Figure 4. Differential OFF Isolation vs Frequency
Figure 5. Differential Crosstalk vs Frequency
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PARAMETER MEASUREMENT INFORMATION
CL
(see Note A)
TEST CIRCUIT
S1 2 × VDD
Open
GND
RL
RL
tPZL
VOH − 0.3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low , except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
50 Ω
VG1
VDD
DUT
50 Ω
VIN
50 Ω
VG2
VI
TEST RL
S1 V∆
CL
VCC VI
tPLZ/tPZL 1.8 V ± 0.1 V 2 × VDD 100 ΩGND No Load 0.3 V
Input Generator
Input Generator
VDD/2
VDD/2
VO
tPHZ/tPZH 1.8 V ± 0.1 V GND 100 ΩVDD No Load 0.3 V
Output Control
(VIN)VDD
VOH
VOL + 0.3 V
VOH
VOL
0 V
tPZH
tPLZ
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
Output
Waveform 1
S1 at 2 y VDD
(see Note B)
VOL
SA
CTRL
VDD/2 VDD/2
TS2PCIE2212
PCI Express™ SIGNAL SWITCH
SCDS209 – JUNE 2006
(Enable and Disable Times)
Figure 6. Test Circuit and Voltage Waveforms
6
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PARAMETER MEASUREMENT INFORMATION
Sx:nP
TS2PCIE2212
Sx:nN
Dx:nP
Dx:nN
Input
Generator VIVO
VCOM
VCOM + 400 mV
Input
Waveform
Output
Waveform
tPHL
tPLH
VCOM
VCRS VCRS
VCOM − 400 mV
VOH
VOL
VCOM = 1.5 V
tsk = |tPLHn – tPHLn|
VCRS is the cross point of the differential signal.
CTRL0
A1 GND
SA:n = DB:n, DA:n = open
TEST PATH
GNDSA:n = DA:n, SB:n = DB:n
VDD
T1(1)
(1) T1 is an external terminal.
VDD
T1(1)
VDD
100 Ω
TS2PCIE2212PCI Express™ SIGNAL SWITCH
SCDS209 – JUNE 2006
Figure 7. Test Circuit for Propagation Delay and Intra-Pair Skew
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SA:nP
SA:nN
SB:nP
SB:nN
DA:nP
DA:nN
DB:nP
DB:nN
50 Ω
TS2PCIE2212
CTRL0
A1 GND
TEST VNA
MEASUREMENT
Differential insertion loss S21
Differential return loss S11
Common-mode insertion loss S21
Network
Analyzer
50 Ω
VDD
VDD
50 Ω
50 Ω
TS2PCIE2212
PCI Express™ SIGNAL SWITCH
SCDS209 – JUNE 2006
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 8. Differential Insertion Loss, Differential Return Loss,and Common-Mode Insertion Loss Test Circuit
8
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TS2PCIE2212PCI Express™ SIGNAL SWITCH
SCDS209 – JUNE 2006
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 9. Differential Crosstalk and OFF Isolation Test Circuit
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TS2PCIE2212ZAHR ACTIVE NFBGA ZAH 48 3000 Pb-Free
(RoHS) SNAGCU Level-3-260C-168 HR
TS2PCIE2212ZAHRG1 ACTIVE NFBGA ZAH 48 3000 Green (RoHS &
no Sb/Br) SNAGCU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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PACKAGE OPTION ADDENDUM
www.ti.com 25-Nov-2008
Addendum-Page 1
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