August 1993
Revised April 1999
74VHC4040 12-Stage Binary Counter
© 1999 Fairchild Semiconductor Corporation DS011641.prf www.fairchildsemi.com
74VHC4040
12-Stage Binary Counter
General Descript ion
The VHC4040 is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi-
pation. The VHC4040 is a 12-stage counter which incre-
ments on the negative edge of the input clock and all
outputs are reset to a low level by applying a logical high
on the reset input. An input protection circuit insures that
0V to 7V can be app lied to the inputs wi thout r egard to the
supply volta ge. This device can be used to inter face 5V to
3V systems and two supply systems such as battery
back u p. T his c ir c ui t pr ev e nt s d e vi ce d es tr uc t io n du e to m is -
matched supply and input voltages.
Features
■High speed; fMAX = 210 MHz at VCC = 5V
■Low power dissipation: ICC = 4 µA (max) at TA = 25°C
■High noise immunity: VNIH =VNIL = 28% VCC (min)
■Power down protection is provided on all inputs
■Wide operat i ng voltage range: VCC (opr) = 2V − 5.5V
■Low noise: VOLP = 0.8V (max)
■Pin and function compatible with 74HC4040
Ordering Code:
Surface m ount pac k ages are als o availa ble on Tape and Reel. Specify by appendi ng the suffix let te r “X” to the or dering co de.
Connection Diagram Pin Descriptions
Order Number Package Number Package Description
74VHC4040M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
74VHC4040MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC4040N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
Q0–Q11 Flip-Flop Outputs
CP Negative Edged Triggered Clock
MR Master Reset
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74VHC4040
Logic Symbols
IEEE/IEC
Logic Diagram
Timing Diagr am
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74VHC4040
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions (Note 2)
Note 1: Absolute Maximum Ratings are values beyond which the device
may be da maged or ha ve its useful life impaire d. The datab ook specific a-
tions should be met, without exception, to ensure that the system design is
reliable over its pow er supply, temperature, and output/inpu t loa ding vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
Note 2: Unused inputs must be held HIGH or LOW. They may not float
DC Electrical Characteristics
Supply Voltage (VCC)−0.5V to +7.0V
DC Input Voltage (VIN)−0.5V to +7.0V
DC Output Voltage (VOUT)−0.5V to VCC + 0.5V
Input Diode Current (IIK)−20 mA
Output Diode Current (IOK)±20 mA
DC Output Current (IOUT)±25 mA
DC VCC/GND Current (ICC)±75 mA
Stora ge Temperature (TSTG)−65°C to +150°C
Lead Temperature (TL)
(Soldering, 10 seconds) 260°C
Supply Voltage (VCC)2.0V to +5.5V
Input Voltage (VIN)0V to +5.5V
Output Voltage (VOUT)0V to V
CC
Operating Temperature (TOPR)−40°C t o +85°C
Input Rise and Fall Time (tr, tf)
VCC = 3.3V ± 0.3V 0 ∼ 100 ns/V
VCC = 5.0V ± 0.5V 0 ∼ 20 ns/V
Symbol Parameter VCC
(V)
TA = 25°CT
A = −40°C to +85°CUnits Conditions
Min Typ Max Min Max
VIH HIGH Level Input 2.0 1.50 1.50 V
Voltage 3.0 − 5.5 0.7 VCC 0.7 VCC
VIL LOW Level Input 2.0 0.50 0.50 V
Voltage 3.0 − 5.5 0.3 VCC 0.3 VCC
VOH HIGH Level Output 2.0 1.9 2.0 1.9
VVIN = VIH
or VIL
IOH = −50 µA
Voltage 3.0 2.9 3.0 2.9
4.5 4.4 4.5 4.4
3.0 2.58 2.48 IOH = −4 mA
4.5 3.94 3.80 IOH = −8 mA
VOL LOW Level Output 2.0 0.0 0.1 0.1
VVIN = VIH
or VIL
IOL = 50 µA
Voltage 3.0 0.0 0.1 0.1
4.5 0.0 0.1 0.1
3.0 0.36 0.44 IOL = 4 mA
4.5 0.36 0.44 IOL = 8 mA
IIN Input Leakage Current 0 − 5.5 ±0.1 ±1.0 µAV
IN = 5.5V or GND
ICC Quiescent Supply Current 5.5 4.0 40.0 µAV
IN = VCC or GND
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74VHC4040
AC Electrical Characteristics
Note 3: CPD is defin ed as the value of th e internal equivalent capa c it anc e which is ca lc ulated fro m t he operating current consumptio n w it hout loa d. Av erage
operat ing current can be obtained by the e quation: ICC (opr) = CPD * VCC * fN + ICC.
AC Operating Requirements
Symbol Parameter VCC
(V)
TA = +25°CT
A = −40°C to +85°CUnits Conditions
Min Typ Max Min Max
tPLH Propagati on Delay T i me 3.3 ± 0.3 7.5 11.9 1.0 14.0 ns CL = 15 pF
tPHL to Q110.0 15.4 1.0 17.5 CL = 50 pF
5.0 ± 0.5 4.8 7.3 1.0 8.5 ns CL = 15 pF
6.3 9.3 1.0 10.5 CL = 50 pF
tPLH Propagati on Delay T i me 3.3 ± 0.3 ns CL = 15 pF
tPHL between Stages from 2.4 4.4 1.0 5.0 CL = 50 pF
Qn to Qn+15.0 ± 0.5 ns CL = 15 pF
1.6 3.1 1.0 3.5 CL = 50 pF
tPHL Propagation Del ay T ime 3.3 ± 0.3 8.3 12.8 1.0 15.0 ns CL = 15 pF
MR–Qn10.8 16.3 1.0 18.5 CL = 50 pF
5.0 ± 0.5 5.6 8.6 1.0 10.0 ns CL = 15 pF
7.1 10.6 1.0 12.0 CL = 50 pF
fMAX Maximum Clock 3.3 ± 0.3 90 140 75 MHz CL = 15 pF
Frequency 55 80 50 CL = 50 pF
5.0 ± 0.5 150 210 125 MHz CL = 15 pF
95 125 80 CL = 50 pF
CIN Input Capacitance 4 10 10 pF VCC = Open
CPD Power Dissipation Capacitance 21 pF (Note 3)
Symbol Parameter VCC
(V)
TA = 25°CT
A = −40°C to +85°CUnits
Typ Guaranteed Minimum
tw(L) Minimum Pulse Width 3.3 ± 0.3 5.0 5.0 ns
tw(H) (CP)5.0 ± 0.5 5.0 5.0
tw(L) Minimum Pulse Width 3.3 ± 0.3 5.0 5.0 ns
(MR) 5.0 ± 0.5 5.0 5.0
tREC Minimum Removal Time 3.3 ± 0.3 5.0 5.0 ns
(MR) 5.0 ± 0.5 5.0 5.0
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74VHC4040
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
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74VHC4040
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
74VHC4040 12-Stage Binary Counter
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r syst ems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instruct ions fo r use pr ovi de d in the labe l ing, can be re a-
sonably expected to result in a significant injury to the
user.
2. A criti cal com ponen t in any compo nent o f a l ife supp ort
device or system whose failure to perform can be rea-
sonabl y e xpec ted to c ause th e fa i lure of the li fe s upp or t
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
