N-Channel JFET Switch calocic CORPORATION J108 J110/SST108 SST110 FEATURES @ Low Cost Automated Insertlon Package e Low Insertion Loss No Offset or Error Voitages Generated by Closed Switch Purely Resistive High Isolation Resistance from Driver APPLICATIONS e Analog Switches @ Choppers e Commutators . Low-Nolse Audio Amplifiers ABSOLUTE MAXIMUM RATINGS (Ta = 25C unless otherwise specified) Fast Switching e Low Noise Gate-Drain or Gate-Source Voltage ................ -25V Gate Currant 2.0... cee ee cee ees ot 50mA Storage Temperature Range ............. -55C to +150C PIN CONFIGURATION Operating Temperature Range ........... -55C to +135C Lead Temperature (Soldering, 10sec) ............. +300C Power Dissipation ..... 0... ccc cece ee ee nee 360mW Derate above 25C . 0... cece eee e eee eee 3.3amW/C NOTE: Stresses above those listed under Absolute Maximum To. Ratings" may cause permanent damage to the device. These are 92 Stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING INFORMATION Part Package Temperature Range G J108-110 Plastic TO-92 -55C to +135C os PRODUCT MARKING (SOT-23) XJ108-110 Sorted Chips in Carriers -55C to 4135C 5018 $ST108 108 $S8T109-110 Plastic SOT-23 -55C to +135C SST109 109 SST110 110 ELECTRICAL CHARACTERISTICS (Ta = 25C unless otherwise specified) 108 109 110 SYMBOL PARAMETER DI MIN | TYP | MAX] MIN | TYP | MAX] MIN | TYP | MAX UNITS TEST CONDITIONS loss Gate Reverse Current (Note 1) +3 -3 -3 nA_ | Vos = OV, Vas = -15V Vasiok) Gate-Source Cutoff Voltage -3 -10 | -2 6 1-05 -4 Vv Vos = 5V, Ip = 1pA BVass Gate-Source Breakdown Voltage | -25 -25 -25 Vos = OV, Ia =-1pA loss Drain Saturation Current (Note 2) | 80 40 10 mA_ | Vos = 15V, Vas = OV lovot Drain Cutoff Current (Note 1) 3 3 3 nA_| Vos =5V, Vas = -10V (DS(on) Drain-Source ON Resistance 8 12 18 Q Vos <0.1V, Vas = OV Cagtott} Drain-Gate OFF Capacitance 15 15 15 Vps =0, : Vas =-10V Cegioth Source-Gate OFF Capacitance 15 15 15 pF (Note 3) f= 1MHz Cagton) Drain-Gate Plus Source-Gate 85 85 85 Vos = Vas = 0 +Cso(on)_| ON Capacitance (Note 3) tdion) Turn On Delay Time 4 4 4 Switching Time Test ise Ti Conditions (Note 3) i Rise Time 1 1 4 J107 J109 110 tavotty Turn OFF Delay Time 6 6 6 "NS lVop 15V 15V. 1.8V ti Fall Time 30 30 30 AoSioth, ev tee the NOTES: 1. Approximately doubles for every 10C increase in Ta. 2. Pulse test duration = 300ys; duty cycle <3%. 3. For design reference only, not 100% tested. 8-40