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FEATURES
NOTE: New and improved versions of the SN74ALVC164245
are available. The new part numbers are SN74LVC16T245 and
SN74LVCH16T245 and should be considered for new designs.
DESCRIPTION/ORDERING INFORMATION
DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
(3.3 V, 5 V) VCCB
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
(3.3 V, 5 V) VCCB
2B5
2B6
GND
2B7
2B8
2DIR
1OE
1A1
1A2
GND
1A3
1A4
VCCA (2.5 V, 3.3 V)
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCCA (2.5 V, 3.3 V)
2A5
2A6
GND
2A7
2A8
2OE
SN74ALVC16424516-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS416P – MARCH 1994 – REVISED NOVEMBER 2005
•Member of the Texas Instruments Widebus™Family
•Max t
pd
of 5.8 ns at 3.3 V• ± 24-mA Output Drive at 3.3 V•Control Inputs V
IH
/V
IL
Levels Are Referencedto V
CCA
Voltage•Latch-Up Performance Exceeds 250 mA PerJESD 17
This 16-bit (dual-octal) noninverting bus transceivercontains two separate supply rails. B port has V
CCB
,which is set to operate at 3.3 V and 5 V. A port hasV
CCA
, which is set to operate at 2.5 V and 3.3 V. Thisallows for translation from a 2.5-V to a 3.3-Venvironment, and vice versa, or from a 3.3-V to a 5-Venvironment, and vice versa.
The SN74ALVC164245 is designed for asynchronouscommunication between data buses. The controlcircuitry (1DIR, 2DIR, 1 OE, and 2 OE) is powered byV
CCA
.
To ensure the high-impedance state during power upor power down, the output-enable ( OE) input shouldbe tied to V
CC
through a pullup resistor; the minimumvalue of the resistor is determined by thecurrent-sinking capability of the driver.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
FBGA – GRD 74ALVC164245GRDRTape and reel VC4245FBGA – ZRD (Pb-free) 74ALVC164245ZRDRTube of 25 SN74ALVC164245DLSSOP – DL SN74ALVC164245DLR ALVC164245Reel of 1000
74ALVC164245DLRG4–40 °C to 85 °C SN74ALVC164245DGGR
Reel of 2000
74ALVC164245DGGRG4TSSOP – DGG ALVC164245SN74ALVC164245DGGT
Reel of 250
74ALVC164245DGGTE4VFBGA – GQL SN74ALVC164245KRReel of 1000 VC4245VFBGA – ZQL (Pb-free) 74ALVC164245ZQLR
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1994–2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
GQL OR ZQL PACKAGE
(TOP VIEW)
J
H
G
F
E
D
C
B
A
21 3 4 65
K
abc
GRD OR ZRD PACKAGE
(TOP VIEW)
J
H
G
F
E
D
C
B
A
21 3 4 65
SN74ALVC164245
16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVERWITH 3-STATE OUTPUTS
SCAS416P – MARCH 1994 – REVISED NOVEMBER 2005
The logic levels of the direction-control (DIR) input and the output-enable ( OE) input activate either the B-portoutputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits datafrom the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when theA-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logicHIGH or LOW level applied to prevent excess I
CC
and I
CCZ
.
TERMINAL ASSIGNMENTS
(1)
(56-Ball GQL/ZQL Package)
1 2 3 4 5 6
A1DIR NC NC NC NC 1 OE
B1B2 1B1 GND GND 1A1 1A2
C1B4 1B3 V
CCB
V
CCA
1A3 1A4
D1B6 1B5 GND GND 1A5 1A6
E1B8 1B7 1A7 1A8
F2B1 2B2 2A2 2A1
G2B3 2B4 GND GND 2A4 2A3
H2B5 2B6 V
CCB
V
CCA
2A6 2A5
J2B7 2B8 GND GND 2A8 2A7
K2DIR NC NC NC NC 2 OE
abc (1) NC – No internal connection
TERMINAL ASSIGNMENTS
(1)
(54-Ball GRD/ZRD Package)
123456
A1B1 NC 1DIR 1 OE NC 1A1
B1B3 1B2 NC NC 1A2 1A3
C1B5 1B4 V
CCB
V
CCA
1A4 1A5
D1B7 1B6 GND GND 1A6 1A7
E2B1 1B8 GND GND 1A8 2A1
F2B3 2B2 GND GND 2A2 2A3
G2B5 2B4 V
CCB
V
CCA
2A4 2A5
H2B7 2B6 NC NC 2A6 2A7
J2B8 NC 2DIR 2 OE NC 2A8
(1) NC – No internal connectionxxxxx
xxxxx
xxxxx
xxxxx
FUNCTION TABLE
(1)
(EACH 8-BIT SECTION)
CONTROL INPUTS OUTPUT CIRCUITS
OPERATIONOE DIR A PORT B PORT
L L Enabled Hi-Z B data to A busL H Hi-Z Enabled A data to B busH X Hi-Z Hi-Z Isolation
(1) Input circuits of the data I/Os always are active.
2
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To Seven Other Channels
1DIR
1A1
1B1
1OE
To Seven Other Channels
2DIR
2A1
2B1
2OE
1
47
24
36
48
2
25
13
Absolute Maximum Ratings
(1)
SN74ALVC16424516-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS416P – MARCH 1994 – REVISED NOVEMBER 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
over operating free-air temperature range for V
CCB
at 5 V and V
CCA
at 3.3 V (unless otherwise noted)
MIN MAX UNIT
V
CCA
–0.5 4.6V
CC
Supply voltage range VV
CCB
–0.5 6Except I/O ports
(2)
–0.5 6V
I
Input voltage range I/O port A
(3)
–0.5 V
CCA
+ 0.5 VI/O port B
(2)
–0.5 V
CCB
+ 0.5I
IK
Input clamp current V
I
< 0 –50 mAI
OK
Output clamp current V
O
< 0 –50 mAI
O
Continuous output current ±50 mAContinuous current through each V
CC
or GND ±100 mADGG package 70DL package 63θ
JA
Package thermal impedance
(4)
°C/WGQL/ZQL package 42GRD/ZRD package 36T
stg
Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) This value is limited to 6 V maximum.(3) This value is limited to 4.6 V maximum.(4) The package thermal impedance is calculated in accordance with JESD 51-7.
3
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Recommended Operating Conditions
(1)
Recommended Operating Conditions
(1)
SN74ALVC164245
16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVERWITH 3-STATE OUTPUTS
SCAS416P – MARCH 1994 – REVISED NOVEMBER 2005
for V
CCB
at 3.3 V and 5 V
MIN MAX UNIT
V
CCB
Supply voltage 3 5.5 VV
IH
High-level input voltage 2 VV
CCB
= 3 V to 3.6 V 0.7V
IL
Low-level input voltage VV
CCB
= 4.5 V to 5.5 V 0.8V
IB
Input voltage 0 V
CCB
VV
OB
Output voltage 0 V
CCB
VI
OH
High-level output current –24 mAI
OL
Low-level output current 24 mA∆t/ ∆v Input transition rise or fall rate 10 ns/VT
A
Operating free-air temperature –40 85 °C
(1) All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
for V
CCA
at 2.5 V and 3.3 V
MIN MAX UNIT
V
CCA
Supply voltage 2.3 3.6 VV
CCA
= 2.3 V to 2.7 V 1.7V
IH
High-level input voltage VV
CCA
= 3 V to 3.6 V 2V
CCA
= 2.3 V to 2.7 V 0.7V
IL
Low-level input voltage VV
CCA
= 3 V to 3.6 V 0.8V
IA
Input voltage 0 V
CCA
VV
OA
Output voltage 0 V
CCA
VV
CCA
= 2.3 V –18I
OH
High-level output current mAV
CCA
= 3 V –24V
CCA
= 2.3 V 18I
OL
Low-level output current mAV
CCA
= 3 V 24∆t/ ∆v Input transition rise or fall rate 10 ns/VT
A
Operating free-air temperature –40 85 °C
(1) All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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Electrical Characteristics
Electrical Characteristics
SN74ALVC16424516-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS416P – MARCH 1994 – REVISED NOVEMBER 2005
over recommended operating free-air temperature range for V
CCA
= 2.7 V to 3.6 V and V
CCB
= 4.5 V to 5.5 V (unlessotherwise noted)
PARAMETER TEST CONDITIONS V
CCA
V
CCB
MIN TYP
(1)
MAX UNIT
I
OH
= –100 µA 2.7 V to 3.6 V V
CC
– 0.22.7 V 2.2B to A I
OH
= –12 mA
3 V 2.4I
OH
= –24 mA 3 V 2V
OH
V4.5 V 4.3I
OH
= –100 µA
5.5 V 5.3A to B
4.5 V 3.7I
OH
= –24 mA
5.5 V 4.7I
OL
= 100 µA 2.7 V to 3.6 V 0.2B to A I
OL
= 12 mA 2.7 V 0.4V
OL
I
OL
= 24 mA 3 V 0.55 VI
OL
= 100 µA 4.5 V to 5.5 V 0.2A to B
I
OL
= 24 mA 4.5 V to 5.5 V 0.55I
I
Control inputs V
I
= V
CCA
/V
CCB
or GND 3.6 V 5.5 V ±5µAI
OZ
(2)
A or B port V
O
= V
CCA
/V
CCB
or GND 3.6 V 5.5 V ±10 µAI
CC
V
I
= V
CCA
/V
CCB
or GND, I
O
= 0 3.6 V 5.5 V 40 µAOne input at V
CCA
/V
CCB
– 0.6 V,∆I
CC
(3)
3 V to 3.6 V 4.5 V to 5.5 V 750 µAOther inputs at V
CCA
/V
CCB
or GNDC
i
Control inputs V
I
= V
CCA
/V
CCB
or GND 3.3 V 5 V 6.5 pFC
io
A or B port V
O
= V
CCA
/V
CCB
or GND 3.3 V 3.3 V 8.5 pF
(1) Typical values are measured at V
CCA
= 3.3 V and V
CCB
= 5 V, T
A
= 25 °C.(2) For I/O ports, the parameter I
OZ
includes the input leakage current.(3) This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than at 0 or the associatedV
CC
.
over recommended operating free-air temperature range for V
CCA
= 2.3 V to 2.7 V and V
CCB
= 3 V to 3.6 V (unless otherwisenoted)
PARAMETER TEST CONDITIONS V
CCA
V
CCB
MIN MAX UNIT
I
OH
= –100 µA 2.3 V to 2.7 V 3 V to 3.6 V V
CCA
– 0.2B to A I
OH
= –8 mA 2.3 V 3 V to 3.6 V 1.7V
OH
I
OH
= –12 mA 2.7 V 3 V to 3.6 V 1.8 VI
OH
= –100 µA 2.3 V to 2.7 V 3 V to 3.6 V V
CCB
– 0.2A to B
I
OH
= –18 mA 2.3 V to 2.7 V 3 V 2.2I
OL
= 100 µA 2.3 V to 2.7 V 3 V to 3.6 V 0.2B to A
I
OL
= 12 mA 2.3 V 3 V to 3.6 V 0.6V
OL
VI
OL
= 100 µA 2.3 V to 2.7 V 3 V to 3.6 V 0.2A to B
I
OL
= 18 mA 2.3 V 3 V 0.55I
I
Control inputs V
I
= V
CCA
/V
CCB
or GND 2.3 V to 2.7 V 3 V to 3.6 V ±5µAI
OZ
(1)
A or B port V
O
= V
CCA
/V
CCB
or GND 2.3 V to 2.7 V 3 V to 3.6 V ±10 µAI
CC
V
I
= V
CCA
/V
CCB
or GND, I
O
= 0 2.3 V to 2.7 V 3 V to 3.6 V 20 µAOne input at V
CCA
/V
CCB
– 0.6 V,∆I
CC
(2)
2.3 V to 2.7 V 3 V to 3.6 V 750 µAOther inputs at V
CCA
/V
CCB
or GND
(1) For I/O ports, the parameter I
OZ
includes the input leakage current.(2) This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than at 0 or the associatedV
CC
.
5
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Switching Characteristics
Operating Characteristics
SN74ALVC164245
16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVERWITH 3-STATE OUTPUTS
SCAS416P – MARCH 1994 – REVISED NOVEMBER 2005
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 4 )
V
CCB
= 3.3 V
V
CCB
= 5 V ±0.5 V±0.3 VFROM TOPARAMETER V
CCA
= 2.5 V V
CCA
= 3.3 V UNIT(INPUT) (OUTPUT) V
CCA
= 2.7 V±0.2 V ±0.3 V
MIN MAX MIN MAX MIN MAX
A B 7.6 5.9 1 5.8t
pd
nsB A 7.6 6.7 1.2 5.8t
en
OE B 11.5 9.3 1 8.9 nst
dis
OE B 10.5 9.2 2.1 9.5 nst
en
OE A 12.3 10.2 2 9.1 nst
dis
OE A 9.3 9 2.9 8.6 ns
T
A
= 25 °C
V
CCB
= 3.3 V V
CCB
= 5 V
PARAMETER TEST CONDITIONS V
CCA
= 2.5 V V
CCA
= 3.3 V UNIT
TYP TYP
Outputs enabled (B) 55 56C
L
= 50 pF, f = 10 MHzOutputs disabled (B) 27 6C
pd
Power dissipation capacitance pFOutputs enabled (A) 118 56C
L
= 50 pF, f = 10 MHzOutputs disabled (A) 58 6
6
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POWER-UP CONSIDERATIONS
(1)
SN74ALVC16424516-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS416P – MARCH 1994 – REVISED NOVEMBER 2005
TI level-translation devices offer an opportunity for successful mixed-voltage signal design. A proper power-upsequence always should be followed to avoid excessive supply current, bus contention, oscillations, or otheranomalies caused by improperly biased device pins. Take these precautions to guard against such power-upproblems:
1. Connect ground before any supply voltage is applied.2. Power up the control side of the device (V
CCA
for all four of these devices).3. Tie OE to V
CCA
with a pullup resistor so that it ramps with V
CCA
.4. Depending on the direction of the data path, DIR can be high or low. If DIR high is needed (A data to B bus),ramp it with V
CCA
. Otherwise, keep DIR low.(1) Refer to the TI application report, Texas Instruments Voltage-Level-Translation Devices, literature number SCEA021.
7
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PARAMETER MEASUREMENT INFORMATION
VOHB
VOLB
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1
VCCB = 6 V
Open
GND
500 Ω
500 Ω
tPLH tPHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
VCCA/2VCCA/2
VCCA/2 VCCA/2 VCCA
0 V
1.5 V 1.5 V VOHB
VOLB
0 V
1.5 V VOL + 0.3 V
1.5 V VOH − 0.3 V
0 V
Input
VCCA
VCCB
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
VCCB = 6 V
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤10 MHz, ZO = 50 Ω, tr≤2 ns, tf≤2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
SN74ALVC164245
16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVERWITH 3-STATE OUTPUTS
SCAS416P – MARCH 1994 – REVISED NOVEMBER 2005
V
CCA
= 2.5 V ±0.2 V to V
CCB
= 3.3 V ±0.3 V
Figure 1. Load Circuit and Voltage Waveforms
8
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PARAMETER MEASUREMENT INFORMATION
SN74ALVC16424516-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS416P – MARCH 1994 – REVISED NOVEMBER 2005
V
CCB
= 3.3 V ±0.3 V to V
CCA
= 2.5 V ±0.2 V
Figure 2. Load Circuit and Voltage Waveforms
9
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PARAMETER MEASUREMENT INFORMATION
tPLH VOH
VOL
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1 2 VCCB
Open
GND
500 Ω
500 Ω
tPHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 VCCB
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
1.5 V1.5 V
1.5 V 1.5 V 2.7 V
0 V
50% VCCB 50% VCCB
VOH
VOL
0 V
20% VCCB
50% VCCB 80% VCCB
0 V
Input
2.7 V
≈VCCB
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 VCCB
GND
TEST S1
50% VCCB
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
SN74ALVC164245
16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVERWITH 3-STATE OUTPUTS
SCAS416P – MARCH 1994 – REVISED NOVEMBER 2005
V
CCA
= 3.3 V ±0.3 V to V
CCB
= 5 V ±0.5 V
Figure 3. Load Circuit and Voltage Waveforms
10
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PARAMETER MEASUREMENT INFORMATION
VOHA
VOLA
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1 VCCA = 6 V
Open
GND
500 Ω
500 Ω
tPLH tPHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
1.5 V1.5 V
1.5 V 1.5 V 3 V
0 V
1.5 V 1.5 V VOHA
VOLA
0 V
1.5 V VOL + 0.3 V
1.5 V VOH − 0.3 V
0 V
Input
3 V
≈3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
VCCA = 6 V
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
SN74ALVC16424516-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS416P – MARCH 1994 – REVISED NOVEMBER 2005
V
CCB
= 5 V ±0.5 V to V
CCA
= 2.7 V and 3.3 V ±0.3 V
Figure 4. Load Circuit and Voltage Waveforms
11
PACKAGE OPTION ADDENDUM
www.ti.com 3-May-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
74ALVC164245DGGRE4 ACTIVE TSSOP DGG 48 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74ALVC164245DGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74ALVC164245DGGTE4 ACTIVE TSSOP DGG 48 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74ALVC164245DGGTG4 ACTIVE TSSOP DGG 48 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74ALVC164245DLG4 ACTIVE SSOP DL 48 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74ALVC164245DLRG4 ACTIVE SSOP DL 48 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74ALVC164245GRDR LIFEBUY BGA
MICROSTAR
JUNIOR
GRD 54 1000 TBD SNPB Level-1-240C-UNLIM
74ALVC164245ZQLR ACTIVE BGA
MICROSTAR
JUNIOR
ZQL 56 1000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
74ALVC164245ZRDR ACTIVE BGA
MICROSTAR
JUNIOR
ZRD 54 1000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
SN74ALVC164245DGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALVC164245DGGT ACTIVE TSSOP DGG 48 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALVC164245DL ACTIVE SSOP DL 48 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALVC164245DLR ACTIVE SSOP DL 48 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALVC164245KR LIFEBUY BGA
MICROSTAR
JUNIOR
GQL 56 1000 TBD SNPB Level-1-240C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
PACKAGE OPTION ADDENDUM
www.ti.com 3-May-2012
Addendum-Page 2
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74ALVC164245 :
•Enhanced Product: SN74ALVC164245-EP
NOTE: Qualified Version Definitions:
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
74ALVC164245GRDR BGA MI
CROSTA
R JUNI
OR
GRD 54 1000 330.0 16.4 5.8 8.3 1.55 8.0 16.0 Q1
74ALVC164245ZQLR BGA MI
CROSTA
R JUNI
OR
ZQL 56 1000 330.0 16.4 4.8 7.3 1.45 8.0 16.0 Q1
74ALVC164245ZRDR BGA MI
CROSTA
R JUNI
OR
ZRD 54 1000 330.0 16.4 5.8 8.3 1.55 8.0 16.0 Q1
SN74ALVC164245DGGR TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1
SN74ALVC164245DGGT TSSOP DGG 48 250 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1
SN74ALVC164245DLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1
SN74ALVC164245KR BGA MI
CROSTA
R JUNI
OR
GQL 56 1000 330.0 16.4 4.8 7.3 1.45 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
74ALVC164245GRDR BGA MICROSTAR
JUNIOR GRD 54 1000 333.2 345.9 28.6
74ALVC164245ZQLR BGA MICROSTAR
JUNIOR ZQL 56 1000 333.2 345.9 28.6
74ALVC164245ZRDR BGA MICROSTAR
JUNIOR ZRD 54 1000 333.2 345.9 28.6
SN74ALVC164245DGGR TSSOP DGG 48 2000 367.0 367.0 45.0
SN74ALVC164245DGGT TSSOP DGG 48 250 367.0 367.0 45.0
SN74ALVC164245DLR SSOP DL 48 1000 367.0 367.0 55.0
SN74ALVC164245KR BGA MICROSTAR
JUNIOR GQL 56 1000 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040048/E 12/01
48 PINS SHOWN
56
0.730
(18,54)
0.720
(18,29)
4828
0.370
(9,40)
(9,65)
0.380
Gage Plane
DIM
0.420 (10,67)
0.395 (10,03)
A MIN
A MAX
0.010 (0,25)
PINS **
0.630
(16,00)
(15,75)
0.620
0.010 (0,25)
Seating Plane
0.020 (0,51)
0.040 (1,02)
25
24
0.008 (0,203)
0.0135 (0,343)
48
1
0.008 (0,20) MIN
A
0.110 (2,79) MAX
0.299 (7,59)
0.291 (7,39)
0.004 (0,10)
M
0.005 (0,13)
0.025 (0,635)
0°–ā8°
0.005 (0,13)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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