OCTOBER 2017
DSC-5313/11
1
©2017 Integrated Device Technology, Inc.
Features
◆◆
◆◆
◆512K x 36, 1M x 18 memory configurations
◆◆
◆◆
◆Supports high performance system speed - 200 MHz
(3.2 ns Clock-to-Data Access)
◆◆
◆◆
◆ZBTTM Feature - No dead cycles between write and read
cycles
◆◆
◆◆
◆Internally synchronized output buffer enable eliminates the
need to control OE
◆◆
◆◆
◆Single R/W (READ/WRITE) control pin
◆◆
◆◆
◆Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
IDT71T75602
IDT71T75802
512K x 36, 1M x 18
2.5V Synchronous ZBT™ SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs
◆◆
◆◆
◆4-word burst capability (interleaved or linear)
◆◆
◆◆
◆Individual byte write (BW1 - BW4) control (May tie active)
◆◆
◆◆
◆Three chip enables for simple depth expansion
◆◆
◆◆
◆2.5V power supply (±5%)
◆◆
◆◆
◆2.5V I/O Supply (VDDQ)
◆◆
◆◆
◆Power down controlled by ZZ input
◆◆
◆◆
◆Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
◆◆
◆◆
◆Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA)
◆ ◆
◆ ◆
◆ Green parts available, see Ordering Information
Functional Block Diagram - 512K x 36
Clk
DQ
DQ
DQ Control Logic
Address
Control
DI DO
Input Register
5313 drw 01
Clock
D
Q
Clk
Output Register
Mux Sel
Gate
512Kx36 BIT
MEMORY ARRAY
JTAG
TMS
TDI
TCK TDO
(
o
p
tional
)
LBO
CE1, CE2, CE2
CEN
BWx
R/W
ADV/LD
OE
TRST
Address A [0:18]
Data I/O [0:31],
I/O P[1:4]
6.42
2
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
However, any pending data transfers (reads or writes) will be com-
pleted. The data bus will tri-state two cycles after the chip is deselected or
a write is initiated.
The IDT71T75602/802 have an on-chip burst counter. In the burst
mode, the IDT71T75602/802 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
external address (ADV/LD = LOW) or increment the internal burst
counter (ADV/LD = HIGH).
The IDT71T75602/802 SRAMs utilize a high-performance 2.5V
CMOS process, and are packaged in a JEDEC Standard 14mm x
20mm 100pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid
array (BGA).
Description
The IDT71T75602/802 are 2.5V high-speed 18,874,368-bit (18 Mega-
bit) synchronous SRAMs. They are designed to eliminate dead bus
cycles when turning the bus around between reads and writes, or writes
and reads. Thus, they have been given the name ZBTTM, or Zero Bus
Turnaround.
Address and control signals are applied to the SRAM during one clock
cycle, and two cycles later the associated data cycle occurs, be it read or
write.
The IDT71T75602/802 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable CEN pin allows operation of the IDT71T75602/802
to be suspended as long as necessary. All synchronous inputs are
ignored when (CEN) is high and the internal device registers will hold their
previous values.
There are three chip enable pins (CE1, CE2, CE2) that allow the user
to deselect the device when desired. If any one of these three is not
asserted when ADV/LD is low, no new memory operation can be initiated.
Functional Block Diagram - 1M x 18
Clk
DQ
DQ
DQ Control Logic
Address
Control
DI DO
Input Register
5313 drw 01b
Clock
D
Q
Clk
Output Register
Mux Sel
Gate
1Mx18 BIT
MEMORY ARRAY
JTAG
TMS
TDI
TCK TDO
(
o
p
tional
)
LBO
CE1, CE2, CE2
CEN
BWx
R/W
ADV/LD
OE
TRST
Address A [0:19]
Data I/O [0:15],
I/O P[1:2]
6.42
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
3
A
0
-A
19
Address Inputs Input Synchronous
CE
1
, CE
2
, CE
2
Chip Enab les Input Synchrono us
OE Output Enab le Input Asynchrono us
R/WRe ad/Write Sig nal Input Synchrono us
CEN Clock Enable Input Synchronous
BW
1
, BW
2
, BW
3
, BW
4
Indiv idual By te Write Se le cts Input Synchrono us
CLK Clock Input N/A
ADV/LD A d vance b urst ad dre ss / Lo ad new ad dre ss Input Synchrono us
LBO Line ar / Inte rle av e d Burs t Ord e r Inp u t S tatic
TMS Test Mode Select Input N/A
TDI Te s t Data Inp ut Inp u t N/ A
TCK Test Clock Input N/A
TDO Te s t Data Inp ut Outp ut N/A
TRST JTAG Reset (Optional) Input Asynchronous
ZZ Sleep Mode Input Synchronous
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
Data Inp ut / Outp ut I/ O S ync hro no us
V
DD
, V
DDQ
Co re P o we r, I/O Po wer S up p ly S tatic
V
SS
Ground Supply Static
5 313 t bl 01
Pin Description Summary
6.42
4
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Pin Definitions(1)
Sy mbo l P in Functi on I /O Active Descri pti on
A
0
-A
19
Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,
ADV/LD lo w, CEN l o w, and true chi p e nab le s .
ADV/LD Ad vanc e / Lo ad I N/A ADV/ LD is a sy nchronous i nput that i s us ed to l oa d the i nternal registers wi th new address an d control when i t is
sampled lo w at the rising edge of clock with the chip selec ted. When ADV/LD is low with the chip deselected,
any b urst in p rog res s is terminated . Whe n ADV/ LD i s s amp l ed hig h the n th e inte rnal b urst c o unte r is ad v anc ed
fo r any b urst that was in p rog ress . The e xte rnal ad d ress es are ig nore d whe n ADV/ LD is sampled high.
R/WRe ad / Wri te I N/ A R/ W si gnal is a synchronous input that i denti fies whethe r the current l oad cycle initiated is a Read o r Write access
to the me mo ry array. The d ata b us activ ity fo r the c urre nt c yc le take s p lac e two c lo ck cy cle s late r.
CEN Clo ck Enab le I LOW Sy nchro nous Clo c k E nable Input. Whe n CEN is samp le d hig h, all o the r sy nchro no us inp uts, inc lud ing clo ck are
ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if the low
to hig h clo c k trans itio n did no t o ccur. Fo r normal operation, CEN must be sampled low at rising edge of clock.
BW
1
-BW
4
Ind i v id ual By te
Wri te Enab le s I LOW Sync hrono us b yte write enab le s. Eac h 9-b it byte has its own active lo w byte write enab le . On lo ad write c yc le s
(whe n R/ W and ADV/ LD are sampled low) the appropriate byte write signal (BW
1
-BW
4
) must be valid. The byte
write s ignal must also be v alid o n e ach cycle of a burs t write . Byte Write signals are ignored when R/W is samp led
high. The appropriate byte(s) of data are written into the device two cycles later. BW
1
-BW
4
can all be tied low if
alway s d o ing write to the e ntire 36-b it word.
CE
1
, CE
2
Chip Enab le s I LOW Sync hrono us ac ti ve lo w chip e nab le . CE
1
and CE
2
are use d with CE
2
t o enabl e the IDT71T75602 /802 (CE
1
or CE
2
sampled high or CE
2
sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle. The
ZBT
TM
has a two c ycle d e se lect, i.e ., the data bus will tri-s tate two clo ck cycle s after dese lect is initiated.
CE
2
Chip Enabl e I HIGH Sync hronous activ e high chi p enabl e. CE
2
is used with CE
1
and CE
2
to ena ble th e c h ip. C E
2
has i n verted p ol arity
but otherwise identical to CE
1
and CE
2
.
CLK Clo ck I N/A This is the clo c k inp ut to the IDT71T75602/ 802. Ex ce p t fo r OE, all tim ing re fe re nce s for the d evic e are mad e with
respect to the rising edge of CLK.
I/O
0
-I/O
31
I/O
P1
-I/O
P4
D at a I npu t/O u tpu t I/O N/A S yn c h ron ou s data inpu t/ou tpu t ( I/ O ) pi n s . Both the da t a i n put path a nd da ta output pa th a r e regi ster ed a nd triggered
by the rising edge of CLK.
LBO Line ar B urst O rd e r I LOW B urst o rd e r s e le c ti o n i np ut. Whe n LBO is high the Interleaved burst sequence is selected. When LBO is lo w the
Line ar b urst s eq uenc e is se le c te d . LBO is a static i nput and it mus t no t chang e d uring de v ice op eratio n.
OE Outp ut Enab l e I LOW A sy nc hro no us o utput en ab le. OE m u st be l ow to read data from the 71 T75602/ 802. When OE is high the I/O pins
are in a hig h-imp e danc e state .OE does not need to be actively controlled for read and write cycles. In normal
operation, OE can be tied low.
TMS Test Mode Select I N/A Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
TDI Te s t Data In put I N/ A Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an internal
pullup.
TCK Te st Cl oc k I N/ A Clock input of TAP controller. Each TAP event is clocked. Test inp uts are captured on rising edge of TCK, while
test outputs are d riven from the falling edge of TCK. This pin has an internal p ull up.
TDO Te s t Da ta O utp u t O N/ A Serial output of registers placed between TDI and TDO. This output is active depending on the state of the TAP
controller.
TRST JTAG Reset
(Optional) ILOW
Optional asynchronous JTAG res et. Can be us ed to reset the TA P controll er, but not requi red. JTA G res et occurs
automatically at po wer up and also rese ts using TM S and TCK p er IEEE 1149.1. If not use d TRST can be left
floating. This pin has an internal pullup. Only available in BGA package.
ZZ Sleep Mode I HIGH Synchro nous sleep mode input. ZZ HIGH will g ate the CLK internal ly and power down the IDT7 1T75602/ 802 to its
lowe st power c onsum ption lev el. Data retenti on is guaranteed in Sleep Mode. This pin has an internal pulldown.
V
DD
Power Supply N/A N/A 2.5V core power supply.
V
DDQ
Power Sup ply N/A N/A 2.5V I/O Supp ly.
V
SS
Ground N/A N/A Ground.
5313 tbl 02
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
5
Recommended Operating
Temperature and Supply Voltage
Pin Configuration — 512K x 36
NOTES:
1. Pins 14, 16, and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH.
2. Pins 38, 39 and 43 will be pulled internally to VDD if not actively driven. To disable the TAP controller without interfering with normal operation, several settings are possible. Pins 38, 39
and 43 could be tied to VDD or VSS and pin 42 should be left unconnected. Or all JTAG inputs (TMS, TDI and TCK) pins 38, 39 and 43 could be left unconnected “NC” and the JTAG
circuit will remain disabled from power up.
Top View
100 TQFP
Recommended DC Operating
Conditions
NOTE:
1. VIL (min.) = –0.8V for pulse width less than tCYC/2, once per cycle.
Symbol Parameter Min. Typ. Max. Unit
V
DD
Co re S up ply Voltag e 2.375 2. 5 2.625 V
V
DDQ
I/O Sup ply Vo ltage 2.375 2.5 2.625 V
V
SS
Ground 0 0 0 V
V
IH
Input High Voltage - Inputs 1.7
____
V
DD
+0.3 V
V
IH
In put H i gh Volta ge - I/O 1 . 7
____
V
DDQ
+0.3 V
V
IL
Input Low Vo ltag e -0.3
(1)
____
0.7 V
5 3 13 t b l 03
Grade Ambient
Temperature
(1)
V
SS
V
DD
V
DDQ
Commercial 0° C to +70° C OV 2.5V ± 5% 2.5V ± 5%
Ind us trial -40° C to +85° C OV 2.5V ± 5% 2.5V ± 5%
5 313 tbl 05
NOTE:
1. During production testing, the case temperature equals the ambient temperature.
100
99
98
97
96
95
94
93
92
91
90
87
86
85
84
83
82
81
89
88
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A
6
A
7
CE
1
CE
2
BW
4
BW
3
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
A
18
A
8
A
9
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC/TCK
(2)
NC/TDO
(2)
NC/TDI
(2)
NC/TMS
(2)
LBO
A
14
A
13
A
12
A
11
A
10
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
I/O
31
I/O
30
V
DDQ
V
SS
I/O
29
I/O
28
I/O
27
I/O
26
V
SS
V
DDQ
I/O
25
I/O
24
V
SS
V
DD
I/O
23
I/O
22
V
DDQ
V
SS
I/O
21
I/O
20
I/O
19
I/O
18
V
SS
V
DDQ
I/O
17
I/O
16
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
I/O
14
V
DDQ
V
SS
I/O
13
I/O
12
I/O
11
I/O
10
V
SS
V
DDQ
I/O
9
I/O
8
V
SS
V
DD
I/O
7
I/O
6
V
DDQ
V
SS
I/O
5
I/O
4
I/O
3
I/O
2
V
SS
V
DDQ
I/O
1
I/O
0
5313 drw 02r
V
DD
(1)
I/O
15
I/O
P3
V
DD
(1)
I/O
P4
A
15
A
16
I/O
P1
V
DD
(1)
I/O
P2
ZZ
A
17
71T75602
PKG100
6.42
6
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Pin Configuration — 1Mx 18
NOTES:
1. Pins 14, 16, and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH.
2. Pins 38, 39 and 43 will be pulled internally to VDD if not actively driven. To disable the TAP controller without interfering with normal operation, several settings are possible. Pins 38, 39
and 43 could be tied to VDD or VSS and pin 42 should be left unconnected. Or all JTAG inputs (TMS, TDI and TCK) pins 38, 39 and 43 could be left unconnected “NC” and the JTAG
circuit will remain disabled from power up.
Top View
100 TQFP
100
99
98
97
96
95
94
93
92
91
90
87
86
85
84
83
82
81
89
88
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A6
A7
CE1
CE2
NC
NC
BW2
BW1
CE2
VDD
VSS
CLK
R/W
CEN
OE
ADV/LD
A19
A8
A9
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
LBO
A15
A14
A13
A12
A11
VDD
VSS
A0
A1
A2
A3
A4
A5
NC
NC
VDDQ
VSS
NC
I/OP2
I/O15
I/O14
VSS
VDDQ
I/O13
I/O12
VSS
VDD
I/O11
I/O10
VDDQ
VSS
I/O9
I/O8
NC
NC
VSS
VDDQ
NC
NC
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NC
VDDQ
VSS
NC
I/OP1
I/O7
I/O6
VSS
VDDQ
I/O5
I/O4
VSS
VDD
I/O3
I/O2
VDDQ
VSS
I/O1
I/O0
NC
NC
VSS
VDDQ
NC
NC
5313 drw 02ra
VDD(1)
NC
NC
VDD(1)
NC
A16
A17
NC
VDD(1)
A10
ZZ
A18
NC/TCK(2)
NC/TDO(2)
NC/TDI(2)
NC/TMS(2)
71T75802
PKG100
6.42
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
7
NOTES:
1. J3, R5, and J5 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. U2, U3, U4 and U6 will be pulled internally to VDD if not actively driven. To disable the TAP controller without interfering with normal operation, several settings are
possible. U2, U3, U4 and U6 could be tied to VDD or VSS and U5 should be left unconnected. Or all JTAG inputs(TMS, TDI, and TCK and TRST) U2, U3, U4 and U6
could be left unconnected “NC” and the JTAG circuit will remain disabled from power up.
3. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
Top View
Pin Configuration — 1M X 18, 119 BGA(1,2)
Top View
Pin Configuration — 512K X 36, 119 BGA(1,2)
1234567
AV
DDQ
A
6
A
4
A
19
A
8
A
16
V
DDQ
BNCCE
2
A
3
ADV/LD A
9
CE
2
NC
CNCA
7
A
2
V
DD
A
13
A
17
NC
DI/O
8
NC V
SS
NC V
SS
I/O
P1
NC
ENCI/O
9
V
SS
CE
1
V
SS
NC I/O
7
FV
DDQ
NC V
SS
OE V
SS
I/O
6
V
DDQ
GNCI/O
10
BW
2
A
18
V
SS
NC I/O
5
HI/O
11
NC V
SS
R/WV
SS
I/O
4
NC
JV
DDQ
V
DD
V
DD
(1)
V
DD
V
DD
(1)
V
DD
V
DDQ
KNCI/O
12
V
SS
CLK V
SS
NC I/O
3
LI/O
13
NC V
SS
NC BW
1
I/O
2
NC
MV
DDQ
I/O
14
V
SS
CEN V
SS
NC V
DDQ
NI/O
15
NC V
SS
A
1
V
SS
I/O
1
NC
PNCI/O
P2
V
SS
A
0
V
SS
NC I/O
0
RNCA
5
LBO V
DD
V
DD
(1)
A
12
NC
TNCA
10
A
15
NC A
14
A
11
ZZ
UV
DDQ NC/TMS
(2)
NC/TDI
(2)
NC/TCK
(2)
NC/TDO
(2)
NC/TRST
(2,3)
V
DDQ
5313 tbl 25c
1234567
AV
DDQ
A
6
A
4
A
18
A
8
A
16
V
DDQ
BNCCE
2
A
3
ADV/LD A
9
CE
2
NC
CNCA
7
A
2
V
DD
A
12
A
15
NC
DI/O
16
I/O
P3
V
SS
NC V
SS
I/O
P2
I/O
15
EI/O
17
I/O
18
V
SS
CE
1
V
SS
I/O
13
I/O
14
FV
DDQ
I/O
19
V
SS
OE V
SS
I/O
12
V
DDQ
GI/O
20
I/O
21
BW
3
A
17
BW
2
I/O
11
I/O
10
HI/O
22
I/O
23
V
SS
R/WV
SS
I/O
9
I/O
8
JV
DDQ
V
DD
V
DD
(1)
V
DD
V
DD
(1)
V
DD
V
DDQ
KI/O
24
I/O
26
V
SS
CLK V
SS
I/O
6
I/O
7
LI/O
25
I/O
27
BW
4
NC BW
1
I/O
4
I/O
5
MV
DDQ
I/O
28
V
SS
CEN V
SS
I/O
3
V
DDQ
NI/O
29
I/O
30
V
SS
A
1
V
SS
I/O
2
I/O
1
PI/O
31
I/O
P4
V
SS
A
0
V
SS
I/O
P1
I/O
0
RNCA
5
LBO V
DD
V
DD
(1)
A
13
NC
T NCNCA
10
A
11
A
14
NC ZZ
UV
DDQ NC/TMS
(2)
NC/TDI
(2)
NC/TCK
(2)
NC/TDO
(2)
NC/TRST
(2,3)
V
DDQ
5313 tbl 25b
6.42
8
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
Absolute Maximum Ratings(1) 100-Pin TQFP Capacitance
(TA = +25°C, f = 1.0MHz)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary; however,
the voltage on any input or I/O pin cannot exceed VDDQ during power supply ramp
up.
7. During production testing, the case temperature equals TA.
Symbol Rating Commercial Industrial Unit
V
TERM
(2) Te rminal Vo ltage with
Re s p e c t to G ND -0.5 to +3.6 -0.5 to +3.6 V
V
TERM
(3,6) Te rminal Vol tag e with
Re s p e c t to G ND -0.5 to V
DD
-0.5 to V
DD
V
V
TERM
(4,6) Te rminal Vol tag e with
Re s p e c t to G ND -0.5 to V
DD
+0.5 -0.5 to V
DD
+0.5 V
V
TERM
(5,6) Te rminal Vol tag e with
Re s p e c t to G ND -0.5 to V
DDQ
+0.5 -0.5 to V
DDQ
+0.5 V
T
A
(7) Operating Ambient
Temperature 0 to + 70 -40 to + 85
o
C
T
BIAS
Te m p e rature Und e r B ia s -55 to + 125 -55 to + 125
o
C
T
STG
Sto rag e Te mp e rature -55 to + 125 -55 to + 125
o
C
P
T
P o we r Dis s ip ati o n 2. 0 2. 0 W
I
OUT
DC Outp ut Curre nt 50 50 mA
5313 tbl 06
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Inp ut Cap ac itanc e V
IN
= 3dV 5 pF
C
I/O
I/ O Cap ac itanc e V
OUT
= 3dV 7 pF
5313 tbl 07
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Inp ut Cap ac itanc e V
IN
= 3dV 7 pF
C
I/O
I/O Cap acitanc e V
OUT
= 3dV 7 pF
5313 tbl 07a
119 BGA Capacitance
(TA = +25°C, f = 1.0MHz)
6.42
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
9
Synchronous Truth Table(1)
Partial Truth Table for Writes(1)
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of the burst
cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will tri-state
two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propagating through the part. The state of all the internal registers and the
I/Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for X18 configuration.
CEN R/WChip
(5)
Enable ADV/LD BWxADDRESS
USED PRE VIOUS CYCLE CURRENT CYCLE I/O
(2 cycles later)
L L Select L Valid External X LOAD WRITE D
(7)
L H Se lect L X External X LOAD READ Q
(7)
L X X H Valid Inte rnal LOAD WRITE /
BURST WRITE BURST WRITE
(Advance burst counter)
(2)
D
(7)
L X X H X Inte rnal LOAD READ /
B URS T RE A D B URS T RE A D
(Advance burst counter)
(2)
Q
(7)
L X De s e le c t L X X X DES ELE CT o r S TOP
(3)
HiZ
L X X H X X DESELECT / NOOP NOOP HiZ
H X X X X X X SUSPEND
(4)
Pre vious Value
5 313 t bl 08
OPERATION R/WBW
1
BW
2
BW
3
(3)
BW
4
(3)
READ H X X X X
WRITE ALL BYTES L L L L L
WRITE BYTE 1 (I/O[0:7], I/O
P1
)
(2)
LLHHH
WRITE BYTE 2 (I/O[8:15], I/O
P2
)
(2)
LHLHH
WRITE BYTE 3 (I/O[16:23], I/O
P3
)
(2,3)
LHHLH
WRITE BYTE 4 (I/O[24:31], I/O
P4
)
(2,3)
LHHHL
NO WRITE L HHHH
53 13 tbl 09
6.42
10
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Linear Bur st Sequence Table (LBO=VSS)
Interleaved Burst Sequence Table ( LBO=VDD)
Functional Timing Dia gram(1)
NOTES:
1. This assumes CEN, CE1, CE2, CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data delay
from the rising edge of clock.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 0 0 1 1 1 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1)
11100100
5 313 t bl 10
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 1 0 1 1 0 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1)
11000110
5313 tbl 11
n+29
A29
C29
D/Q27
ADDRESS
(2)
(A
0
-A
18
)
CONTROL
(2)
(R/W,ADV/LD,BWx)
DATA
(2)
I/O
[0:31]
,I/OP
[1:4]
CYCLE
CLOCK
n+30
A30
C30
D/Q28
n+31
A31
C31
D/Q29
n+32
A32
C32
D/Q30
n+33
A33
C33
D/Q31
n+34
A34
C34
D/Q32
n+35
A35
C35
D/Q33
n+36
A36
C36
D/Q34
n+37
A37
C37
D/Q35
5313drw 03
,
6.42
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
11
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Read Operation(1)
Device Operation - Showing Mixed Load, Burst,
Deselect and NOOP Cycles(2)
NOTES:
1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
2. H = High; L = Low; X = Don’t Care; Z = High Impedance.
Cycle Address R/WADV/LD CE
(1)
CEN BWxOE I/O Comments
nA
0
H L L L X X X Lo ad re ad
n+1 X X H XLXXXBurst read
n+2 A
1
HL LLXLQ
0
Lo ad read
n+3 X X L H L X L Q
0+1
Deselect or STOP
n+4 X X H X L X L Q
1
NOOP
n+5 A
2
H L L L X X Z Load read
n+6 X X H X L X X Z Burst re ad
n+7 X X L H L X L Q
2
Deselect or STOP
n+8 A
3
L L LLLLQ
2+1
Lo ad write
n+9 X X H X L L X Z Burst write
n+10 A
4
LLLLLXD
3
Lo ad write
n+11 X X L H L X X D
3+1
Deselect or STOP
n+12 X X H X L X X D
4
NOOP
n+13 A
5
L L L L L X Z Load write
n+14 A
6
H L L L X X Z Load read
n+15 A
7
LLLLLXD
5
Lo ad write
n+16 X X H X L L L Q
6
Burst write
n+17 A
8
HL LLXXD
7
Lo ad read
n+18 X X H X L X X D
7+1
Burst read
n+19 A
9
L L LLLLQ
8
Lo ad write
5 313 t bl 12
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O Comments
nA
0
H L L L X X X Address and Control meet setup
n+1 X X X XLXXXClock Setup Valid
n+2 X X X XXXLQ
0
Contents of Address A
0
Re ad Out
5 313 t b l 13
6.42
12
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Bur st Write Operation(1)
Bur st Read Operation(1)
Write Operation(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O Comments
nA
0
H L L L X X X Address and Control meet setup
n+1 X X H X L X X X Clock Setup Valid, Advance Counter
n+2 X X H X L X L Q
0
Address A
0
Read Out, Inc. Count
n+3 X X H X L X L Q
0+1
Address A
0+1
Read Out, Inc. Co unt
n+4 X X H X L X L Q
0+2
Address A
0+2
Re ad Out, Inc . Co unt
n+5 A
1
HL LLXLQ
0+3
Address A
0+3
Re ad Out, Lo ad A
1
n+6 X X H X L X L Q
0
Address A
0
Read Out, Inc. Count
n+7 X X H X L X L Q
1
Address A
1
Re ad Out, Inc . Co unt
n+8 A
2
HL LLXLQ
1+1
Address A
1+1
Read Out, Lo ad A
2
5 313 t bl 14
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O Comments
nA
0
L L L L L X X Address and Control meet setup
n+1 X X X XLXXXClock Setup Valid
n+2 X X X X L X X D
0
Write to Address A
0
5 313 t b l 15
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O Comments
nA
0
L L L L L X X Address and Control meet setup
n+1 X X H X L L X X Clo ck Se tup Valid, Inc. Count
n+2 X X H X L L X D
0
Address A
0
Write, Inc. Count
n+3 X X H X L L X D
0+1
Address A
0+1
Write, Inc. Count
n+4 X X H X L L X D
0+2
Address A
0+2
Write, Inc. Count
n+5 A
1
LLLLLXD
0+3
Address A
0+3
Write , Lo ad A
1
n+6 X X H X L L X D
0
Address A
0
Write, Inc. Count
n+7 X X H X L L X D
1
Address A
1
Wri te , Inc . Co unt
n+8 A
2
LLLLLXD
1+1
Address A
1+1
Write , Lo ad A
2
5 313 t bl 16
6.42
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
13
Read Operation with Clock Enable Used(1)
Write Operation with Clock Enable Used(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Cycle Address R/WADV/LD CE(2) CEN BWxOE I/O Comments
nA
0
H L L L X X X Address and Control meet setup
n+1 X X X X H X X X Cloc k n+1 Igno red
n+2 A
1
H L L LXXXClock Valid
n+3 X X X X H X L Q
0
Clock Ignored. Data Q
0
is on the bus.
n+4 X X X X H X L Q
0
Clock Ignored. Data Q
0
is on the bus.
n+5 A
2
HL LLXLQ
0
Address A
0
Re ad o ut (b us trans . )
n+6 A
3
HL LLXLQ
1
Address A
1
Read out (b us trans.)
n+7 A
4
HL LLXLQ
2
Address A
2
Re ad o ut (b us trans . )
5 313 t bl 17
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O Comments
nA
0
L L L L L X X Address and Control meet setup.
n+1 X X X X H X X X Clo ck n+1 Igno re d.
n+2 A
1
L L L L L X X Clock Valid.
n+3 X X X X H X X X Clock Ignored.
n+4 X X X X H X X X Clock Ignored.
n+5 A
2
LLLLLXD
0
Write Data D
0
n+6 A
3
LLLLLXD
1
Write Data D
1
n+7 A
4
LLLLLXD
2
Write Data D
2
5 313 t bl 18
6.42
14
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
Read Operation with Chip Enable Used(1)
Write Operation with Chip Enable Used(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O
(3)
Comments
n X X L H L X X ? Deselected.
n+1 X X L H L X X ? Deselected.
n+2 A
0
H L L L X X Z Address and Control meet setup.
n+3 X X L H L X X Z Deselected or STOP.
n+4 A
1
HL LLXLQ
0
Address A
0
Re ad out. Load A
1
.
n+5 X X L H L X X Z Deselected or STOP.
n+6 X X L H L X L Q
1
Address A
1
Read out. Deselected.
n+7 A
2
H L L L X X Z Address and control meet setup.
n+8 X X L H L X X Z Deselected or STOP.
n+9 X X L H L X L Q
2
Address A
2
Read out. Deselected.
5 313 t bl 19
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O Comments
n X X L H L X X ? Deselected.
n+1 X X L H L X X ? Deselected.
n+2 A
0
L L L L L X Z Ad dre ss and Control me e t se tup .
n+3 X X L H L X X Z Deselected or STOP.
n+4 A
1
LLLLLXD
0
Address D
0
Write in. Load A
1
.
n+5 X X L H L X X Z Deselected or STOP.
n+6 X X L H L X X D
1
Address D
1
Write in. Deselected.
n+7 A
2
L L L L L X Z Address and control meet setup.
n+8 X X L H L X X Z Deselected or STOP.
n+9 X X L H L X X D
2
Address D
2
Write in. Deselected.
5 313 t bl 20
6.42
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
15
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 2.5V±5%)
Figure 2. Lumped Capacitive Load, Typical Derating
AC Test Conditions
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VDD = 2.5V±5%)
Figure 1. AC Test Load
AC Test Load
NOTE:
1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD, and the ZZ pin will be internally pulled to VSS if they are not actively driven in the application.
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.
4. 200MHz is for 71T75802 only.
Symbo l Parameter Test Conditi ons Mi n. Max. Unit
|I
LI
| Inp ut Le akag e Curre nt V
DD
= Max., V
IN
= 0V to V
DD
___
5µA
|I
LI
|LBO, JTAG and ZZ Input Leakage Current
(1)
V
DD
= Max., V
IN
= 0V to V
DD
___
30 µA
|I
LO
| Output Leakage Current V
OUT
= 0V to V
DDQ
, Device Deselected
___
5µA
V
OL
Outp ut Lo w Vol tage I
OL
= +6mA, V
DD
= Min.
___
0.4 V
V
OH
Outp ut Hig h Vo ltag e I
OH
= -6mA, V
DD
= Mi n. 2. 0
___
V
5313 tbl 21
Inp u t Pul se Le v e ls
Inp u t Ris e / Fal l Tim e s
Inp u t Tim ing Re fe re nc e Le v e l s
Output Timing Referenc e Le ve ls
AC Te st Lo ad
0 to 2. 5V
2ns
(V
DDQ
/2)
(V
DDQ
/2)
See Figure 1
5313 tbl 23
V
DDQ
/2
50Ω
I/O Z
0
=50Ω
5313 drw 04
,
1
2
3
4
20 30 50 100 200
∆tCD
(Typical , n s)
Capacitance (pF)
80
5
6
•
••
•
•
5313 dr w 05
Symbol Parameter Test Conditions 200MHz(4) 166MHz 150MHz 133MHz 100MHz Unit
Com'l Ind Com'l Ind Com'l Ind Com'l Ind Com'l Ind
I
DD
Operating Power
Supply Current Device Sel ected, Outputs O pen,
ADV/LD = X, V
DD
= Max.,
V
IN
> V
IH
or < V
IL
, f = f
MAX
(2) 275 295 245 265 215 235 195 215 175 195 mA
I
SB1
CMOS Stan dby Power
Supply Current Device Deselected, Outputs Open,
V
DD
= Max., V
IN
> V
HD
or < V
LD
,
f = 0(2,3) 40 60 40 60 40 60 40 60 40 60 mA
I
SB2
Clock Running Power
Supply Current Device Deselected, Outputs Open,
V
DD
= Max., V
IN
> V
HD
or < V
LD
,
f = f
MAX
(2.3) 80100709060 8050704565 mA
I
SB3
Id le Pow er
Supply Current Device Sel ected, Outputs O pen,
CEN > V
IH
, V
DD
= Max.,
V
IN
> V
HD
or < V
LD
, f = f
MAX
(2,3) 60 80 60 80 60 80 60 80 60 80 mA
I
ZZ
Full Sleep Mode
Supply Current
Device Sel ected, Outputs O pen,
CEN < V
IH
, V
DD
= Max.,
V
IN
> V
HD
or < V
LD
, f = f
MAX
(2,3),ZZ >
V
HD
40 60 40 60 40 60 40 60 40 60 mA
5313 tbl 22
6.42
16
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 2.5V +/-5%, Commercial and Industrial Temperature Ranges)
NOTES:
1. tF = 1/tCYC.
2. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.
3. Transition is measured ±200mV from steady-state.
4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
5. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is faster than tCLZ (device turn-on) at a given temperature and voltage. The specs
as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 2.625V) than tCHZ, which is a Max.
parameter (worse case at 70 deg. C, 2.375V)
6. 200MHz is for 71T75802 only.
200MHz
(6)
166MHz 150MHz 133MHz 100MHz
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tCYC Clock Cycle Time 5
____
6
____
6.7
____
7.5
____
10
____
ns
tF
(1)
Clock Frequency
____
200
____
166
____
150
____
133
____
100 MHz
tCH
(2)
Clock High Pulse Width 1.8
____
1.8
____
2.0
____
2.2
____
3.2
____
ns
tCL
(2)
Clock Low Pulse Width 1.8
____
1.8
____
2.0
____
2.2
____
3.2
____
ns
Output Parameters
tCD Clock High to Valid Data
____
3.2
____
3.5
____
3.8
____
4.2
____
5ns
tCDC Clock High to Data Change 1.0
____
1.0
____
1.5
____
1.5
____
1.5
____
ns
tCLZ
(3,4,5)
Clock High to Output Active 1.0
____
1.0
____
1.5
____
1.5
____
1.5
____
ns
tCHZ
(3,4,5)
Clock High to Data High-Z 1.0 3 1.0 3 1.5 3 1.5 3 1.5 3.3 ns
tOE Output Enable Access Time
____
3.2
____
3.5
____
3.8
____
4.2
____
5ns
tOLZ
(3,4)
Output Enable Low to Data Active 0
____
0
____
0
____
0
____
0
____
ns
tOHZ
(3,4)
Output Enable High to Data High-Z
____
3.2
____
3.5
____
3.8
____
4.2
____
5ns
Set Up Times
tSE Clock Enable Setup Time 1.4
____
1.5
____
1.5
____
1.7
____
2.0
____
ns
tSA Address Setup Time 1.4
____
1.5
____
1.5
____
1.7
____
2.0
____
ns
tSD Data In Setup Time 1.4
____
1.5
____
1.5
____
1.7
____
2.0
____
ns
tSW Read/Write (R/W) Setup Time 1.4
____
1.5
____
1.5
____
1.7
____
2.0
____
ns
tSADV Advance/Load (ADV /LD) Setup Time 1.4
____
1.5
____
1.5
____
1.7
____
2.0
____
ns
tSC Chip Enable/Select Setup Time 1.4
____
1.5
____
1.5
____
1.7
____
2.0
____
ns
tSB Byte Write Enable (BWx) Setup Time 1.4
____
1.5
____
1.5
____
1.7
____
2.0
____
ns
Hold Times
tHE Clock Enable Hold Time 0.4
____
0.5
____
0.5
____
0.5
____
0.5
____
ns
tHA Address Hold Time 0.4
____
0.5
____
0.5
____
0.5
____
0.5
____
ns
tHD Data In Hold Time 0.4
____
0.5
____
0.5
____
0.5
____
0.5
____
ns
tHW Read/Write (R/W) Hold Time 0.4
____
0.5
____
0.5
____
0.5
____
0.5
____
ns
tHADV Advance/Load (ADV /LD) Hold Time 0.4
____
0.5
____
0.5
____
0.5
____
0.5
____
ns
tHC Chip Enable/Select Hold Time 0.4
____
0.5
____
0.5
____
0.5
____
0.5
____
ns
tHB Byte Write Enable (BWx) Hold Time 0.4
____
0.5
____
0.5
____
0.5
____
0.5
____
ns
5313 tbl 24
6.42
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
17
Timing Waveform of Read Cycle(1,2,3,4)
NOTES:
1. Q (A1) represents the first output from the external address A1. Q (A2) represents the first output from the external address A2; Q (A2+1) represents the next output data in the burst sequence
of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control
are loaded into the SRAM.
ADV/LD
(CEN high, eliminates
current L-H clock edge)
t
CD
t
HADV
Pipeline
Read
(Burst Wraps around
to initial state)
t
CDC
t
CLZ
t
CHZ
t
CD
t
CDC
R/W
CLK
CEN
ADDRESS
OE
DATA
OUT
t
HE
t
SE
A1 A2
t
CH
t
CL
t
CYC
t
SADV
t
HW
t
SW
t
HA
t
SA
t
HC
t
SC
Burst Pipeline Read
Pipeline
Read
BW
1
- BW
4
5313 drw 06
CE
1
, CE
2(2)
Q(A
2+3
)Q(A
2
)
Q(A
2+2
)
Q(A
2+2
)
Q(A
2+1
)
Q(A
2
)
Q(A
1
)
6.42
18
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
NOTES:
1. D (A1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence of
the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control
are loaded into the SRAM.
5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two
cycles before the actual data is presented to the SRAM.
Timing Waveform of Write Cycles(1,2,3,4,5)
t
HE
t
SE
R/W
A
1
A
2
CLK
CEN
ADV/LD
ADDRESS
OE
DATA
IN
t
HD
t
SD
t
CH
t
CL
t
CYC
t
HADV
t
SADV
t
HW
t
SW
t
HA
t
SA
t
HC
t
SC
Burst Pipeline Write
Pipeline
Write
Pipeline
Write
t
HB
t
SB
(Burst Wraps around
to initial state)
t
HD
t
SD
(CEN high, eliminates
current L-H clock edge)
(2)
CE1, CE2
D(A2+2)D(A2+3)
D(A1)D(A2)D(A2)
5313 drw 07
B
W1 - BW4
D(A2+1)
6.42
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
19
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two
cycles before the actual data is presented to the SRAM.
Timing Waveform of Combined Read and Write Cycles(1,2,3)
tHE
tSE
R/W
A1A2
CLK
CEN
ADV/LD
ADDRESS
CE1, CE2(2)
BW1 - BW4
DATAOUT Q(A3)
Q(A1)Q(A6)Q(A7)
tCD
Read
tCHZ
5313 drw 08
Write
tCLZ
D(A2)D(A4)
tCDC
D(A5)
Write
tCH tCL
tCYC
tHW
tSW
tHA
tSA
A4
A3
tHC
tSC
tSD tHD
tHADV
tSADV
A6A7A8
A5A9
DATAIN
tHB
tSB
OE
Read
Read
6.42
20
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propagating into the SRAM. The part will behave as if the L-H clock transition did not occur. All internal registers
in the SRAM will retain their previous state.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two
cycles before the actual data is presented to the SRAM.
Timing Waveform of CEN Oper ation(1,2,3,4)
t
HE
t
SE
A
1
A
2
CLK
ADDRESS
DATA
OUT
Q(A
3
)
t
CD
t
CLZ
t
CHZ
t
CH
t
CL
t
CYC
t
HC
t
SC
D(A
2
)
t
SD
t
HD
t
CDC
A
4
A
5
t
HADV
tSADV
t
HW
t
SW
t
HA
t
SA
A
3
t
HB
t
SB
DATA
IN
Q(A
1
)
5313 drw 09
Q(A
1
)
B(A
2
)
R/W
CEN
ADV/LD
CE
1
, CE
2(2)
BW
1
- BW
4
OE
6.42
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
21
Timing Waveform of CS Operation(1,2,3,4)
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3.
2CE
2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propagating into the SRAM. The part will behave as if the L-H clock transition did not occur. All internal registers
in the SRAM will retain their previous state.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two
cycles before the actual data is presented to the SRAM.
A1
CLK
ADDRESS
DATA
Out
Q(A
1
)
t
CD
t
CLZ
t
CHZ
t
CDC
t
CH
t
CL
t
CYC
t
HC
t
SC
t
SD
t
HD
A
5
A
3
t
SB
DATA
In
t
HE
t
SE
A
2
t
HA
t
SA
A
4
t
HW
t
SW
t
HB
t
HADV
t
SADV
5313 drw 10
Q(A
2
)Q(A
4
)
D(A
3
)
R/W
CEN
ADV/LD
CE
1
, CE
2(2)
BW
1
- BW
4
OE
6.42
22
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
JTAG Interface Specification
TCK
Device Inputs
(1)
/
TDI/TMS
Device Outputs
(2)
/
TDO
TRST
(3)
tJCD
tJDC
t
JRST
tJS tJH
tJCYC
t
JRSR
t
JF
t
JCL
t
JR
t
JCH
M5313 drw 01
x
Symbol Parameter Min. Max. Units
t
JCYC
JTAG Clock Input Period 100
____
ns
t
JCH
JTAG Clock HIGH 40
____
ns
t
JCL
JTAG Clock Low 40
____
ns
t
JR
JTAG Clock Rise Time
____
5
(1)
ns
t
JF
JTAG Clock Fall Time
____
5
(1)
ns
t
JRST
JTAG Reset 50
____
ns
t
JRSR
JTAG Reset Recovery 50
____
ns
t
JCD
J TA G D ata Ou tp ut
____
20 ns
t
JDC
JTA G Data Outp ut Ho ld 0
____
ns
t
JS
JTAG Setup 25
____
ns
t
JH
JTAG Hold 25
____
ns
I5313 tbl 01
Reg iste r Nam e Bi t S ize
Ins tructio n (IR) 4
Byp ass (BYR) 1
J TA G Id e n tifi c ati o n (J IDR) 32
Bound ary Scan (BSR) Note (1)
I5 313 tb l 03
NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
2. Device outputs = All device outputs except TDO.
3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
NOTE:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
by contacting your local IDT sales representative.
JTAG AC Electrical
Characteristics(1,2,3,4)
Scan Register Sizes
NOTES:
1. Guaranteed by design.
2. AC Test Load (Fig. 1) on external output signals.
3. Refer to AC Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed
specified in this datasheet.
6.42
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
23
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
Instruction Field Value Description
Revision Number (31:28) 0x2 Reserved for version number.
IDT De vi ce ID (27: 12) 0x 220, 0x222 De fines IDT p art numb e r 71T75602 and 71T75802, re sp e ctive ly.
IDT JEDEC ID (11:1) 0x33 Allows unique identifi cation of device vendor as IDT.
ID Register Indicator Bit (Bit 0) 1 Indicates the presenc e of an ID register.
I5 3 13 tb l 02
JTAG Identification Register Definitions
Instruction Description OPCODE
EXTEST Forces contents of the boundary scan cells onto the device outputs
(1)
.
Places the boundary scan register (BSR) between TDI and TDO. 0000
SAMPLE/PRELOAD
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs
(2)
and outputs
(1)
to be captured
in the b oundary sc an c ells and shifte d se rially thro ug h TDO. PRELOAD
allows data to be input serially into the bo undary scan cells via the TDI.
0001
DEVICE_ID Loads the JTAG ID register (JIDR) with the vendor ID code and places
the register between TDI and TDO. 0010
HIGHZ Places the bypass register (BYR) be tween TDI and TDO. Forces all
device o utput drivers to a High-Z state. 0011
RESERVED
Several combinations are reserved. Do not use codes other than those
identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,
VALIDATE and BY PASS instructio ns.
0100
RESERVED 0101
RESERVED 0110
RESERVED 0111
CLAMP Uses BYR. Forces contents of the bound ary scan cells onto the device
outputs. Places the bypass registe r (BYR) between TDI and TDO. 1000
RESERVED
Same as above.
1001
RESERVED 1010
RESERVED 1011
RESERVED 1100
VALIDATE Automatically loaded into the instruction register whenever the TAP
controller passes through the CAPTURE-IR state. The lower two bits '01'
are mand ated by the IEEE std. 1149.1 specification. 1101
RESERVED Same as above. 1110
BYPASS The BYPASS instruction is used to truncate the boundary scan register
as a sing le b it in le ng th. 1111
I53 13 tbl 04
Available JTAG Instructions
6.42
24
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Timing Waveform of OE Operation(1)
NOTE:
1. A read operation is assumed to be in progress.
Ordering Information
OE
DATA
OUT
t
OHZ
t
OLZ
t
OE
Valid
5313 drw 11
,
Orderable Part Information
Speed
(ns) Orderable Part ID Pkg.
Code Pkg.
Type Temp.
Grade
100 71T75602S100BG BG119 PBGA C
71T75602S100BG8 BG119 PBGA C
71T75602S100BGG BGG119 PBGA C
71T75602S100BGG8 BGG119 PBGA C
71T75602S100BGGI BGG119 PBGA I
71T75602S100BGGI8 BGG119 PBGA I
71T75602S100BGI BG119 PBGA I
71T75602S100BGI8 BG119 PBGA I
5313 tbl 27
Speed
(ns) Orderable Part ID Pkg.
Code Pkg.
Type Temp.
Grade
100 71T75802S100BG BG119 PBGA C
71T75802S100BG8 BG119 PBGA C
71T75802S100BGGI BGG119 PBGA I
71T75802S100BGGI8 BGG119 PBGA I
71T75802S100BGI BG119 PBGA I
71T75802S100BGI8 BG119 PBGA I
5313 tbl 28
100-Pin Plastic Thin Quad Flatpack (PKG100)
119 Ball Grid Array (BGG119)
S
Power
XX
Speed
XX
Package
XXXX
200*
166
150
133
100
Clock Frequency in Megahertz
5313 drw 12a
Device
Type
71T75602
71T75802 512Kx36 Pipelined ZBT SRAM
1Mx18 Pipelined ZBT SRAM
PF
BG
X
Blank
ICommercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
8Tray
Tape and Reel
X
* 200MHz available Only for IDT71T75802
X
GGreen
6.42
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
25
Orderable Part Information (con’t)
Speed
(ns) Orde ra ble Part ID Pkg.
Code Pkg.
Type Temp.
Grade
133 71T75802S133BG BG119 PBGA C
71T75802S133BG8 BG119 PBGA C
71T75802S133BGG BGG119 PBGA C
71T75802S133BGG8 BGG119 PBGA C
71T75802S133BGGI BGG119 PBGA I
71T75802S133BGGI8 BGG119 PBGA I
71T75802S133BGI BG119 PBGA I
71T75802S133BGI8 BG119 PBGA I
71T75802S133PFG PKG100 TQFP C
71T75802S133PFG8 PKG100 TQFP C
71T75802S133PFGI PKG100 TQFP I
71T75802S133PFGI8 PKG100 TQFP I
150 71T75802S150BG BG119 PBGA C
71T75802S150BG8 BG119 PBGA C
71T75802S150BGG BGG119 PBGA C
71T75802S150BGG8 BGG119 PBGA C
71T75802S150BGGI BGG119 PBGA I
71T75802S150BGGI8 BGG119 PBGA I
71T75802S150BGI BG119 PBGA I
71T75802S150BGI8 BG119 PBGA I
71T75802S150PFG PKG100 TQFP C
71T75802S150PFG8 PKG100 TQFP C
166 71T75802S166BG BG119 PBGA C
71T75802S166BG8 BG119 PBGA C
71T75802S166BGG BGG119 PBGA C
71T75802S166BGG8 BGG119 PBGA C
71T75802S166BGGI BGG119 PBGA I
71T75802S166BGGI8 BGG119 PBGA I
71T75802S166BGI BG119 PBGA I
71T75802S166BGI8 BG119 PBGA I
71T75802S166PFG PKG100 TQFP C
71T75802S166PFG8 PKG100 TQFP C
71T75802S166PFGI PKG100 TQFP I
71T75802S166PFGI8 PKG100 TQFP I
200 71T75802S200BG BG119 PBGA C
71T75802S200BG8 BG119 PBGA C
71T75802S200BGG BGG119 PBGA C
71T75802S200BGG8 BGG119 PBGA C
71T75802S200BGI BG119 PBGA I
71T75802S200BGI8 BG119 PBGA I
71T75802S200PFG PKG100 TQFP C
71T75802S200PFG8 PKG100 TQFP C
71T75802S200PFGI PKG100 TQFP I
71T75802S200PFGI8 PKG100 TQFP I
5313 tbl 28a
Speed
(ns) Orderable Part ID Pkg.
Code Pkg.
Type Temp.
Grade
133 71T75602S133BG BG119 PBGA C
71T75602S133BG8 BG119 PBGA C
71T75602S133BGG BGG119 PBGA C
71T75602S133BGG8 BGG119 PBGA C
71T75602S133BGGI BGG119 PBGA I
71T75602S133BGGI8 BGG119 PBGA I
71T75602S133BGI BG119 PBGA I
71T75602S133BGI8 BG119 PBGA I
71T75602S133PFG PKG100 TQFP C
71T75602S133PFG8 PKG100 TQFP C
71T75602S133PFGI PKG100 TQFP I
71T75602S133PFGI8 PKG100 TQFP I
150 71T75602S150BG BG119 PBGA C
71T75602S150BG8 BG119 PBGA C
71T75602S150BGG BGG119 PBGA C
71T75602S150BGG8 BGG119 PBGA C
71T75602S150BGGI BGG119 PBGA I
71T75602S150BGGI8 BGG119 PBGA I
71T75602S150BGI BG119 PBGA I
71T75602S150BGI8 BG119 PBGA I
71T75602S150PFG PKG100 TQFP C
71T75602S150PFG8 PKG100 TQFP C
71T75602S150PFGI PKG100 TQFP I
71T75602S150PFGI8 PKG100 TQFP I
166 71T75602S166BG BG119 PBGA C
71T75602S166BG8 BG119 PBGA C
71T75602S166BGG BGG119 PBGA C
71T75602S166BGG8 BGG119 PBGA C
71T75602S166BGGI BGG119 PBGA I
71T75602S166BGGI8 BGG119 PBGA I
71T75602S166BGI BG119 PBGA I
71T75602S166BGI8 BG119 PBGA I
71T75602S166PFG PKG100 TQFP C
71T75602S166PFG8 PKG100 TQFP C
71T75602S166PFGI PKG100 TQFP I
71T75602S166PFGI8 PKG100 TQFP I
5313 t bl 27a
6.42
26
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Datasheet Document History
Rev Date Pages Description
0 04/20/00 Created New Datasheet
1 05/25/00 Pg.1,14,15,25 Added 166MHz speed grade offering
Pg. 1,2,14 Corrected error in ZZ Sleep Mode
Pg. 23 AddBQ165 Package Diagram Outline
Pg. 24 Corrected 119BGA Package Diagram Outline.
Pg. 25 Corrected topmark on ordering information
2 08/23/01 Pg. 1,2,24 Removed reference of BQ165 Package
Pg. 7 Removed page of the 165 BGA pin configuration
Pg. 23 Removed page of the 165 BGA package diagram outline
3 10/16/01 Pg. 6 Corrected 3.3V to 2.5V in Note 2
10/29/01 Pg. 13 Improved DC Electrical characteristics-parameters improved: Icc, ISB2, ISB3, IZZ.
4 12/21/01 Pg. 4-6 Added clarification to JTAG pins, allow for NC. Added 36M address pin locations.
Pg. 14 Revised 166MHz tCDC(min), tCLZ(min) and tCHZ(min) to 1.0ns
5 06/07/02 Pg. 1-3,6,13,20,21 Added complete JTAG functionality.
Pg. 2,13 Added notes for ZZ pin internal pulldown and ZZ leakage current.
Pg. 13,14,24 Added 200MHz and 225MHz to DC and AC Electrical Characteristics. Updated supply current for
Idd, ISB1, ISB3 and Izz.
6 11/19/02 Pg.1-24 Changed datasheet from Advanced Information to final release.
Pg.13 Updated DC Electrical characteristics temperature and voltage range table.
7 05/23/03 Pg.4,5,13,14,24 Added I-temp to the datasheet.
Pg.5 Updated 165 BGA Capacitance table.
8 04/01/04 Pg. 1 Updated logo with new design.
Pg. 4,5 Clarified ambient and case operating temperatures.
Pg. 6 Updated pin I/O number order for the 119 BGA.
Pg. 23 Updated 119BGA Package Diagram Drawing.
9 10/01/08 Pg. 1,13,14,24 Deleted 225MHz part, added 200MHz Industrial grade and added green packages. Updated the
ordering information by removing the “IDT” notation.
10 04/04/12 Pg. 2,22 Updated text on Page 2 last paragraph. Added Note to ordering information and updated to include
tube or tray and tape & reel.
11 10/04/17 Pg. 1 & 26 Updated IDT logo from Trademark to Registered
Pg. 1- 4 In Features: Added text: "Green parts available, see Ordering Information"
Moved the 512Kx36 FBD from page 3 to page 1, moved the 1Mx18 FBD from page 3 to page 2,
moved the Pin Description Summary from page 1 to page 3 and moved the Pin Definitions from
page 2 to page 4 in accordance with our standard datasheet format
Pg. 5 & 6 Updated the TQFP pin configurations for the 512kx36 and 1Mx18 by rotating package pin labels
and pin numbers 90 degrees counter clockwise, added IDT logo & in accordance with the
packaging code, changed the PK100 designation to PKG100 , changed the text to be in alignment
with new diagram marking specs
Pg. 6 Removed fBGA capacitance table as this package is no longer offered for this device
Pg. 12 Removed “? = don’t know” from Burst Write Operation footnote 1 as it does not apply to this table
Pg. 15 Updated DC Chars table added footnote 4 & reference 4 for the 512K x 36, 119 BGA 200Mhz
speed offered only for the 71T75802 device
Pg. 16 Updated AC Chars table added footnote 6 & reference 6 for the 1M x 18, 119 BGA 200Mhz
speed offered only for the 71T75802 device
Pg. 24 Ordering Information updated to Tray and Green indicator
Updated package codes TQFP to PKG100 and BGA to BGG119
Pg. 24-25 Added Orderable Part Information from idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc. All brands or products are the trademarks or registered trademarks of their respective owners.
ZBT® and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Rd 800-345-7015 or 408-284-8200 sramhelp@idt.com
San Jose, CA 95138 fax: 408-284-2775 408-284-4532
www.idt.com