POWER MANAGEMENT
1www.semtech.com
SC1112
Triple Low Dropout
Regulator Controllers
Features
Applications
Revision: August 30, 2006
Typical Application Circuit
Description
The SC1112 was designed for the latest high speed
motherboards. It includes three low dropout regulator con-
trollers. The controllers provide the power for the system
AGTL bus Termination Voltage, Chipset, and clock circuitry.
An adjustable controller with a 1.2V reference is available,
while two selectable outputs are provided for the VTT
(1.25 V or 1.5V, SC1112) or (1.2V or 1.5V, SC1112A)
and the AGP (1.5V or 3.3V). The SC1112 low dropout
regulators are designed to track the 3.3V power supply
as the VTTIN supply is cycled On and Off. A latched short
circuit protection is also available for the VTT output.
Other features include an integrated charge pump that
provides adequate gate drives for the external MOSFETs,
and a capacitive programable delay for the power good
signal.
Triple linear controllers
Selectable and adjustable output voltages
LDOs track input voltage within 200mV (Function of
the MOSFETs used) until regulation
Integrated charge pump
Programmable power good delay signal
Latched over current protection (VTT)
Pb-free package available, fully WEEE and RoHS
compliant
Pentium® III Motherboards
Triple power supplies
Q1
RA
SC1112/A
PWRGD
DELAY
5VSTBY
VTTSEL
AGPSEL
GND
FC
CAP+
CAP- VTTGATE
VTTSEN
AGPGATE
AGPSEN
ADJGATE
ADJSEN
VTTIN
A
DJ
Q2 C14
330u
C12
330u
AGP SELECT Signal
C8
330u
AGP
C17
0.1u
RB
C16
330u
C3
0.1u
C1
10u
C18
330u
VTT SELECT Signal
POWER GOOD
C5
22n
C10
1u
C13
0.1u
+3.3V
R1
1K
+5V STBY
Q3
C11
0.1u
C9
0.1u
VTT
C6
330u
VTT
C19
330u
C2
22006 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1112
Electrical Characteristics
Absolute Maximum Ratings
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DNGotNESPGA 5ot3.0-V
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CIOS
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CIOS
POSST θ
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Unless specified: 5VSTBY=4.75V to 5.25V; VTTIN=3.3V; TA = 25°C
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Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied.
3
2006 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1112
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WOL=LESTTV,A2ot0=671.1002.1422.1V
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TTV
52.1
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WOL=LESTTV,A2ot0=522.1052.1572.1
TTV
5.1
I
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HGIH=LESTTV,A2ot0=074.1005.1035.1V
PGAegatloVtuptuOPGA
5.1
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WOL=LESPGA,A2ot0=074.1005.1035.1V
PGA
3.3
I
O
HGIH=LESPGA,A2ot0=432.3003.3V
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A2ot0=%2-)BR/AR+1(*2.1%2+V
tnerruCsaiBNESTTV
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saibI
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saibI
NESTTV
15Aµ
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NESPGA
011051071Aµ
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15Aµ
tnerruCetaGTTVecruosI
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V0.3=etagV,V57.4=YBTSV5005Aµ
knisI
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005Aµ
tnerruCetaGPGAecruosI
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knisI
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Electrical Characteristics (Cont.)
Unless specified: 5VSTBY=4.75V to 5.25V; VTTIN=3.3V; TA = 25°C
Notes:
(1) All electrical characteristics are for the application circuit on page 19.
(2) Guaranteed by design
(3) Tracking Difference is defined as the delta between 3.3V Vin and the VTT, AGP, ADJ output voltages during the linear ramp up until
regulation is achieved. The Tracking Voltage difference might vary depending on MOSFETs Rdson, and Load Conditions.
(4) During power up, an internal short circuit glitch timer will start once the VTT Input Voltage exceeds the VTTINTH (1.5V). During the glitch
timer immunity time, determined by the Delay capacitor (Delay time is approximately equal to (Cdelay*SCTH)/ISC), the short circuit
protection is disabled to allow VTT output to rise above the trip threshold (0.7V). If the VTT output has not risen above the trip
threshold after the immunity time has elapsed, the VTT output is latched off and will only be enabled again if either the VTT input
voltage or the 5VSTBY is cycled.
(5) PWRGD pin is kept low during the power up, until the VTT output has reached its PGtd1.2 or PGtd1.5 level. At that time the PWRGD
source current IPG (20uA) is enabled and will start charging the external PWRGD delay capacitor connected to the DELAY pin. Once the
capacitor is charged above the PGDelay_TH (1.5V), the PWRGD pin is released from ground.
42006 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1112
VTTGATE
VTTIN=1.5V
The delay capacitor does not
begin charging until VTTIN has
reached 1.5V and VTT is above
the powergood threshold of
1.08V.
Once DELAY reaches 1.5V,
the PWRGD signal goes high.
VTTGATE initially turns on
hard, until VTT reaches
regulation. Then VTTGATE
drops to its normal regulating
level.
PWRGD
DELAY
VTT
VTTIN
DELAY=1.5V
NORMAL STARTUP CONDITION
The delay capacitor does not
begin charging until VTTIN has
reached 1.5V and VTT is below
the short circuit threshold of
0.7V.
VTTGATE initially turns on hard
and is latched off when DELAY
reaches 1.5V and VTT is below
0.7V
DELAY
VTT
PWRGD
VTTIN
VTTGATE
VTTIN=1.5V
SHORT-CIRCUIT STARTUP
DELAY=1.5V
Timing Diagrams
5
2006 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1112
PWRGD
DELAY=1.5V
DELAY
VTT
SHORT-CIRCUIT DURING NORMAL
OPERATION
Once VTT drops out of
regulation, VTTGATE turns on
harder to try and raise VTT.
When VTT drops below 1.08V,
the delay capacitor is
discharged and PWRGD goes
low. When VTT drops below
0.7V, the delay capacitor
begins charging.
If VTT is still below 0.7V when
DELAY reaches 1.5V,
VTTGATE is latched off.
VTTIN
VTT=0.7V
VTT=1.08V
VTTGATE
VTT=0.7V
PWRGD
VTT=1.08V
DELAY
SHORT-CIRCUIT AND RECOVERY
DURING NORMAL OPERATION
VTT
Once VTT drops out of
regulation, VTTGATE turns on
harder to try and raise VTT.
When VTT drops below 1.08V,
the delay capacitor is discharged
and PWRGD goes low. When
VTT drops below 0.7V, the delay
capacitor begins charging.
If VTT recovers above 0.7V
before DELAY reaches 1.5V,
DELAY is again discharged.
If VTT reaches 1.08V the delay
capacitor begins charging and
normal operation continues.
VTTIN
VTT=1.08V
VTTGATE
DELAY=1.5V
Timing Diagrams (Cont.)
62006 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1112
Pin Configuration Ordering Information
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RTS2111CS
61-OSC°521ot°0TRTS2111CS
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RTSA2111CS
RTST2111CS
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RTSTA2111CS
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Notes:
(1) Only available in tape and reel packaging. A reel contains
2500 devices.
(2) Part Number (SO-16): SC1112STR and SC1112STRT =
1.25V and SC1112ASTR = 1.2V.
Part Number (TSSOP-16): SC1112TSTR = 1.25V and
SC1112ATSTR = 1.2V.
(3) Pb-free product. This product is fully WEEE and RoHS
compliant.
Top View
(16-Pin SOIC or TSSOP)
PWRGD
5VSTBY
DELAY
VTTSEL
AGPSEL
ADJGATE
ADJSEN
CAP+
GND
VTTIN
VTTGATE
AGPGATE
VTTSEN
AGPSEN
FC
CAP-
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
7
2006 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1112
Pin Descriptions
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3YALED TTVfogalFdooGrewoPehtrofyaledehtmargorplliwDNGotnipsihtmorfroticapacA
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4LESTTV VX2.1=TTV,WOL=LESTTV:egatlovtuptuoTTVehtsmargorptahtlangisLTT
V5.1=TTV,HGIH=LESTTV
5LESPGA V5.1=PGA,WOL=LESPGA:egatlovtuptuoPGAehtsmargorptahtlangisLTT
V3.3=PGA,HGIH=LESPGA
6ETAGJDA.PGAroftuptuoevirdetaG
7NESJDA.JDAroftupniesneS
8-PAC.roticapactsoobotnoitcennocevitageN
9+PAC.roticapactsoobotnoitcennocevitisoP
01CF .DNGotnipsihtmorfdetcennocebdluohspmupegrahclanretniehtrofroticapacretliF
11NESPGA.PGAroftupniesneS
21ETAGPGA.PGAroftuptuoevirdetaG
31NESTTV.TTVroftupniesneS
41ETAGTTV.TTVroftuptuoevirdetaG
51NITTV.niV3.3ehtotdetcennocenilesnestiucrictrohS
61DNG.dnuorG
NOTE: (1) All logic level inputs and outputs are open collector TTL compatible.
82006 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1112
Block Diagram
Vref
1.5V
1.08V
+
DELAY
ADJGATE
VTTSEN
1.5V
Bandgap
_
_
Vref
ChargePump
1.2V
Disable3.3
+ _
AGPSEN
0.7V
Disable1.5
5VSTBY
VTTSEN
+
S
_
VTTGATE
GND
1.5V
_
+
AGPGATE
0.7V
_
+
VTTSEL
_
1.5V
+
+
_
R
Pwrgd
Threshold
AGPSEL
+
-
VTTIN
+
1.2V
FC
_
Q
CAP-
1.35V
CAP+
FC
PWRGD
+
+
Disable1.2
Oscillator
1.2V
Disable1.5
ADJSEN
Reference
FC
_
+
_
9
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POWER MANAGEMENT
SC1112
Typical Characteristics
1.4995
1.5000
1.5005
1.5010
1.5015
1.5020
1.5025
1.5030
1.5035
0 10203040506070
Ta (°C.)
VTT1.5 (V)
5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V
1.2445
1.2450
1.2455
1.2460
1.2465
1.2470
1.2475
1.2480
1.2485
0 10203040506070
Ta (°C.)
VTT1.2(V)
5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V
1.5015
1.5020
1.5025
1.5030
1.5035
1.5040
1.5045
1.5050
1.5055
0 10203040506070
Ta (°C.)
VTT1.5(V)
5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V
VTT(1.5V) Output Voltage @ Io = 0A vs Ta
VTT(1.25V) Output Voltage @ Io = 0A vs Ta
VTT Input Supply Threshold vs Ta
VTT(1.5V) Output Voltage @ Io = 2A vs Ta
1.2425
1.2430
1.2435
1.2440
1.2445
1.2450
1.2455
1.2460
1.2465
0 10203040506070
Ta (°C.)
VTT1.2(V)
5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V
VTT(1.5V) Output Voltage @ Io = 2A vs Ta
104
106
108
110
112
114
116
0 10203040506070
Ta (°C.)
IbiasVTTSEN (uA)
5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V
VTT Sense Bias current vs Ta
1.491
1.492
1.493
1.494
1.495
1.496
1.497
1.498
0 10203040506070
Ta (°C.)
VTTINTH(V)
5V Stby = 4.75V
5V Stby = 5.00V
5V Stby = 5.25V
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SC1112
Typical Characteristics (Cont.)
400
450
500
550
600
650
700
750
800
0 10203040506070
Ta (°C.)
IVTT_Gate(uA)
Source current
Sink current
VTT Gate Current @ Vgate = 3V, 5V Stby = 4.75V vs Ta
21.60
21.80
22.00
22.20
22.40
22.60
22.80
23.00
23.20
23.40
23.60
0 10203040506070
Ta (°C.)
ISC(uA)
5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V
VTT Short circuit Delay source current vs Ta
7.70
7.80
7.90
8.00
8.10
8.20
8.30
8.40
0 10203040506070
Ta (°C.)
SCtd(mS)
5V Stby = 4.75V
5V Stby = 5.00V
5V Stby = 5.25V
VTT Short circuit Delay Time (Cdelay = 0.1uF) vs Ta
1.465
1.470
1.475
1.480
1.485
1.490
1.495
1.500
1.505
1.510
1.515
0 10203040506070
Ta (°C.)
SCth(V)
5V Stby = 4.75V
5V Stby = 5.00V
5V Stby = 5.25V
VTT Short circuit Delay Timer Threshold vs Ta
11
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POWER MANAGEMENT
SC1112
7.70
7.80
7.90
8.00
8.10
8.20
8.30
8.40
0 10203040506070
Ta (°C.)
PGtd_1.25(mS)
5V Stby = 4.75V
5V Stby = 5.00V
5V Stby = 5.25V
7.70
7.80
7.90
8.00
8.10
8.20
8.30
8.40
0 10203040506070
Ta (°C.)
PGtd_1.5(mS)
5V Stby = 4.75V
5V Stby = 5.00V
5V Stby = 5.25V
21.40
21.60
21.80
22.00
22.20
22.40
22.60
22.80
23.00
23.20
23.40
23.60
0 10203040506070
Ta (°C.)
IPG(uA)
5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V
Typical Characteristics (Cont.)
1.080
1.082
1.084
1.086
1.088
1.090
1.092
1.094
1.096
1.098
0 10203040506070
Ta (°C.)
PGTH_1.25(V)
5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V
1.350
1.351
1.352
1.353
1.354
1.355
1.356
1.357
1.358
1.359
1.360
1.361
0 10203040506070
Ta (°C.)
PGTH_1.5 (V)
5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V
VTT (1.25V) Power Good Threshold vs Ta VTT (1.25V) Power Good Delay Time vs Ta
VTT (1.5V) Power Good Delay Time vs Ta
VTT Power Good Source current vs Ta
VTT (1.5V) Power Good Threshold vs Ta
122006 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1112
128
130
132
134
136
138
140
142
0 10203040506070
Ta (°C.)
IbiasAGPSEN (uA)
5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V
3.2820
3.2830
3.2840
3.2850
3.2860
3.2870
3.2880
3.2890
3.2900
0 10203040506070
Ta (°C.)
AGP3.3(V)
5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V
3.2820
3.2830
3.2840
3.2850
3.2860
3.2870
3.2880
3.2890
3.2900
0 10203040506070
Ta (°C.)
AGP3.3(V)
5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V
Typical Characteristics (Cont.)
1.5005
1.5010
1.5015
1.5020
1.5025
1.5030
1.5035
1.5040
1.5045
1.5050
1.5055
0 10203040506070
Ta (°C.)
AGP1.5(V)
5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V
AGP (1.5V) Output Voltage @ Io = 0A vs Ta
AGP (3.3V) Output Voltage @ Io = 0A vs Ta
AGP Sense Bias current vs Ta
1.4985
1.4990
1.4995
1.5000
1.5005
1.5010
1.5015
1.5020
1.5025
1.5030
1.5035
0 10203040506070
Ta (°C.)
AGP1.5(V)
5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V
AGP (1.5V) Output Voltage @ Io = 2A vs Ta
AGP (3.3V) Output Voltage @ Io = 2A vs Ta
600
650
700
750
800
850
900
0 10203040506070
Ta (°C.)
IAGP_Gate(uA)
Sink current
Source current
AGP Gate Current @ Vgate = 3V, 5V Stby = 4.75 vs Ta
13
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SC1112
1.1915
1.1920
1.1925
1.1930
1.1935
1.1940
1.1945
1.1950
1.1955
0 10203040506070
Ta (°C.)
ADJ1.2(V)
5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V
600
650
700
750
800
850
900
0 1020304050607
0
Ta (°C.)
IADJ_Gate(uA)
Sink current
Source current
Typical Characteristics (Cont.)
ADJ (1.2V) Output Voltage @ Io = 0A vs Ta
1.1950
1.1960
1.1970
1.1980
1.1990
1.2000
1.2010
1.2020
0 10203040506070
Ta (°C.)
ADJ1.2(V)
5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V
ADJ (1.2V) Output Voltage @ Io = 2A vs Ta
ADJ Sense Bias current vs Ta
150
170
190
210
230
250
270
290
310
330
350
0 10203040506070
Ta (°C.)
IbiasADJSEN (uA)
5V Stby = 4.75V
5V Stby = 5.00V
5V Stby = 5.25V
ADJ Gate Current @ Vgate = 3V, 5V Stby = 4.75V vs Ta
142006 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1112
100.0E-3
110.0E-3
120.0E-3
130.0E-3
140.0E-3
150.0E-3
160.0E-3
170.0E-3
180.0E-3
0 10203040506070
Ta (°C.)
Load Regulation(%)
VTT 1.25V
AGP 1.25V
000.0E+0
20.0E-3
40.0E-3
60.0E-3
80.0E-3
100.0E-3
120.0E-3
140.0E-3
160.0E-3
0 10203040506070
Ta (°C.)
Line Regulation(%)
VTT 1.25V
AGP 1.25V
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
0 10203040506070
Ta (°C.)
Output Select Threshold (V)
VTTSEL
AGPSEL
5.50
5.70
5.90
6.10
6.30
6.50
6.70
6.90
7.10
7.30
7.50
0 10203040506070
Ta (°C.)
I5vstby (mA)
5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V
9.21
9.22
9.23
9.24
9.25
9.26
9.27
9.28
9.29
9.30
9.31
9.32
0 10203040506070
Ta (°C.)
V Charge Pump(V)
V Charge Pump
345
350
355
360
365
370
375
0 10203040506070
Ta (°C.)
Charge Pump Frequency (kHz)
Charge Pump Frequency
Typical Characteristics (Cont.)
I 5V Stby vs Ta
Line Regulation VTTIN = 3.13V to 3.47V Io = 2A vs Ta
Charge Pump Output Voltage vs Ta Charge Pump Frequency vs Ta
Load Regulation VTTIN = 3.3V Io = 0 to 2A vs Ta
Output Select Threshold vs Ta
15
2006 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1112
Typical Gain & Phase Margin
SC1112 Gain / Phase VTT = 1.25V @ 2A
-30
-20
-10
0
10
20
30
40
50
60
10 100 1000 10000 100000 1000000
Freq (Hz)
Gain (dB)
0
20
40
60
80
100
120
140
160
180
200
Phase (deg)
Gain
Phase (deg)
Gain
Phase
SC1112 Gain / Phase VTT = 1.5V @ 2A
-30
-20
-10
0
10
20
30
40
50
60
10 100 1000 10000 100000 1000000
Freq (Hz)
Gain (dB)
0
20
40
60
80
100
120
140
160
180
200
Phase (deg)
Gain
Phase (deg)
Gain
Phase
SC1112 Gain / Phase AGP = 1.5V @ 2A
-20
-10
0
10
20
30
40
50
10 100 1000 10000 100000 1000000
Freq (Hz)
Gain (dB)
0
20
40
60
80
100
120
140
160
180
200
Phase (deg)
Gain
Phase (deg)
Gain
Phase
SC1112 Gain / Phase ADJ = 1.2V @ 2A
-30
-20
-10
0
10
20
30
40
50
10 100 1000 10000 100000 1000000
Freq (Hz)
Gain (dB)
0
20
40
60
80
100
120
140
160
180
200
Phase (deg)
Gain
Phase (deg)
Gain
Phase
162006 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1112
Theory Of Operation
The SC1112 was designed for the latest high speed mother
boards requiring a controlled power up sequencing of
the Outputs, and a programmable delay for the Power
good signal.
Three Linear controllers have been incorporated into the
SC1112. The VTT output can be programmed to either a
1.250V or a 1.500V by applying a LOW or a HIGH control
signal to the VTTSEL pin. AGP output can also be pro-
grammed via AGPSEL pin to a 1.50V or a 3.30V. The
SC1112 also provides an Adjustable output which utilizes
a resistive voltage divider.
The +5VSTBY supply will power the internal Reference,
Charge Pump, Oscillator, and the Fet controllers. After
the +5VSTBY has been established, LDO outputs will track
the VTTIN (3.30V) supply as it is applied.
An external capacitor connected to the Delay pin will pro-
gram the VTT short circuit delay time (SCtd), and the PWRGD
delay time (PGtd).
During power up, an internal short circuit glitch timer will
start once the VTT Input Voltage exceeds the VTTINTH (1.5V).
During the glitch timer immunity time, determined by the
Delay capacitor (Delay time is approximately equal to
(Cdelay*SCTH)/ISC), the short circuit protection is disabled
to allow VTT output to rise above the trip threshold (0.7V).
If the VTT output has not risen above the trip threshold
after the immunity time has elapsed, the VTT output is
latched off and will only be enabled again if either the VTT
input voltage or the 5VSTBY is cycled.
PWRGD pin is kept low during the power up, until the VTT
output has reached its PGtd1.25 or PGtd1.5 level. At that time
the PWRGD source current IPG (20uA) is enabled and will
start charging the external PWRGD delay capacitor
connected to the DELAY pin. Once the capacitor is charged
above the PGDelay_TH (1.5V), the PWRGD pin is released from
ground. A detailed timing diagram is shown on pages 4 to
5.
Also included is an overcurrent protection circuit that
monitors the VTT voltage. If the output voltage drops
below 700mV, as would occur during an overcurrent or
short condition, the device will pull the drive pin low and
latch off the output.
Fixed Output Voltage Options (VTT, AGP)
Please refer to the Application Circuit on Page 1. The VTT
and the AGP fixed output voltage can be programed from
a Control logic signal. Table below shows the possible
voltages:
LESTTVLESPGATTVPGA
00 V52.1V05.1
01 V52.1V03.3
10 V05.1V05.1
11 V05.1V03.3
Once the VTTSEL or the AGPSEL signal is established, an
internal resistive divider is used to compare the bandgap
reference voltage with the feedback output voltage. The
drive pin voltage is then adjusted to
maintain the output voltage set by the internal resistor
divider. Referring to the block diagram on page 8.
It is possible to adjust the output voltage of the VTT or
AGP, by applying an external resistor divider to the sense
pin (please refer to Figure 1 on Page 17). Since the sense
pin sinks a nominal 100µA, the resistor
values should be selected to allow 10mA to flow through
the divider. This will ensure that variations in this current
do not adversely affect output voltage regulation. Thus a
target value for R2 (maximum) can be calculated:
Ω≤ mA10
V
2R )FIXED(OUT
The output voltage can only be adjusted upwards from
the fixed output voltage, and can be calculated using the
following equation:
VoltsA1001R
2R
1R
1VV )FIXED(OUT)ADJUSTED(OUT µ•+
+•=
Applications Infomation
17
2006 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1112
Adjustable Output Voltage Option
The adjustable output voltage option does not have an
internal resistor divider. The adjust pin connects directly to
the inverting input of the error amplifier, and the
output voltage is set using external resistors (please
refer to Figure 2). In this case, the adjust pin sources a
nominal 0.5µA, so the resistor values should be selected
to allow 50µA to flow through the divider. Again, a target
value for RB (maximum) can be
calculated:
Ω≤ A50
V200.1
RB µ
The output voltage can be calculated as follows:
RAA5.0
RB
RA
1200.1VOUT •−
+•= µ
The maximum output voltage that can be obtained from
the adjustable option is determined by the input supply
voltage and the RDS(ON) and gate threshold voltage of the
external MOSFET. Assuming that the MOSFET gate
threshold voltage is sufficiently low for the output
voltage chosen and a worst-case drive voltage of 9V, VOUT(MAX)
is given by:
)MAX)(ON(DS)MAX(OUT)MIN()MAX(OUT RIVTTINV•−=
Applications Infomation (Cont.)
Figure 1: Adjusting The Output Voltage of VTT or AGP
Q1
SC1112
PWRGD
DELAY
5VSTBY
VTTSEL
AGPSEL
GND
FC
CAP+
CAP- VTTGATE
VTTSEN
AGPGATE
AGPSEN
ADJGATE
ADJSEN
VTTIN
C14
330u
AGP SELECT Signal
C8
330u
AGP
C17
0.1u
C16
330u
C3
0.1u
C1
10u
C18
330u
VTT SELECT Signal
+3.3V
+5V STBY
Q3
C9
0.1u
VTT
C19
330u
C2
R1
R2
RA
SC1
1
PWRGD
DELAY
5VSTBY
FC
CAP+
CAP-
ADJGATE
ADJSEN
Q2
C12
330u
RB
POWER GOOD
C5
22n
C10
1u
C13
0.1u
R1
1K
C11
0.1u
C6
330u
VTT
Figure 2
182006 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1112
Short Circuit Protection
The VTT short circuit protection feature of the SC1112
is implemented by using the RDS(ON) of the MOSFET. As
the output current increases, the regulation loop main-
tains the output voltage by turning the FET on more and
more. Eventually, as the RDS(ON) limit is reached, the MOS-
FET will be unable to turn on any further, and the output
voltage will start to fall. When the VTT output voltage falls
to approximately 700mV, the LDO controller is latched off,
setting output voltage to 0V. Power must be cycled to re-
set the latch.
To prevent false latching due to capacitor inrush currents
or low supply rails, the current limit latch is initially
disabled. It is enabled once the short circuit delay time
has elapsed. Timing diagram on pages 4 to 5 will show a
detailed operation of the Short Circuit protection circuitry.
To be most effective, the MOSFET RDS(ON) should not be
selected artificially low. The MOSFET should be
chosen so that at maximum required current, it is almost
fully turned on. If, for example, a supply of 1.5V at 4A is
required from a 3.3V ± 5% rail, the maximum allowable
RDS(ON) would be:
()
Ω≈
•−•
=m400
4
025.15.13.395.0
R)MAX)(ON(DS
To allow for temperature effects 200mΩ would be a
suitable room temperature maximum, allowing a peak
short circuit current of approximately 15A for a short time
before shutdown.
Capacitor Selection
Output Capacitors: Low ESR aluminum electrolytic or tan-
talum capacitors are recommended for bulk
capacitance, with ceramic bypass capacitors for decoupling
high frequency transients.
Input Capacitors: Placement of low ESR aluminum
electrolytic or tantalum capacitors at the input to the
MOSFET (VTTIN) will help to hold up the power supply
during fast load changes, thus improving overall transient
response. The +5VSTBY supply should be bypassed with a
10µF ceramic capacitor.
Layout Guidelines
One of the advantages of using the SC1112 to drive an
external MOSFET is that the bandgap reference and
control circuitry do not need to be located right next to the
power device, thus a very accurate output voltage can be
obtained since heating effects will be minimal.
The 0.1µF bypass capacitor should be located close to the
+5VSTBY supply pin, and connected directly to the ground
plane. The ground pin of the device should also be con-
nected directly to the ground plane. The sense or adjust
pin does not need to be close to the output voltage plane,
but should be routed to avoid noisy traces if at all pos-
sible.
Power dissipation within the device is practically
negligible, requiring no special consideration during
layout.
Applications Infomation (Cont.)
19
2006 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1112
Board Layout Assembly Top Board Layout Assembly Bottom
Board Layout Top Board Layout Bottom
Evaluation Board Gerbers
202006 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1112
*
VTT SELECT Signal
J14
+
C19
330uF GND
J10
C3
0.1uF
+
C12
330uF
+3.3V
J4
AGP
Q3
IRFR120N
ADJ J11
C9
0.1uF
JP2
1
2
RB
ADJ = 1.2*(1+RA/RB)
+
C18
330uF
*
GND J16
*
+
C14
330uF
AGP
J19
GND
J2
C13
0.1uF
GND
J20
R2 100k
**
VTT
J9
R3 100k
C10
1uF
+
C2
330uF
JP1 = SHORT, VTT = 1.25 V
+5VSTBY
J1
**
ADJ J13
VTT
Q2
IRFR120N
GND
J5
+3.3V
C4
0.1uF
+
C6
330uF VTT
U1 SC1112CS
5
3
16
13
11
14
15
6
4
2
1
12
7 10
98
AGPSEL
DELAY
GND
VTTSEN
AGPSEN
VTTGATE
VTTIN
ADJGATE
VTTSEL
PWRGD
5VSTBY
AGPGATE
ADJSEN FC
CAP+CAP-
+
C8
330uF
VTT
J8
C7
0.1uF
AGP SELECT Signal
J15
Q1
IRFR120N
*
C17
0.1uF
GND
J21
JP1 = OPEN, VTT = 1.5 V
JP1 1
2
C1
10uF
AGP
J18
POWER GOOD
J6
**
C15
0.1uF
C5 22nF
+5VSTBY
+3.3V
J3
RA
GND
J12
ADJ
R1
1k
*
GND J17
+
C16
330uF
JP2 = OPEN, AGP = 3.3 V
JP2 = SHORT, AGP = 1.5 V
C11 0.1uF
GND
J7
*
Evaluation Board Schematic
21
2006 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1112
metI.ytQecnerefeRtraPtnirPtooF
111CFu016021
28 91C,81C,61C,41C,21C,8C,6C,2CFu033130./001.SL/57.2.D/LYCPC
38 71C,51C,31C,11C,9C,7C,4C,3CFu1.05080
415CFn225080
51 01CFu15080
62 2PJ,1PJ2PTP2/AIV
711JYBTSV5+2505DE
89 12J,02J,71J,61J,21J,01J,7J,5J,2JDNG2505DE
92 4J,3JV3.3+2505DE
0116JdooGrewoP2505DE
112 9J,8JTTV2505DE
212 21J,11JJDA2505DE
31141JlangiSTCELESTTV2505DE
41151JlangiSTCELESPGA2505DE
512 91J,81JPGA2505DE
613 3Q,2Q,1QN021RFRITEFKAPD
713 BR,AR,1Rk15080
812 3R,2Rk0015080
9111UTRTS2111CS61-OS
Evaluation Board Bill of Materials
222006 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1112
Outline Drawing - TSSOP-16
Land Pattern - TSSOP-16
REFERENCE JEDEC STD MO-153, VARIATION AB.
e/2
D
bxN
bbb C A-B D
DATUMS AND TO BE DETERMINED AT DATUM PLANE
DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
OR GATE BURRS.
2.
4.
3.
NOTES:
1.
-B-
-A-
SIDE VIEW
SEATING
2X N/2 TIPS
aaa C
ccc C
INDICATOR
PIN 1
PLANE
2X
C
B
1
E/2
N
3
2
A
c
L
(L1) 01
DETAIL
SEE DETAIL A
-H-
0.25
A
0.80
0.05
MIN
DIMENSIONS
MILLIMETERS
4.30
0.45
0.09
4.90
0.19
c
D
e
L1
L
E
E1
01
ccc
aaa
bbb
N
b
A
A2
A1
A2
A1
A
E1 E
0° 0°8°
.004
.004
.008
H
GAGE
PLANE
-
.026 BSC
.252 BSC
.173
.196
(.039)
.024
16
.169
.018
.003
.192
.007
-
.031
.002
-
-
-
-
-
.177
.030
.047
.042
.006
.007
.201
.012
-
DIM
eD
INCHES
NOMMIN MAX
8°
0.10
0.20
0.10
-
1.20
1.05
0.15
4.50
0.75
0.20
5.10
0.30
4.40
0.65 BSC
6.40 BSC
(1.0)
0.60
16
5.00
-
-
-
-
-
MAXNOM
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
NOTES:
1.
(.222) (5.65)
ZG
Y
P
(C) 4.10.161
0.65.026
0.40.016
1.55.061
7.20.283
X
INCHES
DIMENSIONS
Z
P
Y
X
DIM
C
G
MILLIMETERS
23
2006 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1112
Outline Drawing - SO-16
Minimum Land Pattern - SO-16
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
Contact Information
SEE DETAIL
DETAIL A
A
.050 BSC
.236 BSC
16
.010
.150
.386
.154
.390
.012 -
16
0.25
1.27 BSC
6.00 BSC
3.90
9.90
-
.157
.394
3.80
9.80
.020 0.31
4.00
10.00
0.51
bxN
2X N/2 TIPS
SEATING
aaa C
E/22X
3
A
D
A1
E1
bbb C A-B D
ccc C
A2
(.041)
.004
.008
-
.028
-
-
-
-
0°
.016
.007
.049
.004
.053
8° 0°
0.20
0.10
-8°
0.40
0.17
1.25
0.10
.041
.010
.069
.065
.010
1.35
(1.04)
0.72
-
1.04
0.25
-
-
-1.75
1.65
0.25
0.25
-
.010 .020 0.50
-
c
L
(L1) 01
0.25
GAGE
PLANE
h
h
PLANE
N
12
3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
-B-
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
DATUMS AND TO BE DETERMINED AT DATUM PLANE
NOTES:
1.
2. -A- -H-
SIDE VIEW
A
e
B
e/2
D
H
C
REFERENCE JEDEC STD MS-012
,
VARIATION AC.4.
A2
A1
D
E1
DIM
N
01
ccc
aaa
bbb
L1
MIN
MILLIMETERS
DIMENSIONS
e
L
h
E
b
c
NOM
INCHES
MIN
A
MAX MAXNOM
E
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
NOTES:
1.
REFERENCE IPC-SM-782A
,
RLP NO. 304A.
2.
.291
.087
.024
.118
(.205)
INCHES
DIMENSIONS
Z
P
Y
X
DIM
C
G
MILLIMETERS
.050
(5.20)
7.40
2.20
0.60
3.00
1.27
ZG
Y
P
(C)
X