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DEMO MANUAL DC2395A
Description
LTC2325/LTC2324/LTC2320
Quad/Octal 16-Bit/14-Bit/12-Bit,
5Msps/2Msps/1.5Msps, Serial,
High Speed SAR ADCs
Demonstration circuit 2395A features the LT C
®
2325/
LTC2324/LTC2320 family. With up to 5Msps, these differ-
ential, multiple channel, 16-bit, serial, high speed succes-
sive approximation register (SAR) ADCs are available in a
52-lead QFN package. Each ADC has an internal 20ppm/°C
maximum drift reference and an SPI-compatible serial
interface that supports CMOS and LVDS logic. Note the
demo board is configured for CMOS operation by default;
see the note under JP8 for LVDS operation. The following
text refers to the LTC2325, but applies to all members of the
family, the only difference being the number of channels,
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PScope
is a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners.
the sample rate and/or the number of bits. The DC2395A
demonstrates the DC and AC performance of the LTC2325
in conjunction with the DC890 PScope™ data collection
board. Alternatively, by connecting the DC2395A into a
customer application, the performance of the LTC2325
can be evaluated directly in that circuit.
Design files for this circuit board are available at
http://www.linear.com/demo/DC2395A
Assembly options
Table 1. DC2395A Assembly Options
VERSION U1 PART NUMBER MAX CONVERSION RATE # OF BITS MAX CLOCK FREQUENCY
DC2395A-A LTC2320CUKG-16#PBF 1.5Msps 16 52.5MHz
DC2395A-B LTC2324CUKG-16#PBF 2Msps 16 110MHz
DC2395A-C LTC2325CUKG-16#PBF 5Msps 16 110MHz
DC2395A-D LTC2320CUKG-14#PBF 1.5Msps 14 52.5MHz
DC2395A-E LTC2324CUKG-14#PBF 2Msps 14 110MHz
DC2395A-F LTC2325CUKG-14#PBF 5Msps 14 110MHz
DC2395A-G LTC2320CUKG-12#PBF 1.5Msps 12 52.5MHz
DC2395A-H LTC2324CUKG-12#PBF 2Msps 12 110MHz
DC2395A-I LTC2325CUKG-12#PBF 5Msps 12 110MHz
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DEMO MANUAL DC2395A
boArD photo
Figure 1. DC2395A Connection Diagram
SIGNAL
GENERATOR
CLOCK SIGNAL
FROM GENERATOR
TO DC890B
7V DC POWER SUPPLY
–7V DC POWER SUPPLY
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DEMO MANUAL DC2395A
Quick stArt proceDure
Demonstration circuit 2395A is easy to set up and evaluate
for performance. Refer to Figure 1 and follow the proce-
dure below.
n Connect the DC2395A to a DC890 USB high speed data
collection board using edge connector P1.
n Connect the DC890 to a host PC with a standard USB
A/B cable.
n Apply a low jitter signal source to J11 to test channel1.
Note that the DC2395A is capable of accepting a
differential input signal as well as a single-ended signal.
See the Hardware Setup section for the jumper positions
that correspond to these configurations.
n As a clock source, apply a low jitter 10dBm sine wave or
square wave to connector J9. See Table 1 for maximum
clock frequencies. Note that J9 has a 50Ω termination
resistor to ground.
n Run the PScope software (Pscope.exe version K73,
or later) supplied with the DC890 or download it from
www.linear.com/software. Complete software doc-
umentation is available from the Help menu. Updates
can be downloaded from the Tools menu. Check for
updates periodically, as new features may be added.
The PScope software should recognize the DC2395A
and configure itself automatically.
n Click the Collect button (Figure 2) to begin acquiring
data. The Collect button then changes to Pause, which
can be used to stop data acquisition.
DRIVE OPTIONS
There are several ways to drive the LTC2325 on the
DC2395A. It can be driven with a true differential source,
or a single-ended source in either pseudo-differential
bipolar or unipolar mode. For details on how to configure
the DC2395A for any of these see Table 2.
An example input circuit for channel 1 is shown in Figure 3.
Table 2. Resistor Values for Different Input Configurations
INPUT CONFIGURATION
R32, 52, 72, 104,
146, 179, 202, 222
R17, 37, 57, 88,
125, 163, 187, 207
R15, 35, 55, 75,
122, 159, 185, 205
R16, 36, 56, 76,
123, 160, 186, 206
R24, 44, 64, 100,
143, 173, 194, 214
Differential 0Ω DNI DNI 0Ω DNI
Single-Ended Differential ADC Drive 0Ω DNI 301Ω 301Ω DNI
Single-Ended Bipolar ADC Drive 0Ω DNI DNI 0Ω 0Ω
Unipolar ADC Drive DNI 0Ω 301Ω 301Ω 0Ω
*DNI = Do not install
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DEMO MANUAL DC2395A
Figure 2. DC2395A PScope Screenshot
Quick stArt proceDure
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DEMO MANUAL DC2395A
Figure 3. Example Input Circuit, Single-Ended Differential ADC Drive
2
2
1
1
D
D
C
C
B
B
A
A
+6V
-6V
VCM_BIAS1
AIN1-
REF_OUT1
AIN1+
R217
0
C124
DNI
C206
10uF
R212 DNI
R222 0
R218
DNI
R207 DNI
R206
301
C203
DNI
+
-
U21B
LT1819CMS8
5
6
7
84
R213
49.9
C123
10uF
R214
1K
R209
DNI
C126
220pF
R210
150
R216
DNI
C125
DNI
J11A
BNC
1
4
3
R208
49.9
R221
DNI
R205
301
R203
0
R219
0
+
-
U21A
LT1819CMS8
3
2
1
8 4
J11B
BNC
2
6
5
C127
DNI
R220 1K
R211
0
R215
0
C129
10uF
C207
10uF
C128
DNI
C204 0.1uF
R204
DNI
C2080.1uF
Quick stArt proceDure
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DEMO MANUAL DC2395A
SIGNAL CONNECTIONS
J2 FPGA Program: Factory use only.
J4 JTAG: Factory use only.
J11 Ch1 Input: In the single-ended configuration, use the
upper BNC connector as the signal input. For differential
operation, use the upper BNC as the Ch1+ input, and the
lower BNC as the Ch1– input.
J10 Ch2 Input: In the single-ended configuration, use the
upper BNC connector as the signal input. For differential
operation, use the upper BNC as the Ch2+ input, and the
lower BNC as the Ch2– input.
J8 Ch3 Input: In the single-ended configuration, use the
upper BNC connector as the signal input. For differential
operation, use the upper BNC as the Ch3+ input, and the
lower BNC as the Ch3– input.
J7 Ch4 Input: In the single-ended configuration, use the
upper BNC connector as the signal input. For differential
operation, use the upper BNC as the Ch4+ input, and the
lower BNC as the Ch4– input.
J6 Ch5 Input: In the single-ended configuration, use the
upper BNC connector as the signal input. For differential
operation, use the upper BNC as the Ch5+ input, and the
lower BNC as the Ch5– input.
J5 Ch6 Input: In the single-ended configuration, use the
upper BNC connector as the signal input. For differential
operation, use the upper BNC as the Ch6+ input, and the
lower BNC as the Ch6– input.
J3 Ch7 Input: In the single-ended configuration, use the
upper BNC connector as the signal input. For differential
operation, use the upper BNC as the Ch7+ input, and the
lower BNC as the Ch7– input.
J1 Ch8 Input: In the single-ended configuration, use the
upper BNC connector as the signal input. For differential
operation, use the upper BNC as the Ch8+ input, and the
lower BNC as the Ch8– input.
J9 CLK: This input has a 50Ω termination resistor, and is
intended to be driven by a low jitter 10dBm sine or square
wave. To achieve the full AC performance of this part,
the clock jitter should be kept under 2ps. This input is
capacitively coupled so that the input clock can be either
0V to 2.5V or ±1.25V. This eliminates the need for level
shifting. To run at the maximum conversion rate, apply
the frequency specified in the Table 1.
JP1 VCCIO: Use this jumper to select the VCCIO supply
voltage. The default setting is 2.5V. The 1.8V setting
selects a 1.8V supply voltage.
JP2 VDD: Use this jumper to select the VDD supply volt-
age. The default setting is 5V. The 3.3V setting selects a
3.3V supply voltage.
JP5 REF INT: Set for INT when using the internal reference.
Set for EXT to disable the internal REFOUT1-4 buffers for
use with external voltage references.
JP11 REF1: Set for ONB to use onboard voltage reference.
Set for EXT to use external reference applied at E14.
JP10 REF2: Set for ONB to use onboard voltage reference.
Set for EXT to use external reference applied at E13.
JP4 REF3: Set for ONB to use onboard voltage reference.
Set for EXT to use external reference applied at E12.
JP3 REF4: Set for ONB to use onboard voltage reference.
Set for EXT to use external reference applied at E11.
hArDwAre setup
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DEMO MANUAL DC2395A
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
JP8 SDR/DDR: Set for SDR for single data rate operation.
Set for DDR for double data rate operation.
JP6 CMOS/LVDS: Use this jumper to select the data output
format from the LTC2325. The default setting is CMOS.
The output data will not be valid if the jumper is moved
to the LVDS position unless the following changes have
been made:
Install 100Ω S0402 resistors at R113, 114, 117, 118,
124, 239
Reprogram the CPLD through J2 using the program-
ming file LTC2325_lvds.pof found at:
http://www.linear.com/demo/DC2395A
Move JP6 to the LVDS position.
JP7 EEPROM: Factory use only.
JP9 OSC: Use this jumper to enable the onboard encode
clock source. The default setting is OFF. The ON setting
energizes this source. Refer to the DC2395A schematic for
additional passive elements required to use the onboard
source.
hArDwAre setup
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DEMO MANUAL DC2395A
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2016
LT 0916 • PRINTED IN USA
DEMONSTRATION BOARD IMPORTANT NOTICE
Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions:
This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT
OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete
in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety
measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union
directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations.
If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date
of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU
OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS
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arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all
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agency certified (FCC, UL, CE, etc.).
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observe good laboratory practice standards. Common sense is encouraged.
This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC application
engineer.
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