DB08-000275-03 May 2006 1 of 30
Version 2.0 Copyright © 2004–2006 by LSI Logic Corporation. All rights reserved.
LSISAS1064E PCI Express to 4-Port
Serial Attached SCSI Controller
Datasheet
Version 2.0
The LSISAS1064E is a four-port, 3.0 Gbit/s SAS/SATA controller that is
compliant with the Fusion-MPT™(Message Passing Technology)
architecture, provides an eight-lane PCI Express interface, and supports
Integrated RAID™technology. The PCI Express software is backward
compatible with previous revisions of the PCI bus and PCI-X bus. The
LSISAS1064E supports the PCI Express Base Specification, Revision
1.0a, and the ANSI Serial Attached SCSI Standard, Revision 1.1.
Figure 1 and Figure 2 provide examples of LSISAS1064E applications.
The point-to-point interconnect feature of the PCI Express bus limits the
electrical load on links, allowing increased transmission and reception
frequencies. The PCI Express transmission and reception data rates for
each full-duplex interconnect is 2.5 Gbits/s. The LSISAS1064E has eight
PCI Express phys, which provide host-side possible maximum
transmission and reception rates of 4.0 Gbytes/s. The LSISAS1064E
supports x8, x4, and x1 PCI Express link widths, and automatically
downshifts if plugged into either a x4 connector or into a x8 connector
that is wired as a x4 connector. The serial PCI Express interconnect
between devices lowers the number of pins per device, which reduces
both the PCI Express board design costs and the overall board design
complexity. The serial connection also makes the PCI Express
performance highly scalable.
Figure 1 LSISAS1064E Direct-Connect Example
Flash ROM/
LSISAS1064E
PCI Express to SAS Controller
NVSRAM
I2C
PCI Express Interface 32-bit Memory
Address/Data
Bus
SAS/SATA
Drives
8
Serial
Interface
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Figure 2 LSISAS1064E Controller and LSISASx12 Expander
Example
PCI Express implements a switch-based technology to interconnect a
large number of devices. Communication over the serial interconnect is
accomplished using packet-based communication protocol. Quality of
Service (QOS) features provide differentiated transmission performance
for different applications. Hot Plug/Hot Swap support enables “always-on”
systems. Enhanced error handling features, such as end-to-end CRC
(ECRC) and Advanced Error Reporting, make PCI Express suitable for
robust, high-end server applications. Hot Plug, power management, error
handling, and interrupt signaling are accomplished using packet-based
messaging rather than sideband signals. This keeps the device pin count
low and reduces the system cost.
Each of the four SAS phys on the LSISAS1064E is capable of SAS/SATA
link rates of 3.0 Gbits/s and 1.5 Gbits/s. The user can configure ports as
wide or narrow. Narrow ports have one phy per port. Wide ports have
two, three, or four phys per port. Each port supports the SSP, SMP, STP,
and SATA protocols.
LSISAS1064E
LSISASx12
Flash ROM/
32-bit Memory
Address/Data
Bus NVSRAM
I2C
LSISASx12
SAS/SATA
Drives
PCI Express Interface
SAS/SATA
Drives
SAS/SATA
Drives SAS/SATA
Drives
8
Serial
Interface
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The SAS interface uses the proven SCSI command set to ensure reliable
data transfers, while providing the connectivity and flexibility of
point-to-point serial data transfers. The SAS interface provides improved
performance, simplified cabling, smaller connectors, lower pin count, and
lower power requirements when compared to parallel SCSI. SAS
controllers leverage an electrical and physical connection interface that
is compatible with SATA technology.
The LSISAS1064E supports the Integrated RAID solution, which is a
highly integrated, low cost RAID implementation. It is designed for
systems requiring redundancy and high availability, but not needing a
full-featured RAID implementation. Integrated RAID technology supports
up to two volumes and ten drives. Each volume can contain up to eight
drives. The Integrated RAID solution includes Integrated Mirroring™(IM)
technology, Integrated Mirroring Enhanced (IME), and
Integrated Striping™(IS) technology. IM provides physical mirroring of
two physical drives, plus a hot spare drive. IME supports 3–8 drives plus
a hot spare drive. IM and IME require an NVSRAM to support write
journaling. IS enables data striping across up to eight physical drives.
The Integrated RAID solution is OS independent, easy to install and
configure, supports up to eight drives at RAID Level 0, and does not
require a special driver. The run-time operation of the Integrated RAID
solution is transparent to the operating system. A single firmware build
supports all Integrated RAID capabilities.
The LSISAS1064E uses the Fusion-MPT architecture, which features a
performance based message passing protocol that offloads the host
CPU by completely managing all I/Os and minimizes system bus
overhead by coalescing interrupts. The proven Fusion-MPT architecture
requires only thin, easy-to-develop device drivers that are independent of
the I/O bus. LSI Logic provides these device drivers.
To meet its flexibility and data transfer requirements, the LSISAS1064E
uses an ARM966 processor that operates at 225 MHz. LSI manufactures
the LSISAS1064E using Gflx™technology.
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Features
This section lists the features of the LSISAS1064E.
SSP and SAS Features
This section describes the SSP and SAS features.
•Each phy supports 3.0 Gbit/s and 1.5 Gbit/s SAS data transfers
•Provides a serial, point-to-point, enterprise-level storage interface
•Supports wide transfers consisting of two, three, or four phys
•Supports narrow ports consisting of a single phy
•Transfers data using SCSI information units
•Is compatible with SATA target devices
SATA and STP Features
This section describes the SATA and STP features.
•Each phy supports 3.0 Gbit/s and 1.5 Gbit/s SATA data transfers
•Each phy supports 3.0 Gbit/s and 1.5 Gbit/s STP data transfers
•Allows addressing of multiple SATA targets through an expander
•Allows multiple initiators to address a single target (in a fail-over
configuration) through an expander
PCI Express Features
The LSISAS1064E supports these PCI Express features.
•Provides eight PCI Express phys
•Supports a single-phy (1 lane) link transfer rate up to 2.5 Gbits/s in
each direction
•Supports x8, x4, and x1 link widths
•Automatically downshifts to a x4 link width if plugged into a x4
connector or into a x8 connector that is wired as a x4 connector
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•Provides a scalable interface
– Single-lane aggregate bandwidth of up to 0.5 Gbytes/s
(500 Mbytes/s)
– Quad-lane aggregate bandwidth of up to 2.0 Gbytes/s
(2000 Mbytes/s)
– 8-lane aggregate bandwidth of up to 4.0 Gbytes/s
(4000 Mbytes/s)
•Offers a maximum payload of 2 Kbytes
•Supports serial, point-to-point interconnections between devices
– Reduces the electrical load of the connection
– Enables higher transmission and reception frequencies
•Supports lane reversal and polarity inversion
•Supports PCI Express Hot Plug
•Supports Power Management
– Supports the PCI Power Management 1.2 specification
– Supports Active State Power Management, including the L0, L0s,
and L1 states, by placing links in a power-savings mode during
times of no link activity
•Uses a packetized and layered architecture
•Achieves a high bandwidth per pin with low overhead and low latency
•PCI Express is software compatible with PCI and PCI-X software
– Leverages existing PCI device drivers
– Supports the Memory, I/O, and Configuration address spaces
– Supports memory read/write transactions, I/O read/write
transactions, and configuration read/write transactions
•Provides 4 Kbytes of PCI Configuration address space per device
•Supports posted and nonposted transactions
•Provides quality of service (QOS) link configuration and arbitration
policies
•Supports Traffic Class 0 and one virtual channel
•Supports Message Signaled Interrupts (both MSI and MSI-X) as well
as INTx interrupt signaling for legacy PCI support
•Supports end-to-end CRC (ECRC) and Advanced Error Reporting
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Integration
These features make the LSISAS1064E easy to integrate:
•Leverages the proven Fusion-MPT technology
•PCI Express device can use PCI-based device drivers, which
reduces integration challenges and risks
•Provides unequaled performance through the Fusion-MPT
architecture
•Reduces time to market with the Fusion-MPT architecture
– Single driver binary for SAS/SATA, Ultra320 SCSI, and
Fibre Channel products
– One firmware build supports all Integrated RAID capabilities
– Thin, easy to develop drivers
– Reduced integration and certification effort
Usability
These usability features are incorporated into the design:
•Simplifies cabling with point-to-point, serial architecture
•Provides drive spin-up sequencing control
•Provides up to two LED signals for each SAS/SATA phy to indicate
drive activity and faults
•Provides a serialized general purpose I/O (SGPIO) interface
Flexibility
These features increase the flexibility of the LSISAS1064E:
•Supports an 8-bit flash ROM interface and an 8-bit nonvolatile RAM
(NVSRAM) interface
•Offers a flexible programming interface to tune I/O performance
•Allows mixed connections to SAS or SATA targets
•Allows a grouping of up to four phys in a wide port
•Leverages compatible connectors for SAS and SATA connections
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•Supports Integrated RAID technology, which provides for
Integrated Mirroring technology and/or Integrated Striping technology
•Provides 17 LED signals
•Provides four independent GPIO signals
Reliability
These features enhance the reliability of the LSISAS1064E:
•Uses proven GigaBlaze®transceivers on both the SAS/SATA phys
and the PCI Express phys
•Isolates the power and ground of I/O pads and internal chip logic
•Provides ESD protection
•Provides latch-up protection
•Has a high proportion of power and ground pins
•Integrated Mirroring technology provides physical mirroring of the
boot volume
Testability
These features enhance the testability of the LSISAS1064E:
•Offers JTAG boundary scan
•Offers ARM®Multi-ICE®technology for debugging the ARM966
processor
Block Diagram Description
Figure 3 provides the block diagram for the LSISAS1064E. The following
subsections discuss the block diagram. There is a single Host Interface
module and a Quad Port module. The Host Interface module supports
the 8-lane PCI Express interface. The Quad Port module supports four
SAS phys.
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Figure 3 LSISAS1064E Block Diagram
Host Interface Module
The LSISAS1064E interfaces with the host through the host interface
module. The host interface module contains the PCI Express interface,
system interface, IOP (ARM966) processor, timer and configuration,
DMA arbiter, PCI timer and configuration, SIO, external memory, I2C, and
UART blocks.
DMA Arbiter
PCI
TimerConfig
IRQ Controller
Context RAM
AHB Arbiter
System Interface
UART
(ARM966)
IOP
PCI
PCI Express TimerConfig
ICE I/F
GPIO/LED
I2C
I2C
Primary AHB Bus
Quad Port Context AHB Bus
SIO A
Host Interface Module
External
Memory
Interface
Express
SAS Phy
SAS Link
AHB Bridge
Port Layer Connection
AHB Interface
SECONDARY
Queue SATA Engine
Manager
Transport Modules
Manager and Switch
SAS Phy
SAS Link
SAS Phy
SAS Link
SAS Phy
SAS Link
Quad Port
DMA Arbiter
AHB Interface
CONTEXT
Quad Port Module
Processor
SIO A
UART
XMEM Bus
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PCI Express Interface
The PCI Express interface block supports an 8-lane PCI Express
interface. This is a high bandwidth, serial interface that features
point-to-point interconnects between devices and an advanced
packetized and layered protocol architecture. The PCI Express software
is backward compatible with previous implementations of the PCI
specification.
System Interface
In combination with the IOP, the system interface supports the
Fusion-MPT architecture. The system interface efficiently passes
messages between the LSISAS1064E and the host interface using a
high-performance, packetized mailbox architecture. The LSISAS1064E
system interface takes advantage of PCI Express point-to-point
connections, thereby allowing a dedicated connection to each device with
no sharing.
IOP (ARM966) Processor
The LSISAS1064E I/O processor (IOP) controls the system interface and
manages the host side of the Fusion-MPT architecture without host
processor intervention, which frees the host processor for other tasks.
Timer and Configuration
This block supports the LSISAS1064E LED and GPIO interfaces. There
are nine LED signals. The GPIO interface contains four independent
GPIO signals. This block also supports internal timing adjustments and
power-on sense configuration options.
DMA Arbiter
The LSISAS1064E provides the ability to transfer system memory blocks
to and from local memory through the descriptor-based DMA arbiter and
router. The DMA channel includes a system DMA FIFO and the internal
bus interface logic.
PCI Timer and Configuration
This PCI timer and configuration module supports the PCI configuration
register space and a power-on reset (POR).
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SIO
The LSISAS1064E provides an SGPIO interface that is compliant with
the SFF-8485 specification. A typical use of the serial I/O (SIO) module
is to provide control of LEDs. The SIO module is SFF-8485 compliant.
External Memory
The external memory controller block provides an interface for flash ROM
and NVSRAM devices. The external memory bus provides a 32-bit
memory bus, parity checking, and chip select signals for NVSRAM and
flash ROM. The flash ROM and NVSRAM are capable of 8-bit accesses.
Typical system configurations require a flash ROM to store firmware,
configuration information, and persistent data information.
I2C
The LSISAS1064E contains an Inter-IC (I2C) block that communicates
with peripherals. The I2C block operates as either a master or a slave on
the bus and sustains data rates up to 400 Kbits/s. The I2C block
accomplishes byte-wise bidirectional data transfers by using either an
interrupt or a polling handshake at the completion of each byte. The I2C
block controls all bus timing and performs bus-specific sequences.
UART
The UART provides test and debug access to the LSISAS1064E.
Quad Port Module
The Quad Port module in the LSISAS1064E implements the SSP, SMP,
and STP/SATA protocols, and manages the SAS/SATA phys. The
Quad Port module supports four phys. The following subsections
describe the Quad Port module.
Transport Modules
The transport modules transmit frames to and from the port layer and
implement the STP, SSP, and SMP protocols. The Quad Port module has
four instances of the transport module, one for each SAS/SATA phy on
the LSISAS1064E. The transport modules also manage DMA transfers.
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Queue Manager
The queue manager is responsible for managing various queue
structures that support the SSP, SMP, and SATA/STP protocols. The
queue structures are the primary means for the IOP to initiate I/Os to the
hardware, and for the hardware to notify the IOP of I/O status.
SATA Engine
The SATA engine provides information to the transport modules to enable
handling of SATA commands. The SATA engine tracks queued
commands per device and provides these tags to the SATA transport
layer blocks.
Port Layer Connection Manager and Switch
The port layer connection manager and switch handles transmission
requests from the transport modules and originates connection requests
to the SAS links. It is also responsible for handling SAS wide port
configurations.
SAS Link
The SAS link layer manages SAS connections between initiator and
target ports, data clocking, and CRC checking on transmitted data. The
SAS link is also responsible for starting a link reset sequence.
SAS Phys
The SAS phys interface to the physical layer, perform serial-to-parallel
conversion of received data and parallel-to-serial conversion of transmit
data, manage phy reset sequences, and perform 8b/10b encoding.
Quad Port DMA Arbiter
The quad port arbiter interfaces with the host interface DMA arbiter and
determines bus priority between the quad port phys for DMA transfers.
Context RAM
The context RAM is a memory that is shared between the host interface
module and the quad port module. The context RAM holds a portion of
the firmware.
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Signal Descriptions
The following subsections provide the signal descriptions for the
LSISAS1064E. A ‘/’ following the signal indicates an active LOW signal.
PCI Express Signals
This section describes the PCI Express signals. Refer to the PCI Express
specification for detailed signal descriptions.
PCI Express System Signals
This section describes the PCI Express system signals.
P_REFCLK_P PCI Express Differential Clock Input
This signal provides half of the PCI Express differential
clock input signal.
P_REFCLK_N PCI Express Differential Clock Input
This signal provides half of the PCI Express differential
clock input signal.
RST/ Reset Input
Asserting the RST/ signal causes a reset.
PCI Express Data Signals
This section describes the PCI Express transmit and receive signals.
P_RX[7:0]+ PCI Express Receive Differential Data Input
P_RX[x]+provides the positive differential data receiver
for PCI Express phy[x].
P_RX[7:0]−PCI Express Receive Differential Data Input
P_RX[x]−provides the negative differential data receiver
for PCI Express phy[x].
P_TX[7:0]+ PCI Express Transmit Differential Data Output
P_TX[x]+provides the positive differential data
transmitter for PCI Express phy[x].
P_TX[7:0]−PCI Express Transmit Differential Data Output
P_TX[x]−provides the negative differential data
transmitter for PCI Express phy[x].
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SAS Signals
This section describes the SAS interface signals.
REFCLK_P, REFCLK_N Input
These pins provide the serial differential clock. Connect
a 75 MHz oscillator with an accuracy of at least 50ppm
to these pins. To use a single-ended crystal, tie the
crystal to REFCLK_P and tie REFCLK_N to a resistor
termination.
RTRIM Resistor Reference Analog
This pin provides the analog resistor reference for the
GigaBlaze transceivers. The resistor provides a reference
to calibrate the 50 Ωtermination.
RX[3:0]−Receive Negative Differential Data Input
RX[x]−provides the negative differential data receiver for
SAS/SATA phy[x].
RX[3:0]+ Receive Positive Differential Data Input
RX[x]+ provides the positive differential data receiver for
SAS/SATA phy[x].
TX[3:0]−Transmit Negative Differential Data Output
TX[x]−provides the negative differential data transmit
signal for SAS/SATA phy[x].
TX[3:0]+ Transmit Positive Differential Data Output
TX[x]+ provides the positive differential data transmit
signal for SAS/SATA phy[x].
I2C and UART Signals
This section describes the I2C and UART signals.
ISTWI_CLK I2C Clock Input/Output
This signal provides the I2C clock signal.
ISTWI_DATA I2C Data Input/Output
This signal provides the I2C data signal.
UART_RX UART Receive Input
This signal provides the UART receive signal.
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UART_TX UART Transmit Output
This signal provides the UART transmit signal.
Memory Interface Signals
This section describes the memory interface signals.
MCLK Memory Clock Output
All synchronous RAM control/data signals reference the
rising edge of this clock.
ADSC/ Address-Strobe-Controller Output
Asserting this active LOW signal initiates read, write, or
chip deselect cycles.
ADV/ Advance Output
Asserting this active LOW signal increments the burst
address counter of the selected synchronous SRAM.
MAD[31:0] Multiplexed Address/Data Input/Output
These signals provide the address and data bus for the
flash ROM and NVSRAM. These signals also provide
Power-On Sense configuration functions to the
LSISAS1064E. These signals are internally pulled LOW.
MADP[3:0] Memory Parity Input/Output
These signals provide parity checking for MAD[31:0].
These signals are internally pulled HIGH.
MOE[1:0]/ Memory Output Enables Output
Asserting these active LOW signals enable the selected
flash ROM or NVSRAM device to drive data. MOE1/
enables flash ROM devices. MOE0/ enables NVSRAM
devices.
MWE[1:0]/ Memory Write Enables Output
The MWE[1:0]/ signals provide memory enable signals.
BWE[3:0]/ Memory Byte Write Enables Output
BWE[3]/ and BWE[2]/ enable partial word writes to the
flash ROM and the NVSRAM if FLASH_CS/ or
NVSRAM_CS/ is asserted.
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NVSRAM_CS/ NVSRAM Chip Select Output
Asserting this active LOW signal selects the NVSRAM
device.
FLASH_CS/ Flash Chip Select Output
Asserting this active LOW signal selects the flash ROM.
The LSISAS1064E maps flash ROM address space into
system memory space.
SIO Signals
This section describes the SIO signals.
SIO_CLK_A SIO Clock Input/Output
This signal provides the clock signal for SIO A.
SIO_DIN_A SIO Data In A Input
This signal provides the data input signal to SIO A.
SIO_DOUT_A SIO Data Out A Output
This signal provides the data output signal to SIO A and
can control the Quad Port LED drives.
SIO_END_A SIO End Control Input/Output
The SIO module drives this output to end control of the
SIO bus.
Configuration and General Purpose Signals
This section describes the configuration and general purpose pins.
TST_RST/ Test Reset Input
Asserting this signal forces the chip into a
Power-On-Reset (POR) state. This signal has an internal
pull-up. The LSISAS1064E does not have an internal
POR.
REFCLK_B ARM Reference Clock Input
This pin provides the ARM reference clock.
MODE[7:0] Mode Select Input
This 8-bit bus defines operational and test modes for the
chip. These pins have internal pull-downs.
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FAULT_LED[3:0]/
Fault LED Input/Output
These output signals indicate a SAS link fault.
ACTIVE_LED[3:0]/
Activity LED Input/Output
These output signals indicate SAS link activity.
GPIO[3:0] General Purpose I/O Input/Output
These signals provide general purpose input/output
signals. These signals have internal pull-ups.
HB_LED/ Heartbeat LED Output
Firmware intermittently asserts this signal to indicate that
the IOP is operational.
JTAG and Test Signals
This section describes the JTAG and test signals.
FSELA Clock Select Input
This is a test signal. Pull this signal LOW.
SCAN_ENABLE
Scan Enable Input
SCAN_MODE Scan Mode Input
TCK JTAG Debug Clock Input
TRST/ JTAG Debug Reset Input
TDI JTAG Debug Test Data In Input
TDO JTAG Debug Test Data Out Output
TMS JTAG Debug Test Mode Select Input
TCK_ICE Multi-ICE Debug Clock Input
RTCK_ICE Multi-ICE Debug Return Clock Output
TRST_ICE/ Multi-ICE Debug Reset Input
TDI_ICE Multi-ICE Debug Test Data In Input
TDO_ICE Multi-ICE Debug Test Data Out Output
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TMS_ICE Multi-ICE Debug Test Mode Select Input
IDDT IDDQ Test Mode Enable Input
This signal is active HIGH.
TN/ 3-State Output Enable Control Input
This signal is active LOW.
PROCMON Process Monitor Test Output Driver Output
TDIODE_P Anode Connection of the Thermal Diode Input
TDIODE_VSS Cathode Connection of the Thermal Diode Output
Power and Ground Signals
This section describes the power and ground signals.
REFPLL_VDD Power
These signals provide 1.2 V power.
REFPLL_VSS Ground
These signals provide ground.
VDD2 Power
These signals provide 1.2 V core power.
VDDIO33 Power
These signals provide 3.3 V I/O power.
VSS Ground
These signals provide ground.
RX_VSS[3:0], RXB_VSS[3:0], TX_VSS[3:0], TXB_VSS[3:0] Ground
These signals provide ground for the SAS GigaBlaze
core.
RX_VDD[3:0], RXB_VDD[3:0], TX_VDD[3:0], TXB_VDD[3:0] Power
These signals provide 1.2 V power for the SAS
GigaBlaze core.
P_RX_VDD[7:0], P_RXB_VDD[7:0], P_TX_VDD[7:0],
P_TXB_VDD[7:0] Power
These signals provide 1.2 V power for the PCI Express
GigaBlaze core.
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P_RX_VSS[7:0], P_RXB_VSS[7:0], P_TX_VSS[7:0],
P_TXB_VSS[7:0] Ground
These signals provide ground for the PCI Express
GigaBlaze core.
Pin Listing
Table 1 provides the signal listing by signal name. Table 2 provides the
signal listing by pin name. Figure 4 provides a BGA diagram.
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Table 1 LSISAS1064E Pin Assignments Listed by Signal Name1
RX_VSS3 F15
RX0- B25
RX0+ B24
RX1- B21
RX1+ B20
RX2- A20
RX2+ A19
RX3- B17
RX3+ A17
RXB_VDD0 C23
RXB_VDD1 C19
RXB_VDD2 F17
RXB_VDD3 E15
RXB_VSS0 F21
RXB_VSS1 F19
RXB_VSS2 E17
RXB_VSS3 G16
SCAN_ENABLE E4
SCAN_MODE F5
SIO_CLK_A H22
SIO_DIN_A J21
SIO_DOUT_A D25
SIO_END_A E25
TCK AB2
TCK_ICE U3
TDI AC1
TDI_ICE T5
TDIODE_P V26
TDIODE_VSS T22
TDO AC2
TDO_ICE V3
TMS AC3
TMS_ICE U4
TN/ AD2
TRST_ICE/ W1
TRST/ Y4
TST_RST/ C2
TX_VDD0 A23
TX_VDD1 D18
TX_VDD2 C17
TX_VDD3 D14
TX_VSS0 E19
TX_VSS1 G18
TX_VSS2 D16
TX_VSS3 E14
TX0- B23
TX0+ B22
TX1- A21
TX1+ A22
TX2- A18
TX2+ B18
TX3- A15
TX3+ A16
TXB_VDD0 F20
TXB_VDD1 E18
TXB_VDD2 F16
TXB_VDD3 A14
TXB_VSS0 E20
TXB_VSS1 B19
TXB_VSS2 E16
TXB_VSS3 F14
UART_RX E26
UART_TX F26
VDD2 A12
VDD2 B10
VDD2 C4
VDD2 C8
VDD2 C10
VDD2 D7
VDD2 D8
VDD2 D9
VDD2 D10
VDD2 E5
VDD2 E6
VDD2 E9
VDD2 E10
VDD2 F12
Signal PinSignal Pin
ACTIVE_LED[0]/ H1
ACTIVE_LED[1]/ H2
ACTIVE_LED[2]/ G1
ACTIVE_LED[3]/ H3
ADSC/ V22
ADV/ V23
BWE[0]/ T21
BWE[1]/ U24
BWE[2]/ R23
BWE[3]/ W25
FAULT_LED[0]/ N1
FAULT_LED[1]/ N3
FAULT_LED[2]/ M1
FAULT_LED[3]/ L1
FLASH_CS/ P25
FSELA E2
GPIO[0] V4
GPIO[1] Y1
GPIO[2] W3
GPIO[3] AB1
HB_LED/ P4
IDDT AB4
ISTWI_CLK G26
ISTWI_DATA K21
MAD[0] J26
MAD[1] H26
MAD[2] K24
MAD[3] J24
MAD[4] J23
MAD[5] M26
MAD[6] M23
MAD[7] J25
MAD[8] K25
MAD[9] L26
MAD[10] L23
MAD[11] K23
MAD[12] K26
MAD[13] N23
MAD[14] R26
MAD[15] P23
MAD[16] V21
MAD[17] Y26
MAD[18] W24
MAD[19] U21
MAD[20] AA26
MAD[21] W23
MAD[22] AA23
MAD[23] Y23
MAD[24] AB25
MAD[25] AB23
MAD[26] AB24
MAD[27] Y21
MAD[28] AC25
MAD[29] AC26
MAD[30] AB22
MAD[31] AD25
MADP[0] L21
MADP[1] U26
MADP[2] W26
MADP[3] AA22
MCLK U23
MODE[0] J6
MODE[1] H4
MODE[2] D1
MODE[3] G4
MODE[4] G5
MODE[5] D2
MODE[6] F4
MODE[7] G6
MOE0/ U25
MOE1/ N24
MWE0/ T23
MWE1/ P24
N/C B14
N/C C24
N/C C25
N/C D3
N/C D23
N/C E1
N/C E3
N/C E13
N/C E22
N/C E23
N/C E24
N/C F1
N/C F6
N/C F22
N/C F23
N/C G20
N/C G21
N/C H5
N/C H6
N/C H21
N/C H23
N/C H25
N/C J1
N/C J2
N/C J3
N/C J4
N/C J5
N/C J22
N/C K1
N/C K5
N/C K6
N/C L4
N/C L5
N/C L6
N/C L22
N/C M5
N/C M6
N/C M21
N/C M22
N/C N6
N/C N21
N/C N22
N/C N25
N/C P2
N/C P6
N/C P21
N/C P22
N/C P26
N/C R1
N/C R4
N/C R5
N/C R6
N/C R22
N/C T6
N/C T26
N/C U1
N/C U2
N/C U5
N/C U6
N/C U22
N/C V1
N/C V2
N/C V5
N/C V6
N/C V24
N/C V25
N/C W2
N/C W4
N/C W5
N/C W6
N/C W7
N/C W21
N/C W22
N/C Y5
N/C Y6
N/C Y22
N/C AA1
N/C AA5
N/C AA6
N/C AB13
N/C AB26
N/C AC12
N/C AC13
N/C AC24
N/C AD1
N/C AD3
N/C AD13
N/C AE3
N/C AE13
N/C AF13
NVSRAM_CS/ N26
P_REFCLK_N AD14
P_REFCLK_P AE14
P_RX_VDD0 AB6
P_RX_VDD1 AC7
P_RX_VDD2 AC9
P_RX_VDD3 AE10
P_RX_VDD4 AC15
P_RX_VDD5 AD18
P_RX_VDD6 AC19
P_RX_VDD7 AB21
P_RX_VSS0 AB7
P_RX_VSS1 AA9
P_RX_VSS2 AD9
P_RX_VSS3 AB12
P_RX_VSS4 AA15
P_RX_VSS5 AC17
P_RX_VSS6 AA18
P_RX_VSS7 AC22
P_RX0- AF4
P_RX0+ AF3
P_RX1- AE7
P_RX1+ AE6
P_RX2- AF8
P_RX2+ AE8
P_RX3- AF11
P_RX3+ AF10
P_RX4- AE17
P_RX4+ AF17
P_RX5- AF20
P_RX5+ AF19
P_RX6- AE21
P_RX6+ AE20
P_RX7- AE25
P_RX7+ AE24
P_RXB_VDD0 Y8
P_RXB_VDD1 AB9
P_RXB_VDD2 AD10
P_RXB_VDD3 AF12
P_RXB_VDD4 AB15
P_RXB_VDD5 AA17
P_RXB_VDD6 AD19
P_RXB_VDD7 AD23
P_RXB_VSS0 AD7
P_RXB_VSS1 Y10
P_RXB_VSS2 AA11
P_RXB_VSS3 AA13
P_RXB_VSS4 Y16
P_RXB_VSS5 AB17
P_RXB_VSS6 AA19
P_RXB_VSS7 AA21
P_TX_VDD0 AB5
P_TX_VDD1 AD4
P_TX_VDD2 AC8
P_TX_VDD3 AC10
P_TX_VDD4 AC14
P_TX_VDD5 AD17
P_TX_VDD6 AC18
P_TX_VDD7 AF23
P_TX_VSS0 AA7
P_TX_VSS1 AA8
P_TX_VSS2 AF7
P_TX_VSS3 AB11
P_TX_VSS4 AB14
P_TX_VSS5 AC16
P_TX_VSS6 Y18
P_TX_VSS7 AB19
P_TX0- AE2
P_TX0+ AF2
P_TX1- AE5
P_TX1+ AE4
P_TX2- AF5
P_TX2+ AF6
P_TX3- AE9
P_TX3+ AF9
P_TX4- AF15
P_TX4+ AF16
P_TX5- AF18
P_TX5+ AE18
P_TX6- AF21
P_TX6+ AF22
P_TX7- AE23
P_TX7+ AE22
P_TXB_VDD0 Y7
P_TXB_VDD1 AD8
P_TXB_VDD2 AB10
P_TXB_VDD3 AA12
P_TXB_VDD4 AF14
P_TXB_VDD5 AA16
P_TXB_VDD6 AB18
P_TXB_VDD7 AA20
P_TXB_VSS0 AC4
P_TXB_VSS1 AB8
P_TXB_VSS2 AA10
P_TXB_VSS3 AC11
P_TXB_VSS4 AA14
P_TXB_VSS5 AB16
P_TXB_VSS6 AE19
P_TXB_VSS7 AB20
PROCMON AA4
REFCLK_B B13
REFCLK_N D12
REFCLK_P C13
REFPLL_VDD D13
REFPLL_VSS A13
RESERVED A3
RESERVED A4
RESERVED A5
RESERVED A6
RESERVED A8
RESERVED A9
RESERVED A10
RESERVED A11
RESERVED B3
RESERVED B4
RESERVED B5
RESERVED B6
RESERVED B7
RESERVED B8
RESERVED B9
RESERVED C3
RESERVED D24
RESERVED D26
RESERVED H24
RESERVED K2
RESERVED K3
RESERVED K4
RESERVED K22
RESERVED G22
RESERVED G23
RESERVED M4
RESERVED N2
RESERVED N4
RESERVED N5
RESERVED P1
RESERVED P3
RESERVED P5
RESERVED R21
RESERVED T1
RST/ AB3
RTCK_ICE T4
RTRIM C14
RX_VDD0 E21
RX_VDD1 D19
RX_VDD2 C18
RX_VDD3 D15
RX_VSS0 D22
RX_VSS1 F18
RX_VSS2 D17
Signal Pin Signal Pin Signal Pin
1. N/C pins are not connected.
LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller 21 of 30
DB08-000275-03 May 2006 - Version 2.0 Copyright © 2004–2006 by LSI Logic Corporation. All rights reserved.
Table 1 LSISAS1064E Pin Assignments Listed by Signal Name1(Cont.)
VSS R17
VSS R19
VSS R24
VSS T3
VSS T8
VSS T10
VSS T12
VSS T14
VSS T16
VSS T19
VSS T24
VSS U8
VSS U11
VSS U13
VSS U15
VSS U17
VSS U19
VSS V8
VSS V19
VSS W8
VSS W9
VSS W10
VSS W11
VSS W12
VSS W13
VSS W14
VSS W15
VSS W16
VSS W17
VSS W18
VSS W19
VSS Y3
VSS Y24
VSS AA3
VSS AA24
VSS AC5
VSS AC6
VSS AC20
VSS AC21
VSS AD11
VSS AD12
VSS AD15
VSS AD16
VSS AD22
VSS AE1
VSS AE26
VSS AF25
Signal PinSignal Pin
VDD2 G7
VDD2 G8
VDD2 K11
VDD2 K13
VDD2 K15
VDD2 K17
VDD2 L10
VDD2 L12
VDD2 L14
VDD2 L16
VDD2 M11
VDD2 M13
VDD2 M15
VDD2 M17
VDD2 N10
VDD2 N12
VDD2 N14
VDD2 N16
VDD2 P11
VDD2 P13
VDD2 P15
VDD2 P17
VDD2 R10
VDD2 R12
VDD2 R14
VDD2 R16
VDD2 T11
VDD2 T13
VDD2 T15
VDD2 T17
VDD2 U10
VDD2 U12
VDD2 U14
VDD2 U16
VDDIO33 A24
VDDIO33 B2
VDDIO33 B11
VDDIO33 B12
VDDIO33 B15
VDDIO33 B16
VDDIO33 C1
VDDIO33 C5
VDDIO33 C6
VDDIO33 C20
VDDIO33 C21
VDDIO33 C26
VDDIO33 F2
VDDIO33 F25
VDDIO33 G2
VDDIO33 G9
VDDIO33 G11
VDDIO33 G12
VDDIO33 G13
VDDIO33 G14
VDDIO33 G15
VDDIO33 G17
VDDIO33 G19
VDDIO33 G25
VDDIO33 H7
VDDIO33 H20
VDDIO33 J7
VDDIO33 J20
VDDIO33 K7
VDDIO33 K20
VDDIO33 L2
VDDIO33 L7
VDDIO33 L20
VDDIO33 L25
VDDIO33 M2
VDDIO33 M7
VDDIO33 M20
VDDIO33 M25
VDDIO33 N7
VDDIO33 N20
VDDIO33 P7
VDDIO33 P20
VDDIO33 R2
VDDIO33 R7
VDDIO33 R20
VDDIO33 R25
VDDIO33 T2
VDDIO33 T7
VDDIO33 T20
VDDIO33 T25
VDDIO33 U7
VDDIO33 U20
VDDIO33 V7
VDDIO33 V20
VDDIO33 W20
VDDIO33 Y2
VDDIO33 Y9
VDDIO33 Y11
VDDIO33 Y12
VDDIO33 Y13
VDDIO33 Y14
VDDIO33 Y15
VDDIO33 Y17
VDDIO33 Y19
VDDIO33 Y20
VDDIO33 Y25
VDDIO33 AA2
VDDIO33 AA25
VDDIO33 AC23
VDDIO33 AD5
VDDIO33 AD6
VDDIO33 AD20
VDDIO33 AD21
VDDIO33 AD24
VDDIO33 AD26
VDDIO33 AE11
VDDIO33 AE12
VDDIO33 AE15
VDDIO33 AE16
VDDIO33 AF24
VSS A2
VSS A7
VSS A25
VSS B1
VSS B26
VSS C7
VSS C9
VSS C11
VSS C12
VSS C15
VSS C16
VSS C22
VSS D4
VSS D5
VSS D6
VSS D11
VSS D20
VSS D21
VSS E7
VSS E8
VSS E11
VSS E12
VSS F3
VSS F7
VSS F8
VSS F9
VSS F10
VSS F11
VSS F13
VSS F24
VSS G3
VSS G10
VSS G24
VSS H8
VSS H9
VSS H10
VSS H11
VSS H12
VSS H13
VSS H14
VSS H15
VSS H16
VSS H17
VSS H18
VSS H19
VSS J8
VSS J19
VSS K8
VSS K10
VSS K12
VSS K14
VSS K16
VSS K19
VSS L3
VSS L8
VSS L11
VSS L13
VSS L15
VSS L17
VSS L19
VSS L24
VSS M3
VSS M8
VSS M10
VSS M12
VSS M14
VSS M16
VSS M19
VSS M24
VSS N8
VSS N11
VSS N13
VSS N15
VSS N17
VSS N19
VSS P8
VSS P10
VSS P12
VSS P14
VSS P16
VSS P19
VSS R3
VSS R8
VSS R11
VSS R13
VSS R15
Signal Pin Signal Pin Signal Pin
1. N/C pins are not connected.
22 of 30 LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller
DB08-000275-03 May 2006 - Version 2.0 Copyright © 2004–2006 by LSI Logic Corporation. All rights reserved.
Table 2 LSISAS1064E Pin Assignments Listed by Pin Number1
N21 N/C
N22 N/C
N23 MAD[13]
N24 MOE1/
N25 N/C
N26 NVSRAM_CS/
P1 RESERVED
P2 N/C
P3 RESERVED
P4 HB_LED/
P5 RESERVED
P6 N/C
P7 VDDIO33
P8 VSS
P10 VSS
P11 VDD2
P12 VSS
P13 VDD2
P14 VSS
P15 VDD2
P16 VSS
P17 VDD2
P19 VSS
P20 VDDIO33
P21 N/C
P22 N/C
P23 MAD[15]
P24 MWE1/
P25 FLASH_CS/
P26 N/C
R1 N/C
R2 VDDIO33
R3 VSS
R4 N/C
R5 N/C
R6 N/C
R7 VDDIO33
R8 VSS
R10 VDD2
R11 VSS
R12 VDD2
R13 VSS
R14 VDD2
R15 VSS
R16 VDD2
R17 VSS
R19 VSS
R20 VDDIO33
R21 RESERVED
R22 N/C
R23 BWE[2]/
R24 VSS
R25 VDDIO33
R26 MAD[14]
T1 RESERVED
T2 VDDIO33
T3 VSS
T4 RTCK_ICE
T5 TDI_ICE
T6 N/C
T7 VDDIO33
T8 VSS
T10 VSS
T11 VDD2
T12 VSS
T13 VDD2
T14 VSS
T15 VDD2
T16 VSS
T17 VDD2
T19 VSS
T20 VDDIO33
T21 BWE[0]/
T22 TDIODE_VSS
T23 MWE0/
T24 VSS
T25 VDDIO33
T26 N/C
Pin SignalPin Signal
A2 VSS
A3 RESERVED
A4 RESERVED
A5 RESERVED
A6 RESERVED
A7 VSS
A8 RESERVED
A9 RESERVED
A10 RESERVED
A11 RESERVED
A12 VDD2
A13 REFPLL_VSS
A14 TXB_VDD3
A15 TX3-
A16 TX3+
A17 RX3+
A18 TX2-
A19 RX2+
A20 RX2-
A21 TX1-
A22 TX1+
A23 TX_VDD0
A24 VDDIO33
A25 VSS
B1 VSS
B2 VDDIO33
B3 RESERVED
B4 RESERVED
B5 RESERVED
B6 RESERVED
B7 RESERVED
B8 RESERVED
B9 RESERVED
B10 VDD2
B11 VDDIO33
B12 VDDIO33
B13 REFCLK_B
B14 N/C
B15 VDDIO33
B16 VDDIO33
B17 RX3-
B18 TX2+
B19 TXB_VSS1
B20 RX1+
B21 RX1-
B22 TX0+
B23 TX0-
B24 RX0+
B25 RX0-
B26 VSS
C1 VDDIO33
C2 TST_RST/
C3 RESERVED
C4 VDD2
C5 VDDIO33
C6 VDDIO33
C7 VSS
C8 VDD2
C9 VSS
C10 VDD2
C11 VSS
C12 VSS
C13 REFCLK_P
C14 RTRIM
C15 VSS
C16 VSS
C17 TX_VDD2
C18 RX_VDD2
C19 RXB_VDD1
C20 VDDIO33
C21 VDDIO33
C22 VSS
C23 RXB_VDD0
C24 N/C
C25 N/C
C26 VDDIO33
D1 MODE[2]
D2 MODE[5]
D3 N/C
D4 VSS
D5 VSS
D6 VSS
D7 VDD2
D8 VDD2
D9 VDD2
D10 VDD2
D11 VSS
D12 REFCLK_N
D13 REFPLL_VDD
D14 TX_VDD3
D15 RX_VDD3
D16 TX_VSS2
D17 RX_VSS2
D18 TX_VDD1
D19 RX_VDD1
D20 VSS
D21 VSS
D22 RX_VSS0
D23 N/C
D24 RESERVED
D25 SIO_DOUT_A
D26 RESERVED
E1 N/C
E2 FSELA
E3 N/C
E4 SCAN_ENABLE
E5 VDD2
E6 VDD2
E7 VSS
E8 VSS
E9 VDD2
E10 VDD2
E11 VSS
E12 VSS
E13 N/C
E14 TX_VSS3
E15 RXB_VDD3
E16 TXB_VSS2
E17 RXB_VSS2
E18 TXB_VDD1
E19 TX_VSS0
E20 TXB_VSS0
E21 RX_VDD0
E22 N/C
E23 N/C
E24 N/C
E25 SIO_END_A
E26 UART_RX
F1 N/C
F2 VDDIO33
F3 VSS
F4 MODE[6]
F5 SCAN_MODE
F6 N/C
F7 VSS
F8 VSS
F9 VSS
F10 VSS
F11 VSS
F12 VDD2
F13 VSS
F14 TXB_VSS3
F15 RX_VSS3
F16 TXB_VDD2
F17 RXB_VDD2
F18 RX_VSS1
F19 RXB_VSS1
F20 TXB_VDD0
F21 RXB_VSS0
F22 N/C
F23 N/C
F24 VSS
F25 VDDIO33
F26 UART_TX
G1 ACTIVE_LED[2]/
G2 VDDIO33
G3 VSS
G4 MODE[3]
G5 MODE[4]
G6 MODE[7]
G7 VDD2
G8 VDD2
G9 VDDIO33
G10 VSS
G11 VDDIO33
G12 VDDIO33
G13 VDDIO33
G14 VDDIO33
G15 VDDIO33
G16 RXB_VSS3
G17 VDDIO33
G18 TX_VSS1
G19 VDDIO33
G20 N/C
G21 N/C
G22 RESERVED
G23 RESERVED
G24 VSS
G25 VDDIO33
G26 ISTWI_CLK
H1 ACTIVE_LED[0]/
H2 ACTIVE_LED[1]/
H3 ACTIVE_LED[3]/
H4 MODE[1]
H5 N/C
H6 N/C
H7 VDDIO33
H8 VSS
H9 VSS
H10 VSS
H11 VSS
H12 VSS
H13 VSS
H14 VSS
H15 VSS
H16 VSS
H17 VSS
H18 VSS
H19 VSS
H20 VDDIO33
H21 N/C
H22 SIO_CLK_A
H23 N/C
H24 RESERVED
H25 N/C
H26 MAD[1]
J1 N/C
J2 N/C
J3 N/C
J4 N/C
J5 N/C
J6 MODE[0]
J7 VDDIO33
J8 VSS
J19 VSS
J20 VDDIO33
J21 SIO_DIN_A
J22 N/C
J23 MAD[4]
J24 MAD[3]
J25 MAD[7]
J26 MAD[0]
K1 N/C
K2 RESERVED
K3 RESERVED
K4 RESERVED
K5 N/C
K6 N/C
K7 VDDIO33
K8 VSS
K10 VSS
K11 VDD2
K12 VSS
K13 VDD2
K14 VSS
K15 VDD2
K16 VSS
K17 VDD2
K19 VSS
K20 VDDIO33
K21 ISTWI_DATA
K22 RESERVED
K23 MAD[11]
K24 MAD[2]
K25 MAD[8]
K26 MAD[12]
L1 FAULT_LED[3]/
L2 VDDIO33
L3 VSS
L4 N/C
L5 N/C
L6 N/C
L7 VDDIO33
L8 VSS
L10 VDD2
L11 VSS
L12 VDD2
L13 VSS
L14 VDD2
L15 VSS
L16 VDD2
L17 VSS
L19 VSS
L20 VDDIO33
L21 MADP[0]
L22 N/C
L23 MAD[10]
L24 VSS
L25 VDDIO33
L26 MAD[9]
M1 FAULT_LED[2]/
M2 VDDIO33
M3 VSS
M4 RESERVED
M5 N/C
M6 N/C
M7 VDDIO33
M8 VSS
M10 VSS
M11 VDD2
M12 VSS
M13 VDD2
M14 VSS
M15 VDD2
M16 VSS
M17 VDD2
M19 VSS
M20 VDDIO33
M21 N/C
M22 N/C
M23 MAD[6]
M24 VSS
M25 VDDIO33
M26 MAD[5]
N1 FAULT_LED[0]/
N2 RESERVED
N3 FAULT_LED[1]/
N4 RESERVED
N5 RESERVED
N6 N/C
N7 VDDIO33
N8 VSS
N10 VDD2
N11 VSS
N12 VDD2
N13 VSS
N14 VDD2
N15 VSS
N16 VDD2
N17 VSS
N19 VSS
N20 VDDIO33
Pin Signal Pin Signal Pin Signal
1. N/C pins are not connected.
LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller 23 of 30
DB08-000275-03 May 2006 - Version 2.0 Copyright © 2004–2006 by LSI Logic Corporation. All rights reserved.
Table 2 LSISAS1064E Pin Assignments Listed by Pin Number1(Cont.)
AE5 P_TX1-
AE6 P_RX1+
AE7 P_RX1-
AE8 P_RX2+
AE9 P_TX3-
AE10 P_RX_VDD3
AE11 VDDIO33
AE12 VDDIO33
AE13 N/C
AE14 P_REFCLK_P
AE15 VDDIO33
AE16 VDDIO33
AE17 P_RX4-
AE18 P_TX5+
AE19 P_TXB_VSS6
AE20 P_RX6+
AE21 P_RX6-
AE22 P_TX7+
AE23 P_TX7-
AE24 P_RX7+
AE25 P_RX7-
AE26 VSS
AF2 P_TX0+
AF3 P_RX0+
AF4 P_RX0-
AF5 P_TX2-
AF6 P_TX2+
AF7 P_TX_VSS2
AF8 P_RX2-
AF9 P_TX3+
AF10 P_RX3+
AF11 P_RX3-
AF12 P_RXB_VDD3
AF13 N/C
AF14 P_TXB_VDD4
AF15 P_TX4-
AF16 P_TX4+
AF17 P_RX4+
AF18 P_TX5-
AF19 P_RX5+
AF20 P_RX5-
AF21 P_TX6-
AF22 P_TX6+
AF23 P_TX_VDD7
AF24 VDDIO33
AF25 VSS
Pin SignalPin Signal
U1 N/C
U2 N/C
U3 TCK_ICE
U4 TMS_ICE
U5 N/C
U6 N/C
U7 VDDIO33
U8 VSS
U10 VDD2
U11 VSS
U12 VDD2
U13 VSS
U14 VDD2
U15 VSS
U16 VDD2
U17 VSS
U19 VSS
U20 VDDIO33
U21 MAD[19]
U22 N/C
U23 MCLK
U24 BWE[1]/
U25 MOE0/
U26 MADP[1]
V1 N/C
V2 N/C
V3 TDO_ICE
V4 GPIO[0]
V5 N/C
V6 N/C
V7 VDDIO33
V8 VSS
V19 VSS
V20 VDDIO33
V21 MAD[16]
V22 ADSC/
V23 ADV/
V24 N/C
V25 N/C
V26 TDIODE_P
W1 TRST_ICE/
W2 N/C
W3 GPIO[2]
W4 N/C
W5 N/C
W6 N/C
W7 N/C
W8 VSS
W9 VSS
W10 VSS
W11 VSS
W12 VSS
W13 VSS
W14 VSS
W15 VSS
W16 VSS
W17 VSS
W18 VSS
W19 VSS
W20 VDDIO33
W21 N/C
W22 N/C
W23 MAD[21]
W24 MAD[18]
W25 BWE[3]/
W26 MADP[2]
Y1 GPIO[1]
Y2 VDDIO33
Y3 VSS
Y4 TRST/
Y5 N/C
Y6 N/C
Y7 P_TXB_VDD0
Y8 P_RXB_VDD0
Y9 VDDIO33
Y10 P_RXB_VSS1
Y11 VDDIO33
Y12 VDDIO33
Y13 VDDIO33
Y14 VDDIO33
Y15 VDDIO33
Y16 P_RXB_VSS4
Y17 VDDIO33
Y18 P_TX_VSS6
Y19 VDDIO33
Y20 VDDIO33
Y21 MAD[27]
Y22 N/C
Y23 MAD[23]
Y24 VSS
Y25 VDDIO33
Y26 MAD[17]
AA1 N/C
AA2 VDDIO33
AA3 VSS
AA4 PROCMON
AA5 N/C
AA6 N/C
AA7 P_TX_VSS0
AA8 P_TX_VSS1
AA9 P_RX_VSS1
AA10 P_TXB_VSS2
AA11 P_RXB_VSS2
AA12 P_TXB_VDD3
AA13 P_RXB_VSS3
AA14 P_TXB_VSS4
AA15 P_RX_VSS4
AA16 P_TXB_VDD5
AA17 P_RXB_VDD5
AA18 P_RX_VSS6
AA19 P_RXB_VSS6
AA20 P_TXB_VDD7
AA21 P_RXB_VSS7
AA22 MADP[3]
AA23 MAD[22]
AA24 VSS
AA25 VDDIO33
AA26 MAD[20]
AB1 GPIO[3]
AB2 TCK
AB3 RST/
AB4 IDDT
AB5 P_TX_VDD0
AB6 P_RX_VDD0
AB7 P_RX_VSS0
AB8 P_TXB_VSS1
AB9 P_RXB_VDD1
AB10 P_TXB_VDD2
AB11 P_TX_VSS3
AB12 P_RX_VSS3
AB13 N/C
AB14 P_TX_VSS4
AB15 P_RXB_VDD4
AB16 P_TXB_VSS5
AB17 P_RXB_VSS5
AB18 P_TXB_VDD6
AB19 P_TX_VSS7
AB20 P_TXB_VSS7
AB21 P_RX_VDD7
AB22 MAD[30]
AB23 MAD[25]
AB24 MAD[26]
AB25 MAD[24]
AB26 N/C
AC1 TDI
AC2 TDO
AC3 TMS
AC4 P_TXB_VSS0
AC5 VSS
AC6 VSS
AC7 P_RX_VDD1
AC8 P_TX_VDD2
AC9 P_RX_VDD2
AC10 P_TX_VDD3
AC11 P_TXB_VSS3
AC12 N/C
AC13 N/C
AC14 P_TX_VDD4
AC15 P_RX_VDD4
AC16 P_TX_VSS5
AC17 P_RX_VSS5
AC18 P_TX_VDD6
AC19 P_RX_VDD6
AC20 VSS
AC21 VSS
AC22 P_RX_VSS7
AC23 VDDIO33
AC24 N/C
AC25 MAD[28]
AC26 MAD[29]
AD1 N/C
AD2 TN/
AD3 N/C
AD4 P_TX_VDD1
AD5 VDDIO33
AD6 VDDIO33
AD7 P_RXB_VSS0
AD8 P_TXB_VDD1
AD9 P_RX_VSS2
AD10 P_RXB_VDD2
AD11 VSS
AD12 VSS
AD13 N/C
AD14 P_REFCLK_N
AD15 VSS
AD16 VSS
AD17 P_TX_VDD5
AD18 P_RX_VDD5
AD19 P_RXB_VDD6
AD20 VDDIO33
AD21 VDDIO33
AD22 VSS
AD23 P_RXB_VDD7
AD24 VDDIO33
AD25 MAD[31]
AD26 VDDIO33
AE1 VSS
AE2 P_TX0-
AE3 N/C
AE4 P_TX1+
Pin Signal Pin Signal Pin Signal
1. N/C pins are not connected.
24 of 30 LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller
DB08-000275-03 May 2006 - Version 2.0 Copyright © 2004–2006 by LSI Logic Corporation. All rights reserved.
Figure 4 LSISAS1064E 636 EPBGA-T – Top View (Sheet 1 of 2)
LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller 25 of 30
DB08-000275-03 May 2006 - Version 2.0 Copyright © 2004–2006 by LSI Logic Corporation. All rights reserved.
Figure 4 LSISAS1064E 636 EPBGA-T – Top View (Sheet 2 of 2)
26 of 30 LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller
DB08-000275-03 May 2006 - Version 2.0 Copyright © 2004–2006 by LSI Logic Corporation. All rights reserved.
Package Drawing
The LSISAS1064E uses a 636 EPBGA-T package. The package code
is 8C. Figure 5 provides the package drawing.
LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller 27 of 30
DB08-000275-03 May 2006 - Version 2.0 Copyright © 2004–2006 by LSI Logic Corporation. All rights reserved.
Figure 5 636-Ball EPBGA-T (8C) Mechanical Drawing (Sheet 1 of 3)
Important: This drawing may not be the latest version. For board layout and manufacturing,
obtain the most recent engineering drawings from your LSI marketing
representative by requesting the outline drawing for package code 8C.
28 of 30 LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller
DB08-000275-03 May 2006 - Version 2.0 Copyright © 2004–2006 by LSI Logic Corporation. All rights reserved.
Figure 5 636-Ball EPBGA-T (8C) Mechanical (Sheet 2 of 3); Bottom View (Cont.)
Important: This drawing may not be the latest version. For board layout and manufacturing,
obtain the most recent engineering drawings from your LSI marketing
representative by requesting the outline drawing for package code 8C.
LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller 29 of 30
DB08-000275-03 May 2006 - Version 2.0 Copyright © 2004–2006 by LSI Logic Corporation. All rights reserved.
Figure 5 636-Ball EPBGA-T (8C) Mechanical (Sheet 3 of 3); Bottom View (Cont.)
vB
Important: This drawing may not be the latest version. For board layout and manufacturing,
obtain the most recent engineering drawings from your LSI marketing
representative by requesting the outline drawing for package code 8C.
30 of 30 LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller
May 2006 Copyright © 2004–2006 by LSI Logic Corporation. All rights reserved.
LSI Logic products are not intended for use in life-support
appliances, devices, or systems. Use of any LSI Logic
product in such applications without written consent of the
appropriate LSI Logic officer is prohibited.
LSI Logic Corporation reserves the right to make changes
to any products and services herein at any time without
notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product
or service described herein, except as expressly agreed to
inwriting by LSI Logic; nor doesthe purchase, lease,or use
of a product or service from LSI Logic convey a license
underanypatentrights,copyrights,trademarkrights,orany
other of the intellectual property rights of LSI Logic or of
third parties.
Purchase of I2C components of LSI Logic Corporation, or
one of its sublicensed Associated Companies, conveys a
license under the Philips I2C Patent Rights to use these
components in an I2C system, provided that the system
conforms to the I2C standard Specification as defined by
Philips.
LSI Logic, the LSI Logic logo design, Fusion-MPT, Gflx,
GigaBlaze, Integrated Mirroring, Integrated RAID, and
Integrated Striping are trademarks or registered trademarks
of LSI Logic Corporation. ARM and Multi-ICE are registered
trademarks of ARM Ltd., used under license. PCI-X is a
registered trademark of PCI SIG. All other brand and
product names may be trademarks of their respective
companies.
AP
Doc. No. DB08-000275-03
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Notes
