Complete 16-Bit
CCD/CIS Signal Processor
Data Sheet
AD80066
FEATURES
16-bit, 24 MSPS analog-to-digital converter (ADC)
4-channel operation up to 24 MHz (6 MHz/channel)
3-channel operation up to 24 MHz (8 MHz/channel)
Selectable input range: 3 V or 1.5 V peak-to-peak
Input clamp circuitry
Correlated double sampling
1×~6× programmable gain
±300 mV programmable offset
Internal voltage reference
Multiplexed byte-wide output
Optional single-byte output mode
3-wire serial digital interface
3 V/5 V digital I/O compatibility
Power dissipation: 490 mW at 24 MHz operation
Reduced power mode and sleep mode available
28-lead SSOP package
APPLICATIONS
Flatbed document scanners
Film scanners
Digital color copiers
Multifunction peripherals
GENERAL DESCRIPTION
The AD80066 is a complete analog signal processor for imaging
applications. It features a 4-channel architecture designed to sample
and condition the outputs of linear charged coupled device (CCD)
or contact image sensor (CIS) arrays. Each channel consists of
an input clamp, correlated double sampler (CDS), offset digital-
to-analog converter (DAC), and programmable gain amplifier
(PGA), multiplexed to a high performance 16-bit ADC. For
maximum flexibility, the AD80066 can be configured as a
4-channel, 3-channel, 2-channel, or 1-channel device.
The CDS amplifiers can be disabled for use with sensors that
do not require CDS, such as CIS and CMOS sensors.
The 16-bit digital output is multiplexed into an 8-bit output word,
which is accessed using two read cycles. There is an optional
single-byte output mode. The internal registers are programmed
through a 3-wire serial interface and enable adjustment of the
gain, offset, and operating mode. The AD80066 operates from a
5 V power supply, typically consumes 490 mW of power, and is
packaged in a 28-lead SSOP.
FUNCTIONAL BLOCK DIAGRAM
DOUT
(D[0:7])
SCLK
SLOAD
SDATA
ADCCLK
OFFSET
AVDD AVSS CML AVDD CAPT CAPB
AD80066
DRVDD DRVSS
GAIN
REGISTERS
OFFSET
REGISTERS
4:1
MUX 16-BIT
ADC
CH. A
CH. B
CH. C
CH. D
8
16
CH. A
CH.B
CH. C
CH. D
6
9
PGA
PGA
PGA
CDS
CDS
CDS
AVSS
VIND
VINC
VINB
VINA
CDS
DIGITAL
CONTROL
INTERFACE
INPUT
CLAMP
BIAS
9-BIT
DAC
9-BIT
DAC
9-BIT
DAC
9-BIT
DAC
PGA
CONFIGURATION
REGISTER
MUX
REGISTER
CDSCLK2CDSCLK1
BAND GAP
REFERENCE
16:8
MUX
08552-001
Figure 1.
Rev. B Document Feedback
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AD80066 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Analog Specifications ................................................................... 3
Digital Specifications ................................................................... 4
Timing Specifications .................................................................. 5
Absolute Maximum Ratings ............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 12
Theory of Operation ...................................................................... 13
4-Channel CDS Mode ................................................................ 13
4-Channel SHA Mode................................................................ 13
1-Channel CDS Mode ............................................................... 13
1-Channel SHA Mode ............................................................... 13
Internal Register Map .................................................................... 14
Internal Register Details ................................................................ 15
Configuration Register .............................................................. 15
Mux Register ............................................................................... 15
PGA Gain Registers ................................................................... 15
Offset Registers ........................................................................... 15
Circuit Operation ........................................................................... 17
Analog Inputs—CDS Mode ...................................................... 17
External Input Coupling Capacitors ........................................ 17
Analog Inputs—SHA Mode ...................................................... 18
Programmable Gain Amplifiers (PGA) .................................. 18
Applications Information .............................................................. 19
Circuit and Layout Recommendations ................................... 19
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 20
REVISION HISTORY
4/15—Rev. A to Rev. B
Changes to Figure 7 .......................................................................... 7
4/10—Revision A: Initial Version
Rev. B | Page 2 of 20
Data Sheet AD80066
SPECIFICATIONS
ANALOG SPECIFICATIONS
TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V, CDS mode, fADCCLK = 24 MHz, fCDSCLK1 = fCDSCLK2 = 6 MHz, PGA gain = 1, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit
MAXIMUM CONVERSION RATE
4-Channel Mode with CDS 24 MSPS
3-Channel Mode with CDS 24 MSPS
2-Channel Mode with CDS 24 MSPS
1-Channel Mode with CDS 12 MSPS
ACCURACY (ENTIRE SIGNAL PATH)
ADC Resolution 16 Bits
Integral Nonlinearity (INL) +20/−5 LSB
Differential Nonlinearity (DNL) ±0.5 LSB
No Missing Codes Guaranteed
ANALOG INPUTS
Input Signal Range1 1.5/3.0 V p-p
Allowable Reset Transient1 2.0 V
Input Limits
2
AVSS − 0.3
AVDD + 0.3
V
Input Capacitance
10
pF
Input Bias Current 10 nA
AMPLIFIERS
PGA Gain Range 1 5.9 V/V
PGA Gain Resolution2 64 Steps
PGA Gain Monotonicity Guaranteed
Programmable Offset Range −305 +295 mV
Programmable Offset Resolution 512 Steps
Programmable Offset Monotonicity
Guaranteed
NOISE AND CROSSTALK
Total Output Noise at PGA Minimum
9.5
LSB rms
Total Output Noise at PGA Maximum
35
LSB rms
Channel-to-Channel Crosstalk
@ 24 MSPS 70 dB
@ 12 MSPS 90 dB
POWER SUPPLY REJECTION
AVDD = 5 V ± 0.25 V 0.1 % FSR
VOLTAGE REFERENCE (T
A
= 25°C)
CAPT − CAPB 0.75 V
TEMPERATURE RANGE
Operating 0 70 °C
Storage −65 +150 °C
POWER SUPPLIES
AVDD 4.5 5.0 5.25 V
DRVDD 3.0 3.3 5.25 V
OPERATING CURRENT
AVDD 95 mA
DRVDD 4 mA
Power-Down Mode Current 300 µA
Rev. B | Page 3 of 20
AD80066 Data Sheet
Parameter Min Typ Max Unit
POWER DISSIPATION
4-Channel Mode at 24 MHz 490 mW
1-Channel Mode at 12 MHz 300 mW
4-Channel Mode at 8 MHz, Slow Power Mode3 165 mW
1 The linear input signal range is up to 3 V p-p when the CCD reference level is clamped to 3 V by the AD80066 input clamp (see Figure 2).
2 The PGA gain is approximately linear-in-dB but varies nonlinearly with register code (see the Programmable Gain Amplifiers (PGA) section for more information).
3 Measured with Bit D1 of the configuration register set high for 8 MHz, low power operation.
Figure 2. Input Signal with the CCD Reference Level Clamped to 3 V
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V, CDS mode, fADCCLK = 24 MHz, fCDSCLK1 = fCDSCLK2 = 6 MHz, CL = 10 pF, unless otherwise noted.
Table 2.
Parameter Symbol Min Typ Max Unit
LOGIC INPUTS
High Level Input Voltage VIH 2.0 V
Low Level Input Voltage VIL 0.8 V
High Level Input Current IIH 10 µA
Low Level Input Current
I
IL
10
µA
Input Capacitance
C
IN
10
pF
LOGIC OUTPUTS (DRVDD = 5 V)
High Level Output Voltage (IOH = 2 mA) VOH 4.5 V
Low Level Output Voltage (IOL = 2 mA) VOL 0.5 V
LOGIC OUTPUTS (DRVDD = 3 V)
High Level Output Voltage (IOH = 2 mA) VOH 2.5 V
Low Level Output Voltage (I
OL
= 2 mA)
V
OL
0.5
V
Rev. B | Page 4 of 20
Data Sheet AD80066
TIMING SPECIFICATIONS
TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V.
Table 3.
Parameter Symbol Min Typ Max Unit
CLOCK PARAMETERS
4-Channel Pixel Rate tPRA 166 ns
1-Channel Pixel Rate tPRB 83 ns
ADCCLK Pulse Width tADCCLK 20 ns
CDSCLK1 Pulse Width tC1 15 ns
CDSCLK2 Pulse Width tC2 15 ns
CDSCLK1 Falling1 to CDSCLK2 Rising tC1C2 0 ns
ADCCLK Falling to CDSCLK2 Rising tADC2 0 ns
CDSCLK2 Rising to ADCCLK Rising tC2ADR 5 ns
CDSCLK2 Falling1 to ADCCLK Falling tC2ADF 20 ns
CDSCLK2 Falling1 to CDSCLK1 Rising tC2C1 5 ns
Aperture Delay for CDS Clocks tAD 2 ns
SERIAL INTERFACE
Maximum SCLK Frequency, Write Operation fSCLK 50 MHz
Maximum SCLK Frequency, Read Operation fSCLK 25 MHz
SLOAD to SCLK Setup Time tLS 5 ns
SCLK to SLOAD Hold Time tLH 5 ns
SDATA to SCLK Rising Setup Time tDS 2 ns
SCLK Rising to SDATA Hold Time tDH 2 ns
SCLK Falling to SDATA Valid tRDV 10 ns
DATA OUTPUT
Output Delay tOD 8 ns
Latency (Pipeline Delay)
3 (fixed)
Cycles
1 CDSCLKx falling edges should not occur within the first 10 ns following an ADCCLK edge.
Timing Diagrams
ANALOG
INPUTS
CDSCLK1
CDSCLK2
ADCCLK
OUTPUT
DATA
(D[7:0])
PIXEL n (A,B,C,D) PIXEL (n + 1)
tAD
tAD
tC2ADF
tC2ADR
tADC2
tOD
tADCCLK
tADCCLK
HIGH
BYTE LOW
BYTE HIGH
BYTE LOW
BYTE HIGH
BYTE LOW
BYTE HIGH
BYTE LOW
BYTE HIGH
BYTE LOW
BYTE HIGH
BYTE LOW
BYTE HIGH
BYTE HIGH
BYTE
LOW
BYTE
C(n – 2)B(n – 2) C(n – 2) D(n – 2) D(n – 2) A(n – 1) A(n – 1) B(n – 1) B(n – 1) C(n – 1) C(n – 1) D(n – 1) D(n – 1) A(n) A(n) B(n)
tPRA
tC2C1
tC1C2 tC2
tC1
08552-003
Figure 3. 4-Channel CDS Mode Timing
Rev. B | Page 5 of 20
AD80066 Data Sheet
t
OD
t
ADCCLK
t
ADCCLK
ANALOG
INPUTS
CDSCLK1
CDSCLK2
ADCCLK
OUTPUT
DATA
(D[7:0])
PIXEL n (A, B, C) PIXEL (n + 1) PIXEL (n + 2)
t
AD
t
AD
t
PRA
t
C2C1
t
C1
t
C2
t
C1C2
t
C2ADF
t
C2ADR
t
ADC2
HIGH
BYTE LOW
BYTE HIGH
BYTE LOW
BYTE HIGH
BYTE LOW
BYTE HIGH
BYTE LOW
BYTE HIGH
BYTE LOW
BYTE HIGH
BYTE LOW
BYTE HIGH
BYTE LOW
BYTE
B(n – 2)
A(n – 2) B(n – 2) C(n – 2) C(n – 2) A(n – 1) A(n – 1) B(n – 1) B(n – 1) C(n – 1) C(n – 1) A(n) A(n) B(n) B(n)
08552-004
Figure 4. 3-Channel CDS Mode Timing
CH 1 (n – 2) CH 2 (n – 2) CH 1 (n – 1) CH 2 ( n – 1) CH 1 ( n)
ANALOG
INPUTS
CDSCLK1
CDSCLK2
ADCCLK
OUTPUT
DATA
(D[7:0])
PIXEL n PIXEL (n + 1) PIXEL (n + 2)
tAD
tAD
tPRA
tC2C1
tC1
tADCCLK tADCCLK
tC2
tC1C2
tC2ADR
tC2ADF
tADC2
HIGH
BYTE LOW
BYTE HIGH
BYTE LOW
BYTE HIGH
BYTE LOW
BYTE HIGH
BYTE LOW
BYTE HIGH
BYTE LOW
BYTE
08552-005
Figure 5. 2-Channel CDS Mode Timing
Rev. B | Page 6 of 20
Data Sheet AD80066
ANALOG
INPUTS
CDSCLK1
PIXEL n PIXEL (n + 1) PIXEL (n + 2)
CDSCLK2
ADCCLK
OUTPUT
DATA
(D[7:0])
NOTES
1. I N 1- CHANNE L CDS M ODE. T HE CDS CLK1 F ALL ING E DGE AND T HE CDS CLK2 RI S ING E DGE M US T O CCUR WHI LE ADCCL K IS LO W.
LOW
BYTE HIGH
BYTE
HIGH
BYTE LOW
BYTE HIGH
BYTE LOW
BYTE
08552-006
t
AD
t
C1
t
AD
t
C2ADR
t
OD
t
C1C2
PIXEL (n – 4)
t
C2ADF
t
ADCCLK
t
ADCCLK
t
C2
PIXEL (n – 4) PIXEL (n – 3) PIXEL (n – 3) PIXEL (n – 2) PIXEL (n – 2)
t
C2C1
t
PRB
Figure 6. 1-Channel CDS Mode Timing
PIXEL n (A, B, C, D)
tAD
tC2 tC2ADF
t
ADC2 tC2ADR
tADCCLK
tADCCLK tOD
C(n – 2)
D(n – 2) D(n – 2) A(n – 1) A(n – 1) A(n) A(n) B(n) B(n)
HIGH
BYTE LOW
BYTE
HIGH
BYTE LOW
BYTE
HIGH
BYTE LOW
BYTE
HIGH
BYTE LOW
BYTE
HIGH
BYTE LOW
BYTE
HIGH
BYTE LOW
BYTE
HIGH
BYTE LOW
BYTE
tPRA
PIXEL (n + 1)
ANALOG
INPUTS
CDSCLK2
ADCCLK
OUTPUT
DATA
(D[7:0]) B(n – 1) B(n – 1) C(n – 1) C(n – 1) D(n – 1) D(n – 1)
08552-007
Figure 7. 4-Channel SHA Mode Timing
Rev. B | Page 7 of 20
AD80066 Data Sheet
Rev. B | Page 8 of 20
ANALOG
INPUTS
CDSCLK2
ADCCLK
OUTPUT
DATA
(D[7:0])
t
OD
PIXEL n
t
AD
HIGH BYTE LOW BYTE LOW BYTEHIGH BYTE HIGH BYTE LOW BYTE
PIXEL (n – 4) PIXEL (n – 4) PIXEL (n – 3) PI XEL (n – 3) PIXEL (n – 2) PIXEL (n – 2)
t
C2ADR
t
C2
t
PRB
t
C2ADF
t
ADCCLK
t
ADCCLK
0
8552-008
PIXEL (n + 1)
Figure 8. 1-Channel SHA Mode Timing
tOD tOD
HIG H BY TE
(DB[15:8]) HI GH BYT E
(DB[15:8]) LOW BYTE
(DB[7:0]) LOW BYTE
(DB[7:0]) HIGH BY TE
(DB[15:8])
ADCCLK
OUTPUT DATA
(D[7:0]) LOW BYTE
(DB[7:0])
PIXEL n PIXEL n
0
8552-009
PIXEL (n + 1) PIXEL (n + 1) PIXEL (n + 2) PIXEL (n + 3)
Figure 9. Digital Output Data Timing
t
OD
ADCCLK
OUTPUT DATA
(D[7:0])
PIXEL n PIXEL (n + 1)
HIGH BYTE
(DB[15:8])
HIGH BYTE
(DB[15:8])
HIGH BYTE
(DB[15:8])
08552-010
PIXEL (n + 2)
Figure 10. Single-Byte Mode Digital Output Data Timing
t
LH
D8 D7 D6 D5 D4 D3 D2 D1 D0
t
DS
t
LS
t
DH
A0A2
R/W
SDATA A1
SCLK
SLOAD
A3
0
8552-011
Figure 11. Serial Write Operation Timing
t
LH
D8 D7 D6 D5 D4 D3 D2 D1 D0
t
RDV
t
LS
A1A3 A2
SDATA
SCLK
S
LOAD
A0
R/W
08552-012
Figure 12. Serial Read Operation Timing
Data Sheet AD80066
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter With Respect To Rating
VINx, CAPT, CAPB AVSS −0.3 V to AVDD + 0.3 V
Digital Inputs
AVSS
−0.3 V to AVDD + 0.3 V
SDATA DRVSS −0.3 V to DRVDD
AVDD AVSS −0.5 V to +6.5 V
DRVDD DRVSS −0.5 V to +6.5 V
AVSS DRVSS −0.3 V to +0.3 V
Digital Outputs
(D[7:0])
DRVSS −0.3 V to DRVDD + 0.3 V
Temperature
Junction 150°C
Storage −65°C to +150°C
Lead (10 sec) 300°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 5. Thermal Resistance
Package Type θJA θJC Unit
28-Lead, 5.3 mm SSOP 109 39 °C/W
ESD CAUTION
Rev. B | Page 9 of 20
AD80066 Data Sheet
Rev. B | Page 10 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD80066
TO P VI EW
(No t to S cale)
AVDD AVSS
D6
D5
D4
D3
D2
D1
(LSB) D0
CDSCLK1
CDSCLK2
ADCCLK
DRVDD
DRVSS
(MSB) D7
VINA
OFFSET
VINB
CML
VINC
CAPT
CAPB
VIND
AVDD
SLOAD
SCLK
SDATA
AVSS
1
2
3
4
28
27
26
25
5
6
7
24
23
22
821
920
10 19
11 18
12 17
13 16
14 15
08552-013
Figure 13. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1 AVDD P 5 V Analog Supply.
2 CDSCLK1 DI CDS Reference Level Sampling Clock.
3 CDSCLK2 DI CDS Data Level Sampling Clock.
4 ADCCLK DI ADC Sampling Clock.
5 DRVDD P Digital Output Driver Supply (3 V or 5 V).
6 DRVSS P Digital Output Driver Ground.
7 D7 (MSB) DO Data Output MSB. ADC DB15 high byte; ADC DB7 low byte.
8 D6 DO Data Output. ADC DB14 high byte; ADC DB6 low byte.
9 D5 DO Data Output. ADC DB13 high byte; ADC DB5 low byte.
10 D4 DO Data Output. ADC DB12 high byte; ADC DB4 low byte.
11 D3 DO Data Output. ADC DB11 high byte; ADC DB3 low byte.
12 D2 DO Data Output. ADC DB10 high byte; ADC DB2 low byte.
13 D1 DO Data Output. ADC DB9 high byte; ADC DB1 low byte.
14 D0 (LSB) DO Data Output LSB. ADC DB8 high byte; ADC DB0 low byte.
15 SDATA DI/DO Serial Interface Data Input/Output.
16 SCLK DI Serial Interface Clock Input.
17 SLOAD DI Serial Interface Load Pulse.
18 AVDD P 5 V Analog Supply.
19 AVSS P Analog Ground.
20 VIND AI Analog Input, D Channel.
21 CAPB AO ADC Bottom Reference Voltage Decoupling.
22 CAPT AO ADC Top Reference Voltage Decoupling.
23 VINC AI Analog Input, C Channel.
24 CML AO Internal Bias Level Decoupling.
25 VINB AI Analog Input, B Channel.
26 OFFSET AO Clamp Bias Level Decoupling.
27 VINA AI Analog Input, A Channel.
28 AVSS P Analog Ground.
1 AI = analog input, AO = analog output, DI = digital input, DO = digital output, and P = power.
Data Sheet AD80066
Rev. B | Page 11 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
0 64,00025,60012,800 38,400 51,200
0
–1.0
1.0
0.5
–0.5
ADC OUT P UT CO DE
DNL (LSB )
08552-014
Figure 14. Typical DNL Performance
PGA REGI STER VALUE (Decimal)
0015
OUTPUT NOISE (LSB)
25
50
30 45 63
10
5
15
20
45
30
35
40
08552-015
Figure 15. Output Noise vs. PGA Gain
0 64,00025,60012,800 38,400 51,200
5
–5
15
10
0
ADC OUT P UT CO DE
INL (LSB)
08552-016
Figure 16. Typical INL Performance
AD80066 Data Sheet
TERMINOLOGY
Integral Nonlinearity (INL)
Integral nonlinearity error refers to the deviation of each
individual code from a line drawn from zero scale through
positive full scale. The point used as zero scale occurs ½ LSB
before the first code transition. Positive full scale is defined as a
level 1½ LSB beyond the last code transition. The deviation is
measured from the middle of each particular code to the true
straight line.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value; therefore, every
code must have a finite width. No missing codes guaranteed to
16-bit resolution indicates that all 65,536 codes must be present
over all operating ranges.
Offset Error
The first ADC code transition should occur at a level ½ LSB above
the nominal zero-scale voltage. The offset error is the deviation
of the actual first code transition level from the ideal level.
Gain Error
The last code transition should occur for an analog value
1½ LSB below the nominal full-scale voltage. Gain error is the
deviation of the actual difference between the first and last code
transitions and the ideal difference between the first and last
code transitions.
Input-Referred Noise
The rms output noise is measured using histogram techniques. The
standard deviation of the ADC output codes is calculated in LSB
and converted to an equivalent voltage, using the relationship
1 LSB = 1.5 V/65,536 = 23 µV. The noise is then referred to the
input of the AD80066 by dividing by the PGA gain.
Channel-to-Channel Crosstalk
In an ideal 3-channel system, the signal in one channel does not
influence the signal level of another channel. The channel-to-
channel crosstalk specification is a measure of the change that
occurs in one channel as the other two channels are varied. In
the AD80066, one channel is grounded and the other two channels
are exercised with full-scale input signals. The change in the output
codes from the first channel is measured and compared with the
result when all three channels are grounded. The difference is
the channel-to-channel crosstalk, stated in LSB.
Aperture Delay
The aperture delay is the delay that occurs from when a sampling
edge is applied to the AD80066 until the actual sample of the
input signal is held. Both CDSCLK1 and CDSCLK2 sample the
input signal during the transition from high to low; therefore,
the aperture delay is measured from each falling edge of the
clock to when the internal sample is taken.
Power Supply Rejection
The power supply rejection specifies the maximum full-scale
change that occurs from the initial value when the supplies are
varied over the specified limits.
Rev. B | Page 12 of 20
Data Sheet AD80066
THEORY OF OPERATION
The AD80066 can be operated in several different modes,
including 4-channel CDS mode, 4-channel SHA mode, 1-channel
CDS mode, and 1-channel SHA mode. Each mode is selected
by programming the configuration register through the serial
interface. For more information on CDS or SHA mode operation,
see the Circuit Operation section.
4-CHANNEL CDS MODE
In 4-channel CDS mode, the AD80066 simultaneously samples
the A, B, C, and D input voltages from the CCD outputs. The
sampling points for each CDS are controlled by CDSCLK1 and
CDSCLK2 (see Figure 17 and Figure 18). The CDSCLK1 falling
edge samples the reference level of the CCD waveform, and the
CDSCLK2 falling edge samples the data level of the CCD wave-
form. Each CDS amplifier outputs the difference between the
CCD reference level and the data level. The output voltage of
each CDS amplifier is then level-shifted by an offset DAC. The
voltages are scaled by the four PGAs before being multiplexed
through the 16-bit ADC. The ADC sequentially samples the
PGA outputs on the falling edges of ADCCLK.
The offset and gain values for the A, B, C, and D channels are
programmed using the serial interface. The order in which the
channels are switched through the multiplexer is selected by
programming the mux register.
Timing for this mode is shown in Figure 3. The falling edge of
CDSCLK2 should occur coincident with or before the rising
edge of ADCCLK. However, this is not required to satisfy the
minimum timing constraints. The rising edge of CDSCLK2
should not occur before the previous falling edge of ADCCLK,
as shown by tADC2. The output data latency is 3 ADCCLK cycles.
4-CHANNEL SHA MODE
In 4-channel SHA mode, the AD80066 simultaneously samples
the A, B, C, and D input voltages. The sampling point is controlled
by CDSCLK2. The falling edge of CDSCLK2 samples the input
waveforms on each channel. The output voltages from the three
SHAs are modified by the offset DACs and then scaled by the
four PGAs. The outputs of the PGAs are then multiplexed
through the 16-bit ADC. The ADC sequentially samples the
PGA outputs on the falling edges of ADCCLK.
The input signal is sampled with respect to the voltage applied to
the OFFSET pin (see Figure 19). With the OFFSET pin grounded,
a 0 V input corresponds to the zero-scale output of the ADC.
The OFFSET pin can also be used as a coarse offset adjustment
pin. A voltage applied to this pin is subtracted from the voltages
applied to the A, B, C, and D inputs in the first amplifier stage
of the AD80066. The input clamp is disabled in this mode. For
more information, see the Analog Inputs—SHA Mode section.
The offset and gain values for the A, B, C, and D channels are
programmed using the serial interface. The order in which the
channels are switched through the multiplexer is selected by
programming the mux register.
Timing for this mode is shown in Figure 7. The CDSCLK1 pin
should be grounded in this mode. Although not required, the
falling edge of CDSCLK2 should occur coincident with or before
the rising edge of ADCCLK. The rising edge of CDSCLK2 should
not occur before the previous falling edge of ADCCLK, as shown
by tADC2. The output data latency is 3 ADCCLK cycles.
1-CHANNEL CDS MODE
The 1-channel CDS mode operates in the same way as the
4-channel CDS mode, except the multiplexer remains fixed.
Only the channel specified in the mux register is processed.
Timing for this mode is shown in Figure 6.
1-CHANNEL SHA MODE
The 1-channel SHA mode operates in the same way as the
4-channel SHA mode, except the multiplexer remains fixed.
Only the channel specified in the mux register is processed.
Timing for this mode is shown in Figure 8. The CDSCLK1 pin
should be grounded in this mode of operation.
Rev. B | Page 13 of 20
AD80066 Data Sheet
INTERNAL REGISTER MAP
Table 7. Internal Register Map
Address Data Bits
Register Name A3 A2 A1 A0 D8 D7 D6 D5 D4 D3 D2 D1 D0
Configuration 0 0 0 0 0 0 0 VREF 2/1 byte CDS on Input range Fast/slow Power on
Mux 0 0 0 1 0 0 0 0 Ch. order Ch. A Ch. B Ch. C Ch. D
Gain A 0 0 1 0 0 0 0 MSB LSB
Gain B 0 0 1 1 0 0 0 MSB LSB
Gain C 0 1 0 0 0 0 0 MSB LSB
Gain D 0 1 0 1 0 0 0 MSB LSB
Offset A 0 1 1 0 MSB LSB
Offset B 0 1 1 1 MSB LSB
Offset C
1
0
0
0
MSB
LSB
Offset D 1 0 0 1 MSB LSB
Rev. B | Page 14 of 20
Data Sheet AD80066
INTERNAL REGISTER DETAILS
CONFIGURATION REGISTER
The configuration register controls the AD80066 operating mode
and bias levels. The D8, D7, and D6 bits should always be set low.
Bit D2 sets the full-scale input voltage range of the AD80066 ADC
to either 3 V (high) or 1.5 V (low). Bit D5 controls the internal
voltage reference. If the AD80066 internal voltage reference is
used, this bit is set low. Setting Bit D5 high disables the internal
voltage reference, allowing an external voltage reference to be
used. Setting Bit D3 low enables the CDS mode of operation and
setting this bit high enables the SHA mode of operation. If Bit D4
is set high, the 16-bit ADC output is multiplexed into two bytes.
The most significant byte is output on the ADCCLK rising edge,
and the least significant byte is output on the ADCCLK falling
edge (see Figure 10). If Bit D1 is set high, the AD80066 is con-
figured for slow operation (8 MHz) to reduce power consumption.
Bit D0 controls the power-down mode. Setting Bit D0 low places the
AD80066 into a very low power sleep mode. All register contents
are retained while the AD80066 is in the power-down state.
MUX REGISTER
The mux register controls the sampling channel order in the
AD80066. The D8, D7, D6, and D5 bits should always be set
low. Bit D4 is used when operating in 4-channel mode. Setting
Bit D4 low sequences the multiplexer to sample the A channel
first, and then the B, C, and D channels. When in this mode,
the CDSCLK2 pulse always resets the multiplexer to sample the
A channel first. When Bit D4 is set high, the channel order is
reversed to D, C, B, and A. The CDSCLK2 pulse always resets the
multiplexer to sample the D channel first. Bits D[3:0] are used
when operating in 1-channel mode. Bit D3 is set high to sample
the A channel. Bit D2 is set high to sample the B channel. Bit D1
is set high to sample the C channel. Bit D0 is set high to sample the
D channel. The multiplexer remains stationary in 1-channel mode.
PGA GAIN REGISTERS
There are four PGA registers for individually programming the
gain for the A, B, C, and D channels. The D8, D7, and D6 bits in
each register must be set low, and the D5 through D0 bits control
the gain range in 64 increments. See Figure 22 for the PGA gain vs.
the PGA register value. The coding for the PGA registers is straight
binary, with a word of all 0s corresponding to the minimum gain
setting (1×) and a word of all 1s corresponding to the maximum
gain setting (5.9×).
OFFSET REGISTERS
There are four offset registers for individually programming the
offset in the A, B, C, and D channels. The D8 through D0 bits
control the offset range from −300 mV to +300 mV in 512 incre-
ments. The coding for the offset registers is sign magnitude, with
D8 as the sign bit. Table 11 shows the offset range as a function
of the D8 through D0 bits.
Table 8. Configuration Register Settings
D8 D7 D6 D5 D4 D3 D2 D1 D0
Set to 0 Set to 0 Set to 0 Internal voltage
reference
2/1 byte output CDS operation Input range Fast/slow Power mode
1 = disabled
1 = one byte
1 = SHA mode
1 = 3 V
1 = 8 MHz
1 = on (normal)
0 = enabled1 0 = two bytes1 0 = CDS mode1 0 = 1.5 V1 0 = 24 MHz1 0 = off1
1 Power-on default.
Table 9. Mux Register Settings
D8 D7 D6 D5 D4 D3 D2 D1 D0
Set to 0 Set to 0 Set to 0 Set to 0 Mux order Channel A Channel B Channel C Channel D
1 = D, C, B, A
1 = channel used 1 = channel used 1 = channel used 1 = channel used
0 = A, B, C, D1 0 = not used1 0 = not used1 0 = not used1 0 = not used1
1 Power-on default.
Table 10. PGA Gain Register Settings
(MSB) (LSB)
D81 D71 D61 D5 D4 D3 D2 D1 D0 Gain (V/V) Gain (dB)
0 0 0 0 0 0 0 0 02 1.0 0.0
0
0
0
0
0
0
0
0
1
1.013
0.12
… … … … … … … … … … …
0 0 0 1 1 1 1 1 0 5.56 14.9
0 0 0 1 1 1 1 1 1 5.9 15.56
1 Must be set to 0.
2 Power-on default.
Rev. B | Page 15 of 20
AD80066 Data Sheet
Table 11. Offset Register Settings
(MSB) (LSB)
D8 D7 D6 D5 D4 D3 D2 D1 D0 Offset (mV)
0 0 0 0 0 0 0 0 01 0
0 0 0 0 0 0 0 0 1 +1.2
… … … … … … … … … …
0 1 1 1 1 1 1 1 1 +300
1 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 1 −1.2
… … … … … … … … … …
1 1 1 1 1 1 1 1 1 −300
1 Power-on default value.
Rev. B | Page 16 of 20
Data Sheet AD80066
Rev. B | Page 17 of 20
CIRCUIT OPERATION
ANALOG INPUTS—CDS MODE
Figure 17 shows the analog input configuration for the CDS
mode of operation. Figure 18 shows the internal timing for the
sampling switches. The CCD reference level is sampled when
CDSCLK1 transitions from high to low, opening S1. The CCD
data level is sampled when CDSCLK2 transitions from high to
low, opening S2. S3 is then closed, generating a differential
output voltage that represents the difference between the two
sampled levels.
The input clamp is controlled by CDSCLK1. When CDSCLK1
is high, S4 closes and the internal bias voltage is connected to
the analog input. The bias voltage charges the external 0.1 μF
input capacitor, level-shifting the CCD signal into the input
common-mode range of the AD80066. The time constant of the
input clamp is determined by the internal 5 kΩ resistance and
the external 0.1 μF input capacitance.
AD80066
S1
S2
2pF
S3
2pF
CML
CML
AVDD
S4
5kΩ
1.7kΩ
OFFSET
CIN
0.1µF
CCD SIGNAL
0.1µF1µF+
3V 2.2kΩ
6.9kΩ
VINA
0
8552-017
Figure 17. CDS Mode Input Configuration (All Four Channels Are Identical)
CDSCLK1
CDSCLK2
Q3
(INTERNAL)
S1, S4 CLOSED S1, S4 CLOSED
S2 CLOSED S2 CLOSED
S3 CLOSED S3 CLOSED
S3 OPEN
S2 OPEN
S1, S4 OPEN
08552-018
Figure 18. CDS Mode Internal Switch Timing
EXTERNAL INPUT COUPLING CAPACITORS
The recommended value for the input coupling capacitors is
0.1 μF. Although it is possible to use a smaller capacitor, this
larger value is preferable for several reasons:
Signal attenuation: The input coupling capacitor creates
a capacitive divider using the input capacitance from an
integrated CMOS circuit, which, in turn, attenuates the
CCD signal level. CIN should be large relative to the 10 pF
input capacitance of the IC in order to minimize this effect.
Linearity: Some of the input capacitance of a CMOS IC is
junction capacitance, which varies nonlinearly with applied
voltage. If the input coupling capacitor is too small, the
attenuation of the CCD signal varies nonlinearly with signal
level. This degrades the system linearity performance.
Sampling errors: The internal 2 pF sampling capacitors retain
a memory of the previously sampled pixel. There is a charge
redistribution error between CIN and the internal sample
capacitors for larger pixel-to-pixel voltage swings. As the
value of CIN is reduced, the resulting error in the sampled
voltage increases. With a CIN value of 0.1 μF, the charge
redistribution error is less than 1 LSB for a full-scale, pixel-
to-pixel voltage swing.
AD80066 Data Sheet
Rev. B | Page 18 of 20
ANALOG INPUTS—SHA MODE
Figure 19 shows the analog input configuration for the SHA
mode of operation. Figure 20 shows the internal timing for the
sampling switches. The input signal is sampled when CDSCLK2
transitions from high to low, opening S1. The voltage on the
OFFSET pin is also sampled on the falling edge of CDSCLK2,
when S2 opens. S3 is then closed, generating a differential
output voltage that represents the difference between the
sampled input voltage and the OFFSET voltage. The input
clamp is disabled during SHA mode operation.
AD80066
S1 2pF
S3
CML
INPUT SIGNAL
S2 2pF
CML
OFFSET
OPTIONAL DC OFFSET
(OR CONNECT TO GND)
VINA
VINB
VINC
VIND
A
B
C
D
CML
CML
CML
CML
CML
CML
08552-019
Figure 19. SHA Mode Input Configuration (All Four Channels Are Identical)
CDSCLK2
Q3
(INTERNAL)
S1, S2 CLOSED S1, S2 CLOSED
S3 CLOSED S3 CLOSED
S3 OPEN
S1, S2 OPEN
08552-020
Figure 20. SHA Mode Internal Switch Timing
Figure 21 shows how the OFFSET pin can be used in a CIS
application for coarse offset adjustment. Many CIS signals have
dc offsets ranging from several hundred millivolts to more than
1 V. By connecting the appropriate dc voltage to the OFFSET pin,
the large dc offset is removed from the CIS signal. Then, the
signal can be scaled using the PGA to maximize the dynamic
range of the ADC.
AD80066
OFFSET
A OFFSET
VINA
VINB
VINC
0.1µF
AVDD
VOLTAGE
REFERENCE
FROM CIS
MODULE
R1
B OFFSET
C OFFSET
DC OFFSET
R2
SHA
SHA
SHA
08552-021
Figure 21. SHA Mode Used with External DC Offset
PROGRAMMABLE GAIN AMPLIFIERS (PGA)
The AD80066 uses one PGA for each channel. Each PGA has a
gain range from 1× (0 dB) to 5.8× (15.5 dB), adjustable in
64 steps. Figure 22 shows the PGA gain as a function of the
PGA register value. Although the gain curve is approximately
linear-in-dB, the gain in V/V varies nonlinearly with register
code, following the equation
63
63
4.91
5.9
G
Gain
where G is the decimal value of the gain register contents and
varies from 0 to 63.
GAIN (V/V)
5.9
PGA REGISTER VALUE (Decimal)
0
GAIN (dB)
1
5
12
9
6
3
0
5.0
4.0
3.0
2.0
1.0
4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 63
08552-022
Figure 22. PGA Gain Transfer Function
Data Sheet AD80066
APPLICATIONS INFORMATION
CIRCUIT AND LAYOUT RECOMMENDATIONS
Figure 23 shows the recommended circuit configuration for
4-channel CDS mode operation. The recommended input
coupling capacitor value is 0.1 µF (see the Analog Inputs—CDS
Mode section). A single ground plane is recommended for the
AD80066. A separate power supply can be used for DRVDD,
the digital driver supply, but this supply pin should still be
decoupled to the same ground plane as the rest of the AD80066.
The loading of the digital outputs should be minimized, either
by using short traces to the digital ASIC or by using external
digital buffers. To minimize the effect of digital transients
during major output code transitions, the falling edge of
CDSCLK2 should occur coincident with or before the rising
edge of ADCCLK (see Figure 3 through Figure 8 for timing).
All 0.1 µF decoupling capacitors should be located as close as
possible to the AD80066 pins. When operating in 1-channel
mode, the unused analog inputs should be grounded.
Figure 24 shows the recommended circuit configuration for
4-channel SHA mode. All of the previously explained consid-
erations also apply to this configuration, except that the analog
input signals are directly connected to the AD80066 without the
use of coupling capacitors. Before connecting the signals, the
analog input signals must be dc-biased between 0 V and 1.5 V
or 3 V (see the Analog Inputs—SHA Mode section).
CLOCK
INPUTS
TOP VIEW
(No t t o Scal e)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD80066
AVDD AVSS
A INPUT
DATA
INPUTS
3.3V
5V
5V
SERIAL
INTERFACE
VINA
OFFSET
VINB
CML
VINC
CAPT
CAPB
VIND
AVSS
AVDD
SLOAD
SCLK
SDATA
CDSCLK1
CDSCLK2
ADCCLK
DRVDD
DRVSS
(MSB) D7
D6
D5
D4
D3
D2
D1
(LSB) D0
C INPUT
D INPUT
B INPUT
0.1µF 0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
1.0µF
0.1µF
0.1µF
10µF 0.1µF
0.1µF
08552-023
Figure 23. Recommended Circuit Configuration, 4-Channel CDS Mode
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
2
CLOCK
INPUTS
AVDD
DATA
INPUTS
3.3V
5V
CDSCLK1
CDSCLK2
ADCCLK
DRVDD
DRVSS
(MSB) D7
D6
D5
D4
D3
D2
D1
(LSB) D0
0.1µF
0.1µF
TOP VIEW
(No t t o Scal e)
AD80066
A INPUT
5V
SERIAL
INTERFACE
C INPUT
D INPUT
B INPUT
0.1µF
0.1µF
0.1µF
10µF0.1µF
0.1µF
AVSS
VINA
OFFSET
VINB
CML
VINC
CAPT
CAPB
VIND
AVSS
AVDD
SLOAD
SCLK
SDATA
08552-024
Figure 24. Recommended Circuit Configuration, 4-Channel SHA Mode (Analog Inputs Sampled with Respect to Ground)
Rev. B | Page 19 of 20
AD80066 Data Sheet
OUTLINE DIMENSIONS
COMPLIANT TO JE DE C S TANDARDS MO-150- AH
060106-A
28 15
14
1
10.50
10.20
9.90
8.20
7.80
7.40
5.60
5.30
5.00
SEATING
PLANE
0.05 M IN
0.65 BSC
2.00 M AX
0.38
0.22
COPLANARITY
0.10
1.85
1.75
1.65
0.25
0.09
0.95
0.75
0.55
8°
4°
0°
Figure 25. 28-Lead Shrink Small Outline Package [SSOP]
(RS-28)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD80066KRSZ 0°C to 70°C 28-Lead SSOP RS-28
AD80066KRSZRL 0°C to 70°C 28-Lead SSOP RS-28
1 Z = RoHS Compliant Part.
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08552-0-4/15(B)
Rev. B | Page 20 of 20