ICL7660SIBAZAT - Intersil Corporation

FN3179.5

ICL7660S

Super Voltage Converter

The ICL7660S Super Volt ag e Converter is a monolithic

CMOS voltage conversion IC that guarante es significa nt

performance advantages over other simi lar devi ce s. It is a

direct replacement for the indu stry st andard ICL 7660 offering

an extended operating supply voltage range up to 12V, with

lower supply current. No external diode is n eeded fo r the

ICL7660S. In addition, a Frequency Boost pin has be en

incorporated to enable th e user to achieve lower output

impedance despite using smaller cap aci tors. All

improvements are highlighted in the “Electrical S pecification s”

section on pa ge 3. Critical p arameters are guaranteed over

the entire commercial, industrial and milit ary temperature

ranges.

The ICL7660S performs supply voltage conversion from

positive to negative for an i nput range of 1.5V to 12V,

resulting in complementary output voltages of -1.5V to -12V.

Only 2 non-critical external capacitors are needed for the

charge pump and charge reservoir functions. The ICL7660S

can be connected to function as a voltage doubler and will

generate up to 22.8V with a 12V input. It can also be used as

a voltage multiplier or voltage divider.

The chip contains a series DC power supply regulator, RC

oscillator, voltage level translator, and four output power

MOS switches. The oscillator , when unloaded, oscillates at a

nominal frequency of 10kHz for an input supply voltage of

5.0V. This frequency can be lowered by the additi on of an

external capacitor to the “OSC” terminal, or the oscillator

may be over-driven by an external clock.

The “LV” terminal may be tied to GND to bypass the internal

series regulator and improve low voltage (LV) operation. At

medium to high voltages (3.5V to 12V), the LV pin is left

floating to prevent device latchup.

Pinout ICL7660S

(8 LD PDIP, SOIC)

TOP VIEW

Features

• Guaranteed Lower Max Supply Current for All

Temperature Ranges

• Wide Operating Voltage Range 1.5V to 12V

• 100% Tested at 3V

• No External Diode Over Full Temperature and Voltage

Range

• Boost Pin (Pin 1) for Higher Switching Frequency

• Guaranteed Minimum Power Efficiency of 96%

• Improved Minimum Open Circuit Voltage Conversion

Efficiency of 99%

• Improved SCR Latchup Protection

• Simple Conversion of +5V Logic Supply to ±5V Supplies

• Simple Voltage Multiplication VOUT = (-)nVIN

• Easy to Use - Requires Only 2 External Non-Critical

Passive Components

• Improved Direct Replacement fo r Industry Standard

ICL7660 and Other Second Source Devices

• Pb-Free Available (RoHS Compliant)

Applications

• Simple Conversion of +5V to ±5V Supplies

• Voltage Multiplication VOUT = ±nVIN

• Negative Supplies for Data Acquisition Systems and

Instrumentation

• RS232 Power Supplies

• Supply Splitter, VOUT = ±VS/2

BOOST

CAP+

GND

CAP-

V+

OSC

VOUT

Data Sheet March 6, 2008

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

2FN3179.5

March 6, 2008

Ordering Information

PART NUMBER PART MARKING TEMP. RANGE

(°C) PACKAGE PK G. D W G. #

ICL7660SCBA 7660 SCBA 0 to +70 8 Ld SOIC M8.15

ICL7660SCBA-T

(Note 3) 7660 SCBA 0 to +70 8 Ld SOIC Tape and Reel M8.15

ICL7660SCBAZ

(Note 1) 7660 SCBAZ 0 to +70 8 Ld SOIC

(Pb-free) M8.15

ICL7660SCBAZ-T

(Notes 1, 3) 7660 SCBAZ 0 to +70 8 Ld SOIC Tape and Reel

(Pb-free) M8.15

ICL7660SCPA 7660S CPA 0 to +70 8 Ld PDIP E8.3

ICL7660SCPAZ

(Note 1) 7660S CPAZ 0 to +70 8 Ld PDIP*

(Pb-free) E8.3

ICL7660SIBA 7660 SIBA -40 to +85 8 Ld SOIC M8.15

ICL7660SIBAT

(Note 3) 7660 SIBA -40 to +85 8 Ld SOIC Tape and Reel M8.15

ICL7660SIBAZ

(Note 1) 7660 SIBAZ -40 to +85 8 Ld SOIC

(Pb-free) M8.15

ICL7660SIBAZT

(Notes 1, 3) 7660 SIBAZ -40 to +85 8 Ld SOIC Tape and Reel

(Pb-free) M8.15

ICL7660SIPA 7660 SIPA -40 to +85 8 Ld PDIP E8.3

ICL7660SIPAZ

(Note 1) 7660S IPAZ -40 to +85 8 Ld PDIP*

(Pb-free) E8.3

*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.

NOTES:

1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%

matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering

operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of

IPC/JEDEC J STD-020.

2. Add /883B to part number if 883B processing is required.

3. Please refer to TB347 for details on reel specifications.

ICL7660S

3FN3179.5

March 6, 2008

Absolute Maximum Ratings Thermal Information

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13.0V

LV and OSC Input Voltage (Note 4)

V+ < 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V+ + 0.3V

V+ > 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . .V+ -5.5V to V+ +0.3V

Current into LV (Note 4)

V+ > 3.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20μA

Output Short Duration

VSUPPLY ≤ 5.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Continuous

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C

Operating Conditions

Temperature Range

ICL7660SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

ICL7660SC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Thermal Resistance (Typical, Note 5) θJA (°C/W)

8 Ld PDIP* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

8 Ld Plastic SOIC. . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

*Pb-free PDIPs can be used for through hole wave solder

processing only. They are not intended for use in Reflow solder

processing. applications.

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

4. Connecting any terminal to voltages greater than V+ or less than GND may cause destructive latchup. It is recommended that no inputs from

sources operating from external supplies be applied prior to “power up” of ICL7660S.

5. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications V+ = 5V, TA = +25°C, OSC = Free running, Test Circuit Figure 12, Unless Otherwise Specified.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Supply Current (Note 8) I+ RL = ∞, +25°C - 80 160 µA

0°C < TA < +70°C - - 180 µA

-40°C < TA < +85°C - - 180 µA

-55°C < TA < +125°C - - 200 µA

Supply Voltage Range - High

(Note 9) V+HRL = 10k, LV Open, TMIN < TA < TMAX 3.0 - 12 V

Supply Voltage Range - Low V+LRL = 10k, LV to GND, TMIN < TA < TMAX 1.5 - 3.5 V

Output Source Resistance ROUT IOUT = 20mA - 60 100 Ω

IOUT = 20mA, 0°C < TA < +70°C - - 120 Ω

IOUT = 20mA, -25°C < TA < +85°C - - 120 Ω

IOUT = 20mA, -55°C < TA < +125°C - - 150 Ω

IOUT = 3mA, V+ = 2V, LV = GND,

0°C < TA < +70°C - - 250 Ω

IOUT = 3mA, V+ = 2V, LV = GND,

-40°C < TA < +85°C - - 300 Ω

IOUT = 3mA, V+ = 2V, LV = GND,

-55°C < TA < +125°C - - 400 Ω

Oscillator Frequency (Note 7) fOSC COSC = 0, Pin 1 Open or GND 5 10 - kHz

COSC = 0, Pin 1 = V+ - 35 - kHz

Power Efficiency PEFF RL = 5kΩ96 98 - %

TMIN < TA < TMAX RL = 5kΩ95 97 - -

V o ltage Conversion Efficiency VOUTEFF RL = ∞99 99.9 - %

ICL7660S

4FN3179.5

March 6, 2008

Oscillator Impedance ZOSC V+ = 2V - 1 - MΩ

V+ = 5V - 100 - kΩ

NOTES:

6. Derate linearly above +50°C by 5.5mW/°C

7. In the test circuit, there is no external capacitor applied to pin 7. However, when the device is plugged into a test socket, there is usually a very

small but finite stray capacitance present, of the order of 5pF.

8. The Intersil ICL7660S can operate without an external diode over the full temperature and voltage range. This device will function in existing

designs which incorporate an external diode with no degradation in overall circuit performance.

9. All significant improvements over the industry standard ICL7660 are highlighted.

Electrical Specifications V+ = 5V, TA = +25°C, OSC = Free running, Test Circuit Figure 12, Unless Otherwise Specified. (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Typical Performance Curves (Test Circuit Figure 12)

FIGURE 1. OPERA TING VOL T AGE AS A

FUNCTION OF TEMPERATURE FIGURE 2. OUTPUT SOURCE RESIST ANCE AS A

FUNCTION OF SUPPLY VOLTAGE

FIGURE 3. OUTPUT SOURCE RESISTANCE AS A

FUNCTION OF TEMPERATURE FIGURE 4. POWER CONVERSION EFFICIENCY AS A

FUNCTION OF OSCILLATOR FREQUENCY

-55 -25 0 25 50 100 125

SUPPLY VOLTAGE (V)

TEMPERATURE (°C)

SUPPLY VOLTAGE RANGE

(NO DIODE REQUIRED)

250

200

150

100

002 4681012

SUPPLY VOLTAGE (V)

OUTPUT SOURCE RESISTANCE (W)

TA = +125°C

TA = +25°C

TA = -55°C

350

300

250

200

150

100

OUTPUT SOURCE RESISTANCE (Ω)

-50 -25 0 25 50 75 100 125

TEMPERATURE (°C)

IOUT = 20mA,

V+ = 12V

IOUT = 20mA,

V+ = 5V

IOUT = 20mA,

V+ = 5V

IOUT = 3mA,

V+ = 2V

POWER CONVERSION EFFICIENCY (%)

100 1k 10k 50k

OSC FREQUENCY fOSC (Hz)

V+ = 5V

TA = +25°C

IOUT = 1mA

ICL7660S

5FN3179.5

March 6, 2008

FIGURE 5. FREQUENCY OF OSCILLA TION AS A FUNCTION

OF EXTERNAL OSCILLATOR CAPACITANCE FIGURE 6. UNLOADED OSCILLATOR FREQUENCY AS A

FUNCTION OF TEMPERATURE

FIGURE 7. OUTPUT VOLTAGE AS A FUNCTION

OF OUTPUT CURRENT FIGURE 8. SUPPLY CURRENT AND POWER CONVERSION

EFFICIENCY AS A FUNCTION OF LOAD

CURRENT

FIGURE 9. OUTPUT VOL TAGE AS A FUNCTION OF OUTPUT

CURRENT FIGURE 10. SUPPL Y CU RRENT AND POWER CONVERSION

EFFICIENCY AS A FUNCTION OF LOAD CURRENT

Typical Performance Curves (Test Circuit Figure 12) (Continued)

1 10 100 1k

OSCILLATOR FREQUENCY fOSC (kHz)

COSC (pF)

V+ = 5V

TA = +25°C

OSCILLATOR FREQUENCY fOSC (kHz)

-55 -25 0 25 50 75 100 125

TEMPERATURE (°C)

V+ = 10V

V+ = 5V

OUTPUT VOLTAGE (V)

-1

-2

-3

-4

-5

010203040

LOAD CURRENT (mA)

V+ = 5V

TA = +25°C

POWER CONVERSION EFFICIENCY (%)

100

LOAD CURRENT (mA)

0102030 40 5060

V+ = 5V

TA = +25°C

SUPPLY CURRENT (mA)

OUTPUT VOLTAGE (V)

-1

-2 012 3456789

LOAD CURRENT (mA)

TA = +25°C

V+ = 2V

100

0 1.5 3.0 4.5 6.0 7.5 9.0

LOAD CURRENT (mA)

V+ = 2V

TA = +25°C

POWER CONVERSION

EFFICIENCY (%)

SUPPLY CURRENT (mA) (NOTE 9)

ICL7660S

6FN3179.5

March 6, 2008

Detailed Description

The ICL7660S contains all the necessary circuitry to

complete a negative voltage converter, with the exception of

2 external capacitors which may be inexpensive 10µF

polarized electrolytic types. The mode of operation of the

device may be best understood by considering Figu re 12,

which shows an idealized negati ve vo ltage converte r.

Capacitor C1 is charged to a voltage, V+, for the half cycle

when switches S1 and S3 are closed. (Note: Switches S2

and S4 are open during th is half cycle). During the second

half cycle of operation, switches S2 and S4 are closed, with

S1 and S3 open, thereby shifting capacitor C1 to C2 such

that the voltage on C2 is exactly V+, assuming ideal switches

and no load on C2. The ICL7660S approaches this ideal

situation more closely than existing non-mechanical circuits.

In the ICL7660S, the 4 switches of Figure 13 are MOS

power switches; S1 is a P-Channel devices and S2, S3 and

S4 are N-Channel devices. The main difficulty with this

approach is that in integrating the switches, the substrates of

S3 and S4 must always remain reverse biase d with respect

to their sources, but not so much as to degrade their “ON”

resistances. In addition, at circuit start-up, and under output

short circuit conditions (VOUT = V+), the output voltage must

be sensed and the substrate bias adjusted acco rdingly.

Failure to accomplish this would result in high power losses

and probable device latch-up.

This problem is eliminated in the ICL7660S by a logic network

which senses the output voltage (VOUT) together with the

level translators, and switch es the substrates of S3 and S4 to

the correct level to maintain necessary reverse bias.

The voltage regulator portion of the ICL7660S is an integral

part of the anti-latchup circuitry, however its inherent voltage

drop can degrade operation at low voltages. Therefore, to

improve low voltage operation “LV” pin should be connected

to GND, disabling the regulator. For supply voltages greater

than 3.5V the L V terminal must be left open to insure latchup

proof operation, and prevent device damage.

Theoretical Power Efficiency

Considerations

In theory, a voltage converter can approach 100% efficiency

if certain conditions are met:

1. The drive circuitry consumes minimal power.

2. The output switches have extremely low ON resistance

and virtually no offset.

3. The impedance of the pump and reservoir capacitors are

negligible at the pump frequency.

FIGURE 11. OUTPUT SOURCE RESISTANCE AS A FUNCTION OF OSCILLATOR FREQUENCY

NOTE:

10. These curves include in the supply current that current fed directly into the load RL from the V+ (See Figure 12). Thus, approximately half the

supply current goes directly to the positive side of the load, and the other half, through the ICL7660S, to the negative side of the load. Ideally,

VOUT ∼ 2VIN, IS ∼ 2IL, so VIN x IS ∼ VOUT x IL.

Typical Performance Curves (Test Circuit Figure 12) (Continued)

OUTPUT RESISTANCE (Ω)

400

300

200

100

100 1k 10k 100k

OSCILLATOR FREQUENCY (Hz)

V+ = 5V

TA = +25°C

I = 10mA

C1 = C2 = 10mF

C1 = C2 = 1mF

C1 = C2 = 100mF

10µF

ISV+(+5V)

-VOUT

10µF

ICL7660S

V+

NOTE: For large values of COSC (>1000pF) the values of C1 and C2

should be increased to 100µF.

FIGURE 12. ICL7660S TEST CIRCUIT

ICL7660S

7FN3179.5

March 6, 2008

The ICL7660S approaches these conditions for negative

voltage conversion if large values of C1 and C2 are used.

ENERGY IS LOST ONL Y IN THE TRANSFER OF CHARGE

BETWEEN CAPACITORS IF A CHANGE IN VOLTAGE

OCCURS. The energy lost is defined by:

where V1 and V2 are the voltages on C1 during the pump

and transfer cycles. If the impedances of C1 and C2 are

relatively high at the pump frequency (refer to Figure 13)

compared to the value of RL, there will be substantial

difference in the voltages V1 and V2. Therefore it is not only

desirable to make C2 as large as possible to eliminate output

voltage ripple, but also to employ a correspondingly large

value for C1 in order to achieve maximum efficiency of

operation.

Do’s and Don’ts

1. Do not exceed maximum supply voltages.

2. Do not connect LV te rminal to GND for supply voltage

greater than 3.5V.

3. Do not short circuit the output to V+ supply for supply

voltages above 5.5V for extended periods, however,

transient conditions including start-up are okay.

4. When using polarized capacitors, the + terminal of C1

must be connected to pin 2 of the ICL7660S and the +

terminal of C2 must be connected to GND.

5. If the voltage supply driving the ICL7660S has a large

source impedance (25Ω to 30Ω), then a 2.2μF capacitor

from pin 8 to ground may be required to limit rate of rise

of input voltage to less than 2V/µs.

6. User should insure that the output (pin 5) does not go

more positive than GND (pin 3). Device latch up will occur

under these conditions. A 1N914 or similar diode placed

in parallel with C2 will prevent the device from latching up

under these conditions. (Anode pin 5, Cathode pin 3).

Typical Applications

Simple Negative Voltage Converter

The majority of applications will undoubtedly util ize the

ICL7660S for generation of negative supply voltages.

Figure 14 shows typical connecti ons to provide a negative

supply where a positive supply of +1.5V to +12V is available.

Keep in mind that pin 6 (LV) is tied to the supply negative

(GND) for supply voltage below 3.5V.

The output characteristics of the circuit in Figure 14 can be

approximated by an ideal voltage source in series with a

resistance as shown in Figure 14B. The voltage source has

a value of -(V+). The output impedance (RO) is a function of

the ON resistance of the internal MOS switches (shown in

Figure 13), the switching frequency, the value of C1 and C2,

and the ESR (equivalent series resistance) of C1 and C2. A

good first order approximation for RO is:

Combining the four RSWX terms as RSW, we see that:

RSW, the total switch resistance, i s a function of supply

voltage and te mp erature (See the Output Source Resist ance

graphs), typically 23Ω at +25°C and 5V. Careful selection of

C1 and C2 will reduce the remaining te rms, minimizing the

output impedance. High value cap a citors will reduce the

1/(fPUMP x C1) comp onent, and low ESR capacito rs will lower

the ESR term. Increasing the oscillator fre quen cy will red uce

the 1/(fPUMP x C1) term, but may have the side ef fect of a net

increase in output impedance when C1 > 10µF and is not long

enough to fully charge the capacito rs every cycle. In a typical

application where fOSC = 10kH z an d C = C1 = C 2 = 10µF:

---C1V12V22

–()=(EQ. 1)

VOUT = -VIN

VIN

S3S4

S1S2

FIGURE 13. IDEALIZED NEGATIVE VOLTAGE CONVERTER

10µF

ICL7660S

VOUT = -V+ V++

ROVOUT

V+

14A. 14B.

FIGURE 14. SIMPLE NEGATIVE CONVERTER AND ITS

OUTPUT EQUIVALENT

R02R

SW1 RSW3 ESRC1

++()2R

SW2 RSW4 ESRC1

++()++(≅

(EQ. 2)

fPUMP C1

--------------------------------ESRC2

fPUMP fOSC

--------------

=RSWX MOSFET Switch Resistance=()

R02xRSW 1

fPUMP C1

--------------------------------4xESRC1 ESRC2

+++≅(EQ. 3)

ICL7660S

8FN3179.5

March 6, 2008

Since the ESRs of the capacitors are reflected in the output

impedance multiplied by a factor of 5, a high value could

potentially swamp out a low 1/fPUMP x C1) term, rendering

an increase in switching frequency or filter capacitance

ineffective. Typical electrolytic capacitors may have ESRs as

high as 10Ω.

Output Ripple

ESR also affects the ripple voltage seen at the output. The

total ripple is determined by 2 voltages, A and B, as shown in

Figure 15. Segment A is the voltage drop across the ESR of

C2 at the instant it goes from being charged by C1 (current

flowing into C2) to being discharged through the load

(current flowing out of C2). The magnitude of this current

change is 2 x IOUT, hence the total drop is 2 x IOUT x

ESRC2V. Segment B is the voltage change across C2 during

time t2, the half of the cycle when C2 supplies current the

load. The drop at B is IOUT x t2/C2V. The peak-to-peak ripple

voltage is the sum of these voltage drops:

Again, a low ESR capacitor will result in a higher

performance output.

Parallelin g De vic e s

Any number of ICL7660S voltage converters may be

paralleled to reduce output resistance. The reservoir

capacitor, C2, serves all devices while each device requires

its own pump capacitor, C1. The resultant output resistance

would be approximately:

Cascading Devices

The ICL7660S may be cascaded as shown to produce larger

negative multiplication of the initial supply voltage. However ,

due to the finite efficiency of each de vice, the practical limit i s

10 devices for light loads. The output voltage is defined by:

where n is an integer representing the number of devices

cascaded. The resulting output resistance would be

approximately the weighted sum of the individual ICL7660S

ROUT values.

Changing the ICL7660S Oscill at or Fre q ue n cy

It may be desirable in some application s, due to noise or other

considerations, to alter the oscillator frequency. This can be

achieved simply by one of several methods described in the

following.

By connecting the Boost Pin (Pin 1) to V+, the oscillator

charge and discharge current is increased and, hence, the

oscillator frequency is increased by approximately 31/2

times. The result is a decrease in the output impedance and

ripple. This is of major importance for surface mount

applications where capacitor size and cost are critical.

Smaller capacitors, e.g. 0.1µF, can be used in conjunction

with the Boost Pin in order to achieve similar output currents

compared to the device free running with C1 = C2 = 10µF or

100µF. (Refer to graph of Output Source Resistance as a

Function of Oscillator Frequency).

Increasing the oscillator freque ncy can also be achieved by

overdriving the oscillator from an external clock, as shown in

Figure 18. In order to prevent device latchup, a 1kΩ resistor

must be used in series with the clock output. In a situation

where the designer has generated th e external clock

frequency using TTL logic, the addition of a 10kΩ pull-up

resistor to V+ supply is required. Note that the pump

frequency with external clocking, as with internal clocking,

will be 1/2 of the clock frequency . Output transitions occur on

the positive going edge of the clock.

It is also possible to increase the conversion efficiency of the

ICL7660S at low load levels by lowering the oscillator

frequency. This reduces the switching losses, and is shown

in Figure 19. However, lowering the oscillator frequency will

cause an undesirable increase in the impedance of the

pump (C1) and reservoir (C2) capacitors; this is overcome by

increasing the values of C1 and C2 by the same factor that

the frequency has been reduced. For example, the addition

of a 100pF capacitor between pin 7 (OSC and V+ will lowe r

the oscillator frequency to 1kHz from its nominal frequency

of 10kHz (a multiple of 10), and thereby necessitate

corresponding increase in the value of C1 and C2 (from

10µF to 100µF).

R02x23 1

510

×10×10 6–

---------------------------------------------------4xESRC1 ESRC2

+++≅(EQ. 4)

R046 20 5++ ESRC

×≅

VRIPPLE 1

PUMP

×C2

----------------------------------------- 2ESRC2 IOUT

×+

⎝⎠

⎛⎞

≅(EQ. 5)

ROUT ROUT of ICL7660S()

n number of devices()

---------------------------------------------------------

=(EQ. 6)

VOUT nV

()–= (EQ. 7)

10µF

ICL7660S

VOUT

V+

-10µF

V+

CMOS

GATE

1kΩ

FIGURE 15. EXTERNAL CLOCKING

ICL7660S

9FN3179.5

March 6, 2008

Positive Voltage Doubling

The ICL7660S may be employed to achieve positive voltage

doubling using the circuit shown in Figure 20. In this

application, the pump inverter switches of the ICL7660S are

used to charge C1 to a voltage level of V+ -VF (where V+ is

the supply voltage and VF is the forward voltage on C1 plus

the supply voltage (V+) is applied through diode D2 to

capacitor C2. The voltage thus created on C2 becomes

(2V+) - (2VF) or twice the supply voltage minus the

combined forward voltage drops of diodes D1 and D2.

The source impedance of th e output (VOUT) will depend on

the output current, but for V+ = 5V and an output current of

10mA it will be approximately 60Ω.

Combined Negative Voltage Conversion and

Positive Supply Doubling

Figure 21 combines the functions shown in Figure 14 and

Figure 20 to provide negative voltage conversion and

positive voltage doubling simultaneously. This approach

would be, for example, suitable for generating +9V and -5V

from an existing +5V supply. In this instance capacitors C1

and C3 perform the pump and reservoir functions

respectively for the generation of the negative voltage, while

capacitors C2 and C4 are pump and reservoir respectively

for the doubled positive voltage. There is a penalty in this

configuration which combines both functions, however, in

that the source impedances of the generated supplies will be

somewhat higher due to the finite impedance of the common

charge pump driver at pin 2 of the device.

Voltage Splitting

The bidirectional characteristics can also be used to split a

high supply in half, as shown in Figure 22. The combined

load will be evenly shared between the two sides, and a high

value resistor to the LV pin ensures start-up. Because the

switches share the load in parallel, the output impedance is

much lower than in the standard circuits, and higher currents

can be drawn from the device. By using this circuit, and then

the circuit of Figure 17, +15V can be converted (via +7.5,

and -7.5 to a nominal -15V, although with rather high series

output resistance (∼250Ω).

Regulated Negative Voltage Supply

In some cases, the output impedance of the ICL7660S can

be a problem, particularly if the load current varies

substantially. The circuit of Figure 23 can be used to

overcome this by controlling the input voltage, via an

ICL7611 low-p ower CMOS op amp, in such a way as to

maintain a nearly constant output voltage. Direct feedback is

inadvisable, since the ICL7660S’s output does not respond

instantaneously to change in input, but only after the

switching delay. The circuit shown supplies enough delay to

accommodate the ICL7660S, while maintaining adequate

feedback. An increase in pump and stora ge capacitors is

desirable, and the values shown provides an output

impedance of less than 5Ω to a load of 10mA.

ICL7660S

VOUT

V+

-C2

COSC

FIGURE 16. LOWERING OSCILLATOR FREQUENCY

ICL7660S

V+

VOUT =

(2V+) - (2VF)

NOTE: D1 and D2 can be any suitable diode.

FIGURE 17. POSITIVE VOLTAGE DOUBLER

ICL7660S

V+

VOUT = (2V+) -

(VFD1) - (VFD2)

VOUT = -VIN

C1+

FIGURE 18. COMBINED NEGATIVE VOLTAGE CONVERTER

AND POSITIVE DOUBLER

50µF

RL1

VOUT = V+ - V-

2ICL7660S

V+

V-

RL2

FIGURE 19. SPLITTING A SUPPLY IN HALF

ICL7660S

10 FN3179.5

March 6, 2008

Other Applications

Further informati on on the operation and use of the

ICL7660S may be found in AN051 “Pri nciples and

Applications of the ICL7660 CMOS Voltage Converter”.

100µF

ICL7660S

100µF

VOUT

-10µF

ICL7611

100Ω

50k

+8V

100k

50k

ICL8069

56k

+8V

800k 250k

VOLTAGE

ADJUST +

FIGURE 20. REGULATING THE OUTPUT VOLTAGE

ICL7660S

10µF

TTL DATA

INPUT

10µF

13 14

12 11

+5V LOGIC SU PP LY

RS232

DATA

OUTPUT

IH5142

3+5V

-5V

FIGURE 21. RS232 LEVELS FROM A SINGLE 5V SUPPLY

ICL7660S

11 FN3179.5

March 6, 2008

ICL7660S

Dual-In-Line Plastic Packages (PDIP)

-B-

INDEX 12 3 N/2

AREA

SEATING

BASE

PLANE

-C-

B1 Be

-A-

0.010 (0.25) C AMBS

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between

English and Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated

in JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protru-

sions. Mold flash or protrusions shall not exceed 0.010 inch

(0.25mm).

6. E and are measured with the leads constrained to be per-

pendicular to datum .

7. eB and eC are measured at the lead tips with the leads uncon-

strained. eC must be zero or greater.

8. B1 maximum dimensions do not include dambar protrusions.

Dambar protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,

E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch

(0.76 - 1.14mm).

-C-

E8.3 (JEDEC MS-001-BA ISSUE D)

8 LEAD DUAL-IN-LINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A-0.210 -5.33 4

A1 0.015 -0.39 -4

A2 0.115 0.195 2.93 4.95 -

B0.014 0.022 0.356 0.558 -

B1 0.045 0.070 1.15 1.77 8, 10

C0.008 0.014 0.204 0.355 -

D0.355 0.400 9.01 10.16 5

D1 0.005 -0.13 -5

E0.300 0.325 7.62 8.25 6

E1 0.240 0.280 6.10 7.11 5

e 0.100 BSC 2.54 BSC -

eA0.300 BSC 7.62 BSC 6

eB-0.430 -10.92 7

L0.115 0.150 2.93 3.81 4

N8 89

Rev. 0 12/93

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of I nter sil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN3179.5

March 6, 2008

ICL7660S

Small Outline Plastic Packages (SOIC)

INDEX

AREA E

123

-B-

0.25(0.010) C AMBS

-A-

-C-

SEATING PLANE

0.10(0.004)

h x 45°

H0.25(0.010) BM M

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9

C 0.0075 0.0098 0.19 0.25 -

D 0.1890 0.1968 4.80 5.00 3

E 0.1497 0.1574 3.80 4.00 4

e 0.050 BSC 1.27 BSC -

H 0.2284 0.2440 5.80 6.20 -

h 0.0099 0.0196 0.25 0.50 5

L 0.016 0.050 0.40 1.27 6

N8 87

α0° 8° 0° 8° -

Rev. 1 6/05