HRF-AT4611
31.5 dB, DC - 4GHz, 6 Bit Serial Digital Attenuator
The Honeywell HRF-AT4611 is a 6-bit digital attenuator that is ideal for use in
broadband communication system applications that require accuracy, speed
and low power consumption. The HRF-AT4611 is manufactured with
Honeywell's patented Silicon On Insulator (SOI) CMOS manufacturing
technology, which provides the performance of GaAs with the economy and
integration capabilities of conventional CMOS. These attenuators are DC
coupled to improve lower operating frequency, frequency response and
reduce the number of DC bias points required.
FEATURES
• Very Low DC Power Consumption
• Attenuation In Steps From 0.5 dB To 31.5 dB
• Single Positive Power Supply Voltage
• Serial Data Interface
• 50 Ohm Impedance
• DC-coupled, bi-directional RF path
• Space Saving VQFN Surface Mount Packaging
• Lead-free, RoHS compliant and Green
RF ELECTRICAL SPECIFICATIO NS @ + 25oC
Results @ VDD = 5.0 +/- 10%, VSS = 0 unless otherwise stated, Z0 = 50 Ohm s
Contact Honeywell for relative perform ance at other supply configurations
HR
AT4611 in VQFN Packa
e
Parameter Test Condition Frequency Minimum Typical Maximum Units
Insertion Loss
1.0 GHz
2.5 GHz
3.0 GHz
4.0 GHz
2.5
3.0
3.6
5.5
2.9
3.5
3.9
5.8
dB
dB
dB
dB
1dB Compression VSS = 0V, Input Power
VSS = -3V, Input Power 2.0 GHz
2.0 GHz 24
29 dBm
dBm
Input IP3 VSS = 0V, Two-tone inputs, up to +5
dBm @ 0 dB attenuation 2.0 GHz 38 dBm
Input IP3 Vss = -3V, Two-tone inputs, up to +5
dBm @ 0 dBm attenuation 2.0 GHz >38 dBm
Return Loss Any Bit or Combination -11 -13 dB
Attenuation Accuracy
All attenuation states
All attenuation states
All attenuation states
All attenuation states
1.0 GHz
2.5 GHz
3.0 GHz
4.0 GHz
+/-(0.3 + 3.0% of programmed IL)
+/-(0.3 + 4.0% of programmed IL)
+/-(0.3 + 5.5% of programmed IL)
+/-(0.3 + 7.0% of programmed IL)
dB
dB
dB
dB
Trise, Tfall
Ton, Toff (Tpd) 10% To 90%
50% Cntl To 90% / 10%RF 10
15 nS
nS
T clock Period (Tprd) T high / T low = ½ minimum clock period 50 nS
T data set up (Tsup) Set up to rising edge of clock 5 nS
T data hold (Thld) Data hold after rising edge of clock 2 nS
T latch set up (Tlsup) Data set up to rising edge of OE 5 nS