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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DControlled Baseline
− One Assembly/Test Site, One Fabrication
Site
DEnhanced Diminishing Manufacturing
Sources (DMS) Support
DEnhanced Product-Change Notification
DQualification Pedigree†
D2-A Low-Dropout Voltage Regulator
DAvailable in 1.5-V, 1.8-V, 2.5-V, 3.3-V Fixed
Output and Adjustable Versions
DOpen Drain Power-On Reset With 100-ms
Delay (TPS752xx)
DOpen Drain Power-Good (PG) Status
Output (TPS754xx)
DDropout Voltage Typically 210 mV at 2 A
(TPS75233)
†Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over the specified
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
DUltralow 75-µA Typical Quiescent Current
DFast Transient Response
D2% Tolerance Over Specified Conditions
for Fixed-Output Versions
D20-Pin TSSOP (PWP) PowerPAD Package
DThermal Shutdown Protection
description
The TPS752xx and TPS754xx are low dropout regulators with integrated power-on reset and power good (PG)
functions respectively. These devices are capable of supplying 2 A of output current with a dropout of 210 mV
(TPS75233, TPS75433). Quiescent current is 75 µA at full load and drops down to 1 µA when the device is disabled.
TPS752xx and TPS754xx are designed to have fast transient response for larger load current changes.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 210 mV at an
output current of 2 A for the TPS75x33) and is directly proportional to the output current. Additionally, since the
PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading
(typically 75 µA over the full range of output current, 1 mA to 2 A). These two key specifications yield a significant
improvement in operating life for battery-powered systems.
The device is enabled when the EN pin is connected to a low-level input voltage. This LDO family also features a
sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current
to 1 µA at TJ = 25°C.
The RESET (SVS, POR, or power on reset) output of the TPS752xx initiates a reset in microcomputer and
microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS752xx
monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.
When the output reaches 95% of its regulated voltage, RESET goes to a high-impedance state after a 100-ms delay.
RESET goes to a logic-low state when the regulated output voltage is pulled below 95% (i.e., over load condition)
of its regulated voltage.
Copyright 2003, Texas Instruments Incorporated
!"#$%&" ' ()##*& %' "! +),-(%&" .%&*/
#".)(&' ("!"#$ &" '+*(!(%&"' +*# &0* &*#$' "! *1%' '&#)$*&'
'&%.%#. 2%##%&3/ #".)(&" +#"(*''4 ."*' "& *(*''%#-3 (-).*
&*'&4 "! %-- +%#%$*&*#'/
PowerPAD is a trademark of Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PWP PACKAGE
(TOP VIEW)
GND/HEATSINK
NC
IN
IN
EN
RESETor PG‡
FB/SENSE
OUTPUT
OUTPUT
GND/HEATSINK
GND/HEATSINK
NC
NC
GND
NC
NC
NC
NC
NC
GND/HEATSINK
NC − No internal connection
‡PG is on the TPS754xx and RESET is on the TPS752xx
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TJ − Junction Temperature − °C
−40 10 11060
− Dropout Voltage − mV
VDO
TPS75x33
DROPOUT VOLTAGE
vs
JUNCTION TEMPERATURE
300
160
250
200
150
100
50
0
IO = 0.5 A
IO = 1.5 A
IO = 2 A
t − Time − ms
TPS75x33
LOAD TRANSIENT RESPONSE
I − Output Current − A
OVO− Change in∆
Output Voltage − mV
−150
321457689100
0
0
50
−50
IL=2 A
CL=100 µF (Tantalum)
VO=3.3 V
−100
2
1
description (continued)
The TPS754xx has a power good terminal (PG) as an active high, open drain output, which can be used to
implement a power-on reset or a low-battery indicator.
The TPS752xx or the TPS754xx are offered in 1.5-V, 1.8-V, 2.5-V, and 3.3-V fixed-voltage versions and in an
adjustable version (programmable over the range of 1.5 V to 5 V). Output voltage tolerance is specified as a
maximum of 2% over line, load, and temperature ranges. The TPS752xx and the TPS754xx families are available
in 20 pin TSSOP (PWP) packages.
AVAILABLE OPTIONS/ORDERING INFORMATION†
TJ
OUTPUT VOLTAGE
TSSOP (PWP)
T
J
OUTPUT VOLTAGE
(TYP) RESET PG
3.3 V TPS75233QPWPEP TPS75433QPWPEP‡
2.5 V TPS75225QPWPEP TPS75425QPWPEP‡
−40°C to 125°C1.8 V TPS75218QPWPEP TPS75418QPWPEP‡
−40 C to 125 C
1.5 V TPS75215QPWPEP TPS75415QPWPEP‡
Adjustable 1.5 V to 5 V TPS75201QPWPEP TPS75401QPWPEP‡
†The TPS75x01 is programmable using an external resistor divider (see application information). The
PWP package is available taped and reeled. Add an R suffix to the device type (e.g.,
TPS75201QPWPREP) to indicate tape and reel.
‡Product preview
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†See application information section for capacitor selection details.
PG or
RESET
OUT
OUT
4
3
5
IN
IN
EN
GND
17
6
8
9
VI
0.22 µF
PG or RESET Output
VO
47 µF
+CO†
SENSE 7
Figure 1. Typical Application Configuration (For Fixed Output Options)
functional block diagram—adjustable version
100 ms Delay
(for RESET Option)
_
+
Vref = 1.1834 V
OUT
FB
EN
GND
PG or RESET
_
+
IN
R1
R2
External to the device
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functional block diagram—fixed-voltage version
_
+
Vref = 1.1834 V
OUT
EN
GND
R1
R2
PG or RESET
_
+
IN
SENSE
100 ms Delay
(for RESET Option)
Terminal Functions (TPS752xx)
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
EN 5 I Enable Input
FB/SENSE 7 I Feedback input voltage for adjustable device (sense input for fixed-voltage option)
GND 17 Regulator ground
GND/HEATSINK 1, 10, 11, 20 Ground/heatsink
IN 3, 4 IInput voltage
NC 2, 12, 13, 14,
15, 16, 18, 19 No connection
OUTPUT 8, 9 ORegulated output voltage
RESET 6 O Reset output
Terminal Functions (TPS754xx)
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
EN 5 I Enable Input
FB/SENSE 7 I Feedback input voltage for adjustable device (sense input for fixed-voltage option)
GND 17 Regulator ground
GND/HEATSINK 1, 10, 11, 20 Ground/heatsink
IN 3, 4 IInput voltage
NC 2, 12, 13, 14,
15, 16, 18, 19 No connection
OUTPUT 8, 9 ORegulated output voltage
PG 6 O Power good output
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TPS752xx RESET timing diagram
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
VI
Vres
(see Note A) Vres
t
t
t
VO
Threshold
Voltage
RESET
Output 100 ms
Delay 100 ms
Delay
Output
Undefined
Output
Undefined
VIT+(see Note B)
VIT−(see Note B) VIT−(see Note B)
VIT+(see Note B)
Less than 5% of the
output voltage
NOTES: A. Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards
for semiconductor symbology.
B. VIT −Trip voltage is typically 5% lower than the output voltage (95%VO) VIT− to VIT+ is the hysteresis voltage.
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TPS754xx PG timing diagram
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
VI
VPG
(see Note A) VPG
t
t
t
VO
Threshold
Voltage
PG
Output
Output
Undefined
Output
Undefined
VIT+(see Note B)
VIT−(see Note B) VIT−(see Note B)
VIT+(see Note B)
NOTES: A. VPG is the minimum input voltage for a valid PG. The symbol VPG is not currently listed within EIA or JEDEC standards for
semiconductor symbology.
B. VIT −Trip voltage is typically 17% lower than the output voltage (83%VO) VIT− to VIT+ is the hysteresis voltage.
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absolute maximum ratings over operating junction temperature range (unless otherwise noted)Ĕ
Input voltage range‡, VI −0.3 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at EN −0.3 V to 16.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum RESET voltage (TPS752xx) 16.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum PG voltage (TPS754xx) 16.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak output current Internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage, VO (OUTPUT, FB) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See dissipation rating tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ −40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD rating, HBM 2 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡All voltage values are with respect to network terminal ground.
DISSIPATION RATING TABLE 1 − FREE-AIR TEMPERATURES
PACKAGE AIR FLOW
(CFM) TA < 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 85°C
POWER RATING
PWP§
02.9 W 23.5 mW/°C1.9 W 1.5 W
PWP§
300 4.3 W 34.6 mW/°C 2.8 W 2.2 W
PWP¶
03 W 23.8 mW/°C1.9 W 1.5 W
PWP¶
300 7.2 W 57.9 mW/°C4.6 W 3.8 W
§This parameter is measured with the recommended copper heat sink pattern on a 1-layer PCB, 5-in × 5-in PCB, 1 oz. copper, 2-in × 2-in coverage
(4 in2).
¶This parameter is measured with the recommended copper heat sink pattern on a 8-layer PCB, 1.5-in × 2-in PCB, 1 oz. copper with layers 1, 2, 4,
5, 7, and 8 at 5% coverage (0.9 in2) and layers 3 and 6 at 100% coverage (6 in2). For more information, refer to TI technical brief SLMA002.
recommended operating conditions
MIN MAX UNIT
Input voltage, VI#2.7 5 V
Output voltage range, VO1.5 5 V
Output current, IO0 2.0 A
Operating virtual junction temperature, TJ−40 125 °C
# To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load).
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electrical characteristics over recommended operating junction temperature range (TJ = −40°C to
125°C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, Co = 47 µF (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Adjustable
1.5 V ≤ VO ≤ 5 V, TJ = 25°C VO
Adjustable
Voltage 1.5 V ≤ VO ≤ 5 V 0.98VO1.02VO
1.5 V Output
TJ = 25°C, 2.7 V < VIN < 5 V 1.5
1.5 V Output 2.7 V < VIN < 5 V 1.470 1.530
Output voltage
1.8 V Output
TJ = 25°C, 2.8 V < VIN < 5 V 1.8
V
Output voltage
(see Notes 1 and 3) 1.8 V Output 2.8 V < VIN < 5 V 1.764 1.836 V
(see Notes 1 and 3)
2.5 V Output
TJ = 25°C, 3.5 V < VIN < 5 V 2.5
2.5 V Output 3.5 V < VIN < 5 V 2.450 2.550
3.3 V Output
TJ = 25°C, 4.3 V < VIN < 5 V 3.3
3.3 V Output 4.3 V < VIN < 5 V 3.234 3.366
Quiescent current (GND current) (see Note 1)
TJ = 25°C, See Note 3 75
A
Quiescent current (GND current) (see Note 1) See Note 3 125 µA
Output voltage line regulation (
∆
VO/VO)
VO + 1 V < VI ≤ 5 V, TJ = 25°C, 0.01
%/V
Output voltage line regulation (∆VO/VO)
(see Notes 1 and 2) VO + 1 V < VI < 5 V 0.1 %/V
Load regulation (see Note 3) 1 mV
Output noise voltage BW = 300 Hz to 50 kHz, VO = 1.5 V
CO = 100 µF, TJ = 25°C60 µVrms
Output current Limit VO = 0 V 3.3 4.5 A
Thermal shutdown junction temperature 150 °C
Standby current
EN = VI, TJ = 25°C, 1 µA
Standby current EN = VI10 µA
FB input current TPS75x01 FB = 1.5 V −1 1 µA
High level enable input voltage 2 V
Low level enable input voltage 0.7 V
Power supply ripple rejection (see Note 2) f = 100 Hz, CO = 100 µF,
TJ = 25°C, See Note 1, IO = 2 A 60 dB
Minimum input voltage for valid
RESET IO(RESET) = 300µA, V(RESET) ≤ 0.8 V 1 1.3 V
Reset
Trip threshold voltage VO decreasing 92 98 %VO
Reset
(TPS752xx)
Hysteresis voltage Measured at VO0.5 %VO
(TPS752xx)
Output low voltage VI = 2.7 V, IO(RESET) = 1 mA 0.15 0.4 V
Leakage current V(RESET) = 5 V 1µA
RESET time-out delay 100 ms
NOTES: 1. Minimum IN operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. Maximum IN voltage 5V.
2. If VO≤ 1.8 V then Vimin = 2.7 V, Vimax = 5 V:
Line Reg. (mV) +ǒ%ńVǓ VOǒVimax *2.7 VǓ
100 1000
If VO ≥ 2.5 V then Vimin = VO + 1 V, Vimax = 5 V:
Line Reg. (mV) +ǒ%ńVǓ
VOǒVimax *ǒVO)1V
ǓǓ
100 1000
3. IO = 1 mA to 2 A
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electrical characteristics over recommended operating junction temperature range (TJ = −40°C to
125°C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, Co = 47 µF (unless otherwise noted) (continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Minimum input voltage for valid PG IO(PG) = 300 µAV(PG) ≤ 0.8 V 1.1 1.3 V
PG
Trip threshold voltage VO decreasing 80 86 %VO
PG
(TPS754xx)
Hysteresis voltage Measured at VO0.5 %VO
(TPS754xx)
Output low voltage IO(PG) = 1 mA 0.15 0.4 V
Leakage current V(PG) = 5.5 V 1µA
Input current (EN)
EN = VI−1 1 µA
Input current (EN)EN = 0 V −1 0 1 µA
High level EN input voltage 2 V
Low level EN input voltage 0.7 V
Dropout voltage (3.3 V Output) (see Note 4)
IO = 2 A,
TJ = 25°CVI = 3.2 V, 210
mV
Dropout voltage (3.3 V Output) (see Note 4)
IO = 2 A, VI = 3.2 V 400
mV
NOTE 4: IN voltage equals VO(T yp) − 100 mV; TPS75x15, TPS75x18 and TPS75x25 dropout voltage limited by input voltage range limitations (i.e.,
TPS75x33 input voltage needs to drop to 3.2 V for purpose of this test).
Table of Graphs
FIGURE
VO
Output voltage
vs Output current 2, 3
VOOutput voltage vs Junction temperature 4, 5,
Ground current vs Junction temperature 6
Power supply ripple rejection vs Frequency 7
Output spectral noise density vs Frequency 8
ZoOutput impedance vs Frequency 9
VDO
Dropout voltage
vs Input voltage 10
VDO Dropout voltage vs Junction temperature 11
Input voltage (min) vs Output voltage 12
Line transient response 13, 15
Load transient response 14, 16
VOOutput voltage vs Time 17
Equivalent series resistance (ESR) vs Output current 19, 20
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TYPICAL CHARACTERISTICS
Figure 2
IO − Output Current − mA
TPS75x33
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.303
3.297
3.301
3.299
3.295 500 1500
3.305
0
− Output Voltage − V
VO
1000
VO
2000
VI = 4.3 V
TJ = 25°C
Figure 3
IO − Output Current − mA
TPS75x15
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
1.502
1.499
1.501
1.5
1.498
1.503
0
− Output Voltage − V
VO
1.497 500 15001000 2000
VO
VI = 2.7 V
TJ = 25°C
TJ − Junction Temperature − °C
TPS75x33
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
− Output Voltage − V
V
O
Figure 4
3.31
−50 0
3.33
150
3.35
3.29
50 100
3.25
3.27
1 mA
3.23
3.37
2 A
TJ − Junction Temperature − °C
TPS75x15
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
− Output Voltage − V
VO
Figure 5
1.48
−40 10
1.50
11060 160
1.52
1.51
1.49
1.47
1.53
1 mA
2 A
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TYPICAL CHARACTERISTICS
TJ − Junction Temperature − °C
TPS75xxx
GROUND CURRENT
vs
JUNCTION TEMPERATURE
Ground Current − Aµ
10 11060−40 160
90
70
60
80
85
75
65
55
50
Figure 6
VI = 5 V
IO = 2 A
100k10k
PSRR − Power Supply Ripple Rejection − dB
f − Frequency − Hz
POWER SUPPLY RIPPLE REJECTION
vs
FREQUENCY
70
60
50
40
30
20
10
0
TPS75x33
90
80
1k10010 1M
VI = 4.3 V
CO = 100 µF
IO = 1 mA
TJ = 25°C
VI = 4.3 V
CO = 100 µF
IO = 2 A
TJ = 25°C
100
10M
Figure 7
Figure 8
f − Frequency − Hz
1010 100 1k 10k 50k
1.8
1.4
1.2
0.8
0.4
0
1.6
1
0.6
0.2
2
VI = 4.3 V
VO = 3.3 V
CO = 100 µF
TJ = 25°C
IO = 1 mA
IO = 2 A
nV/ Hz− Voltage Noise −Vn
TPS75x33
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
Figure 9
TPS75x33
OUTPUT IMPEDANCE
vs
FREQUENCY
f − Frequency − Hz
− Output Impedance −ZoΩ
10 100 100K 1M
10−1
10K1K 10M
1
101
10−2
CO = 100 µF
IO = 1 mA
CO = 100 µF
IO = 2 A
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TYPICAL CHARACTERISTICS
Figure 10
TPS75x01
DROPOUT VOLTAGE
vs
INPUT VOLTAGE
VI − Input Voltage − V
150
034
100
50
3.52.5
− Dropout Voltage − mV
4.5 5
VDO
250
200
300
350
TJ = 125°C
TJ = 25°C
TJ = −40°C
IO = 2 A
Figure 11
TJ − Junction Temperature − °C
−40 10 11060
− Dropout Voltage − mV
VDO
TPS75x33
DROPOUT VOLTAGE
vs
JUNCTION TEMPERATURE
300
160
250
200
150
100
50
0
IO = 0.5 A
IO = 1.5 A
IO = 2 A
Figure 12
3
2.7
21.5 1.75 2 2.25 2.5 2.75
− Input Voltage (Min) − V
INPUT VOLTAGE (MIN)
vs
OUTPUT VOLTAGE
4
3 3.25 3.5
VI
VO − Output Voltage − V
IO = 2 A
TA = 25°C
TA = 125°C
TA = −40°C
Figure 13
VO− Change in
4
100
0
TPS75x15
LINE TRANSIENT RESPONSE
VI
t − Time − ms
0 0.30.20.1 0.4 0.5 0.70.6 0.8 0.9 1
− Input Voltage − V ∆
Output Voltage − mV
IO=2 A
CO=100 µF
VO=1.5 V
3
−100
dv
dt +1V
ms
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TYPICAL CHARACTERISTICS
t − Time − ms
TPS75x15
LOAD TRANSIENT RESPONSE
I − Output Current − A
OVO− Change in∆
Output Voltage − mV
−100
0
032145768910
0
50
−50
IL=2 A
CL=100 µF (Tantalum)
VO=1.5 V
−150
2
1
Figure 14
TPS75x33
LINE TRANSIENT RESPONSE
t − Time − ms
VO− Change in
VI− Input Voltage − V ∆
Output Voltage − mV
0.30.20.1 0.4 0.5 0.70.6 0.8 0.9 10
−100
5.3
0
4.3
IO=2 A
CO=100 µF
VO=3.3 V
100
dv
dt +1V
ms
Figure 15
Figure 16
t − Time − ms
TPS75x33
LOAD TRANSIENT RESPONSE
I − Output Current − A
OVO− Change in∆
Output Voltage − mV
−150
321457689100
0
0
50
−50
IO=2 A
CO=100 µF (Tantalum)
VO=3.3 V
−100
2
1
Figure 17
t − Time − ms
VI = 4.3 V
TJ = 25°C
0
3.3
0
0
4.3
0.2 10.4 0.6 0.8
− Output Voltage − V
VO
Enable Voltage − V
TPS75x33
OUTPUT VOLTAGE
vs
TIME (STARTUP)
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TYPICAL CHARACTERISTICS
IN
EN
OUT
+
GND CO
ESR
RL
VITo Load
Figure 18. Test Circuit for Typical Regions of Stability (Figures 19 and 20) (Fixed Output Options)
0.010 0.5 1 1.5 2
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE†
vs
OUTPUT CURRENT
10
IO − Output Current − A
ESR − Equivalent series restance − Ω
1
Region of Instability
0.1
Region of Stability
Vo = 3.3 V
Co = 100 µF
VI = 4.3 V
TJ = 25°C
0.05
Figure 19 Figure 20
0.010 0.5 1 1.5 2
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE†
vs
OUTPUT CURRENT
10
IO − Output Current − A
ESR − Equivalent series restance − Ω
1
Region of Instability
0.1
Region of Stability
Vo = 3.3 V
Co = 47 µF
VI = 4.3 V
TJ = 25°C
†Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally,
and PWB trace resistance to Co.
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APPLICATION INFORMATION
The TPS752xx or TPS754xx families include four fixed-output voltage regulators (1.5 V, 1.8 V, 2.5 V and 3.3 V), and
an adjustable regulator, the TPS75x01 (adjustable from 1.5 V to 5 V).
minimum load requirements
The TPS752xx and TPS754xx families are stable even at no load; no minimum load is required for operation.
pin functions
enable (EN)
The EN terminal is an input which enables or shuts down the device. If EN is a logic high, the device will be in
shutdown mode. When EN goes to logic low, then the device will be enabled.
power good (PG) (TPS752xx)
The PG terminal is an open drain, active high output that indicates the status of VO (output of the LDO). When VO
reaches 83% of the regulated voltage, PG will go to a high impedance state. It will go to a low-impedance state when
VO falls below 83% (i.e. over load condition) of the regulated voltage. The open drain output of the PG terminal
requires a pullup resistor.
sense (SENSE)
The SENSE terminal of the fixed-output options must be connected to the regulator output, and the connection
should be a s short as possible. Internally, SENSE connects to a high-impedance wide-bandwidth amplifier through
a resistor-divider network and noise pickup feeds through to the regulator output. It is essential to route the SENSE
connection in such a way to minimize/avoid noise pickup. Adding RC networks between the SENSE terminal and
VO to filter noise is not recommended because it may cause the regulator to oscillate.
feedback (FB)
FB is an input terminal used for the adjustable-output options and must be connected to an external feedback
resistor divider. The FB connection should be as short as possible. It is essential to route it in such a way to
minimize/avoid noise pickup. Adding RC networks between FB terminal and VO to filter noise is not recommended
because it may cause the regulator to oscillate.
reset (RESET) (TPS754xx)
The RESET terminal is an open drain, active low output that indicates the status of VO. When VO reaches 95% of
the regulated voltage, RESET will go to a low-impedance state after a 100-ms delay. RESET will go to a
high-impedance state when VO is below 95% of the regulated voltage. The open-drain output of the RESET terminal
requires a pullup resistor.
GND/HEATSINK
All GND/HEATSINK terminals are connected directly to the mount pad for thermal-enhanced operation. These
terminals could be connected to GND or left floating.
input capacitor
For a typical application, an input bypass capacitor (0.22 µF − 1 µF) is recommended for device stability. This
capacitor should be as close to the input pins as possible. For fast transient condition where droop at the input of
the LDO may occur due to high inrush current, it is recommended to place a larger capacitor at the input as well.
The size of this capacitor is dependant on the output current and response time of the main power supply, as well
as the distance to the load (LDO).
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APPLICATION INFORMATION
output capacitor
As with most LDO regulators, the TPS752xx and TPS754xx require an output capacitor connected between OUT
and GND to stabilize the internal control loop. The minimum recommended capacitance value is 47 µF and the ESR
(equivalent series resistance) must be between 100 mΩ and 10 Ω. Solid tantalum electrolytic, aluminum electrolytic,
and multilayer ceramic capacitors are all suitable, provided they meet the requirements described in this section.
Larger capacitors provide a wider range of stability and better load transient response.
This information, along with the ESR graphs, is included to assist in selection of suitable capacitance for the user’s
application. When necessary to achieve low height requirements along with high output current and/or high load
capacitance, several higher ESR capacitors can be used in parallel to meet these guidelines.
ESR and transient response
LDOs typically require an external output capacitor for stability. In fast transient response applications, capacitors
are used to support the load current while LDO amplifier is responding. In most applications, one capacitor is used
to support both functions.
Besides its capacitance, every capacitor also contains parasitic impedances. These parasitic impedances are
resistive as well as inductive. The resistive impedance is called equivalent series resistance (ESR), and the
inductive impedance is called equivalent series inductance (ESL). The equivalent schematic diagram of any
capacitor can therefore be drawn as shown in Figure 21.
RESR LESL C
Figure 21. ESR and ESL
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APPLICATION INFORMATION
In most cases one can neglect the effect of inductive impedance ESL. Therefore, the following application focuses
mainly on the parasitic resistance ESR.
Figure 22 shows the output capacitor and its parasitic impedances in a typical LDO output stage.
LDO
VI
VESR
IO
RESR
CO
RLOAD VO
+
−
Figure 22. LDO Output Stage With Parasitic Resistances ESR and ESL
In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage across the
capacitor is the same as the output voltage (V(CO) = VO). This means no current is flowing into the CO branch. If
IO suddenly increases (transient condition), the following occurs:
DThe LDO is not able to supply the sudden current need due to its response time (t1 in Figure 24). Therefore,
capacitor CO provides the current for the new load condition (dashed arrow). CO now acts like a battery with
an internal resistance, ESR. Depending on the current demand at the output, a voltage drop will occur at RESR.
This voltage is shown as VESR in Figure 23.
DWhen CO is conducting current to the load, initial voltage at the load will be VO = V(CO) – VESR. Due to the
discharge of C O, the output voltage VO will drop continuously until the response time t1 of the LDO is reached
and the LDO will resume supplying the load. From this point, the output voltage starts rising again until it reaches
the regulated voltage. This period is shown as t2 in Figure 24.
The figure also shows the impact of different ESRs on the output voltage. The left brackets show different levels
of ESRs where number 1 displays the lowest and number 3 displays the highest ESR.
From above, the following conclusions can be drawn:
DThe higher the ESR, the larger the droop at the beginning of load transient.
DThe smaller the output capacitor, the faster the discharge time and the bigger the voltage droop during the LDO
response period.
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APPLICATION INFORMATION
conclusion
To minimize the transient output droop, capacitors must have a low ESR and be large enough to support the
minimum output voltage requirement.
ESR 1
ESR 2
ESR 3
3
1
2
t1t2
IO
VO
Figure 23. Correlation of Different ESRs and Their Influence to the Regulation of VO at a
Load Step From Low-to-High Output Current
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APPLICATION INFORMATION
programming the TPS75x01 adjustable LDO regulator
The output voltage of the TPS75x01 adjustable regulator is programmed using an external resistor divider as shown
in Figure 24. The output voltage is calculated using:
VO+Vref ǒ1)R1
R2Ǔ(1)
Where:
V
ref
= 1.1834 V typ (the internal reference voltage)
Resistors R1 and R2 should be chosen for approximately 40-µA divider current. Lower value resistors can be used
but offer no inherent advantage and waste more power. Higher values should be avoided as leakage currents at
FB increase the output voltage error. The recommended design procedure is to choose
R2 = 30.1 kΩ to set the divider current at 40 µA and then calculate R1 using:
R1 +ǒVO
Vref *1Ǔ R2 (2)
OUTPUT
VOLTAGE R1 R2
2.5 V
3.3 V
3.6 V
UNIT
33.2
53.6
61.9
30.1
30.1
30.1
kΩ
kΩ
kΩ
OUTPUT VOLTAGE
PROGRAMMING GUIDE
VO
VIRESET/
PG
OUT
FB/SENSE
R1
R2
GND
EN
IN
≤0.7 V
≥2 V
TPS75x01
RESET or PG Output
0.22 µF250 kΩ
NOTE: To reduce noise and prevent
oscillation, R1 and R2 need to be as close
as possible to the FB/SENSE terminal.
CO
Figure 24. TPS75x01 Adjustable LDO Regulator Programming
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APPLICATION INFORMATION
regulator protection
The TPS752xx and TPS754xx PMOS-pass transistors has a built-in back diode that conducts reverse currents
when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the
output to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may
be appropriate.
The TPS752xx and TPS754xx also feature internal current limiting and thermal protection. During normal operation,
the TPS752xx and TPS754xx limit output current to approximately 3.3 A. When current limiting engages, the output
voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross
device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature
of the device exceeds 150°C(typ), thermal-protection circuitry shuts it down. Once the device has cooled below
130°C(typ), regulator operation resumes.
power dissipation and junction temperature
Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature
should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation the
regulator can handle in any given application. To ensure the junction temperature is within acceptable limits,
calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or
equal to PD(max).
The maximum-power-dissipation limit is determined using the following equation:
PD(max) +TJmax *TA
RqJA
Where:
TJmax is the maximum allowable junction temperature
TA is the ambient temperature.
RθJA is the thermal resistance junction-to-ambient for the package, i.e., 34.6°C/W for the 20-terminal
PWP with no airflow (see Table 1).
(3)
The regulator dissipation is calculated using:
PD+ǒVI*VOǓ IO(4)
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger the thermal
protection circuit.
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THERMAL INFORMATION
thermally enhanced TSSOP-20 (PWP − PowerPad)
The thermally enhanced PWP package is based on the 20-pin TSSOP, but includes a thermal pad [see
Figure 25(c)] to provide an effective thermal contact between the IC and the PWB.
Traditionally, surface mount and power have been mutually exclusive terms. A variety of scaled-down TO220-type
packages have leads formed as gull wings to make them applicable for surface-mount applications. These
packages, however, suffer from several shortcomings: they do not address the very low profile requirements (<2
mm) of many of today’s advanced systems, and they do not offer a pin-count high enough to accommodate
increasing integration. On the other hand, traditional low-power surface-mount packages require power-dissipation
derating that severely limits the usable range of many high-performance analog circuits.
The PWP package (thermally enhanced TSSOP) combines fine-pitch surface-mount technology with thermal
performance comparable to much larger power packages.
The PWP package is designed to optimize the heat transfer to the PWB. Because of the very small size and limited
mass of a TSSOP package, thermal enhancement is achieved by improving the thermal conduction paths that
remove heat from the component. The thermal pad is formed using a lead-frame design (patent pending) and
manufacturing technique to provide the user with direct connection to the heat-generating IC. When this pad is
soldered or otherwise coupled to an external heat dissipator, high power dissipation in the ultrathin, fine-pitch,
surface-mount package can be reliably achieved.
DIE
Side View (a)
End View (b)
Bottom View (c)
DIE
Thermal
Pad
Figure 25. Views of Thermally Enhanced PWP Package
Because the conduction path has been enhanced, power-dissipation capability is determined by the thermal
considerations in the PWB design. For example, simply adding a localized copper plane (heat-sink surface), which
is coupled to the thermal pad, enables the PWP package to dissipate 2.5 W in free air (reference
Figure 27(a), 8 cm2 of copper heat sink and natural convection). Increasing the heat-sink size increases the power
dissipation range for the component. The power dissipation limit can be further improved by adding airflow to a
PWB/IC assembly (see Figures 26 and 27). The line drawn at 0.3 cm2 in Figures 26 and 27 indicates performance
at the minimum recommended heat-sink size, illustrated in Figure 29.
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THERMAL INFORMATION
thermally enhanced TSSOP-20 (PWP − PowerPad) (continued)
The thermal pad is directly connected to the substrate of the IC, which for the TPS752xxQPWPEP and
TPS754xxQPWPEP series is a secondary electrical connection to device ground. The heat-sink surface that is
added to the PWP can be a ground plane or left electrically isolated. In TO220-type surface-mount packages, the
thermal connection is also the primary electrical connection for a given terminal which is not always ground. The
PWP package provides up to 16 independent leads that can be used as inputs and outputs (Note: leads 1, 10, 11,
and 20 are internally connected to the thermal pad and the IC substrate).
100
75
50
25 0235
− Thermal Resistance −
125
THERMAL RESISTANCE
vs
COPPER HEAT-SINK AREA
150
78
1460.3
Natural Convection
50 ft/min
250 ft/min
300 ft/min
C/W
°
Copper Heat-Sink Area − cm2
100 ft/min
150 ft/min
200 ft/min
RJA
θ
Figure 26
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THERMAL INFORMATION
thermally enhanced TSSOP-20 (PWP − PowerPad) (continued)
1
0.5
3
00246
2
1.5
2.5
3.5
8
0.3
300 ft/min
150 ft/min
Natural Convection
Copper Heat-Sink Size − cm2
TA = 55°C
(b)
1
0.5
3
00246
2
1.5
2.5
3.5
8
0.3
300 ft/min 150 ft/min
Natural Convection
Copper Heat-Sink Size − cm2
TA = 105°C
(c)
1
0.5
3
00246
− Power Dissipation Limit − W
2
1.5
2.5
3.5
8
0.3
300 ft/min
150 ft/min
Natural Convection
PD
Copper Heat-Sink Size − cm2
TA = 25°C
(a)
− Power Dissipation Limit − W
PD
− Power Dissipation Limit − W
PD
Figure 27. Power Ratings of the PWP Package at Ambient Temperatures of 25°C, 55°C, and 105°C
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THERMAL INFORMATION
thermally enhanced TSSOP-20 (PWP − PowerPad) (continued)
Figure 28 is an example of a thermally enhanced PWB layout for use with the new PWP package. This board
configuration was used in the thermal experiments that generated the power ratings shown in Figure 26 and Figure
27. As discussed earlier, copper has been added on the PWB to conduct heat away from the device. RθJA for this
assembly is illustrated in Figure 26 as a function of heat-sink area. A family of curves is included to illustrate the ef fect
of airflow introduced into the system.
Board thickness 62 mils
Board size 3.2 in. × 3.2 in.
Board material FR4
Copper trace/heat sink 1 oz
Exposed pad mounting 63/67 tin/lead solder
Heat-Sink Area
1 oz Copper
Figure 28. PWB Layout (Including Copper Heatsink Area) for Thermally Enhanced PWP Package
From Figure 26, RθJA for a PWB assembly can be determined and used to calculate the maximum power-dissipation
limit for the component/PWB assembly, with the equation:
PD(max) +TJmax *TA
RqJA(system)
Where:
(5)
TJmax is the maximum specified junction temperature (150°C absolute maximum limit, 125°C recommended
operating limit) and TA is the ambient temperature.
PD(max) should then be applied to the internal power dissipated by the TPS75233QPWPEP regulator. The equation
for calculating total internal power dissipation of the TPS75233QPWPEP is:
PD(total) +ǒVI*VOǓ IO)VI IQ(6)
Since the quiescent current of the TPS75233QPWPEP is very low, the second term is negligible, further simplifying
the equation to:
PD(total) +ǒVI*VOǓ IO(7)
For the case where TA = 55°C, airflow = 200 ft/min, copper heat-sink area = 4 cm2, the maximum power-dissipation
limit can be calculated. First, from Figure 26, we find the system RθJA is 50°C/W; therefore, the maximum
power-dissipation limit is:
PD(max) +TJmax *TA
RqJA(system) +125 C *55 C
50 CńW+1.4 W
°
°° (8)
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THERMAL INFORMATION
thermally enhanced TSSOP-20 (PWP − PowerPad) (continued)
If the system implements a TPS75233QPWPEP regulator, where VI = 5 V and IO = 800 mA, the internal power
dissipation is:
PD(total) +ǒVI*VOǓ IO+(5 *3.3) 0.8 +1.36 W (9)
Comparing P D(total) with PD(max) reveals that the power dissipation in this example does not exceed the calculated
limit. When it does, one of two corrective actions should be made: raising the power-dissipation limit by increasing
the airflow or the heat-sink area, or lowering the internal power dissipation of the regulator by reducing the input
voltage or the load current. In either case, the above calculations should be repeated with the new system
parameters.
mounting information
The primary requirement is to complete the thermal contact between the thermal pad and the PWB metal. The
thermal pad is a solderable surface and is fully intended to be soldered at the time the component is mounted.
Although voiding in the thermal-pad solder-connection is not desirable, up to 50% voiding is acceptable. The data
included in Figures 26 and 27 is for soldered connections with voiding between 20% and 50%. The thermal analysis
shows no significant difference resulting from the variation in voiding percentage.
Figure 29 shows the solder-mask land pattern for the
PWP package. The minimum recommended heat-
sink area is also illustrated. This is simply a copper
plane under the body extent of the package, including
metal routed under terminals 1, 10, 11, and 20.
Figure 29. PWP Package Land Pattern
Location of Exposed
Thermal Pad on
PWP Package
Minimum Recommended
Heat-Sink Area
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS75201QPWPREP ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75215QPWPREP ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75218QPWPREP ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75225QPWPREP ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75233QPWPREP ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
V62/03635-01XE ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
V62/03635-02XE ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
V62/03635-03XE ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
V62/03635-04XE ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
V62/03635-05XE ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
OTHER QUALIFIED VERSIONS OF TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP :
•Catalog: TPS75201,TPS75215,TPS75218,TPS75225,TPS75233
•Automotive: TPS75201-Q1,TPS75215-Q1,TPS75218-Q1,TPS75225-Q1,TPS75233-Q1
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS75201QPWPREP HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS75215QPWPREP HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS75218QPWPREP HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS75225QPWPREP HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS75233QPWPREP HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-May-2011
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS75201QPWPREP HTSSOP PWP 20 2000 346.0 346.0 33.0
TPS75215QPWPREP HTSSOP PWP 20 2000 346.0 346.0 33.0
TPS75218QPWPREP HTSSOP PWP 20 2000 346.0 346.0 33.0
TPS75225QPWPREP HTSSOP PWP 20 2000 346.0 346.0 33.0
TPS75233QPWPREP HTSSOP PWP 20 2000 346.0 346.0 33.0
PACKAGE MATERIALS INFORMATION
www.ti.com 5-May-2011
Pack Materials-Page 2
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