S-35770 Series
www.ablicinc.com
FOR AUTOMOTIVE 125°C OPERATION 2-WIRE COUNTER
CONVENIENCE TIMER
© ABLIC Inc., 2015-2018 Rev.1.3_00
1
The convenience timer is a CMOS timer IC which operates with low current consumption, and is suitable for the time
management of the relative time.
The S-35770 Series counts the number of clocks input from an external device.
The counter is a 24-bit binary up counter.
The counter data can be read via a 2-wire serial interface.
Caution This product can be used in vehicle equipment and in-vehicle equipment. Before using the product in the
purpose, contact to ABLIC Inc. is indispensable.
Features
• External clock signal count function: Countable from 0 to 16,777,215, with output pin for counter loop flag
• Low current consumption: 0.01 μA typ. (VDD = 3.0 V, Ta = +25°C, out of communication (CLKIN pin = 0 V))
• Wide range of operation voltage: 1.5 V to 5.5 V
• 2-wire (I2C-bus) CPU interface
• Operation temperature range: Ta = −40°C to +125°C
• Lead-free (Sn 100%), halogen-free
• AEC-Q100 qualified*1
*1. Contact our sales office for details.
Application
• Various pulse counters
Package
• TMSOP-8
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FOR AUTOMOTIVE 125°C OPERATION 2-WIRE COUNTER CONVENIENCE TIMER
S-35770 Series Rev.1.3_00
2
Block Diagram
Counter
(24-bit)
Power-on
detection
circuit
SDA
CLKIN
SCL
VSS
LOOP
N.C.
Pull-up
RST
VDD
Internal reset signal
Count register
(24-bit)
Free register
(24-bit)
Serial interface
Figure 1
FOR AUTOMOTIVE 125°C OPERATION 2-WIRE COUNTER CONVENIENCE TIMER
Rev.1.3_00 S-35770 Series
3
AEC-Q100 Qualified
This IC supports AEC-Q100 for operation temperature grade 1.
Contact our sales office for details of AEC-Q100 reliability specification.
Product Name Structure
1. Product name
S-35770 E xx A - K8T2 U
Product name
Environmental code
U: Lead-free (Sn 100%), halogen-free
Package abbreviation and IC packing specification*1
K8T2: TMSOP-8, Ta
p
e
Operation temperature
A: Ta = −40°C to +125°C
Option code*2
Fixed value
*1. Refer to the tape drawing.
*2. A sequence number added by the optional function that is user-selected.
2. Package
Table 1 Package Drawing Codes
Package Name Dimension Tape Reel
TMSOP-8 FM008-A-P-SD FM008-A-C-SD FM008-A-R-SD
3. Product name list
Table 2
Product Name RST
_
_____
_
Pin*1 LOOP Pin Output Form*2 LOOP Pin Output*3
S-35770E01A-K8T2U Without pull-up resistor CMOS output "L"
*1. The pin with / without pull-up resistor is selectable. Refer to " Pin Functions".
*2. The pin of Nch open-drain output / CMOS output is selectable. Refer to " Pin Functions".
*3. The output status at power-on.
Remark Please contact our sales office for products with specifications other than the above.
FOR AUTOMOTIVE 125°C OPERATION 2-WIRE COUNTER CONVENIENCE TIMER
S-35770 Series Rev.1.3_00
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Pin Configuration
1. TMSOP-8
7
6
5
8
2
3
4
1
Top view
Figure 2
Table 3 List of Pins
Pin No. Symbol Description I/O Configuration
1 RST
_______
Input pin for
reset signal Input
CMOS input
(With / without
pull-up resistor is selectable)
2 NC*1 No connection − −
3 CLKIN
Input pin for
external clock Input CMOS input
4 VSS GND pin − −
5 LOOP Output pin for
counter loop flag Output Nch open-drain output /
CMOS output is selectable
6 SDA I/O pin for serial
data Bi-directional Nch open-drain output,
CMOS input
7 SCL Input pin for
serial clock Input CMOS input
8 VDD
Pin for positive
power supply − −
*1. The NC pin is electrically open.
Therefore, leave it open or connect it to VDD pin or VSS pin.
FOR AUTOMOTIVE 125°C OPERATION 2-WIRE COUNTER CONVENIENCE TIMER
Rev.1.3_00 S-35770 Series
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Pin Functions
1. SDA (I/O for serial data) pin
This is a data input / output pin for I2C-bus interface. The SDA pin inputs / outputs data by synchronizing with a clock
pulse from the SCL pin. This pin has CMOS input and Nch open-drain output. Generally in use, the SDA pin is pulled
up to VDD potential via a resistor, and is used with wired-OR connection of other device of Nch open-drain output or
open collector output.
2. SCL (Input for serial clock) pin
This is a clock input pin for I2C-bus interface. The SDA pin inputs / outputs data by synchronizing with this clock
3. RST
_______
(Input for reset signal) pin
This pin inputs the reset signal. The counter is reset when inputting "L" to the RST
_______
pin. When inputting "H" to the
RST
_______
pin, the count-up action of the counter is started.
Also, the RST
_______
pin with / without a pull-up resistor can be selected.
4. CLKIN (Input for external clock) pin
This pin inputs an external clock. The counter is incremented by 1 when the CLKIN pin input changes from "L" to "H".
5. LOOP (Output for counter loop flag) pin
Each time the counter loops back to 0 after reaching 16,777,215, the LOOP pin performs a toggle operation.
Regarding the operation of the LOOP pin, refer to " LOOP Pin".
The LOOP pin output form of Nch open-drain output / CMOS output can be selected.
6. VDD (Positive power supply) pin
Connect this pin with a positive power supply. Regarding the values of voltage to be applied, refer to
" Recommended Operation Condition".
7. VSS pin
Connect this pin to GND.
FOR AUTOMOTIVE 125°C OPERATION 2-WIRE COUNTER CONVENIENCE TIMER
S-35770 Series Rev.1.3_00
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Equivalent Circuits of Pins
CLKIN, SCL
Figure 3 CLKIN Pin and SCL Pin
SDA
Figure 4 SDA Pin
RST
_
______
Figure 5 RST
_______
Pin (With Pull-up Resistor)
RST
_
______
Figure 6 RST
_______
Pin (Without Pull-up Resistor)
LOOP
Figure 7 LOOP Pin (Nch Open-drain Output)
LOOP
Figure 8 LOOP Pin (CMOS Output)
FOR AUTOMOTIVE 125°C OPERATION 2-WIRE COUNTER CONVENIENCE TIMER
Rev.1.3_00 S-35770 Series
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Absolute Maximum Ratings
Table 4
Item Symbol Applied Pin Absolute Maximum Rating Unit
Power supply voltage VDD − V
SS − 0.3 to VSS + 6.5 V
Input voltage VIN CLKIN, SDA, SCL, RST
_
_____
_
*1 VSS − 0.3 to VSS + 6.5 V
RST
_
_____
_
*2 VSS − 0.3 to VDD + 0.3 ≤ VSS + 6.5 V
Output voltage VOUT SDA, LOOP*3 VSS − 0.3 to VSS + 6.5 V
LOOP *4 VSS − 0.3 to VDD + 0.3 ≤ VSS + 6.5 V
Operation ambient
temperature*5 Topr − −40 to +125 °C
Storage temperature Tst
g
− −55 to +150 °C
*1. When a product without a pull-up resistor is selected.
*2. When a product with a pull-up resistor is selected.
*3. When an Nch open-drain output product is selected.
*4. When a CMOS output product is selected.
*5. Conditions with no condensation or frost. Condensation or frost causes short-circuiting between pins, resulting in a
malfunction.
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
Recommended Operation Condition
Table 5
(VSS = 0 V)
Item Symbol Condition Min. Typ. Max. Unit
Operation power supply voltage VDD Ta = −40°C to +125°C 1.5 − 5.5 V
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S-35770 Series Rev.1.3_00
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DC Electrical Characteristics
Table 6
(Ta = −40°C to +125°C, VSS = 0 V)
Item Symbol Applied Pin Condition Min. Typ. Max. Unit
Current
consumption 1 IDD1 −
VDD = 3.0 V,
Ta = −40°C to +85°C,
Out of communication
(CLKIN pin = 0 V),
LOOP pin = no load
− 0.01 0.1
μA
VDD = 3.0 V,
Ta = +125°C,
Out of communication
(CLKIN pin = 0 V),
LOOP pin = no load
− 0.7 0.95 μA
Current
consumption 2 IDD2 −
VDD = 3.0 V,
fSCL = 1 MHz,
During communication,
LOOP pin = no load
− 170 300 μA
High level input
leakage current IIZH
CLKIN, SDA, SCL,
RST
_______
VIN = VDD −0.5 − 0.5 μA
Low level input
leakage current IIZL
CLKIN, SDA, SCL,
RST
_______
*1 VIN = VSS −0.5 − 0.5 μA
High level output
leakage current IOZH SDA VOUT = VDD −0.5 − 0.5 μA
Low level output
leakage current IOZL SDA VOUT = VSS −0.5 − 0.5 μA
High level input
voltage VIH
CLKIN, SDA, SCL,
RST
_______
*1 − 0.7 × VDD − V
SS + 5.5 V
RST
_
_____
_
*2 − 0.7 × VDD − V
DD + 0.3 V
Low level input
voltage VIL
CLKIN, SDA, SCL,
RST
_______
− V
SS − 0.3 − 0.3 × VDD V
Low level output
voltage VOL SDA IOL = 2.0 mA − − 0.4 V
Low level input
current*2 IIL RST
_______
VDD = 3.0 V,
VIN = VSS −100 −30 −5 μA
*1. When a product without a pull-up resistor is selected.
*2. When a product with a pull-up resistor is selected.
FOR AUTOMOTIVE 125°C OPERATION 2-WIRE COUNTER CONVENIENCE TIMER
Rev.1.3_00 S-35770 Series
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AC Electrical Characteristics
Table 7 Measurement Conditions
0.8 × VDD
Input pulse voltage Output reference voltage
0.2 × VDD
0.7 × VDD
0.3 × VDD
Figure 9 Input / Output Waveform during AC Measurement
Input pulse voltage VIH = 0.8 × VDD,
VIL = 0.2 × VDD
Input pulse rise / fall time 20 ns
Output reference voltage VOH = 0.7 × VDD,
VOL = 0.3 × VDD
Output load 100 pF
Table 8 AC Electrical Characteristics
(Ta = −40°C to +125°C)
Item Symbol VDD = 1.5 V to 2.5 V VDD = 2.5 V to 5.5 V Unit
Min. Max. Min. Max.
SCL clock frequency fSCL 0 400 0 1000 kHz
SCL clock "L" time tLOW 1.3 − 0.4 − μs
SCL clock "H" time tHIGH 0.6 − 0.3 − μs
SDA output delay time*1 tAA − 0.9 − 0.5 μs
Start condition set-up time tSU.STA 0.6 − 0.25 − μs
Start condition hold time tHD.STA 0.6 − 0.25 − μs
Data input set-up time tSU.DAT 100 − 80 − ns
Data input hold time tHD.DAT 0 − 0 − ns
Stop condition set-up time tSU.STO 0.6 − 0.25 − μs
SCL, SDA rise time tR − 0.3 − 0.3 μs
SCL, SDA fall time tF − 0.3 − 0.3 μs
Bus release time tBUF 1.3 − 0.5 − μs
Noise suppression time tl− 50 − 50 ns
CLKIN clock frequency fCLKIN 0 400 0 1000 kHz
CLKIN clock "L" time tCLKIN
_
L 1.3 − 0.4 − μs
CLKIN clock "H" time tCLKIN
_
H 0.6 − 0.3 − μs
CLKIN rise time tCLKIN
_
R − 0.3 − 0.3 μs
CLKIN fall time tCLKIN
_
F − 0.3 − 0.3 μs
*1. Since the output form of the SDA pin is Nch open-drain output, the SDA output delay time is determined by the values of
the load resistance and load capacitance outside the IC. Figure 11 shows the relationship between the output load
values.
FOR AUTOMOTIVE 125°C OPERATION 2-WIRE COUNTER CONVENIENCE TIMER
S-35770 Series Rev.1.3_00
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SCL
SDA
(S-35770 input)
SDA
(S-35770 output)
tBUF
tR
tSU.STO
tSU.DAT
tHD.DAT
tAA
tHIGH tLOW
tHD.STA
tSU.STA
tF
Figure 10 Bus Timing
1
3
5
7
9
11
13
15
Load capacitance [pF]
Maximum pull-up resistance [k]
10
fSCL = 1.0 MHz
fSCL = 400 kHz
100 1000
Figure 11 Output Load
CLKIN
tCLKIN_H tCLKIN_L tCLKIN_F tCLKIN_R
Figure 12 CLKIN Pin Clock Timing
FOR AUTOMOTIVE 125°C OPERATION 2-WIRE COUNTER CONVENIENCE TIMER
Rev.1.3_00 S-35770 Series
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External Clock Signal Count Function
The S-35770 Series detects the change of the CLKIN pin from "L" to "H", and then starts the count-up action of the
counter. The counter is a 24-bit binary counter which can count from 0 to 16,777,215 (FFFFFF h). After reaching
16,777,215, the S-35770 Series detects the change of the CLKIN pin from "L" to "H", the counter loops back to 0.
The counter value can be confirmed by reading the count register. To initialize the counter, input "L" to the RST
_______
pin or
input the reset command to the free register. Regarding the count register and the reset command, refer to
" Configuration of registers".
RST
CLKIN
Counter 16,777,21516,777,214
100 0 0123 123 123
The counter starts the count-up action
at the rising edge of CLKIN pin.
The counter is reset by
the reset command.
The counter loops back to 0.
The counter does
not start the
count-up action at
RST pin = "L".
The counter is reset
at RST pin = "L".
Figure 13 Counter Operation
During communication, the S-35770 Series does not detect the change of the CLKIN pin from "L" to "H" and maintains
the counter data. The duration of the communication is defined as the time period from the start condition to the stop
condition. The count-up action of the counter is executed 1 time if the CLKIN pin is "L" when the start condition is
recognized and if the CLKIN pin is "H" when the stop condition is recognized.
SDA
STA STA STA STA STASTO STO STO STO STO
CLKIN
Counter 012 34 5 6
RST
The counter does not
start the count-up action
during communication.
The counter does not
start the count-up action
during communication.
The counter does not start
the count-up action.
The counter does not start the count-up action during
communication.
The counter starts the count-up action 1 time when
communication ends.
Figure 14 Counter Operation during Communication
FOR AUTOMOTIVE 125°C OPERATION 2-WIRE COUNTER CONVENIENCE TIMER
S-35770 Series Rev.1.3_00
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LOOP Pin
The S-35770 Series detects the change of the CLKIN pin from "L" to "H", and then starts the count-up action of the
counter. The counter loops back to 0 after reaching 16,777,215. At this time, the LOOP pin changes from "H" to "L". To
change the LOOP pin to "H", input "L" to the RST
_______
pin or input the reset command to the free register.
Furthermore, if the counter loops back to 0 again after reaching 16,777,215 under the condition the LOOP pin maintains
"L", the LOOP pin changes from "L" to "H". In other word, each time the counter loops back to 0 after reaching
16,777,215, the LOOP pin performs a toggle operation.
Remark The above description is the example of Nch open-drain output product.
In CMOS output product, the LOOP pin output is the inverse logic of Nch open-drain output product.
CLKIN
Counter 16,777,21516,777,21516,777,21516,777,214
10000023 12 12 12
RST
LOOP
Counter reset
LOOP pin "H""L"
Counter reset
LOOP pin"L""H"
Counter reset
by RST pin = "L" input or reset command input.
LOOP pin"L""H"
Figure 15 LOOP Pin Operation (Nch Open-drain Output)
CLKIN
Counter
16,777,21516,777,21516,777,21516,777,214
10000023 12 12 12
RST
LOOP
Counter reset
LOOP pin "L""H"
Counter reset
LOOP pin "H""L"
Counter reset
by RST pin = "L" input or reset command input.
LOOP pin"H""L"
Figure 16 LOOP Pin Operation (CMOS Output)
FOR AUTOMOTIVE 125°C OPERATION 2-WIRE COUNTER CONVENIENCE TIMER
Rev.1.3_00 S-35770 Series
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Configuration of Registers
1. Count register
The count register is a 3-byte register that stores the counter value as binary code.
The count register is read-only.
Perform the read operation of the count register in 3-byte unit from CNT23 to CNT0.
Example: 3 (0000_0000_0000_0000_0000_0011)
45 (0000_0000_0000_1010_1000_1100)
19,800 (0000_0000_0100_1101_0101_1000)
CNT0
CNT1
CNT2
CNT3
CNT4
CNT5
CNT6
CNT7
B7 B0
CNT8
CNT9
CNT10
CNT11
CNT12
CNT13
CNT14
CNT15
B7 B0
CNT16
CNT17
CNT18CNT19
CNT20
CNT21CNT22 CNT23
B7 B0
Figure 17
2. Free register
The free register is a 3-byte register that can be freely read and written by the user. The lower 3 bits, RST2 to RST0 are
used as a register to input the counter reset command. The counter is reset by writing RST2 = "0", RST1 = "1", and
RST0 = "0". The data of F20 to F0 are not reset when inputting the reset command; however, the data when the reset
command is input are set.
When only the data of F20 to F0 are rewritten without resetting the counter, write the data except for the above
mentioned ones, such as RST2 = "1", RST1 = "1" and RST0 = "1" to the free register.
Perform the write and read operation of the free register in 3-byte unit.
RST0 RST1
RST2
F0
F1F2F3
F4
B7 B0
F5
F6
F7 F8
F9 F10
F11
F12
B7 B0
F13
F14
F15 F16 F17 F18 F19
F20
B7 B0
Figure 18
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S-35770 Series Rev.1.3_00
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Serial Interface
The S-35770 Series transmits and receives various commands via I2C-bus serial interface to read / write data.
1. Start condition
When SDA changes from "H" to "L" with SCL at "H", the S-35770 Series recognizes start condition and the access
operation is started.
2. Stop condition
When SDA changes from "L" to "H" with SCL at "H", the S-35770 Series recognizes stop condition and the access
operation is completed. The S-35770 Series enters standby mode, consequently.
t
SU.STA
t
HD.STA
t
SU.STO
Start condition Stop condition
SDA
SCL
Figure 19 Start / Stop Condition
3. Data transmission and acknowledge
The data transmission is performed at every one byte after the start condition detection. Pay attention to the
specification of tSU.DAT and tHD.DAT when changing SDA, and perform the operation when SCL is "L". If SDA changes
when SCL is "H", the start / stop condition is recognized even during the data transmission, and the access operation
will be interrupted.
Whenever a one-byte data is received during data transimmion, the receiving device returns an acknowledge. For
example, as shown in Figure 20, assume that the S-35770 Series is a receiving device, and the master device is a
transmitting device. If the clock pulse at the 8th bit falls, the master device releases SDA. Consequently, the S-35770
Series, as an acknowledge, sets SDA to "L" during the 9th bit pulse. The access operation is not performed properly
when the S-35770 Series does not output an acknowledge.
tHD.DAT
tSU.DAT
1 8 9
Acknowledge
output
(Active "L")
tAA
Start Condition
SCL
(S-35770 input)
SDA
(
Master device output)
SDA
(S-35770 output)
High-Z
Release SDA
High-Z
Figure 20 Acknowledge Output Timing
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4. Data transmission format
After the start condition transmission, the 1st byte is a slave address and a command (read / write bit) that shows the
transmission direction at the 2nd byte or subsequent bytes.
The slave address of the S-35770 Series is specified to "0110010". The data can be written to the free register when
read / write bit is "0", and the data of count register or the free regiister can be read when read / write bit is "1".
When the data can be written to the free register, input the data from the master device in order of B7 to B0. The
acknowledge ("L") is output from the S-35770 Series whenever a one-byte data is input.
When the data of the count register or the free register can be read, the data from the S-35770 Series is output in
order of B7 to B0 in byte unit. Input the acknowledge ("L") from the master device whenever a one-byte data is input.
However, do not input the acknowledge for the last byte (NO_ACK). By this, the end of the data read is informed.
After the master device receives / transmits the acknowledge for the last byte data, input the stop condition to the
S-35770 Series to finish the access operation.
When the master device inputs start condition instead of stop condition, the S-35770 Series becomes restart condition,
and can transmit / receive the data if the master device inputs the slave address continuously.
A
: Master device input data
: S-35770 output data
Slave address
Slave address
Slave address
Data Data Data Data
A
A
A
A
0
B7 B1 B7 B0 B7 B0 B7 B0 B7 B0
SPST
A
Data Data Data
A
A
A
1
B7 B0 B7 B0 B7 B0
A
Data Data Data Data
A
A
A
A
0
B7 B0 B7 B0 B7 B0 B7 B0
A
Slave address Data Data Data
A
A
A
1
B7 B1 R/W B7 B0 B7 B0 B7 B0
SP ST
ST
ST
B7 B1
B7 B1
SP
A
:
Start condition
: Acknowledge
A A
: Stop condition
ST SP
R/W
R/W
R/W
1918 27 36 45
Data write
format
Data read
f
ormat
Restart format
SCL
SD
A
SD
A
SD
A
Figure 21 Data Transmission Format of Serial Interface
In the time period from the start condition to the stop condition, the S-35770 Series does not detect the change of the
CLKIN pin from "L" to "H" and maintains the counter data. Therefore, the output data of the count register does not
change even if an external clock is input during a read operation of the count register.
Regarding the counter operation during communication, refer to " External Clock Signal Count Function".
FOR AUTOMOTIVE 125°C OPERATION 2-WIRE COUNTER CONVENIENCE TIMER
S-35770 Series Rev.1.3_00
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5. Read operation of count register
Transmit the start condition and slave address from the master device. The slave address of the S-35770 Series is
specified to "0110010". The data of the count register can be read when the read / write bit is "1".
The 2nd byte to the 4th byte are used as the count register. Each byte from B7 is transmitted.
When the read operation of the count register is finished, transmit "1" (NO_ACK) to the acknowledge after B0 is output
from the master device, and then transmit the stop condition.
The count register is a 3-byte register. "1" is read if the read operation is performed continuously after reading 3 bytes
of the count register. Regarding the count register, refer to " Configuration of Registers".
Disable time period of count-up action
ACK
CNT23
CNT22
CNT21
CNT20
CNT19
CNT18
CNT17
CNT16
CNT15
CNT13
CNT12
CNT11
CNT10
CNT9
CNT8
CNT7
CNT14
CNT6
CNT5
CNT4
CNT3
CNT2
CNT1
CNT0
118927 36
0
Slave address
(0110010)
Input NO_ACK after the 3rd byte data is transmitted.
Count register (3-byte)
: Master device input data
: S-35770 output data
START
11
B7
001 10
B1 R/
W
A
C
K
A
C
K
NO_ACK
STOP
B7 B0 B7 B7B0 B0
SCL
SD
A
Figure 22 Read Timing of Count Register
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Rev.1.3_00 S-35770 Series
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6. Write operation of free register
Transmit the start condition and slave address from the master device. The slave address of the S-35770 Series is
specified to "0110010". Next, transmit "0" to the read / write bit.
Transmit the 2nd byte data. Set B7 to "1" since it is an address pointer. Set B6 to B1 to "0" or "1" since they are dummy
data. Be sure to set B0 to "1" since it is a test bit.
B7 in the 3rd byte to B3 in the 5th byte are used as the free register.
B2 to B0 (RST2 to RST0) in the 5th byte are used as a register to input the counter reset command. The counter is
reset when transmitting RST2 = "0", RST1 = "1" and RST0 = "0". When not resetting the counter, transmit the data
except for the above mentioned ones, such as RST2 = "1", RST1 = "1" and RST0 = "1".
Transmit the stop condition from the master device to finish the access operation.
Regarding the free register, refer to " Configuration of Registers".
Write operation of the free register is performed each byte, so transmit the data in 3-byte unit. Note that the S-35770
Series may not operate as desired if the data is not transmitted in 3-byte unit.
Dummy data
*1
Slave address
(0110010)
Free register (3-byte)
Make sure to set B0 to "1" since it is a test bit.
: Master device input data
: S-35770 output data
S
CL
S
DA
Set B7 as an address pointer.
F[20:13]
Write timing
F[12:5]
Write timing
F[4:0], RST[2:0]
Write timing
0
START
11001 1
0
B1 R/W
STOP
ACK
F20
B7 B0 B7 B7B0 B0
01
ACK
F19
F18
F17
F16
F15
F14
F13
ACK
ACK
ACK
F12
F11
F10
F9
F8
F7
F6
F5
F4
F3
F2
F1
F0
RST2
RST1
RST0
B7B0
1 189 27 36 45
B7
Disable time period of count-up action
*1. Set B6 to B1 to "0" or "1" since they are dummy data.
Figure 23 Write Timing of Free Register
FOR AUTOMOTIVE 125°C OPERATION 2-WIRE COUNTER CONVENIENCE TIMER
S-35770 Series Rev.1.3_00
18
7. Read operation of free register
Perform the read operation of the free register with the restart format. Regarding the restart format, refer to
"4. Data transmission format".
Transmit the start condition and the slave address from the master device. The slave address of the S-35770 Series is
specified to "0110010". Next, transmit "0" to the read / write bit.
B7 in the 2nd byte is an address pointer. Set B7 to "0" when reading the free register. Next, transmit the dummy data to
B6 to B1. Make sure to set B0 to "1" since it is a test bit. This processing is called "dummy write".
Then transmit the start condition, the slave address and the read / write bit. If the read / write bit is set to "1", the
S-35770 Series becomes the mode to read the free register.
Consequently, the data of the free register is output from the S-35770 Series. Each byte from B7 is transmitted.
When the read operation of the free register is finished, transmit "1" (NO_ACK) to the acknowledge after B0 output
from the master device, and then transmit the stop condition.
The free register is a 3-byte register. "1" is read if the read operation is performed continuously after reading 3 bytes of
the free register.
Regarding the free register, refer to " Configuration of Registers".
Moreover, the internal address pointer is reset if recognizing the stop condition. Therefore, do not transmit the stop
condition after dummy write operation. The counter data is read when reading the free register after transmission of
the stop condition.
19 181 9 18 27 36
SCL
1
ACK
ACK
START
ACK
ACK
NO_ACK
STOP
F20
F19
F18
F17
F16
F15
F14
F13
0100110
B1B7 B0B7 B0B7 B0B7
F12
F11
F10
F9
F8
F7
F6
F5
F4
F3
F2
F1
F0
RST2
RST1
RST0
SDA
Free register (3-byte)
0
B0B7
Dummy data*1
Dummy write
Slave address
(0110010)
1
ACK
START
0100110
B1
R/W
0
R/W
B7
Slave address
(0110010)
Make sure to set B0 to "1" since it is a test bit.
Input NO_ACKafter
the 3rd byte transmission.
Set B7 as an address pointer.
*1. Set B6 to B1 to "0" or "1" since they are dummy data.
: S-35770 output data
: Master device input data
Disable time period of count-up action
Figure 24 Read Timing of Free Register
FOR AUTOMOTIVE 125°C OPERATION 2-WIRE COUNTER CONVENIENCE TIMER
Rev.1.3_00 S-35770 Series
19
Release of SDA
The RST
_______
pin of the S-35770 Series does not perform the reset operation of the communication interface. Therefore,
the stop condition is input to reset the internal interface circuit usually.
However, the S-35770 Series does not accept the stop condition from the master device when in the status that SDA
outputs "L" (at the time of acknowledge outputting or reading). Consequently, it is necessary to finish the acknowledge
output or the read operation. Figure 25 shows the SDA release method.
First, input the start condition from the master device (since SDA of the S-35770 Series outputs "L", the S-35770 Series
can not detect the start condition). Next, input the clocks for 1-byte data access (9 clocks) from SCL. During the time,
release SDA of the master device. By this, the SDA input / output before communication interrupt is completed, and
SDA of the S-35770 Series becomes release status. Continuously, if the stop condition is input, the internal circuit
resets and the communication returns to normal status.
It is strongly recommended that the SDA release method is performed at the time of system initialization after the power
supply voltage of the master device rises.
12 8 9
SCL
SDA
(S-35770 output) "L" or High-Z
"L" High-Z
"L" or High-Z
Start condition Clocks for 1-byte data access Stop condition
SDA
(Master device output)
"L"
SDA
Figure 25 SDA Release Method
Power-on Detection Circuit
In order for the power-on detection circuit to operate normally, raise the power supply voltage of the IC from 0.2 V or lower
so that it reaches 1.5 V of the operation power supply voltage minimum value within 10 ms, as shown in Figure 26.
Within 10 ms
1.5 V
(Operation power
supply voltage min.)
0 V
*1
0.2 V or lower
*1. 0 V means that there is no potential difference between the VDD pin and the VSS pin of the S-35770 Series.
Figure 26 How to Raise the Power Supply Voltage
FOR AUTOMOTIVE 125°C OPERATION 2-WIRE COUNTER CONVENIENCE TIMER
S-35770 Series Rev.1.3_00
20
Example of Application Circuit
VIN VOUT
VSS
VR
VDD
VSS
SCL
SDA
RST
S-35770
VCC
VSS
V
CC
12 V CPU
LOOP
CLKIN
External clock
S-19xxx
1 kΩ
1 kΩ
10 kΩ
10 kΩ
*1
*2
*1. This resistor is unnecessary when a CMOS output product is selected.
*2. This resistor is unnecessary when a product with a pull-up resistor is selected.
Figure 27
Caution 1. Start communication under stable condition after turning on the system power supply.
2. The above connection diagrams do not guarantee operation. Set the constants after performing
sufficient evaluation using the actual application.
FOR AUTOMOTIVE 125°C OPERATION 2-WIRE COUNTER CONVENIENCE TIMER
Rev.1.3_00 S-35770 Series
21
Precautions
• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
• ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by products
including this IC of patents owned by a third party.
FOR AUTOMOTIVE 125°C OPERATION 2-WIRE COUNTER CONVENIENCE TIMER
S-35770 Series Rev.1.3_00
22
Characteristics (Typical Data)
1. Current consumption 1 vs.
Power supply voltage characteristics
2. Current consumption 2
vs.
SCL frequency characteristics
Ta = +25°C Ta = +25°C
6
0.0
1.0
0.8
0.6
0.4
0.2
420
IDD1 [A]
VDD
[V]
1500
0
600
10005000
I
DD2
[A]
SCL frequency [kHz]
300
200
100
400
500 V
DD
= 5.0 V
V
DD
= 3.0 V
3. Current consumption 1 vs.
Temperature characteristics
4. Current consumption 1 vs. CLKIN frequency characteristics
40 25 0 25 50 75 100 125
Ta [°C]
0.0
1.0
0.8
0.6
0.4
0.2
I
DD1
[A]
V
DD
= 3.0 V
V
DD
= 5.0 V
1500
0
90
10005000
IDD1
[A]
CLKIN frequency [kHz]
80
70
60
50
40
30
20
10
VDD = 5.0 V
VDD = 3.0 V
5. Low level output current vs. Output voltage characteristics
6. High level output current vs. V
DD
−
V
OUT
characteristics
LOOP pin, SDA pin,
Ta = +25°C
LOOP pin, Ta = +25°C,
CMOS output product
6
0
70
420
IOL [mA]
VOUT
[V]
60
50
40
30
20
10
VDD = 5.0 V
VDD = 3.0 V
6
25
0
420
IOH [mA]
VDD VOUT
[V]
5
10
15
20
VDD = 3.0 V
VDD = 5.0 V
7. Low level input current vs. Power supply voltage characteristics
RST
_______
pin, Ta = +25°C,
Product with pull-up resistor
60
0
420
I
IL
[A]
30
40
50
20
10
V
DD
[V]
6
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
2.90±0.2
85
0.2±0.1
0.65±0.1
0.13±0.1
14
TMSOP8-A-PKG Dimensions
No. FM008-A-P-SD-1.2
FM008-A-P-SD-1.2
mm
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
0.30±0.05
1.00±0.1
1.05±0.05
1.5
2.00±0.05
4.00±0.1
3.25±0.05
4.00±0.1
1
4
58
TMSOP8-A-Carrier Tape
Feed direction
No. FM008-A-C-SD-2.0
FM008-A-C-SD-2.0
+0.1
-0
mm
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
16.5max.
13.0±0.3
QTY. 4,000
(60°)
(60°)
13±0.2
Enlarged drawing in the central part
TMSOP8-A-Reel
No. FM008-A-R-SD-1.0
FM008-A-R-SD-1.0
mm
Disclaimers (Handling Precautions)
1. All the information described herein
(product data,
specifications,
figures,
tables,
programs,
algorithms and application
circuit examples,
etc.)
is current as of publishing date of this document and is subject to change without notice.
2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not responsible for damages caused by the reasons other than the products described herein
(hereinafter "the products") or infringement of third-party intellectual property right and any other right due to the use
of the information described herein.
3. ABLIC Inc. is not responsible for damages caused by the incorrect information described herein.
4. Be careful to use the products within their specified ranges. Pay special attention to the absolute maximum ratings,
operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not responsible for damages caused by failures and / or accidents, etc. that occur due to the use of the
products outside their specified ranges.
5. When using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7. The products must not be used or provided (exported) for the purposes of the development of weapons of mass
destruction or military use. ABLIC Inc. is not responsible for any provision (export) to those whose purpose is to
develop, manufacture, use or store nuclear, biological or chemical weapons, missiles, or other military use.
8. The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses. Do
not apply the products to the above listed devices and equipments without prior written permission by ABLIC Inc.
Especially, the products cannot be used for life support devices, devices implanted in the human body and devices
that directly affect human life, etc.
Prior consultation with our sales office is required when considering the above uses.
ABLIC Inc. is not responsible for damages caused by unauthorized or unspecified use of our products.
9. Semiconductor products may fail or malfunction with some probability.
The user of the products should therefore take responsibility to give thorough consideration to safety design including
redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing injury or
death, fires and social damage, etc. that may ensue from the products' failure or malfunction.
The entire system must be sufficiently evaluated and applied on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc.
The information described herein does not convey any license under any intellectual property rights or any other
rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any
part of this document described herein for the purpose of disclosing it to a third-party without the express permission
of ABLIC Inc. is strictly prohibited.
14. For more details on the information described herein, contact our sales office.
2.2-2018.06
www.ablic.com
