February 2008 Rev 1 1/10
EMIF02-MIC03M6
2-line IPAD™, EMI filter and ESD protection for microphone
Features
■EMI symmetrical (I/O) low-pass filter
■High efficiency in EMI filtering
■Very low PCB space consumption:
1.0 mm x 1.45 mm
■Very thin package: 0.6 mm max
■High efficiency in ESD suppression
■High reliability offered by monolithic integration
■High reduction of parasitic elements through
integration and wafer level packaging.
■Lead-free and halogen-free package
Complies with following standards
■IEC 61000-4-2 level 4, input and output pins
– 8 kV (contact discharge)
Application
■Mobile phones
Description
The EMIF02-MIC03M6 is a 2-line highly
integrated device designed to suppress EMI/RFI
noise in all systems exposed to electromagnetic
interference.
This filter includes ESD protection circuitry, which
prevents damage to the application when
subjected to ESD surges up to 8 kV on all pins.
Figure 1. Pin configuration (top view)
Figure 2. Basic cell configuration
TM: IPAD is a trademark of STMicroelectronics
Micro QFN 6 leads
1.45 mm x 1.00 mm
(bottom view)
Pin 1
6
25
4
MICR in MICR out
MICL in MICL out
GND GND
1
3
Input Output
Low-pass filter
GND GND GND
R = 68 , Cline = 45 pF typ.Ω
www.st.com
Characteristics EMIF02-MIC03M6
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1 Characteristics
Table 1. Absolute ratings (limiting values at Tamb = 25 °C unless otherwise specified)
Symbol Parameter Value Unit
VPP ESD discharge IEC61000-4-2 contact discharge 8 kV
TjJunction temperature 125 °C
Top Operating temperature range -40 to + 85 °C
Tstg Storage temperature range -55 to +150 °C
Table 2. Electrical characteristics (Tamb = 25 °C)
Symbol Parameter
VBR Breakdown voltage
IRM Leakage current @ VRM
VRM Stand-off voltage
VCL Clamping voltage
RdDynamic resistance
IPP Peak pulse current
RI/O Series resistance between Input & Output
Cline Input capacitance per line
Symbol Test conditions Min. Typ. Max. Unit
VBR IR = 1 mA 6 8 V
IRM VRM = 3 V per line 500 nA
RI/O Tolerance ± 20% 68 Ω
Cline (1) VR = 0 V, F = 1 MHz, VOSC = 30 mV 45 pF
1. Tolerance ±20%
I
V
I
PP
V
CL
V
BR
V
RM
I
R
I
RM
I
RM
I
R
I
PP
V
RM
V
BR
V
CL
Figure 3. S21 attenuation measurement Figure 4. Analog cross talk measurements
(MIC R / MIC L)
300.0k 1.0M 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G
-40.00
-35.00
-30.00
-25.00
-20.00
-15.00
-10.00
-5.00
0.00
dB
F (Hz)
300.0k 1.0M 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G
-80.00
-70.00
-60.00
-50.00
-40.00
-30.00
-20.00
-10.00
0.00
R-L Xtalk L-R
300.0k 1.0M 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G
-80.00
-70.00
-60.00
-50.00
-40.00
-30.00
-20.00
-10.00
0.00
Xtalk L
dB
F (Hz)
EMIF02-MIC03M6 Ordering information scheme
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2 Ordering information scheme
Figure 7. Ordering information scheme
Figure 5. ESD response to IEC 61000-4-2
(+8 kV air discharge) on MIC lines
Figure 6. ESD response to IEC 61000-4-2
(-8 kV air discharge) on MIC lines
vi = 20 V/d
vo = 10 V/d
20 ns/d
Input
Output
vi = 20 V/d
vo = 10 V/d
20 ns/d
Input
Output
EMIF yy - xxx zz Mx
EMI Filter
Number of lines
Information
Package
xxx = application
zz = version
Mx = Micro QFN x leads
Package information EMIF02-MIC03M6
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3 Package information
●Epoxy meets UL94, V0
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at
www.st.com.
Table 3. Micro QFN 1.45 x 1.00 6L dimensions
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 0.50 0.55 0.60 0.020 0.022 0.024
A1 0.00 0.02 0.05 0.000 0.001 0.002
b 0.18 0.25 0.30 0.007 0.010 0.012
D 1.45 0.057
E 1.00 0.039
e 0.50 0.020
K 0.20 0.008
L 0.30 0.35 0.40 0.012 0.014 0.016
Figure 8. Footprint in mm [inches] Figure 9. Marking
E
D
A
A1
e
b
k
L
N
1
1
2
2
0.50
[0.020]
0.25
[0.010]
0.60
[0.023]
0.30
[0.012]
1.60
[0.063]
Dot : Pi n 1 Identification
L
EMIF02-MIC03M6 Package information
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Figure 10. Tape and reel specification
Note: Product marking may be rotated by 90° for assembly plant differentiation. In no case should
this product marking be used to orient the component for its placement on a PCB. Only pin
1 mark is to be used for this purpose.
4.00+/-0.1
1.75 +/- 0.1
4.00
φ1.5 +/- 0.1
3.5 +/- 0.03
User direction of unreeling
8.0 +/- 0.3
0.75
2.0+/-0.05 4.00+/-0.1
1.75 +/- 0.1
4.00
φ1.5 +/- 0.1
3.5 +/- 0.03
User direction of unreeling
All dimensions in mm
8.0 +/- 0.3
0.75 1.20
1.65
2.0+/-0.05
Dot identifying pin 1 location
LL L
Recommendation on PCB assembly EMIF02-MIC03M6
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4 Recommendation on PCB assembly
4.1 Stencil opening design
1. General recommendation on stencil opening design
a) Stencil opening dimensions: L (Length), W (Width), T (Thickness).
Figure 11. Stencil opening dimensions
b) General design rule
Stencil thickness (T) = 75 ~ 125 µm
2. Reference design
a) Stencil opening thickness: 100 µm
b) Stencil opening for leads: Opening to footprint ratio is 90%.
Figure 12. Recommended stencil window position
L
TW
Aspect Ratio W
T
----- 1.5≥=
Aspect Area LW×
2T L W+()
----------------------------0.66≥=
250 µm
650 µm
620 µm
236 µm
15 µm
15 µm
7µm 7µm
Footprint
Stencil window
Footprint
EMIF02-MIC03M6 Recommendation on PCB assembly
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4.2 Solder paste
1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004.
2. “No clean” solder paste is recommended.
3. Offers a high tack force to resist component movement during high speed.
4. Solder paste with fine particles: powder particle size is 20-45 µm.
4.3 Placement
1. Manual positioning is not recommended.
2. It is recommended to use the lead recognition capabilities of the placement system, not
the outline centering.
3. Standard tolerance of ± 0.05 mm is recommended.
4. 3.5 N placement force is recommended. Too much placement force can lead to
squeezed out solder paste and cause solder joints to short. Too low placement force
can lead to insufficient contact between package and solder paste that could cause
open solder joints or badly centered packages.
5. To improve the package placement accuracy, a bottom side optical control should be
performed with a high resolution tool.
6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is
recommended during solder paste printing, pick and place and reflow soldering by
using optimized tools.
4.4 PCB design preference
1. To control the solder paste amount, the closed via is recommended instead of open
vias.
2. The position of tracks and open vias in the solder area should be well balanced. The
symmetrical layout is recommended, in case any tilt phenomena caused by
asymmetrical solder paste amount due to the solder flow away.
Recommendation on PCB assembly EMIF02-MIC03M6
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4.5 Reflow profile
Figure 13. ST ECOPACK® recommended soldering reflow profile for PCB mounting
Note: Minimize air convection currents in the reflow oven to avoid component movement.
0
01234567
Time (min)
Temperature (°C)
2°C/s recommended
6°C/s max
220°C
125 °C
260°C max
255°C
180°C
90 sec max
10-30 sec
90 to 150 sec
3°C/s max
0
01234567
Time (min)
Temperature (°C)
2°C/s recommended
6°C/s max
220°C
125 °C
260°C max
255°C
180°C
90 sec max
10-30 sec
90 to 150 sec
3°C/s max
EMIF02-MIC03M6 Ordering information
9/10
5 Ordering information
6 Revision history
Table 4. Ordering information
Order code Marking Package Weight Base qty Delivery mode
EMIF02-MIC03M6 L(1)
1. The marking can be rotated by 90° to differentiate assembly location
Micro QFN 2.2 mg 3000 Tape and reel (7”)
Table 5. Document revision history
Date Revision Changes
13-Feb-2008 1Initial release
EMIF02-MIC03M6
10/10
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