 
   
    
SGLS175 − AUGUST 2003
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DQualification in Accordance With
AEC-Q100
DQualified for Automotive Applications
DCustomer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval
DESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
DOutput Swing Includes Both Supply Rails
DExtended Common-Mode Input Voltage
Range ...0 V to 4.5 V (Min) With 5-V Single
Supply
DNo Phase Inversion
DLow Noise . . . 18 nV/Hz Typ at f = 1 kHz
DLow Input Offset Voltage
950 µV Max at TA = 25°C (TLV2422A)
DLow Input Bias Current ...1 pA Typ
DMicropower Operation ...50 µA Per
Channel
D600- Output Drive
Contact factory for details. Q100 qualification data available on
request.
description
The TLV2422 and TLV2422A are dual low-voltage
operational amplifiers from Texas Instruments.
The common-mode input voltage range for this
device has been extended over the typical CMOS
amplifiers making them suitable for a wide range
of applications. In addition, the devices do not
phase invert when the common-mode input is driven to the supply rails. This satisfies most design requirements
without paying a premium for rail-to-rail input performance. They also exhibit rail-to-rail output performance for
increased dynamic range in single- or split-supply applications. This family is fully characterized at 3-V and 5-V
supplies and is optimized for low-voltage operation. The TLV2422 only requires 50 µA of supply current per
channel, making it ideal for battery-powered applications. The TLV2422 also has increased output drive over
previous rail-to-rail operational amplifiers and can drive 600- loads for telecom applications.
Other members in the TLV2422 family are the high-power, TLV2442, and low-power, TLV2432, versions.
The TLV2422, exhibiting high input impedance and low noise, is excellent for small-signal conditioning for
high-impedance sources, such as piezoelectric transducers. Because of the micropower dissipation levels and
low-voltage operation, these devices work well in hand-held monitoring and remote-sensing applications. In
addition, the rail-to-rail output feature with single- or split-supplies makes this family a great choice when
interfacing with analog-to-digital converters (ADCs). For precision applications, the TLV2422A is available with
a maximum input offset voltage of 950 µV.
Copyright 2003, Texas Instruments Incorporated
  !"#$%" & '##% & "! (')*%" %+
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Advanced LinCMOS is a trademark of Texas Instruments.
Figure 1
V
OH
− High-Level Output Voltage − V
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
0
5
2
0816243240
IOH − High-Level Output Current − mA
4
1
3
412202836
TA = 85°C
TA = 125°C
TA = −40°C
TA = 25°C
VDD = 5 V
D PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
1OUT
1IN
1IN+
VDD/GND
VDD+
2OUT
2IN
2IN+
 
   
    
SGLS175 − AUGUST 2003
2POST OFFICE BOX 655303 DALLAS, TEXAS 75265
description (continued)
If the design requires single operational amplifiers, see the TI TLV2211/21/31. This is a family of rail-to-rail output
operational amplifiers in the SOT-23 package. Their small size and low power consumption, make them ideal
for high density, battery-powered equipment.
ORDERING INFORMATION
TAVIOmax
AT 25°CPACKAGEORDERABLE
PART NUMBER TOP-SIDE
MARKING
−40°C to 125°C
950 µVSOIC (D) Tape and reel TLV2422AQDRQ1 2422AQ
−40°C to 125°C2.5 mV SOIC (D) Tape and reel TLV2422QDRQ1 2422Q1
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available
at www.ti.com/sc/package.
1
1
1111
SGLS175 − AUGUST 2003
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3
equivalent schematic (each amplifier)
Q27
R9
Q29Q22
Q23
Q26
Q25
Q24
Q31 Q34 Q36
Q32
Q33 Q35
Q37
D1
Q30
R10
VB3
VB2
VB4
VDD+
VDD−/GND
OUT
R8
R1 R2
Q2 Q5
Q1 Q4
Q3
Q12
Q11
Q10Q6
Q7
Q8
Q9
VB3
VB4
C1
C2
C3
R5
R6
Q13 Q15
Q16
Q17
Q14
Q19
Q18
Q20
Q21
R7
R3 R4
V
B2
IN+
IN−
VB1
COMPONENT
COUNT
Transistors
Diodes
Resistors
Capacitors
69
5
26
6
 
   
    
2
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VDD (see Note 1) 12 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID (see Note 2) ±VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI (any input, see Note 1): C and I suffix 0.3 V to VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current, II (each input) ±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total current into VDD+ ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total current out of VDD ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duration of short-circuit current at (or below) 25°C (see Note 3) unlimited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: Q suffix 40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VDD+ and VDD .
2. Differential voltages are at IN+ with respect to IN−. Excessive current flows if input is brought below VDD − 0.3 V.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded.
DISSIPATION RATING TABLE
PACKAGE
TA
25
°
C
DERATING FACTOR
TA = 70
°
C
TA = 85
°
C
TA = 125
°
C
PACKAGE
TA 25 C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70 C
POWER RATING
TA = 85 C
POWER RATING
TA = 125 C
POWER RATING
D725 mW 5.8 mW/°C464 mW 377 mW 145 mW
recommended operating conditions
MIN MAX UNIT
Supply voltage, VDD±2.7 10 V
Input voltage range, VIVDD VDD+0.8 V
Common-mode input voltage, VIC VDD VDD+0.8 V
Operating free-air temperature, TA−40 125 °C
 
   
    
2
SGLS175 − AUGUST 2003
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electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TLV2422-Q1 TLV2422A-Q1
UNIT
PARAMETER
TEST CONDITIONS
A
MIN TYP MAX MIN TYP MAX
UNIT
VIO
Input offset voltage
25°C 300 2000 300 950
V
VIO Input offset voltage Full range 2500 1800 µV
VIO
Temperature
coefficient of input
2
2
V/°C
αVIO
coefficient of input
offset voltage Full range 2 2 µV/°C
Input offset voltage
long-term drift (see
Note 4)
VIC = 0,
VO = 0, VDD± = ±1.5 V
,
RS = 50 25°C0.003 0.003 µV/mo
IIO
Input offset current
25°C 0.5 60 0.5 60
pA
IIO Input offset current Full range 150 150 pA
IIB
Input bias current
25°C 1 60 1 60
pA
IIB Input bias current Full range 300 300 pA
VICR
Common-mode input
|VIO| 5 mV,
RS = 50
25°C0
to
2.5
−0.25
to
2.75
0
to
2.5
−0.25
to
2.75
V
VICR
Common-mode input
voltage range |VIO| 5 mV, RS = 50
Full range 0
to
2.2
0
to
2.2
V
High-level output
IOH = −100 µA 25°C 2.97 2.97
V
OH
High-level output
voltage
IOH = −500 A
25°C 2.75 2.75 V
VOH
voltage
IOH = −500 µAFull range 2.5 2.5
V
Low-level output
VIC = 0, IOL = 100 µA 25°C 0.05 0.05
V
OL
Low-level output
voltage
VIC = 0,
IOL = 250 A
25°C 0.2 0.2 V
VOL
voltage
VIC = 0, IOL = 250 µAFull range 0.5 0.5
V
Large-signal
V = 1.5 V,
RL = 10 k
25°C 6 10 6 10
A
VD
Large-signal
differential voltage VIC = 1.5 V,
VO = 1 V to 2 V
R
L
= 10 k
Full range 2 2 V/mV
AVD
differential voltage
amplification
V
O
= 1 V to 2 V
RL = 1 M25°C 700 700
V/mV
ri(d) Differential input
resistance 25°C1012 1012
ri(c) Common-mode input
resistance 25°C1012 1012
ci(c) Common-mode input
capacitance f = 10 kHz 25°C 8 8 pF
zoClosed-loop output
impedance f = 100 kHz, AV = 10 25°C 130 130
CMRR
Common-mode
VIC = VICR min, VO = 1.5 V,
25°C 70 83 70 83
dB
CMRR
Common-mode
rejection ratio
VIC = VICR min, VO = 1.5 V,
RS = 50 Full range 70 70 dB
kSVR
Supply-voltage
rejection ratio
VDD = 2.7 V to 8 V,
25°C 80 95 80 95
dB
kSVR
rejection ratio
(VDD/VIO)
VDD = 2.7 V to 8 V,
VIC = VDD/2, No load Full range 80 80 dB
IDD
Supply current
VO = 1.5 V,
No load
25°C 100 150 100 150
µA
I
DD
Supply current
V
O
= 1.5 V,
No load
Full range 175 175 µ
A
Full range is −40°C to 125°C for Q level part.
Referenced to 1.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
 
   
    
2
SGLS175 − AUGUST 2003
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
operating characteristics at specified free-air temperature, VDD = 3 V
PARAMETER
TEST CONDITIONS
TA
TLV2422-Q1,
TLV2422A-Q1
UNIT
PARAMETER
TEST CONDITIONS
TA
MIN TYP MAX
UNIT
VO = 1.1 V to 1.9 V,
RL = 10 k,
25°C 0.01 0.02
SR Slew rate at unity gain VO = 1.1 V to 1.9 V,
CL = 100 pFRL = 10 k
,Full
range 0.008 V/µs
Vn
Equivalent input noise voltage
f = 10 Hz 25°C 100
nV/Hz
VnEquivalent input noise voltage f = 1 kHz 25°C 23
nV/Hz
VN(PP)
Peak-to-peak equivalent input noise voltage
f = 0.1 Hz to 1 Hz 25°C 2.7
V
VN(PP) Peak-to-peak equivalent input noise voltage f = 0.1 Hz to 10 Hz 25°C 4 µV
InEquivalent input noise current 25°C 0.6 fAHz
THD + N
Total harmonic distortion plus noise
VO = 0.5 V to 2.5 V,
f = 1 kHz,
AV = 1
25°C
0.25%
THD + N Total harmonic distortion plus noise
O
f = 1 kHz,
R
L
= 10 kAV = 10 25°C1.8%
Gain-bandwidth product f = 10 kHz,
CL = 100 pFRL = 10 k,25°C 46 kHz
BOM Maximum output-swing bandwidth VO(PP) = 1 V,
RL = 10 k,AV = 1,
CL = 100 pF25°C 8.3 kHz
AV = −1,
To 0.1%
8.6
ts
Settling time
AV = −1,
Step = 0.5 V to 2.5 V,
To 0.1%
25°C
8.6
s
tsSettling time
Step = 0.5 V to 2.5 V,
R
L
= 10 k,
To 0.01%
25°C
16
µs
s
RL = 10 k,
C
L
= 100 pFTo 0.01% 16
φmPhase margin at unity gain
RL = 10 k‡,
CL = 100 pF
25°C62°
Gain margin
R
L
= 10 k
‡,
C
L
= 100 pF
25°C11 dB
Full range is −40°C to 125°C for Q level part.
Referenced to 1.5 V
 
   
    
2
SGLS175 − AUGUST 2003
8POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TLV2422-Q1 TLV2422A-Q1
UNIT
PARAMETER
TEST CONDITIONS
A
MIN TYP MAX MIN TYP MAX
UNIT
VIO
Input offset voltage
25°C 300 2000 300 950
V
VIO Input offset voltage Full range 2500 1800 µV
VIO
Temperature
coefficient of input
2
2
V/°C
αVIO
coefficient of input
offset voltage Full range 2 2 µV/°C
Input offset voltage
long-term drift (see
Note 4)
VIC = 0,
VO = 0, VDD± = ±2.5 V
,
RS = 50 25°C0.003 0.003 µV/mo
IIO
Input offset current
25°C 0.5 60 0.5 60
pA
IIO Input offset current Full range 150 150 pA
IIB
Input bias current
25°C 1 60 1 60
pA
IIB Input bias current Full range 300 300 pA
VICR
Common-mode input
|VIO| 5 mV,
RS = 50
25°C0
to
4.5
−0.25
to
4.75
0
to
4.5
−0.25
to
4.75
V
VICR
Common-mode input
voltage range |VIO| 5 mV, RS = 50
Full range 0
to
4.2
0
to
4.2
V
High-level output
IOH = −100 µA 25°C 4.97 4.97
V
OH
High-level output
voltage
IOH = −1 mA
25°C 4.75 4.75 V
VOH
voltage
IOH = −1 mA Full range 4.5 4.5
V
Low-level output
VIC = 2.5 V, IOL = 100 µA 25°C 0.04 0.04
V
OL
Low-level output
voltage
VIC = 2.5 V,
IOL = 500 A
25°C 0.15 0.15 V
VOL
voltage
VIC = 2.5 V, IOL = 500 µAFull range 0.5 0.5
V
Large-signal
V = 2.5 V,
RL = 10 k
25°C 8 12 8 12
A
VD
Large-signal
differential voltage VIC = 2.5 V,
VO = 1 V to 4 V
R
L
= 10 k
Full range 3 3 V/mV
AVD
differential voltage
amplification
V
O
= 1 V to 4 V
RL = 1 M25°C 1000 1000
V/mV
ri(d) Differential input
resistance 25°C1012 1012
ri(c) Common-mode input
resistance 25°C1012 1012
ci(c) Common-mode input
capacitance f = 10 kHz 25°C 8 8 pF
zoClosed-loop output
impedance f = 100 kHz, AV = 10 25°C 130 130
CMRR
Common-mode
VIC = VICR min, VO = 2.5 V,
25°C 70 90 70 90
dB
CMRR
Common-mode
rejection ratio
VIC = VICR min, VO = 2.5 V,
RS = 50 Full range 70 70 dB
kSVR
Supply-voltage
rejection ratio
VDD = 4.4 V to 8 V,
25°C 80 95 80 95
dB
kSVR
rejection ratio
(VDD/VIO)
VDD = 4.4 V to 8 V,
VIC = VDD/2, No load Full range 80 80 dB
IDD
Supply current
VO = 2.5 V,
No load
25°C 100 150 100 150
µA
I
DD
Supply current
V
O
= 2.5 V,
No load
Full range 175 175 µ
A
Full range is −40°C to 125°C for Q level part.
Referenced to 2.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
 
   
    
2
SGLS175 − AUGUST 2003
9
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
TA
TLV2422-Q1,
TLV2422A-Q1
UNIT
PARAMETER
TEST CONDITIONS
TA
MIN TYP MAX
UNIT
VO = 1.5 V to 3.5 V,
RL = 10 k,
25°C 0.01 0.02
SR Slew rate at unity gain VO = 1.5 V to 3.5 V,
CL = 100 pF
RL = 10 k
,
Full
0.008
V/µs
SR
Slew rate at unity gain
CL = 100 pF
Full
range 0.008
V/µs
Vn
Equivalent input noise voltage
f = 10 Hz 25°C 100
nV/Hz
VnEquivalent input noise voltage f = 1 kHz 25°C 18
nV/Hz
VN(PP)
Peak-to-peak equivalent input noise voltage
f = 0.1 Hz to 1 Hz 25°C 1.9
V
VN(PP) Peak-to-peak equivalent input noise voltage f = 0.1 Hz to 10 Hz 25°C 2.8 µV
InEquivalent input noise current 25°C 0.6 fAHz
THD + N
Total harmonic distortion plus noise
VO = 1.5 V to 3.5 V,
f = 1 kHz,
AV = 1
25°C
0.24%
THD + N Total harmonic distortion plus noise
O
f = 1 kHz,
R
L
= 10 kAV = 10 25°C1.7%
Gain-bandwidth product f = 10 kHz,
CL = 100 pFRL =10 k,25°C 52 kHz
BOM Maximum output-swing bandwidth VO(PP) = 2 V,
RL = 10 k,AV = 1,
CL = 100 pF25°C 5.3 kHz
AV = −1,
To 0.1%
8.5
ts
Settling time
AV = −1,
Step = 1.5 V to 3.5 V,
To 0.1%
25°C
8.5
s
tsSettling time
Step = 1.5 V to 3.5 V,
R
L
= 10 k,
To 0.01%
25°C
15.5
µs
s
RL = 10 k,
C
L
= 100 pFTo 0.01% 15.5
φmPhase margin at unity gain
RL = 10 k‡,
CL = 100 pF
25°C66°
Gain margin
R
L
= 10 k
‡,
C
L
= 100 pF
25°C11 dB
Full range is −40°C to 125°C for Q level part.
Referenced to 2.5 V
 
   
    
2
SGLS175 − AUGUST 2003
10 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO
Input offset voltage
Distribution
2,3
VIO Input offset voltage
Distribution
vs Common-mode input voltage
2,3
4,5
αVIO Input offset voltage temperature coefficient Distribution 6,7
IIB/IIO Input bias and input offset currents vs Free-air temperature 8
VOH High-level output voltage vs High-level output current 9,11
VOL Low-level output voltage vs Low-level output current 10,12
VO(PP) Maximum peak-to-peak output voltage vs Frequency 13
IOS
Short-circuit output current
vs Supply voltage
14
IOS Short-circuit output current
vs Supply voltage
vs Free-air temperature
14
15
VID Differential input voltage vs Output voltage 16,17
Differential gain vs Load resistance 18
AVD
Large-signal differential voltage amplification
vs Frequency
19,20
AVD Differential voltage amplification
vs Frequency
vs Free-air temperature
19,20
21,22
zoOutput impedance vs Frequency 23,24
CMRR
Common-mode rejection ratio
vs Frequency
25
CMRR Common-mode rejection ratio
vs Frequency
vs Free-air temperature
25
26
kSVR
Supply-voltage rejection ratio
vs Frequency
27,28
kSVR Supply-voltage rejection ratio
vs Frequency
vs Free-air temperature
27,28
29
IDD Supply current vs Supply voltage 30
SR
Slew rate
vs Load capacitance
31
SR Slew rate
vs Load capacitance
vs Free-air temperature
31
32
VOInverting large-signal pulse response 33,34
VOVoltage-follower large-signal pulse response 35,36
VOInverting small-signal pulse response 37,38
VOVoltage-follower small-signal pulse response 39,40
VnEquivalent input noise voltage vs Frequency 41, 42
Noise voltage (referred to input) Over a 10-second period 43
THD + N Total harmonic distortion plus noise vs Frequency 44,45
Gain-bandwidth product
vs Supply voltage
46
Gain-bandwidth product
vs Supply voltage
vs Free-air temperature
46
47
φm
Phase margin
vs Frequency
19,20
φmPhase margin
vs Frequency
vs Load capacitance
19,20
48
Gain margin vs Load capacitance 49
B1Unity-gain bandwidth vs Load capacitance 50
 
   
    
2
SGLS175 − AUGUST 2003
11
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 2
DISTRIBUTION OF TLV2422
INPUT OFFSET VOLTAGE
Percentage of Amplifiers − %
16
14
12
10
8
6
4
2
0−0.4 VIO − Input Offset Voltage − mV
452 Amplifiers from 1 Wafer Lot
18
−0.3
VDD = 3 V
RL = 10 k
TA = 25°C
−0.2 −0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Figure 3
454 Amplifiers from 1 Wafer Lot
DISTRIBUTION OF TLV2422
INPUT OFFSET VOLTAGE
Percentage of Amplifiers − %
20
15
10
5
0
VDD = 5 V
RL = 10 k
TA = 25°C
−0.4 VIO − Input Offset Voltage − mV
−0.3 −0.2−0.1 0 0.1 0.2 0.3 0.4 0.5 0.6
Figure 4
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
−0.5
2
1
0
−1
−2 0 0.5 1 2.5 3
VIC − Common-Mode Input Voltage − V
2
1.5 VDD = 3 V
VIO − Input Offset Voltage − mV
0.5
−0.5
−1.5
1.5
Figure 5
VDD = 5 V
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
2
1
0
−1
−2
1.5
0.5
−0.5
−1.5
−0.5 0 0.5 1 2.5 5
VIC − Common-Mode Input Voltage − V
21.5 3 4.543.5
VIO − Input Offset Voltage − mV
 
   
    
2
SGLS175 − AUGUST 2003
12 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 6
10
5
0−4 −3 −2 −1 0 1
15
20
25
234
32 Amplifiers From 1 Wafer Lot
VDD = ± 1.5 V
TA = 25°C to 125°C
Percentage of Amplifiers − %
DISTRIBUTION OF TLV2422 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
αVIO − Temperature Coefficient µV/°C
Figure 7
10
5
0−4 −3 −2 −1 0 1
15
20
25
234
32 Amplifiers From 1 Wafer Lot
VDD = ± 2.5 V
TA = 25°C to 125°C
Percentage of Amplifiers − %
DISTRIBUTION OF TLV2422 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
αVIO − Temperature Coefficient µV/°C
Figure 8
INPUT BIAS AND INPUT OFFSET CURRENTS
vs
FREE-AIR TEMPERATURE
−55
200
120
80
40
0−40 0 25 85 125
TA − Free-Air Temperature − °C
70
IIB
160
IIO
VDD = ±2.5 V
IIB − Input Bias and Input Offset Currents − pAand IIO
Figure 9
VOH− High-Level Output Voltage − V
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
0
3
2
1
036 91215
IOH − High-Level Output Current − mA
TA = 85°C
VDD = 3 V
2.5
1.5
0.5
TA = 125°C
TA = 0°C
TA = 25°C
 
   
    
2
SGLS175 − AUGUST 2003
13
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 10
VOL− Low-Level Output Voltage − V
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0
1.6
1
0.4
012 3 4 5
IOL − Low-Level Output Current − mA
TA = 85°C
VDD = 3 V
1.2
0.8
0.2
TA = 125°C
TA = −40°C
TA = 25°C
0.6
1.4
Figure 11
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
0
5
2
0816243240
IOH − High-Level Output Current − mA
4
1
3
412202836
TA = 85°C
TA = 125°C
TA = −40°C
TA = 25°C
VDD = 5 V
VOH− High-Level Output Voltage − V
Figure 12
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0
1
0.4
012 3 4 5
IOL − Low-Level Output Current − mA
TA = 85°C
VDD = 5 V
1.2
0.8
0.2
TA = 125°C
TA = −40°C
TA = 25°C
0.6
VOH− High-Level Output Voltage − V
Figure 13
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
VDD = 5 V RL = 10 k
TA = 25°C
4
1
5
3
0
102103104106
f − Frequency − Hz
VO(PP)− Maximum Peak-to-Peak Output Voltage − V
2
105
VDD = 3 V
 
   
    
2
SGLS175 − AUGUST 2003
14 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 14
IOS− Short-Circuit Output Current − mA
SHORT-CIRCUIT OUTPUT CURRENT
vs
SUPPLY VOLTAGE
2
20
−5
−20
−30 34567
VDD − Supply Voltage − V
10
−10
−25
−15
15
VO = VDD/2
VIC = VDD/2
TA = 25°C
30
0
5
25
8910
Figure 15
SHORT-CIRCUIT OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
−55
2
−4
−8 0 70 125
0
−6
−2
−40 25 85
VDD = 5 V
8
6
4
VID = −100 mV
VID = 100 mV
TA − Free-Air Temperature − °C
IOS− Short-Circuit Output Current − mA
Figure 16
VID − Differential Input Voltage −
DIFFERENTIAL INPUT VOLTAGE
vs
OUTPUT VOLTAGE
0
0
−600
−1000 123
−200
−800
−400
0.5 1.5 2.5
600
400
200
VO − Output Voltage − V
1000
800
µV
VDD = 3 V
RL = 10 k
TA = 25°C
Figure 17
012345
VDD = 5 V
RL = 10 k
TA = 25°C
VID − Differential Input Voltage −
0
−600
−1000
−200
−800
−400
600
400
200
1000
800
µV
VO − Output Voltage − V
DIFFERENTIAL INPUT VOLTAGE
vs
OUTPUT VOLTAGE
 
   
    
2
SGLS175 − AUGUST 2003
15
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Differential Gain − V/mV
DIFFERENTIAL GAIN
vs
LOAD RESISTANCE
10
10
11000
100
100
10000
1000
VID = 5 V
RL − Load Resistance − k
VID = 3 V
Figure 18
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE MARGIN
vs
FREQUENCY
50
30
10
−50
f − Frequency − Hz
40
20
0
AVD− Large-Signal Differential
104105
Voltage Amplification − dB
−45
−90
m
φ− Phase Margin − °
VDD = 3 V
RL = 10 k
CL = 100 pF
106
−10
−30
−20
−40
103
180
45
0
90
135
GAIN
PHASE
Figure 19
 
   
    
2
SGLS175 − AUGUST 2003
16 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE MARGIN
vs
FREQUENCY
60
40
20
−40
f − Frequency − Hz
50
30
10
AVD− Large-Signal Differential
103104
Voltage Amplification − dB
m
φ− Phase Margin − °
105
0
−20
−10
−30
106
−45
−90
180
45
0
90
135
GAIN
PHASE
VDD = 5 V
RL = 10 k
CL = 100 pF
Figure 20
Figure 21
TA − Free-Air Temperature − °C
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
−75
10
1
100
−50
10000
1000
VDD = 3 V
RL = 10 k
−25 0 25 50 75 100 125
AVD− Differential Voltage Amplication − V/mV
RL = 1 M
Figure 22
TA − Free-Air Temperature − °C
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
−75
10
1
100
−50
10000
1000
VDD = 5 V
RL = 10 k
−25 0 25 50 75 100 125
AVD− Differential Voltage Amplication − V/mV
RL = 1 M
 
   
    
2
SGLS175 − AUGUST 2003
17
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 23
OUTPUT IMPEDANCE
vs
FREQUENCY
1000
100
10
1
f − Frequency − Hz
102103105
VDD = 3 V
TA = 25°C
104
AV = 10
AV = 1
AV = 100
zo− Output Impedance −
Figure 24
OUTPUT IMPEDANCE
vs
FREQUENCY
1000
100
10
1
f − Frequency − Hz
102103105
VDD = 5 V
TA = 25°C
104
AV = 10
AV = 1
AV = 100
zo− Output Impedance −
Figure 25
80
40
0
f − Frequency − Hz
100
60
20
CMRR − Common-Mode Rejection Ratio − dB
102103106
TA = 25°C
104105
VDD = 3 V
VDD = 5 V
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
Figure 26
CMRR − Common-Mode Rejection Ratio − dB
COMMON-MODE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
−55
91
90
88
86
84 −40 25 70 85 125
TA − Free-Air Temperature − °C
89
87
85
0
94
93
92
VDD = 3 V
VDD = 5 V