S71VS/XS-R Memory Subsystem Solutions MirrorBit(R) 1.8 Volt-only Simultaneous Read/Write, Burst Mode Multiplexed Flash Memory and Burst Mode pSRAM 256/128/64 Mb (16/8/4 Mb x 16-bit) Flash, 128/64/32 Mb (8/4/2 Mb x 16-bit) pSRAM S71VS/XS-R Memory Subsystem Solutions Cover Sheet Data Sheet Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions. Publication Number S71VS_XS-R_00 Revision 08 Issue Date April 9, 2010 D at a S hee t Notice On Data Sheet Designations Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content: "This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice." Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content: "This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications." Combination Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category: "This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur." Questions regarding these document designations may be directed to your local sales office. 2 S71VS/XS-R Memory Subsystem Solutions S71VS_XS-R_00_08 April 9, 2010 S71VS/XS-R Memory Subsystem Solutions MirrorBit(R) 1.8 Volt-only Simultaneous Read/Write, Burst Mode Multiplexed Flash Memory and Burst Mode pSRAM 256/128/64 Mb (16/8/4 Mb x 16-bit) Flash, 128/64/32 Mb (8/4/2 Mb x 16-bit) pSRAM Data Sheet Features Power supply voltage of 1.7 V to 1.95 V Flash / pSRAM Burst Speed: 108 MHz, 104 MHz, 83 MHz MCP BGA Packages - 52 ball, 7.5 x 5.0 mm, 0.5 mm ball pitch - 56 ball, 7.7 x 6.2 mm, 0.5 mm ball pitch - 56 ball, 9.2 x 8.0 mm, 0.5 mm ball pitch Operating Temperature - Wireless, -25C to +85C General Description The S71VS-R Series is a product line of stacked Multi-Chip Package (MCP) memory solutions and consists of the following items: One or more S29VS-R or S29XS-R Flash memory die One or more pSRAM The products covered by this document are listed in the table below. For details about their specifications, please refer to their individual data sheet for further details. Flash Density pSRAM Density Product 64 Mb 32 Mb S71VS064RB0 128 Mb 32 Mb S71VS128RB0 128 Mb 64 Mb S71VS128RC0 256 Mb 64 Mb S71VS256RC0 256 Mb 128 Mb S71VS256RD0 256 Mb 128 Mb S71XS256RD0 Publication Number S71VS_XS-R_00 Revision 08 Issue Date April 9, 2010 D at a S hee t For detailed specifications, please refer to the individual data sheets: 4 Document Publication Identification Number S29VS-R S29VS_XS-R_00 S29XS-R S29VS_XS-R_00 128 Mb MUX pSRAM Type 5 pSRAM_39 64 Mb MUX pSRAM Type 3 muxpsram_15 32 Mb MUX pSRAM Type 3 muxpsram_10 32 Mb MUX pSRAM CustComspec_01 32 Mb CellularRAM Address/Data multiplexed SWM032D108M1R_03 32 Mb CellularRAM Address/Data multiplexed SWM032D108M1N_01 64 Mb CellularRAM Address/Data multiplexed SWM064D108M1N_01 64 Mb CellularRAM Address/Data multiplexed SWM064D108M1R_01 S71VS/XS-R Memory Subsystem Solutions S71VS_XS-R_00_08 April 9, 2010 Data 1. She et Ordering Information The order number is formed by a valid combinations of the following: S71VS 256 R C 0 ZH K Z0 0 Packing Type 0 = Tray 2 = 7-inch Tape and Reel 3 = 13-inch Tape and Reel Model Number See Valid Combinations table below Package Modifier T = 7.5 x 5.0, 52-ball BGA, 0.5 mm ball pitch (0.3 mm ball diameter) K = 7.7 x 6.2, 56-ball BGA, 0.5 mm ball pitch (0.3 mm ball diameter) E = 9.2 x 8.0, 56-ball BGA, 0.5 mm ball pitch (0.3 mm ball diameter) Package Type ZH = Very Thin Fine-Pitch Ball Grid Array (VFBGA)---1.2 mm max height with 0.5 mm pitch; Lead (Pb)-free Package; Low-Halogen AH = Very Thin Fine-Pitch Ball Grid Array (VFBGA)---1.0 mm max height with 0.5 mm pitch; Lead (Pb)-free Package; Low-Halogen Chip Contents 0 = No content (default) pSRAM Density B = 32 Mb C = 64 Mb D = 128 Mb Process Technology R = 65 nm MirrorBit(R) Technology Flash Density 256 = 256 Mb 128 = 128 Mb 64 = 64 Mb Product Family S71VS = Multi-Chip Product 1.8 Volt-only Simultaneous Read/Write Burst Mode Address and Data Multiplexed (ADM) Flash Memory + pSRAM S71XS = Multi-Chip Product 1.8V-only Simultaneous Read/Write Burst Mode, Address-High, Address-Low Data Multiplexed (AADM) Flash Memory + pSRAM April 9, 2010 S71VS_XS-R_00_08 S71VS/XS-R Memory Subsystem Solutions 5 D at a 1.1 S hee t Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. Base Ordering Part Number Package S71VS064RB0 AHT Model Number Packing Type pSRAM Type Flash Boot Flash / pSRAM Speed 00 104 MHz MUX pSRAM 04 83 MHz 2L SWM032D108M1N 0L SWM032D108M1R 20 MUX pSRAM Type 3 4L SWM064D108M1R 108 MHz 2L SWM064D108M1N 108 MHz S71VS128RB0 Pinout and Package Notes Pinout: S71VS-R 52-ball Package: RSB052 108 MHz AHK 104 MHz Pinout: S71VS-R 56-ball Package: RSD056 S71VS128RC0 S71VS128RC0 20 24 ZHK 2L 104 MHz MUX pSRAM Type 3 0, 2, 3 Top Boot SWM064D108M1N 20 83 MHz 108 MHz 104 MHz MUX pSRAM Type 3 S71VS256RC0 24 AHK 4L 83 MHz SWM064D108M1R 108 MHz 40 104 MHz 44 83 MHz S71VS256RD0 ZHE Pinout: S71VS-R 56-ball Package: RSD056 Pinout: S71VS-R 56-ball Package: NLB056--56-ball MUX pSRAM Type 5 40 104 MHz 44 83 MHz S71XS256RD0 6 Pinout: S71VS-R 56-ball Package: NSD056 S71VS/XS-R Memory Subsystem Solutions Pinout: S71XS-R 56-ball Package: NLB056 S71VS_XS-R_00_08 April 9, 2010 Data 2. She et Input/Output Descriptions Table 2.1 identifies the input and output package connections provided on the device. Table 2.1 Input/Output Descriptions Flash RAM AMAX - A16 Symbol Address inputs X X A/DQ15-A/DQ0 Multiplexed Address/Data X X OE# Output Enable input. Asynchronous relative to CLK for the Burst mode. X X WE# Write Enable input. X X VSS Ground X X VSSQ Input/Output Ground X X No Connect; not connected internally X X X X X X X X NC Description Ready output; indicates the status of the Burst read. Flash Memory RDY (using default "Active HIGH" configuration) VOL = data invalid VOH = data valid F-RDY/R-WAIT Note: The default polarity for the pSRAM WAIT signal is opposite the default polarity of the Flash RDY signal. pSRAM WAIT (using default "Active HIGH" configuration) VOL = data valid VOH = data invalid To match polarities, change bit 10 of the pSRAM Bus Configuration Register to 0 (Active LOW WAIT). Alternately, change bit 10 of the Flash Configuration Register to 0 (Active LOW RDY) CLK Clock input. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal address counter. Should be at VIL or VIH while in asynchronous mode Address Valid input. Indicates to device that the valid address is present on the address inputs. AVD# Low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched. High = device ignores address inputs F-RST# Hardware reset input. Low = device resets and returns to reading array data X F-VPP Accelerated input. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions. X R-CE# Chip-enable input for pSRAM. F-CE# Chip-enable input for Flash. Asynchronous relative to CLK for Burst Mode. R-CRE Control Register Enable (pSRAM). VCC Flash and pSRAM 1.8 Volt-only single power supply. X X VCCQ Flash and pSRAM Input/Output Power Supply X X X X X R-UB# Upper Byte Control (pSRAM). X R-LB# Lower Byte Control (pSRAM) X RFU Reserved For Future Use April 9, 2010 S71VS_XS-R_00_08 S71VS/XS-R Memory Subsystem Solutions 7 D at a S hee t 3. MCP Block Diagram Figure 3.1 S71VS-R MCP Block Diagram 8 F-RST# RST# F-VPP F-RDY/R-WAIT F-CE# OE# WE# AVD# VPP RDY CE# OE# WE# AVD# VSS, VSSQ VSS VSSQ R-UB# UB# R-LB# LB# R-CE# CE# OE# WE# ADV# VSS VSSQ WAIT A/DQ15-A/DQ0 MUX FLASH MEMORY VS-R v CLK Amax-A16 VCC VCCQ ADQ15-ADQ0 CLK v Amax-A16 VCC VCCQ A/DQ15-A/DQ0 MUX pSRAM MEMORY CLK Amax-A16 VCC VCCQ S71VS/XS-R Memory Subsystem Solutions CRE R-CRE S71VS_XS-R_00_08 April 9, 2010 Data She et Figure 3.2 S71XS-R MCP Block Diagram F-RST# RST# F-VPP F-RDY/R-WAIT F-CE# OE# WE# AVD# VPP RDY CE# OE# WE# AVD# VSS VSS VSSQ R-UB# UB# R-LB# LB# R-CE# CE# OE# WE# ADV# VSS VSSQ WAIT Amax-A16 (no connect) ADQ15-ADQ0 FLASH MEMORY XS-R (AADM) CLK VCC VCCQ v ADQ15-ADQ0 CLK VCC VCCQ ADQ15-ADQ0 CLK April 9, 2010 S71VS_XS-R_00_08 pSRAM MEMORY Amax-A16 VCC VCCQ S71VS/XS-R Memory Subsystem Solutions CRE Amax-A16 R-CRE 9 D at a 4. S hee t Connection Diagrams/Physical Dimensions This section contains the I/O designations and package specifications for the S71VS-R. 4.1 Special Handling Instructions for FBGA Packages Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time. 4.2 Connection Diagrams Figure 4.1 S71VS-R 56-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Legend A NC NC Flash/RAM Shared B No Connect C NC RFU F-RDY/ R-WAIT A21 VCCQ A16 VSS A/DQ7 R-LB# R-UB# VCC WE# RFU NC A17 A22 Do Not Use D VSS CLK F-VPP A19 Flash Only E A20 AVD# RFU A18 F-CE# VSS A/DQ2 A/DQ9 A/DQ8 OE# A/DQ4 A/DQ11 A/DQ10 VCCQ A/DQ1 A/DQ0 RFU NC A23 F-RST# RAM Only F A/DQ6 A/DQ13 A/DQ12 A/DQ3 G A/DQ15 A/DQ14 VSSQ A/DQ5 H NC RFU R-CE# R-CRE J K NC 10 NC S71VS/XS-R Memory Subsystem Solutions S71VS_XS-R_00_08 April 9, 2010 Data She et Figure 4.2 S71VS-R 52-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down) 1 2 3 NC RFU F-RDY/ R-WAIT A21 VSS VCCQ A16 A20 4 5 6 7 R-LB# R-UB# CLK VCC WE# F-VPP AVD# RFU F-RST# RFU 8 9 10 Legend RFU NC No Connect A19 A17 RFU A18 F-CE# VSS A B Do Not Use Reserved for Future Use C Flash Only D VSS ADQ7 ADQ6 ADQ13 ADQ12 ADQ3 ADQ2 ADQ9 ADQ8 OE# RAM Only E ADQ15 ADQ14 VSS ADQ5 ADQ4 ADQ11 ADQ10 VCCQ ADQ1 ADQ0 Flash/RAM Shared F NC R-CE# RFU R-CRE RFU NC Notes 1. Addresses are shared between Flash and RAM depending on the density of the pSRAM. 2. VSS and VSSQ must be connected together. MCP Flash-Only Addresses Shared Addresses S71VS064RB0 A21 A20-A16 S71VS128RC0 A22 A21-A16 S71VS256RC0 A23-A22 A21-A16 S71VS256RD0 A23 A22-A16 Shared ADQ Pins A/DQ15-A/DQ0 April 9, 2010 S71VS_XS-R_00_08 S71VS/XS-R Memory Subsystem Solutions 11 D at a S hee t Figure 4.3 S71XS-R 56-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Legend A NC NC Flash/RAM Shared B No Connect C NC RFU F-RDY/ R-WAIT A21 VCCQ A16 VSS A/DQ7 R-LB# R-UB# VCC WE# RFU NC A17 A22 Do Not Use D VSS CLK F-VPP A19 Flash Only E A20 AVD# RFU A18 F-CE# VSS A/DQ2 A/DQ9 A/DQ8 OE# A/DQ4 A/DQ11 A/DQ10 VCCQ A/DQ1 A/DQ0 RFU NC RFU F-RST# RAM Only F A/DQ6 A/DQ13 A/DQ12 A/DQ3 G A/DQ15 A/DQ14 VSS A/DQ5 H NC RFU R-CE# R-CRE J K NC 12 NC MCP pSRAM-Only Addresses Shared Addresses Shared ADQ Pins S71XS256RD0 A22-A16 N/A A/DQ15-A/DQ0 S71VS/XS-R Memory Subsystem Solutions S71VS_XS-R_00_08 April 9, 2010 Data 4.3 She et Physical Dimensions Figure 4.4 NLB056--56-ball VFBGA 9.2 x 8.0 mm D1 A D eD 0.10 C (2X) 14 13 12 11 10 9 8 7 6 5 4 3 E eE SE 7 E1 2 1 K J H G F E D C B A INDEX MARK PIN A1 CORNER B 9 TOP VIEW 7 SD 0.10 C (2X) PIN A1 CORNER BOTTOM VIEW 0.20 C A A2 A1 C 56X 0.08 C SIDE VIEW 6 b 0.15 M C A B 0.08 M C NOTES: PACKAGE NLB 056 JEDEC N/A DxE 9.20 mm x 8.00 mm PACKAGE SYMBOL MIN NOM MAX A --- --- 1.20 A1 0.20 --- --- A2 0.85 --- 0.97 NOTE PROFILE BODY SIZE E 8.00 BSC. BODY SIZE D1 4.50 BSC. MATRIX FOOTPRINT E1 6.50 BSC. MATRIX FOOTPRINT MD 10 MATRIX SIZE D DIRECTION ME 14 MATRIX SIZE E DIRECTION 56 0.25 0.30 ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. BALL COUNT 0.35 eE 0.50 BSC. BALL PITCH 0.50 BSC BALL PITCH 0.25 BSC. SOLDER BALL PLACEMENT A2 ~ A13,B1 ~ B14 C1,C2,C5,C6,C9,C10,C13,C14 D1,D2,D13,D14,E1,E2,E13,E14,F1,F2,F13,F14 G1,G2,G13,G14,H1,H2,H5,H6,H9,H10,H13,H14 J1 ~ J14, K2 ~ K13 WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. BALL DIAMETER eD SD / SE 2. BODY THICKNESS 9.20 BSC. n DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. BALL HEIGHT D Ob 1. DEPOPULATED SOLDER BALLS WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT. 3507\ 16-038.22 \ 7.14.5 April 9, 2010 S71VS_XS-R_00_08 S71VS/XS-R Memory Subsystem Solutions 13 D at a S hee t Figure 4.5 NSD056--56-ball VFBGA 7.7 x 6.2 mm NOTES: PACKAGE NSD 056 JEDEC N/A DxE 7.70 mm x 6.20 mm PACKAGE SYMBOL MIN NOM MAX A --- --- 1.20 A1 0.20 --- --- A2 0.85 --- 0.97 NOTE PROFILE 7.70 BSC. BODY SIZE 6.20 BSC. BODY SIZE D1 6.50 BSC. MATRIX FOOTPRINT E1 4.50 BSC. MATRIX FOOTPRINT MD 14 MATRIX SIZE D DIRECTION ME 10 MATRIX SIZE E DIRECTION n 56 0.30 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. BALL HEIGHT E 0.25 DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. BODY THICKNESS D Ob 1. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. BALL COUNT 0.35 WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. BALL DIAMETER eE 0.50 BSC. BALL PITCH eD 0.50 BSC BALL PITCH SD SE 0.25 BSC. SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT. 3628 \ 16-038.22 \ 2.21.07 14 S71VS/XS-R Memory Subsystem Solutions S71VS_XS-R_00_08 April 9, 2010 Data She et Figure 4.6 RSD056--56-ball VFBGA 7.7 x 6.2 mm NOTES: PACKAGE RSD 056 JEDEC N/A DxE SYMBOL 7.70 mm x 6.20 mm PACKAGE MIN NOM NOTE A 0.80 0.90 1.00 0.18 --- --- A2 0.62 BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010. --- 0.74 PROFILE e REPRESENTS THE SOLDER BALL GRID PITCH. BALL HEIGHT 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. BODY THICKNESS 7.70 BSC BODY SIZE E 6.20 BSC BODY SIZE D1 6.50 BSC MATRIX FOOTPRINT E1 4.50 BSC MD 14 MATRIX SIZE D DIRECTION ME 10 MATRIX SIZE E DIRECTION n 56 BALL COUNT 0.30 ALL DIMENSIONS ARE IN MILLIMETERS. 3. 4. D 0.25 DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. 2. MAX A1 Ob 1. MATRIX FOOTPRINT 0.35 SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. BALL DIAMETER eE 0.50 BSC BALL PITCH eD 0.50 BSC BALL PITCH SE SD 0.25 BSC SOLDER BALL PLACEMENT WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. DEPOPULATED SOLDER BALLS 10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT. 3719 \ f16-038.63 \ 1.26.9 April 9, 2010 S71VS_XS-R_00_08 S71VS/XS-R Memory Subsystem Solutions 15 D at a S hee t Figure 4.7 RSB052--52-ball VFBGA 5.0 x 7.5 mm NOTES: PACKAGE RSB 052 JEDEC N/A DxE 7.50 mm x 5.00 mm PACKAGE SYMBOL MIN NOM MAX A 0.80 --- 1.00 A1 0.18 --- --- A2 0.62 --- 0.77 NOTE PROFILE BODY SIZE E 5.00 BSC BODY SIZE D1 4.50 BSC MATRIX FOOTPRINT E1 2.50 BSC MATRIX FOOTPRINT MD 10 MATRIX SIZE D DIRECTION ME 6 MATRIX SIZE E DIRECTION 52 0.25 ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. BALL HEIGHT 7.50 BSC n DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. 2. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. BODY THICKNESS D Ob 1. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. BALL COUNT 0.30 0.35 e 0.50 BSC BALL PITCH SE / SD 0.25 BSC BALL PITCH 3A,3F,4A,4F,7A,7F,8A,8F WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. BALL DIAMETER WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. DEPOPULATED SOLDER BALLS 3711 \ 16-038.63 \ 10.24.8 16 S71VS/XS-R Memory Subsystem Solutions S71VS_XS-R_00_08 April 9, 2010 Data She et 5. Revision History Section Description Revision 01 (August 25, 2008) Initial release Revision 02 (November 4, 2008) Global Added OPNs S71VS064RB0AHT00/04/80/84 Connection Diagrams Added S71VS-R 52-ball connection diagram Physical Dimensions Added RSB052 General Description Changed 128 Mb Mux pSRAM PID from TBD to pSRAM_39 Revision 03 (November 10, 2008) General Description Changed 64 Mb MUX pSRAM Type 3 PID from muxpsram_14 to muxpsram_15 Revision 04 (January 13, 2009) Physical Dimensions Replaced NLD056 with NSD056 Revision 05 (January 23, 2009) Valid Combinations Added OPN S71VS128RC0AHK20 Physical Dimensions Added RSD056 Revision 06 (March 11, 2009) Valid Combinations Added 108 MHz speed grade to S71VS128RC0 and S71VS256RC0 Revision 07 (September 29, 2009) General Description Added S71VS128RB0; added muxpsram_10 Valid Combinations Added OPN S71VS128RB0 Revision 08 (April 9, 2010) General Description Added SWM064D108M1R Updated pSRAM documentation names Added OPNs: Valid Combinations S71VS128RC0AHK4L S71VS256RC0AHK4L Connection Diagrams Updated VSSQ ball to VSS Removed Bottom Boot options April 9, 2010 S71VS_XS-R_00_08 S71VS/XS-R Memory Subsystem Solutions 17 D at a S hee t Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c) 2008-2010 Spansion Inc. All rights reserved. Spansion(R), the Spansion Logo, MirrorBit(R), MirrorBit(R) EclipseTM, ORNANDTM, EcoRAMTM and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. 18 S71VS/XS-R Memory Subsystem Solutions S71VS_XS-R_00_08 April 9, 2010