IRFZ24NS/LPbF
HEXFET® Power MOSFET
PD - 95147
lAdvanced Process Technology
lSurface Mount (IRFZ24NS)
lLow-profile through-hole (IRFZ24NL)
l175°C Operating Temperature
lFast Switching
lFully Avalanche Rated
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 3.3
RθJA Junction-to-Ambient ( PCB Mounted,steady-state)** ––– 40
Thermal Resistance
°C/W
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 17
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V12 A
IDM Pulsed Drain Current  68
PD @TA = 25°C Power Dissipation 3.8 W
PD @TC = 25°C Power Dissipation 45 W
Linear Derating Factor 0.30 W/°C
VGS Gate-to-Source Voltage ± 20 V
EAS Single Pulse Avalanche Energy 71 mJ
IAR Avalanche Current10 A
EAR Repetitive Avalanche Energy4.5 mJ
dv/dt Peak Diode Recovery dv/dt  6.8 V/ns
TJOperating Junction and -55 to + 175
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
°C
Absolute Maximum Ratings
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power MOSFETs
are well known for, provides the designer with an extremely
efficient and reliable device for use in a wide variety of
applications.
The D2Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible on-
resistance in any existing surface mount package. The
D2Pak is suitable for high current applications because of
its low internal connection resistance and can dissipate
up to 2.0W in a typical surface mount application.
The through-hole version (IRFZ24NL) is available for low-
profile applications.
Description
VDSS = 55V
RDS(on) = 0.07Ω
ID = 17A
2
D Pak
TO-262
S
D
G
04/19/04
lLead-Free
IRFZ24NS/LPbF
Starting TJ = 25°C, L =1.0mH
RG = 25Ω, IAS = 10A. (See Figure 12)
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Notes:
** When mounted on 1" square PCB (FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
ISD ≤ 10A, di/dt ≤ 280A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
Pulse width ≤ 280µs; duty cycle ≤ 2%.
Uses IRFZ24N data and test conditions
Parameter Min. Typ. Max. Units Conditions
ISContinuous Source Current MOSFET symbol
(Body Diode) ––– ––– showing the
ISM Pulsed Source Current integral reverse
(Body Diode) ––– ––– p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 10A, VGS = 0V
trr Reverse Recovery Time ––– 56 83 ns TJ = 25°C, IF = 10A
Qrr Reverse Recovery Charge ––– 120 180 nC di/dt = 100A/µs 
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Source-Drain Ratings and Characteristics
A
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 55 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJBreakdown Voltage Temp. Coefficient ––– 0.052 ––– V/°C Reference to 25°C, ID =1mA
RDS(on) Static Drain-to-Source On-Resistance ––– ––– 0.07 ΩVGS =10V, ID = 10A
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA
gfs Forward Transconductance 4.5 ––– ––– S VDS = 25V, ID = 10A
––– ––– 25 µA VDS = 55V, VGS = 0V
––– ––– 250 VDS = 44V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 100 VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -100 nA VGS = -20V
QgTotal Gate Charge ––– ––– 20 ID = 10A
Qgs Gate-to-Source Charge ––– ––– 5.3 nC VDS = 44V
Qgd Gate-to-Drain ("Miller") Charge ––– ––– 7.6 VGS = 10V, See Fig. 6 and 13 
td(on) Turn-On Delay Time ––– 4.9 ––– VDD = 28V
trRise Time ––– 34 ––– ID = 10A
td(off) Turn-Off Delay Time ––– 19 ––– RG = 24Ω
tfFall Time ––– 27 ––– RD = 2.6Ω, See Fig. 10 
Between lead,
––– ––– and center of die contact
Ciss Input Capacitance ––– 370 ––– VGS = 0V
Coss Output Capacitance ––– 140 ––– pF VDS = 25V
Crss Reverse Transfer Capacitance ––– 65 ––– ƒ = 1.0MHz, See Fig. 5
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
IGSS
ns
IDSS Drain-to-Source Leakage Current
nH
7.5
LSInternal Source Inductance
17
68
S
D
G
IRFZ24NS/LPbF
Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
1
10
100
0.1 1 10 100
I , Drain-to-Source Current (A)
D
V , Drain-to-Source Volta
g
e
(
V
)
DS
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
20
µ
s PULSE WIDTH
T = 25°C
C
A
4.5V
1
10
100
0.1 1 10 100
4.5V
I , Drain-to-Source Current (A)
D
V , Drain-to-Source Volta
g
e
(
V
)
DS
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
20
µ
s PULSE WIDTH
T = 175°C
C
1
10
100
45678910
T = 25°C
J
GS
V , Gate-to-Source Volta
g
e
(
V
)
D
I , Drain-to-Source Current (A)
T = 175°C
J
V = 25V
20µs PULSE W IDTH
DS
0.0
0.5
1.0
1.5
2.0
2.5
3.0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
J
T , Junction Temperature (°C)
R , Drain-to-Source O n R esistance
DS(on)
(Normalized)
V = 10V
GS
I = 17A
D
TJ = 25°C TJ = 175°C
IRFZ24NS/LPbF
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 8. Maximum Safe Operating Area
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
0
100
200
300
400
500
600
700
1 10 100
C, Capacitance (pF)
DS
V , Drain-to-Source Volta
g
e
(
V
)
A
V = 0V , f = 1M H z
C = C + C , C SHORTED
C = C
C = C + C
GS
iss
g
s
g
d ds
rss
g
d
oss ds
g
d
C
iss
C
oss
C
rss
1
10
100
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
T = 25°C
J
V = 0V
GS
V , Source-to-Drain Volta
g
e
(
V
)
I , Reverse Drain Current (A)
SD
SD
T = 175°C
J
1
10
100
1000
1 10 100
V , Drain-to-Source Volta
g
e
(
V
)
DS
I , Drain Current (A)
OPE RATION IN THIS AREA LIMITE D
BY R
D
DS(on)
10µs
100µs
1ms
10ms
T = 25°C
T = 175°C
Sin
g
le P u ls e
C
J
0
4
8
12
16
20
048121620
Q , Total Gate Char
g
e
(
nC
)
G
V , Gate-to-Source Voltage (V)
GS
A
FOR TEST CIRCUIT
SEE FIGURE 13
V = 44V
V = 28V
I = 10A
DS
DS
D
IRFZ24NS/LPbF
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10a. Switching Time Test Circuit
VDS
90%
10%
VGS
t
d(on)
t
r
t
d(off)
t
f
Fig 10b. Switching Time Waveforms
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
10V
+
-
VDD
25 50 75 100 125 150 175
0
4
8
12
16
20
T , Case Temperature ( C)
I , Drain Current (A)
°
C
D
0.01
0.1
1
10
0.00001 0.0001 0.001 0.01 0.1 1
Notes:
1. Duty factor D = t / t
2. Peak T = P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Thermal Response (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
IRFZ24NS/LPbF
Fig 12a. Unclamped Inductive Test Circuit
Fig 12b. Unclamped Inductive Waveforms
Fig 13a. Basic Gate Charge Waveform
V
DS
L
D.U.T.
V
DD
I
AS
t
p
0.01Ω
R
G
+
-
tp
VDS
IAS
VDD
V(BR)DSS
10 V
D.U.T. VDS
ID
IG
3mA
VGS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
Fig 13b. Gate Charge Test Circuit
QG
QGS QGD
VG
Charge
10 V
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
0
20
40
60
80
100
120
140
25 50 75 100 125 150 175
J
E , Single Pulse Avalanche Energy (mJ)
AS
Startin
g
T , Junction Tem
p
erature
(
°C
)
I
TOP 4.2A
7.2A
BOTTOM 10A
V = 25V
D
DD
IRFZ24NS/LPbF
Peak Diode Recovery dv/dt Test Circuit
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
VGS=10V
VDD
ISD
Driver Gate Drive
D.U.T. ISD Waveform
D.U.T. VDS Waveform
Inductor Curent
D = P. W .
Period
+
-
+
+
+
-
-
-
Fig 14. For N-Channel HEXFETS
* VGS = 5V for Logic Level Devices
RG
VDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
*
IRFZ24NS/LPbF
D2Pak Part Marking Information (Lead-Free)
D2Pak Package Outline
Note: "P" in as s embly line
pos ition indicates "L ead- F ree"
F530S
T HIS IS AN IRF 530S WIT H
LOT CODE 8024
ASS E MBLE D ON WW 02, 2000
IN THE ASSEMBLY LINE "L"
AS S E MB L Y
LOT CODE
INT E R NAT IONAL
R E CT IF IE R
LOGO
PART NUMBER
DATE CODE
YE AR 0 = 2000
WEEK 02
LINE L
OR
F530S
A = AS S E MB L Y S IT E CODE
WEE K 02
P = DE S IGNAT E S L E AD-F R E E
PRODUCT (OPTIONAL)
R ECT IFIE R
INT ER NAT IONAL
LOGO
LOT CODE
AS S E MB L Y
YEAR 0 = 2000
DATE CODE
PART NUMBER
IRFZ24NS/LPbF
TO-262 Part Marking Information
TO-262 Package Outline
AS S E MB L Y
LOT CODE
RECTIFIE R
IN T E R N AT ION AL
AS S E MB L E D ON WW 19, 1997
Note: "P" in assembly line
pos i tion indicates "L ead-F ree"
IN T H E AS S E MB L Y L INE "C" LOGO
T H IS IS AN IRL3103L
LOT CODE 1789
EXAMPLE:
LINE C
DATE CODE
WE E K 19
YE AR 7 = 1997
PART NUMBER
PART NUMBER
LOGO
LOT CODE
AS S E MB L Y
IN T E R N AT ION AL
RECTIFIE R
PRODUCT (OPTIONAL)
P = DE S IGNAT E S L E AD-F R E E
A = AS S E MB L Y S IT E CODE
WE E K 19
YE AR 7 = 1997
DATE CODE
OR
IRFZ24NS/LPbF
D2Pak Tape & Reel Information
3
4
4
TRR
FEED DIRECTION
1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
TRL
FEED DIRECTION
10.90 (.429)
10.70 (.421)
16.10 (.634)
15.90 (.626)
1.75 (.069)
1.25 (.049)
11.60 (.457)
11.40 (.449) 15.42 (.609)
15.22 (.601)
4.72 (.136)
4.52 (.178)
24.30 (.957)
23.90 (.941)
0.368 (.0145)
0.342 (.0135)
1.60 (.063)
1.50 (.059)
13.50 (.532)
12.80 (.504)
330.00
(14.173)
MAX.
27.40 (1.079)
23.90 (.941)
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
26.40 (1.039)
24.40 (.961)
NOTES :
1. COMFORMS TO EIA-418.
2. CO N TR O LLING D IM E N SIO N : M IL LIMETER .
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 04/04
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/