19-6294; Rev 6/12 DS1210 Nonvolatile Controller Chip FEATURES PIN ASSIGNMENT Converts CMOS RAMs into Nonvolatile Memories Unconditionally Write Protects when VCC is Out-of-Tolerance Automatically Switches to Battery when Power-Fail Occurs Space-Saving 8-Pin PDIP or 16-Pin SO Packages Consumes <100nA of Battery Current Tests Battery Condition on Power up Provides for Redundant Batteries Optional 5% or 10% Power-Fail Detection Low Forward Voltage Drop on the VCC Switch Optional Industrial (N) Temperature Range of -40C to +85C VCCO 1 8 VCCI VBAT1 2 7 VBAT2 TOL 3 6 CEO GND 4 5 CE DS1210 8-pin PDIP (300 mils) NC 1 2 16 15 NC VCCO NC 3 14 NC VBAT1 4 13 VBAT2 NC 5 12 NC TOL 6 11 CEO NC 7 10 NC GND 8 9 CE VCCI DS1210S 16-pin SO (300 mils) PIN DESCRIPTION VCCO VBAT1 TOL GND CE CEO VBAT2 VCCI NC DESCRIPTION - RAM Supply - + Battery 1 - Power Supply Tolerance - Ground - Chip Enable Input - Chip Enable Output - + Battery 2 - + Supply - No Connect The DS1210 Nonvolatile Controller Chip is a CMOS circuit which solves the application problem of converting CMOS RAM into nonvolatile memory. Incoming power is monitored for an out-of-tolerance condition. When such a condition is detected, chip enable is inhibited to accomplish write protection and the battery is switched on to supply the RAM with uninterrupted power. Special circuitry uses a lowleakage CMOS process which affords precise voltage detection at extremely low battery consumption. The 8-pin DIP package keeps PC board real estate requirements to a minimum. By combining the DS1210 Nonvolatile Controller Chip with a CMOS memory and batteries, nonvolatile RAM operation can be achieved. 1 of 8 DS1210 OPERATION The DS1210 nonvolatile controller performs five circuit functions required to battery back up a RAM. First, a switch is provided to direct power from the battery or the incoming supply (VCCI) depending on which is greater. This switch has a voltage drop of less than 0.3V. The second function which the nonvolatile controller provides is power-fail detection. The DS1210 constantly monitors the incoming supply. When the supply goes out of tolerance, a precision comparator detects power-fail and inhibits chip enable ( CEO ). The third function of write protection is accomplished by holding the CEO output signal to within 0.2 volts of the VCCI or battery supply. If CE input is low at the time power-fail detection occurs, the CEO output is kept in its present state until CE is returned high. The delay of write protection until the current memory cycle is completed prevents the corruption of data. Power-fail detection occurs in the range of 4.75 volts to 4.5 volts with the tolerance (TOL) pin grounded. If TOL in connected to VCCO, then powerfail detection occurs in the range of 4.5 volts to 4.25 volts. During nominal supply conditions CEO will follow CE with a maximum propagation delay of 20ns. The fourth function the DS1210 performs is a battery status warning so that potential data loss is avoided. Each time that the circuit is powered up the battery voltage is checked with a precision comparator. If the battery voltage is less than 2.0 volts, the second memory cycle is inhibited. Battery status can, therefore, be determined by performing a read cycle after power-up to any location in memory, verifying that memory location content. A subsequent write cycle can then be executed to the same memory location altering the data. If the next read cycle fails to verify the written data, then the batteries are less than 2.0V and data is in danger of being corrupted. The fifth function of the nonvolatile controller provides for battery redundancy. In many applications, data integrity is paramount. In these applications it is often desirable to use two batteries to ensure reliability. The DS1210 controller provides an internal isolation switch which allows the connection of two batteries. During battery backup operation the battery with the highest voltage is selected for use. If one battery should fail, the other will take over the load. The switch to a redundant battery is transparent to circuit operation and to the user. A battery status warning will occur when the battery in use falls below 2.0 volts. A grounded VBAT2 pin will not activate a battery-fail warning. In applications where battery redundancy is not required, a single battery should be connected to the BAT1 pin, and the BAT2 battery pin must be grounded. The nonvolatile controller contains circuitry to turn off the battery backup. This is to maintain the battery(s) at its highest capacity until the equipment is powered up and valid data is written to the SRAM. While in the freshness seal mode the CEO and VCCO will be forced to VOL. When the batteries are first attached to one or both of the VBAT pins, VCCO will not provide battery back-up until VCCI exceeds VCCTP, as set by the TOL pin, and then falls below VBAT. Figure 1 shows a typical application incorporating the DS1210 in a microprocessor-based system. Section A shows the connections necessary to write protect the RAM when VCC is less than 4.75 volts and to back up the supply with batteries. Section B shows the use of the DS1210 to halt the processor when VCC is less than 4.75 volts and to delay its restart on power-up to prevent spurious writes. 2 of 8 SECTION A - BATTERY BACKUP Figure 1 BATTERY BACKUP CURRENT DRAIN EXAMPLE CONSUMPTION DS1210 IBAT RAM ICC02 Total Drain 100 nA 10 A 10.1 A SECTION B - PROCESSOR RESET 3 of 8 DS1210 DS1210 ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground Operating Temperature Range Storage Temperature Range Soldering Temperature (reflow, SO) Lead Temperature (soldering, 10s) -0.3V to +7.0V 0C to +70C, -40C to +85C for N parts -55C to +125C +260C +300C This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. PACKAGE THERMAL CHARACTERISTICS (Note 1) PDIP SO Note 1: Junction-to-Ambient Thermal Resistance (JA)..............................................................110C/W Junction-to-Case Thermal Resistance (JC)..................................................................40C/W Junction-to-Ambient Thermal Resistance (JA)..............................................................70C/W Junction-to-Case Thermal Resistance (JC)..................................................................23C/W Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board for the SO. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. RECOMMENDED OPERATING CONDITIONS PARAMETER TOL = GND Supply Voltage TOL = VCCO Supply Voltage Logic 1 Input Logic 0 Input Battery Input SYMBOL VCCI VCCI VIH VIL VBAT1, VBAT2 MIN 4.75 4.5 2.2 -0.3 2.0 4B TYP 5.0 5.0 MAX 5.5 5.5 VCC+0.3 +0.8 4.0 UNITS V V V V V (Note 10) NOTES 2 2 2 2 2, 3 0B DC ELECTRICAL CHARACTERISTICS PARAMETER Supply Current Supply Voltage Supply Current Input Leakage Output Leakage CEO Output @ 2.4V CEO Output @ 0.4V VCC Trip Point (TOL=GND) VCC Trip Point (TOL=VCCO) CEO Output VBAT1 or VBAT2 Battery Current Battery Backup Current @ VCCO = VBAT - 0.3V SYMBOL ICCI VCCO ICCO1 IIL ILO IOH IOL VCCTP VCCTP VOHL (Note 10; VCCI = 4.75 to 5.5V, TOL = GND) (VCCI = 4.5 to 5.5V, TOL = VCCO) MIN TYP MAX UNITS NOTES 5 mA 4 VCC-0.2 V 2 80 mA 5 -1.0 +1.0 A -1.0 +1.0 A -1.0 mA 6 4.0 mA 6 4.50 4.62 4.74 V 2 4.25 4.37 4.49 V 2 VBAT-0.2 V 8 1B IBAT 100 nA 3, 4 ICCO2 50 A 7, 8 4 of 8 DS1210 CAPACITANCE PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT MIN AC ELECTRICAL CHARACTERISTICS PARAMETER CE Propagation Delay CE High to Power-Fail SYMBOL tPD tPF MAX 5 7 2B (Note 10; VCCI = 4.75V to 5.5V, TOL = GND) (VCCI = 4.5V to 5.5V, TOL = VCCO) MIN TYP MAX UNITS NOTES 5 10 20 ns 6 0 ns 3B AC ELECTRICAL CHARACTERISTICS Recovery at Power Up VCC Slew Rate Power-Down VCC Slew Rate Power-Down VCC Slew Rate Power-Up CE Pulse Width TYP (TA = +25C) UNITS NOTES pF pF tREC tF tFB tR tCE 2 300 10 0 (Note 10; VCCI = 4.75V, TOL = GND) (VCCI < 4.5, TOL = VCCO) 80 125 ms s s s 1.5 s 9 NOTES: 2. All voltages are referenced to ground. 3. Only one battery input is required. Unused battery inputs must be grounded. 4. Measured with VCCO and CEO open. 5. ICC01 is the maximum average load which the DS1210 can supply to the memories. 6. Measured with a load as shown in Figure 2. 7. ICC02 is the maximum average load current which the DS1210 can supply to the memories in the battery backup mode. 8. tCE max must be met to ensure data integrity on power loss. 9. CEO can only sustain leakage current in the battery backup mode. 10. All AC and DC electrical characteristics are valid for the full temperature range. For commercial products, this range is 0 to +70C. For industrial products (N), this range is -40C to +85C. 11. DS1210 is recognized by Underwriters Laboratories (UL) under file E99151. 5 of 8 DS1210 TIMING DIAGRAM: POWER-UP TIMING DIAGRAM: POWER-DOWN OUTPUT LOAD Figure 2 6 of 8 DS1210 ORDERING INFORMATION PART DS1210+ DS1210N+ DS1210S+ DS1210SN+ TEMP RANGE 0C to +70C -40C to +85C 0C to +70C -40C to +85C PINPACKAGE 8 PDIP 8 PDIP 16 SO 16 SO +Denotes a lead(Pb)-free/RoHS-compliant package. PACKAGE INFORMATION For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 8 PDIP 16 SO PACKAGE CODE P8+4 W16+2 OUTLINE NO. 21-0043 21-0042 7 of 8 LAND PATTERN NO. 90-0107 DS1210 REVISION HISTORY REVISION DATE DESCRIPTION PAGES CHANGED 6/12 Added lead temperature and soldering temperature information to the Absolute Maximum Ratings section; changed "Pin 3" to "TOL" in multiple places; added the Package Thermal Characteristics section; added the Ordering Information and Package Information sections 1, 2, 4, 5, 8 8 of 8 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, Inc. 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 (c) 2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.