November 2003 AS7C1026B (R) 5 V 64K X 16 CMOS SRAM * Easy memory expansion with CE, OE inputs * TTL-compatible, three-state I/O * JEDEC standard packaging Features * Product AS7C1026B * Industrial and commercial versions * Organization: 65,536 words x 16 bits * Center power and ground pins for low noise * High speed - 10/12/15/20 ns address access time - 5, 6, 7, 8 ns output enable access time * Low power consumption: ACTIVE - 605 mW / max @ 10 ns * Low power consumption: STANDBY - 44-pin 400 mil SOJ - 44-pin TSOP 2-400 - 48-ball 6 x 8 mm mBGA * ESD protection 2000 volts * Latch-up current 200 mA Pin and ball arrangement 44-Pin SOJ (400 mil), TSOP 2 - 28 mW / max CMOS I/O Logic block diagram A0 A2 A3 A4 A5 A6 VCC Row decoder A1 64 K x 16 Array GND A7 I/O buffer Control circuit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC 0000048 - BGA Ball-Grid-Array Package A 1 2 3 4 5 6 LB OE A0 A1 A2 NC I/O0 B I/O8 UB A3 A4 CE C I/O9 I/O10 A5 A6 I/O1 I/O2 D VSS I/O11 NC A7 I/O3 VDD E VDD I/O12 NC NC I/O4 VSS F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A11 NC A10 A15 A14 A13 A11 UB OE LB CE A12 A8 A9 Column decoder WE A10 I/O0-I/O7 I/O8-I/O15 A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC AS7C1026B * 6 T 0.18 u CMOS technology Selection guide -10 -12 -15 -20 Unit Maximum address access time 10 12 15 20 ns Maximum output enable access time 5 6 7 8 ns 110 100 90 80 mA 5 5 5 5 mA Maximum operating current Maximum CMOS standby current 11/13/03, v 1.1 Alliance Semiconductor P. 1 of 11 Copyright (c) Alliance Semiconductor. All rights reserved. AS7C1026B (R) Functional description The AS7C1026B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words x 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for high-performance applications. When CE is high, the device enters standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full standby power is reached (ISB1). For example, the AS7C1026B is guaranteed not to exceed 28 mW under nominal full standby conditions. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output drivers stay in high-impedance mode. The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15. All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The device is packaged in common industry standard packages. Chip scale BGA packaging, easy to use in manufacturing, provides the smallest possible footprint. This 48-ball JEDECregistered package has a ball pitch of 0.75 mm and external dimensions of 8 mm x 6 mm. Absolute maximum ratings Parameter Symbol Min Max Unit Voltage on VCC relative to GND Vt1 -0.50 +7.0 V Voltage on any pin relative to GND Vt2 -0.50 VCC +0.50 V Power dissipation PD - 1.0 W Storage temperature (plastic) Tstg -65 +150 C Ambient temperature with VCC applied Tbias -55 +125 C DC current into outputs (low) IOUT - 20 mA Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE LB UB I/O0-I/O7 I/O8-I/O15 Mode H X X X X High Z High Z Standby (ISB), ISBI) L H L L H DOUT High Z Read I/O0-I/O7 (ICC) L H L H L High Z DOUT Read I/O8-I/O15 (ICC) L H L L L DOUT DOUT Read I/O0-I/O15 (ICC) L L X L L DIN DIN Write I/O0-I/O15 (ICC) L L X L H DIN High Z Write I/O0-I/O7 (ICC) L L X H L High Z DIN Write I/O8-I/O15 (ICC) L L H X H X X H X H High Z High Z Output disable (ICC) Key: H = high, L = low, X = don't care. 11/13/03, v 1.1 Alliance Semiconductor P. 2 of 11 AS7C1026B (R) Recommended operating conditions Parameter Supply voltage Input voltage Ambient operating temperature commercial industrial Symbol Min Nominal Max Unit VCC 4.5 5.0 5.5 V VIH 2.2 - VCC + 0.5 V VIL1 -0.5 - 0.8 TA TA 0 - -40 - V 70 o C 85 o C 1 VIL min. = -3.0 V for pulse width less than tRC/2. DC operating characteristics (over the operating range)1 -10 -12 -15 -20 Parameter Sym Test conditions Input leakage current | ILI | VCC = Max, VIN = GND to VCC - 1 - 1 - 1 - 1 A Output leakage current | ILO | VCC = Max, CE = VIH, VOUT = GND to VCC - 1 - 1 - 1 - 1 A Operating power supply current ICC VCC = Max, CE VIL, outputs open, f = fMax = 1/tRC - 110 - 100 - 90 - 80 mA ISB VCC = Max, CE VIL, outputs open, f = fMax = 1/tRC - 50 - 45 - 45 40 mA ISB1 VCC = Max, CE VCC-0.2 V, VIN GND + 0.2 V or VIN VCC-0.2 V, f = 0 - 5 - 5 - 5 - 5 mA VOL IOL = 8 mA, VCC = Min - 0.4 - 0.4 - 0.4 - 0.4 V VOH IOH = -4 mA, VCC = Min 2.4 - 2.4 - 2.4 - 2.4 - V Standby power supply current Output voltage Min Max Min Max Min Max Min Max Unit Capacitance (f = 1MHz, Ta = 25 C, VCC = NOMINAL)2 Parameter Symbol Signals Test conditions Max Unit Input capacitance CIN A, CE, WE, OE, LB, UB VIN = 0 V 5 pF I/O capacitance CI/O I/O VIN = VOUT = 0 V 7 pF 11/13/03, v 1.1 Alliance Semiconductor P. 3 of 11 AS7C1026B (R) Read cycle (over the operating range)3,9 -10 Parameter -12 -15 Symbol Min Max Min Max Min Read cycle time tRC 10 - 12 - Address access time tAA - 10 - Chip enable (CE) access time tACE - 10 Output enable (OE) access time tOE - Output hold from address change tOH CE low to output in low Z -20 Max Min Max Unit Notes 15 - 20 - ns 12 - 15 - 20 ns 3 - 12 - 15 - 20 ns 3 5 - 6 - 7 - 8 ns 3 - 3 - 3 - 3 - ns 5 tCLZ 3 - 3 - 3 - 3 - ns 4, 5 CE high to output in high Z tCHZ - 4 - 5 - 6 - 7 ns 4, 5 OE low to output in low Z tOLZ 0 - 0 - 0 - 0 - ns 4, 5 Byte select access time tBA - 5 - 6 - 7 - 8 ns Byte select Low to low Z tBLZ 0 - 0 - 0 - 0 - ns 4, 5 Byte select High to high Z tBHZ - 5 - 6 - 6 - 7 ns 4, 5 OE high to output in high Z tOHZ - 4 - 5 - 6 - 7 ns 4, 5 Power up time tPU 0 - 0 - 0 - 0 - ns 4, 5 Power down time tPD - 10 - 12 - 15 - 20 ns 4, 5 Key to switching waveforms Rising input Falling input Read waveform 1 (address controlled)3,6,7,9 Undefined output/don't care tRC Address DataOUT 11/13/03, v 1.1 tOH Previous data valid tAA tOH Data valid Alliance Semiconductor P. 4 of 11 AS7C1026B (R) Read waveform 2 (OE, CE, UB, LB controlled)3,6,8,9 tRC Address tAA OE tOE tOLZ tOH CE tLZ tOHZ tHZ tACE LB, UB tBA tBLZ tBHZ DataIN Data valid Write cycle (over the operating range) 11 -10 Parameter -12 -15 -20 Symbol Min Max Min Max Min Max Min Max Unit Notes Write cycle time tWC 10 - 12 - 15 - 20 - ns Chip enable (CE) to write end tCW 8 - 9 - 10 - 12 - ns Address setup to write end tAW 8 - 9 - 10 - 12 - ns Address setup time tAS 0 - 0 - 0 - 0 - ns Write pulse width tWP 7 - 8 - 9 - 12 - ns Write recovery time tWR 0 - 0 - 0 - 0 - ns Address hold from end of write tAH 0 - 0 - 0 - 0 - ns Data valid to write end tDW 5 - 6 - 8 - 10 - ns Data hold time tDH 0 - 0 - 0 - 0 - ns 5 Write enable to output in high Z tWZ - 5 - 6 - 7 - 8 ns 4, 5 Output active from write end tOW 1 - 1 - 1 - 2 - ns 4, 5 Byte select low to end of write tBW 7 - 8 - 9 - 9 - ns 11/13/03, v 1.1 Alliance Semiconductor P. 5 of 11 AS7C1026B (R) Write waveform 1 (WE controlled)11 tWC tAH Address tWR tCW CE tBW LB, UB tAW tAS tWP WE tDW DataIN tDH Data valid tWZ DataOUT tOW Data undefined Write waveform 2 (CE controlled)11 high Z tWC tAH Address tAS CE tWR tCW tAW tBW LB, UB tWP WE tDH tDW Data valid DataIN tCLZ DataOUT 11/13/03, v 1.1 high Z tWZ Data undefined Alliance Semiconductor tOW high Z P. 6 of 11 AS7C1026B (R) AC test conditions - - - - Output load: see Figure B. Input pulse level: GND to 3.5 V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5 +5 V +3.5V GND 90% 10% 90% 2 ns 10% Figure A: Input pulse DOUT 255 480 C13 Thevenin Equivalent: 168 DOUT +1.728 V GND Figure B: 5 V Output load Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A and B. These parameters are specified with CL = 5 pF, as in Figures B. Transition is measured 500 mV from steady-state voltage. This parameter is guaranteed, but not tested. WE is high for read cycle. CE and OE are low for read cycle. Address is valid prior to or coincident with CE transition low. All read cycle timings are referenced from the last valid address to the first transitioning address. N/A. All write cycle timings are referenced from the last valid address to the first transitioning address. Not applicable. C = 30 pF, except all high Z and low Z parameters where C = 5 pF. 11/13/03, v 1.1 Alliance Semiconductor P. 7 of 11 AS7C1026B (R) Package dimensions c 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 44-pin TSOP 2 Min (mm) A E He 44-pin TSOP 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 D l A2 A A1 0-5 e b 1.2 A1 0.05 0.15 A2 0.95 1.05 b 0.30 0.45 c 0.120 0.21 D 18.31 18.52 E 10.06 10.26 He 11.68 11.94 e l 0.80 (typical) 0.40 0.60 44-pin SOJ 400 mil D e Min (in) Max (in) 44-pin SOJ E1 E2 Pin 1 c B A2 A A1 b Seating plane E A 0.128 0.148 A1 0.025 - A2 0.105 0.115 B 0.026 0.032 b 0.015 0.020 c 0.007 0.013 D 1.120 1.130 E Alliance Semiconductor 0.370 NOM E1 0.395 0.405 E2 0.435 0.445 e 11/13/03, v 1.1 Max (mm) 0.050 NOM P. 8 of 11 AS7C1026B (R) 48-ball BGA Bottom View Top View Ball #A1 index 6 5 4 3 2 Ball A1 1 * A B C SRAM DIE D C C1 F G H J Elastomer A B B1 *pin 1 indicator will show as engraved circle and/or Inc. trademark Detail View Side View A E2 D E E2 E Die Minimum Typical Maximum A - 0.75 - B 5.90 6.00 6.10 B1 - 3.75 - C 7.90 8.00 8.10 C1 - 5.25 - D 0.25 0.30 0.40 E - - 1.20 E2 0.16 0.22 0.27 Y - - 0.10 11/13/03, v 1.1 Y Die Notes 1 Bump counts: 48 (8 row x 6 column). 2 Pitch: (x,y) = 0.75 mm x 0.75 mm (typ). 3 Units: millimeters. 4 All tolerance are 0.050 unless otherwise specified. 5 Typ: typical. 6 Y is coplanarity: 0.10 (max). Alliance Semiconductor P. 9 of 11 AS7C1026B (R) Ordering codes Package \ Access time Plastic SOJ, 400 mil TSOP 2, 10.2 x 18.4 mm BGA, 6 x 8 mm Temp 10 ns 12 ns 15 ns 20 ns commercial AS7C1026B-10JC AS7C1026B-12JC AS7C1026B-15JC AS7C1026B-20JC industrial AS7C1026B-10JI AS7C1026B-12JI AS7C1026B-15JI AS7C1026B-20JI commercial AS7C1026B-10TC AS7C1026B-12TC AS7C1026B-15TC AS7C1026B-20TC industrial AS7C1026B-10TI AS7C1026B-12TI AS7C1026B-15TI AS7C1026B-20TI commercial AS7C1026B-10BC AS7C1026B-12BC AS7C1026B-15BC AS7C1026B-20BC industrial AS7C1026B-10BI AS7C1026B-12BI AS7C1026B-15BI AS7C1026B-20BI Note: Add suffix `N' to the above ordering part number for LEAD FREE PARTS (Ex: AS7C1026B-10JCN) Part numbering system AS7C 1026B -XX X X X Package: SRAM prefix Device number 11/13/03, v 1.1 Temperature range: Access J = SOJ 400 mil C = commercial: 0 C to 70 C time T = TSOP 2, 10.2 x 18.4 mm I = industrial: -40 C to 85 C B = BGA, 6 x 8 mm Alliance Semiconductor N = LEAD FREE PART P. 10 of 11 AS7C1026B (R) (R) Alliance Semiconductor Corporation Copyright (c) Alliance Semiconductor 2575, Augustine Drive, All Rights Reserved Santa Clara, CA 95054 Part Number: AS7C1026B Tel: 408 - 855 - 4900 Document Version: v 1.1 Fax: 408 - 855 - 4999 www.alsc.com (c) Copyright 2003 Alliance Semiconductor Corporation. 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