ENELOOP4 2000-2 - PANASONIC - Datasheet.Directory

 2013 Microchip Technology Inc. Preliminary DS20005002D-page 1

Features

• Organized as 4M x16

• Single Voltage Read and Write Operations

- 2.7-3.6V

• Superior Reliability

- Endurance: 100,000 Cycles minimum

- Greater than 100 years Data Retention

• Low Power Consumption (typical values at 5 MHz)

- Active Current: 25 mA (typical)

- Standby Current: 5 μA (typical)

- Auto Low Power Mode: 5 μA (typical)

• 128-bit Unique ID

• Security-ID Feature

- 248 Word, user One-Time-Programmable

• Protection and Security Features

- Hardware Boot Block Protection/WP# Input Pin,

Uniform (32 KWord), and Non-Uniform

(8 KWord) options available

- User-controlled individual block (32 KWord) pro-

tection, using software only methods

- Password protection

• Hardware Reset Pin (RST#)

• Fast Read and Page Read Access Times:

- 70 ns Read access time

- 25 ns Page Read access times

- 8-Word Page Read buffer

• Latched Address and Data

• Fast Erase Times:

- Block-Erase Time: 18 ms (typical)

- Chip-Erase Time: 40 ms (typical)

• Erase-Suspend/-Resume Capabilities

• Fast Word and Write-Buffer Programming Times:

- Word-Program Time: 7 μs (typical)

- Write Buffer Programming Time: 1.75 μs / Word

(typical)

- 16-Word Write Buffer

• Automatic Write Timing

- Internal VPP Generation

• End-of-Write Detection

- Toggle Bits

- Data# Polling

- RY/BY# Output

• CMOS I/O Compatibility

• JEDEC Standard

- Flash EEPROM Pinouts and command sets

• CFI Compliant

• Packages Available

- 48-lead TSOP

- 48-ball TFBGA

• All non-Pb (lead-free) devices are RoHS compliant

Description

The SST38VF6401B, SST38VF6402B, SST38VF6403B,

and SST38VF6404B devices are 4M x16 CMOS

Advanced Multi-Purpose Flash Plus (Advanced MPF+)

manufactured with Microchip proprietary, high-perfor-

mance CMOS SuperFlash technology. The split-gate cell

design and thick-oxide tunneling injector attain better reli-

ability and manufacturability compared with alternate

approaches. The SST38VF6401B/6402B/6403B/6404B

write (Program or Erase) with a 2.7-3.6V power supply.

These devices conform to JEDEC standard pin assign-

ments for x16 memories.

Featuring high performance Word-Program, the

SST38VF6401B/6402B/6403B/6404B provide a typical

Word-Program time of 7 μsec. For faster word-pro-

gramming performance, the Write-Buffer Programming

feature, has a typical word-program time of 1.75 μsec.

These devices use Toggle Bit, Data# Polling, or the RY/

BY# pin to indicate Program operation completion. In

addition to single-word Read, Advanced MPF+ devices

provide a Page-Read feature that enables a faster

word read time of 25 ns, eight words on the same page.

To protect against inadvertent write, the

SST38VF6401B/6402B/6403B/6404B have on-chip

hardware and Software Data Protection schemes.

Designed, manufactured, and tested for a wide spec-

trum of applications, these devices are available with

100,000 cycles minimum endurance. Data retention is

rated at greater than 100 years.

The SST38VF6401B/6402B/6403B/6404B are suited for

applications that require the convenient and economi-

cal updating of program, configuration, or data mem-

ory. For all system applications, Advanced MPF+

significantly improve performance and reliability, while

lowering power consumption. These devices inherently

use less energy during Erase and Program than alter-

native flash technologies. The total energy consumed

is a function of the applied voltage, current, and time of

application. For any given voltage range, the Super-

Flash technology uses less current to program and has

SST38VF6401B / SST38VF6402B

SST38VF6403B / SST38VF6404B

64 Mbit (x16) Advanced Multi-Purpose Flash Plus

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

DS20005002D-page 2 Preliminary  2013 Microchip Technology Inc.

a shorter erase time; therefore, the total energy con-

sumed during any Erase or Program operation is less

than alternative flash technologies.

These devices also improve flexibility while lowering

the cost for program, data, and configuration storage

applications. The SuperFlash technology provides

fixed Erase and Program times, independent of the

number of Erase/Program cycles that have occurred.

Therefore, the system software or hardware does not

have to be modified or de-rated as is necessary with

alternative flash technologies, whose Erase and Pro-

gram times increase with accumulated Erase/Program

cycles.

The SST38VF6401B/6402B/6403B/6404B also offer

flexible data protection features. Applications that

require memory protection from program and erase

operations can use the Boot Block, Individual Block

Protection, and Advanced Protection features. For

applications that require a permanent solution, the Irre-

versible Block Locking feature provides permanent

protection for memory blocks.

To meet high-density, surface mount requirements, the

SST38VF6401B/6402B/6403B/6404B devices are

offered in 48-lead TSOP and 48-ball TFBGA packages.

See Figures 2-1 and for pin assignments and Table 2-

1 for pin descriptions.

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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

Errata

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devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision

of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

 2013 Microchip Technology Inc. Preliminary DS20005002D-page 3

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

1.0 FUNCTIONAL BLOCK DIAGRAM

FIGURE 1-1: FUNCTIONAL BLOCK DIAGRAM

Y-Decoder

I/O Buffers and Data Latches

1309 B1.1

Address Buffer Latches

X-Decoder

DQ15 -DQ

Memory Address

OE#

CE#

WE#

SuperFlash

Memory

Control Logic

WP#

RST#

RY/BY#

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

DS20005002D-page 4 Preliminary  2013 Microchip Technology Inc.

2.0 PIN ASSIGNMENTS

FIGURE 2-1: PIN ASSIGNMENTS FOR 48-LEAD TSOP

FIGURE 2-2: PIN ASSIGNMENTS FOR 48-BALL TFBGA

A15

A14

A13

A12

A11

A10

A19

A20

WE#

RST#

A21

WP#

RY/BY#

A18

A17

A16

VSS

DQ15

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VDD

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

VSS

CE#

25002 48-tsop P1.0

Standard Pinout

Top View

Die Up

25002 48-tfbga P1.0

ABCDEFGH

TOP VIEW (balls facing down)

A13

WE#

RY/BY#

A12

RST#

WP#

A17

A14

A10

A21

A18

A15

A11

A19

A20

A16

DQ7

DQ5

DQ2

DQ0

DQ14

DQ12

DQ10

DQ8

CE#

DQ15

DQ13

VDD

DQ11

DQ9

OE#

VSS

DQ6

DQ4

DQ3

DQ1

VSS

 2013 Microchip Technology Inc. Preliminary DS20005002D-page 5

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

TABLE 2-1: PIN DESCRIPTION

Symbol Pin Name Functions

AMS1-A0Address Inputs To provide memory addresses.

During Block-Erase AMS-A15 address lines will select the block.

DQ15-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a Write cycle.

The outputs are in tri-state when OE# or CE# is high.

WP# Write Protect To protect the top/bottom boot block from Erase/Program operation when

grounded.

RY/BY# Ready/Busy To indicate when the device is actively programming or erasing.

RST# Reset To reset and return the device to Read mode.

CE# Chip Enable To activate the device when CE# is low.

OE# Output Enable To gate the data output buffers.

WE# Write Enable To control the Write operations.

VDD Power Supply To provide power supply voltage: 2.7-3.6V

VSS Ground

NC No Connection Unconnected pins.

1. AMS = Most significant address

AMS =A

21 for SST38VF6401B/6402B/6403B/6404B

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

DS20005002D-page 6 Preliminary  2013 Microchip Technology Inc.

3.0 MEMORY MAPS

TABLE 3-1: SST38VF6401B AND SST38VF6402B MEMORY MAPS

SST38VF6401B

Block1

1. Each block, B0-B127 is 32KWord.

Size Address A21-A152

2. X=0or1.Block Address (BA) = A21 -A

VPB3

3. Each block has an associated VPB and NVPB.

NVPB3WP#4

4. Block B0 is the boot block.

B0432 KWord 0000000 YES YES YES

B1 32 KWord 0000001 YES YES NO

B2 32 KWord 0000010 YES YES NO

B3 32 KWord 0000011 YES YES NO

B4 32 KWord 0000100 YES YES NO

B5 32 KWord 0000101 YES YES NO

B6 32 KWord 0000110 YES YES NO

B7 32 KWord 0000111 YES YES NO

B8 - B119 follow the same pattern

B120 32 KWord 1111000 YES YES NO

B121 32 KWord 1111001 YES YES NO

B122 32 KWord 1111010 YES YES NO

B123 32 KWord 1111011 YES YES NO

B124 32 KWord 1111100 YES YES NO

B125 32 KWord 1111101 YES YES NO

B126 32 KWord 1111110 YES YES NO

B127 32 KWord 1111111 YES YES NO

SST38VF6402B

Block1Size Address A21-A152VPB3NVPB3WP#5

5. Block B127 is the boot block.

B0 32 KWord 0000000 YES YES NO

B1 32 KWord 0000001 YES YES NO

B2 32 KWord 0000010 YES YES NO

B3 32 KWord 0000011 YES YES NO

B4 32 KWord 0000100 YES YES NO

B5 32 KWord 0000101 YES YES NO

B6 32 KWord 0000110 YES YES NO

B7 32 KWord 0000111 YES YES NO

B8 - B119 follow the same pattern

B120 32 KWord 1111000 YES YES NO

B121 32 KWord 1111001 YES YES NO

B122 32 KWord 1111010 YES YES NO

B123 32 KWord 1111011 YES YES NO

B124 32 KWord 1111100 YES YES NO

B125 32 KWord 1111101 YES YES NO

B126 32 KWord 1111110 YES YES NO

B127532 KWord 1111111 YES YES YES

 2013 Microchip Technology Inc. Preliminary DS20005002D-page 7

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

TABLE 3-2: SST38VF6403B AND SST38VF6404B MEMORY MAPS (SHEET 1 OF 2)

SST38VF6403B

Block1Size Address A21-A152VPB3NVPB3WP#4

B03,44 KWord 0000000000 YES YES YES

B1 4 KWord 0000000001 YES YES YES

B2 4 KWord 0000000010 YES YES NO

B3 4 KWord 0000000011 YES YES NO

B4 4 KWord 0000000100 YES YES NO

B5 4 KWord 0000000101 YES YES NO

B6 4 KWord 0000000110 YES YES NO

B7 4 KWord 0000000111 YES YES NO

B8 32 KWord 0000001XXX YES YES NO

B9 32 KWord 0000010XXX YES YES NO

B10 32 KWord 0000011XXX YES YES NO

B11 32 KWord 0000100XXX YES YES NO

B12 32 KWord 0000101XXX YES YES NO

B13 32 KWord 0000110XXX YES YES NO

B14 32 KWord 0000111XXX YES YES NO

B15 32 KWord 0001000XXX YES YES NO

B16 - B126 follow the same pattern

B127 32 KWord 1111000XXX YES YES NO

B128 32 KWord 1111001XXX YES YES NO

B129 32 KWord 1111010XXX YES YES NO

B1230 32 KWord 1111011XXX YES YES NO

B1231 32 KWord 1111100XXX YES YES NO

B1232 32 KWord 1111101XXX YES YES NO

B133 32 KWord 1111110XXX YES YES NO

B134 32 KWord 1111111XXX YES YES NO

SST38VF6404B

Block1Size Address A21-A152VPB3NVPB3WP#5

B0 32 KWord 0000000XXX YES YES NO

B1 32 KWord 0000001XXX YES YES NO

B2 32 KWord 0000010XXX YES YES NO

B3 32 KWord 0000011XXX YES YES NO

B4 32 KWord 0000100XXX YES YES NO

B5 32 KWord 0000101XXX YES YES NO

B6 32 KWord 0000110XXX YES YES NO

B7 32 KWord 0000111XXX YES YES NO

B8 - B119 follow the same pattern

B120 32 KWord 1111000XXX YES YES NO

B121 32 KWord 1111001XXX YES YES NO

B122 32 KWord 1111010XXX YES YES NO

B123 32 KWord 1111011XXX YES YES NO

B124 32 KWord 1111100XXX YES YES NO

B125 32 KWord 1111101XXX YES YES NO

B126 32 KWord 1111110XXX YES YES NO

B1273, 54 KWord 1111111000 YES YES NO

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

DS20005002D-page 8 Preliminary  2013 Microchip Technology Inc.

B128 4 KWord 1111111001 YES YES NO

B129 4 KWord 1111111010 YES YES NO

B130 4 KWord 1111111011 YES YES NO

B131 4 KWord 1111111100 YES YES NO

B132 4 KWord 1111111101 YES YES NO

B133 4 KWord 1111111110 YES YES YES

B134 4 KWord 1111111111 YES YES YES

1. Each block, B0-B127 is 32KWord.

2. X=0or1.Block Address (BA) = A21 -A

3. Each block has an associated VPB and NVPB, except for some blocks in SST38VF6403B and SST38VF6404B.

In SST38VF6403B, Block B0 does not have a single VPB or NVPB for all 32 KWords. Instead, each block (4 KWord) in Block

B0 has its own VPB and NVPB.

In SST38VF6404B, Block B127 does not have a single VPB or NVPB for all 32 KWords. Instead, each block (4 KWord) in

Block B127 has its own VPB and NVPB.

4. The 8KWord boot block consists of S0 and S1 in Block B0.

5. The 8KWord boot block consists of S1022 and S1023 in Block B127.

TABLE 3-2: SST38VF6403B AND SST38VF6404B MEMORY MAPS (CONTINUED) (SHEET 2 OF 2)

 2013 Microchip Technology Inc. Preliminary DS20005002D-page 9

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

4.0 DEVICE OPERATION

The memory operations functions of these devices are

initiated using commands written to the device using

standard microprocessor Write sequences. A com-

mand is written by asserting WE# low while keeping

CE# low. The address bus is latched on the falling edge

of WE# or CE#, whichever occurs last. The data bus is

latched on the rising edge of WE# or CE#, whichever

occurs first.

The SST38VF6401B/6402B/6403B/6404B also have the

Auto Low Power mode which puts the device in a near-

standby mode after data has been accessed with a

valid Read operation. This reduces the IDD active read

current from typically 6 mA to typically 5 μA. The device

requires no access time to exit the Auto Low Power

mode after any address transition or control signal tran-

sition used to initiate another Read cycle. The device

does not enter Auto-Low Power mode after power-up

with CE# held steadily low, until the first address tran-

sition or CE# is driven high.

4.1 Read

The Read operation of the SST38VF6401B/6402B/

6403B/6404B is controlled by CE# and OE#, both of

which have to be low for the system to obtain data from

the outputs. CE# is used for device selection. When

CE# is high, the chip is deselected and only standby

power is consumed. OE# is the output control and is

used to gate data from the output pins. The data bus is

in high impedance state when either CE# or OE# is

high. Refer to Figure 6-1, the Read cycle timing dia-

gram, for further details.

4.2 Page Read

The Page Read operation utilizes an asynchronous

method that enables the system to read data from the

SST38VF6401B/6402B/6403B/6404B at a faster rate.

This operation allows users to read an eight-word page

of data at an average speed of 33 ns per word.

In Page Read, the initial word read from the page

requires TACC to be valid, while the remaining seven

words in the page require only TPACC. All eight words in

the page have the same address bits, A21-A3, which

are used to select the page. Address bits A2-A0 are tog-

gled, in any order, to read the words within the page.

The Page Read operation of the SST38VF6401B/

6402B/6403B/6404B is controlled by CE# and OE#.

Both CE# and OE# must be low for the system to obtain

data from the output pins. CE# controls device selec-

tion. When CE# is high, the chip is deselected and only

standby power is consumed. OE# is the output control

and is used to gate data from the output pins. The data

bus is in high impedance state when either CE# or OE#

is high. Refer to Figure 6-3, the Page Read cycle timing

diagram, for further details.

4.3 Word-Program Operation

The SST38VF6401B/6402B/6403B/6404B can be pro-

grammed on a word-by-word basis. Before program-

ming, the block where the word exists must be fully

erased. The Program operation is accomplished in

three steps. The first step is the three-byte load

sequence for Software Data Protection. The second

step is to load word address and word data. During the

Word-Program operation, the addresses are latched

on the falling edge of either CE# or WE#, whichever

occurs last. The data is latched on the rising edge of

either CE# or WE#, whichever occurs first. The third

step is the internal Program operation which is initiated

after the rising edge of the fourth WE# or CE#, which-

ever occurs first. The Program operation, once initi-

ated, will be completed within 7 μs. See Figures 6-3

and 6-4 for WE# and CE# controlled Program opera-

tion timing diagrams and Figure 6-19 for flowcharts.

During the Program operation, the only valid reads are

Data# Polling, Toggle Bits, and RY/BY#. During the

internal Program operation, the host is free to perform

additional tasks. Any commands issued during the

internal Program operation are ignored. During the

command sequence, WP# should be statically held

high or low.

When programming more than a few words, Microchip

recommends Write-Buffer Programming.

4.4 Write-Buffer Programming

The SST38VF6401B/6402B/6403B/6404B offer Write-

Buffer Programming, a feature that enables faster

effective word programming. To use this feature, write

up to 16 words with the Write-to-Buffer command, then

use the Program Buffer-to-Flash command to program

the Write-Buffer to memory.

The Write-to-Buffer command consists of between 5

and 20 write cycles. The total number of write cycles in

the Write-to-Buffer command sequence is equal to the

number of words to be written to the buffer plus four.

The first three cycles in the command sequence tell the

device that a Write-to-Buffer operation will begin.

The fourth cycle tells the device the number of words to

be written into the buffer and the block address of these

words. Specifically, the write cycle consists of a block

address and a data value called the Word Count (WC),

which is the number of words to be written to the buffer

minus one. If the WC is greater than 15, the maximum

buffer size minus 1, then the operation aborts.

For the fifth cycle, and all subsequent cycles of the

Write-to-Buffer command, the command sequence

consists of the addresses and data of the words to be

written into the buffer. All of these cycles must have the

same A21 - A4 address, otherwise the operation aborts.

The number of Write cycles required is equal to the

number of words to be written into the Write-Buffer,

which is equal to WC plus one. The correct number of

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

DS20005002D-page 10 Preliminary  2013 Microchip Technology Inc.

Write cycles must be issued or the operation will abort.

Each Write cycle decrements the Write-Buffer counter,

even if two or more of the Write cycles have identical

address values. Only the final data loaded for each buf-

fer location is held in the Write-Buffer.

Once the Write-to-Buffer command sequence is com-

pleted, the Program Buffer-to-Flash command should

be issued to program the Write-Buffer contents to the

specified block in memory. The block address (i.e. A21

- A15) in this command must match the block address

in the 4th write cycle of the Write-to-Buffer command or

the operation aborts. See Table 5-2 for details on

Write-to-Buffer and Program-Buffer-to-Flash com-

mands.

While issuing these command sequences, the Write-

Buffer Programming Abort detection bit (DQ1) indi-

cates if the operation has aborted. There are several

cases in which the device can abort:

• In the fourth write cycle of the Write-to-Buffer

command, if the WC is greater than 15, the opera-

tion aborts.

• In the fifth and all subsequent cycles of the Write-

to-Buffer command, if the address values, A21 -

A4, are not identical, the operation aborts.

• If the number of write cycles between the fifth to

the last cycle of the Write-to-Buffer command is

greater than WC +1, the operation aborts.

• After completing the Write-to-Buffer command

sequence, issuing any command other than the

Program Buffer-to-Flash command, aborts the

operation.

• Loading a block address, i.e. A21-A15, in the Pro-

gram Buffer-to-Flash command that does not

match the block address used in the Write-to-Buf-

fer command aborts the operation.

If the Write-to-Buffer or Program Buffer-to-Flash opera-

tion aborts, then DQ1 = 1 and the device enters Write-

Buffer-Abort mode. To execute another operation, a

Write-to-Buffer Abort-Reset command must be issued

to clear DQ1 and return the device to standard read

mode.

After the Write-to-Buffer and Program Buffer-to-Flash

commands are successfully issued, the programming

operation can be monitored using Data# Polling, Tog-

gle Bits, and RY/BY#.

4.5 Block-Erase Operations

The Block-Erase operation allows the system to erase

the device on a block-by-block basis.

The Block-Erase architecture is based on block size of

32 KWords. In SST38VF6401B and SST38VF6402B

devices, the Block-Erase command can erase any

32KWord Block (B0-B127). For the non-uniform boot

block devices, SST38VF6403B and SST38VF6404B,

the Block-Erase command can erase any 32 KWord

block except the block that contains the boot area. In

the boot area, Block-Erase only erases a 4KWord

block.

The Block-Erase operation is initiated by executing a

six-byte command sequence with Block-Erase com-

mand (30H) and block address (BA) in the last bus

cycle. The block address is latched on the falling edge

of the sixth WE# pulse, while the command (30H) is

latched on the rising edge of the sixth WE# pulse. The

internal Erase operation begins after the sixth WE#

pulse. The End-of-Erase operation can be determined

using either Data# Polling or Toggle Bit methods. The

RY/BY# pin can also be used to monitor the erase

operation. For more information, see Figure 6-10 for

timing waveforms and Figure 6-24 for the flowchart.

Any commands, other than Erase-Suspend, issued

during the Block-Erase operation are ignored. Any

attempt to Block-Erase memory inside a block pro-

tected by Volatile Block Protection, Non-Volatile Block

Protection, or WP# (low) will be ignored. During the

command sequence, WP# should be statically held

high or low.

4.6 Erase-Suspend/Erase-Resume

Commands

The Erase-Suspend operation temporarily suspends a

Block-Erase operation thus allowing data to be read or

programmed into any block that is not engaged in an

Erase operation. The operation is executed with a one-

byte command sequence with Erase-Suspend com-

mand (B0H). The device automatically enters read

mode within 20 μs (max) after the Erase-Suspend com-

mand had been issued. Valid data can be read, using

a Read or Page Read operation, from any block that is

not being erased. Reading at an address location

within Erase-Suspended blocks will output DQ2 tog-

gling and DQ6 at ‘1’. While in Erase-Suspend, a Word-

Program or Write-Buffer Programming operation is

allowed anywhere except the block selected for Erase-

Suspend.

To resume a suspended Block-Erase operation, the

system must issue the Erase-Resume command. The

operation is executed by issuing one byte command

sequence with Erase-Resume command (30H) at any

address in the last Byte sequence.

When an erase operation is suspended, or re-sus-

pended, after resume the cumulative time needed for

the erase operation to complete is greater than the

erase time of a non-suspended erase operation. If the

hold time from Erase-Resume to the next Erase- Sus-

pend operation is less than 200μs, the accumulative

erase time can become very long Therefore, after issu-

ing an Erase-Resume command, the system must wait

at least 200μs before issuing another Erase-Suspend

command. The Erase-Resume command will be

ignored until any program operations initiated during

Erase-Suspend are complete.

 2013 Microchip Technology Inc. Preliminary DS20005002D-page 11

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

Bypass mode can be entered while in Erase-Suspend,

but only Bypass Word-Program is available for those

blocks that are not suspended. Bypass Block-Erase,

Bypass Chip-Erase, Erase-Suspend, and Erase-

Resume are not available. In order to resume an Erase

operation, the Bypass mode must be exited before

issuing Erase-Resume. For more information about

Bypass mode, see “Bypass Mode” on page 14.

4.7 Chip-Erase Operation

The SST38VF6401B/6402B/6403B/6404B devices

provide a Chip-Erase operation, which erases the

entire memory array to the ‘1’ state. This operation is

useful when the entire device must be quickly erased.

The Chip-Erase operation is initiated by executing a

six-byte command sequence with Chip-Erase com-

mand (10H) at address 555H in the last byte sequence.

The Erase operation begins with the rising edge of the

sixth WE# or CE#, whichever occurs first. During the

Erase operation, the only valid reads are Toggle Bit,

Data# Polling, or RY/BY#. See Table 5-2 for the com-

mand sequence, Figure 6-9 for timing diagram, and

Figure 6-24 for the flowchart. Any commands issued

during the Chip-Erase operation are ignored. If WP# is

low, or any VPBs or NVPBs are in the protect state, any

attempt to execute a Chip-Erase operation is ignored.

During the command sequence, WP# should be stati-

cally held high or low.

4.8 Write Operation Status Detection

To optimize the system Write cycle time, the

SST38VF6401B/6402B/6403B/6404B provide two soft-

ware means to detect the completion of a Write (Pro-

gram or Erase) cycle The software detection includes

two status bits: Data# Polling (DQ7) and Toggle Bit

(DQ6). The End-of-Write detection mode is enabled

after the rising edge of WE#, which initiates the internal

Program or Erase operation.

The actual completion of the nonvolatile write is asyn-

chronous with the system. Therefore, Data# Polling or

Toggle Bit maybe be read concurrent with the comple-

tion of the write cycle. If this occurs, the system may

possibly get an incorrect result from the status detec-

tion process. For example, valid data may appear to

conflict with either DQ7 or DQ6. To prevent false

results, upon detection of failures, the software routine

should loop to read the accessed location an additional

two times. If both reads are valid, then the device has

completed the Write cycle, otherwise the failure is valid.

For the Write-Buffer Programming feature, DQ1

informs the user if either the Write-to-Buffer or Program

Buffer-to-Flash operation aborts. If either operation

aborts, then DQ1 = 1. DQ1 must be cleared to '0' by

issuing the Write-to-Buffer Abort Reset command.

The SST38VF6401B/6402B/6403B/6404B also pro-

vide a RY/BY# signal. This signal indicates the status

of a Program or Erase operation.

If a Program or Erase operation is attempted on a pro-

tected block, the operation will abort. After the device

initiates an abort, the corresponding Write Operation

Status Detection Bits will stay active for approximately

200ns (program or erase) before the device returns to

read mode.

For the status of these bits during a Write operation,

see Table 4-1.

4.8.1 DATA# POLLING (DQ7)

When the SST38VF6401B/6402B/6403B/6404B are in

an internal Program operation, any attempt to read

DQ7 will produce the complement of true data. For a

Program Buffer-to-Flash operation, DQ7 is the comple-

ment of the last word loaded in the Write-Buffer using

the Write-to-Buffer command. Once the Program oper-

ation is completed, DQ7 will produce valid data. Note

that even though DQ7 may have valid data immediately fol-

lowing the completion of an internal Write operation, the

remaining data outputs may still be invalid. Valid data on the

entire data bus will appear in subsequent successive Read

cycles after an interval of 1 μs.

During an internal Erase operation, any attempt to read

DQ7 will produce a ‘0’. Once the internal Erase opera-

tion is completed, DQ7 will produce a ‘1’. The Data#

Polling is valid after the rising edge of fourth WE# (or

CE#) pulse for Program operation. For Block- or Chip-

Erase, the Data# Polling is valid after the rising edge of

sixth WE# (or CE#) pulse. See Figure 6-7 for Data#

Polling timing diagram and Figure 6-21 for a flowchart.

4.8.2 TOGGLE BITS (DQ6 AND DQ2)

During the internal Program or Erase operation, any

consecutive attempts to read DQ6 will produce alternat-

ing ‘1’s and ‘0’s, i.e., toggling between ‘1’ and ‘0’. When

the internal Program or Erase operation is completed,

the DQ6 bit will stop toggling, and the device is then

ready for the next operation. For Block- or Chip-Erase,

the toggle bit (DQ6) is valid after the rising edge of sixth

WE# (or CE#) pulse. DQ6 will be set to ‘1’ if a Read

operation is attempted on an Erase-Suspended Block.

If Program operation is initiated in a block not selected

in Erase-Suspend mode, DQ6 will toggle.

An additional Toggle Bit is available on DQ2, which can

be used in conjunction with DQ6 to check whether a

particular block is being actively erased or erase-sus-

pended. Table 4-1 shows detailed bit status informa-

tion. The Toggle Bit (DQ2) is valid after the rising edge

of the last WE# (or CE#) pulse of Write operation. See

Figure 6-8 for Toggle Bit timing diagram and Figure 6-

21 for a flowchart.

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

DS20005002D-page 12 Preliminary  2013 Microchip Technology Inc.

4.8.3 DQ1

If an operation aborts during a Write-to-Buffer or Pro-

gram Buffer-to-Flash operation, DQ1 is set to ‘1’. To

reset DQ1 to ‘0’, issue the Write-to-Buffer Abort Reset

command to exit the abort state. A power-off/power-on

cycle or a Hardware Reset (RST# = 0) will also clear

DQ1.

4.8.4 RY/BY#

The RY/BY# pin can be used to determine the status of

a Program or Erase operation. The RY/BY# pin is valid

after the rising edge of the final WE# pulse in the com-

mand sequence. If RY/BY# = 0, then the device is

actively programming or erasing. If RY/BY# = 1, the

device is in Read mode. The RY/BY# pin is an open

drain output pin. This means several RY/BY# can be

tied together with a pull-up resistor to VDD..

4.9 Data Protection

The SST38VF6401B/6402B/6403B/6404B provide both

hardware and software features to protect nonvolatile

data from inadvertent writes.

4.9.1 HARDWARE DATA PROTECTION

4.9.1.1 Noise/Glitch Protection

A WE# or CE# pulse of less than 5 ns will not initiate a

write cycle.

4.9.1.2 VDD Power Up/Down Detection

The Write operation is inhibited when VDD is less than 1.5V.

4.9.1.3 Write Inhibit Mode

Forcing OE# low, CE# high, or WE# high will inhibit the

Write operation. This prevents inadvertent writes

during power-up or power-down.

4.9.2 HARDWARE BLOCK PROTECTION

The SST38VF6402B and SST38VF6404B devices

support top hardware block protection, which protects

the top boot block of the device. For SST38VF6402B,

the boot block consists of the top 32 KWord block, and

for SST38VF6404B the boot block consists of the top

two 4 KWord blocks (8 KWord total).

The SST38VF6401B and SST38VF6403B devices

support bottom hardware block protection, which pro-

tects the bottom boot block of the device. For

SST38VF6401B, the boot block consists of the bottom

32 KWord block, and for SST38VF6403B the Boot

Block consists of the bottom two 4 KWord blocks (8

KWord total). The boot block addresses are described

in Table 4-2.

TABLE 4-1: WRITE OPERATION STATUS

Status DQ71DQ6DQ21DQ1RY/BY#2

Normal

Operation

Standard Program DQ7# Toggle No Toggle 0 0

Standard Erase 0 Toggle Toggle N/A 0

Erase-Suspend

Mode

Read from Erase-Suspended Block 1 No

toggle

Toggle N/A 1

Read from Non- Erase-Suspended

Block

Data Data Data Data 1

Program DQ7# Toggle N/A N/A 0

Program Buffer-

to-Flash

Busy DQ7#3Toggle N/A 0 0

Abort DQ7#3Toggle N/A 1 0

1. DQ7and DQ2require a valid address when reading status information.

2. RY/BY# is an open drain pin. RY/BY# is high in Read mode, and Read in Erase-Suspend mode.

3. During a Program Buffer-to-Flash operation, the datum on the DQ7pin is the complement of DQ7of the last word loaded in

the Write-Buffer using the Write-to-Buffer command.

TABLE 4-2: BOOT BLOCK ADDRESS

RANGES

Product Size Address Range

Bottom Boot

Uniform

SST38VF6401B 32 KW 000000H-007FFFH

Top Boot Uniform

SST38VF6402B 32 KW 3F8000H-3FFFFFH

Bottom Boot Non-

Uniform

SST38VF6403B 8 KW 000000H-001FFFH

Top Boot Non-

Uniform

SST38VF6404B 8 KW 3FE000H-3FFFFFH

 2013 Microchip Technology Inc. Preliminary DS20005002D-page 13

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

Program and Erase operations are prevented on the

Boot Block when WP# is low. If WP# is left floating, it is

internally held high via a pull-up resistor. When WP# is

high, the Boot Block is unprotected, which allows Pro-

gram and Erase operations on that area.

4.9.3 HARDWARE RESET (RST#)

The RST# pin provides a hardware method of resetting

the device to read array data. When the RST# pin is

held low for at least TRP, any in-progress operation will

terminate and return to Read mode. When no internal

Program/Erase operation is in progress, a minimum

period of TRHR is required after RST# is driven high

before a valid Read can take place. See Figure 6-15 for

more information.

The interrupted Erase or Program operation must be

re-initiated after the device resumes normal operation

mode to ensure data integrity.

4.9.4 SOFTWARE DATA PROTECTION (SDP)

The SST38VF6401B/6402B/6403B/6404B devices

implement the JEDEC approved Software Data Protec-

tion (SDP) scheme for all data alteration operations,

such as Program and Erase. These devices are

shipped with the Software Data Protection permanently

enabled. See Table 5-2 for the specific software com-

mand codes.

All Program operations require the inclusion of the

three-byte sequence. The three-byte load sequence is

used to initiate the Program operation, providing opti-

mal protection from inadvertent Write operations. SDP

for Erase operations is similar to Program, but a six-

byte load sequence is required for Erase operations.

During SDP command sequence, invalid commands

will abort the device to read mode within TRC. The con-

tents of DQ15-DQ8 can be VIL or VIH, but no other

value, during any SDP command sequence.

The SST38VF6401B/6402B/6403B/6404B devices

provide Bypass Mode, which allows for reduced Pro-

gram and Erase command sequence lengths. In this

mode, the SDP portion of Program and Erase com-

mand sequences are omitted. See “Bypass Mode” on

page 14 for further details.

4.10 Common Flash Memory Interface

(CFI)

The SST38VF6401B/6402B/6403B/6404B contain Com-

mon Flash Memory Interface (CFI) information that

describes the characteristics of the device. In order to

enter the CFI Query mode, the system can write a one-

byte sequence using a standard CFI Query Entry com-

mand. Once the device enters the CFI Query mode, the

system can read CFI data at the addresses given in

Tables 5-4 through 5-7.

The system must write the CFI Exit command to return

to Read mode. Note that the CFI Exit command is

ignored during an internal Program or Erase operation.

See Table 5-2 for software command codes, Figures 6-

12 and 6-14 for timing waveform, and Figures 6-22 and

6-23 for flowcharts.

4.11 Product Identification

The Product Identification mode identifies the devices

as the SST38VF6401B, SST38VF6402B,

SST38VF6403B, or SST38VF6404B, and the manu-

facturer as Microchip. See Table 4-3 for specific

address and data information. Product Identification

mode is accessed through software operations. The

software Product Identification operations identify the

part, and can be useful when using multiple manufac-

turers in the same socket. For details, see Table 5-2 for

software operation, Figure 6-11 for the software ID

Entry and Read timing diagram, and Figure 6-22 for the

software ID Entry command sequence flowchart.

While in Product Identification mode, the Read Block

Protection Status command determines if a block is

protected. The status returned indicates if the block has

been protected, but does not differentiate between Vol-

atile Block Protection and Non-Volatile Block Protec-

tion. See Table 5-2 for further details.

The Read-Irreversible Block-Lock Status command

indicates if the Irreversible Block Command has been

issued. If DQ0 = 0, then the Irreversible Lock command

has been previously issued.

In order to return to the standard Read mode, the soft-

ware Product Identification mode must be exited. The

exit is accomplished by issuing the software ID Exit

command sequence, which returns the device to the

Read mode. See Table 5-2 for software command

codes, Figure 6-14 for timing waveform, and Figures 6-

22 and 6-23 for flowcharts.

4.12 Security ID

The SST38VF6401B/6402B/6403B/6404B devices offer

a Security ID feature. The Secure ID space is divided

into two segments — one factory programmed 128 bit

segment and one user programmable 248 word seg-

ment. See Table 4-4 for address information. The first

segment is programmed and locked at Microchip and

TABLE 4-3: PRODUCT IDENTIFICATION

Add

Data

Add

Data

Add

Data

Manufacturer’s ID

00H BFH

Device ID

SST38VF6401B

01H 227EH 0EH

220CH

0FH 2200H

SST38VF6402B

01H 227EH 0EH

220CH

0FH 2201H

SST38VF6403B

01H 227EH 0EH 2210H 0FH 2200H

SST38VF6404B

01H 227EH 0EH 2210H 0FH 2201H

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

DS20005002D-page 14 Preliminary  2013 Microchip Technology Inc.

contains a 128 bit Unique ID which uniquely identifies

the device. The user segment is left un-programmed

for the customer to program as desired.

The user segment of the Security ID can be pro-

grammed by first using the SEC ID Entry command to

enter the Secure ID space. Once in the Secure ID

space, for smaller data sets, use the Word-Program

command to program data. To program larger sets of

data more quickly, use the Write-Buffer Programming

feature. Note that Bypass Mode is not available.

To detect end-of-write for the SEC ID, read the toggle

bits. Do not use Data# Polling to detect end of Write.

Once the programming is complete, lock the Sec ID by

programming bit ‘0’ in the PSR with the PSR Program

command. Locking the Sec ID disables any corruption of

this space. Note that regardless of whether or not the Sec

ID is locked, the Sec ID segments can not be erased.

The Secure ID space can be queried by executing a

three-byte command sequence with Enter Sec ID com-

mand (88H) at address 555H in the last byte sequence.

To exit this mode, the Exit Sec ID command should be

executed. Refer to Table 5-2 for software commands

and Figures 6-22 and 6-23 for flow charts.

4.13 Bypass Mode

Bypass mode shortens the time needed to issue pro-

gram and erase commands by reducing these com-

mands to two write cycles each. After using the Bypass

Entry command to enter the Bypass mode, only the

Bypass Word-Program, Bypass Block Erase, Bypass

Chip Erase, Erase-Suspend, and Erase-Resume com-

mands are available. The Bypass Exit command exits

Bypass mode. See Table 5-2 for further details.

Entering Bypass Mode while already in Erase-Suspend

limits the available commands. See “Erase-Suspend/

Erase-Resume Commands” on page 10 for more infor-

mation.

4.14 Protection Settings Register (PSR)

The Protection Settings Register (PSR) is a user-pro-

grammable register that allows for further customiza-

tion of the SST38VF6401B/6402B/6403B/6404B

protection features. The 16-bit PSR provides four One

Time Programmable (OTP) bits for users, each of

which can be programmed individually. However, once

an OTP bit is programmed to ‘0’, the value cannot be

changed back to a ‘1’. The other 12 bits of the PSR are

reserved. See Table 4-5 for the definition of all 16-bits

of the PSR.

Note that DQ4, DQ2, DQ1, DQ0 do not have to be pro-

grammed at the same time. In addition, DQ2 and DQ1

cannot both be programmed to ‘0’. The valid combina-

tions of states of DQ2 and DQ1 are shown in Table 4-6.

The PSR can be accessed by issuing the PSR Entry

command. Users can then use the PSR Program and

PSR Read commands. The PSR Exit command must

be issued to leave this mode. See Table 5-2 for further

details.

4.15 Individual Block Protection

The SST38VF6401B/6402B/6403B/6404B provide two

methods for Individual Block protection: Volatile Block

Protection and Non-Volatile Block Protection. Data in

protected blocks cannot be altered.

4.15.1 VOLATILE BLOCK PROTECTION

The Volatile Block Protection feature provides a faster

method than Non-Volatile Protection to protect and

unprotect 32 KWord blocks. Each block has it’s own

Volatile Protection Bit (VPB). In the SST38VF6401B/

6402B, the 32 KWord boot block also has a VPB. In the

TABLE 4-4: ADDRESS RANGE FOR SEC ID

Size Address

Microchip Unique ID 128 bits 000H – 007H

User 248 W 008H – 0FFH

TABLE 4-5: PSR BIT DEFINITIONS

Bit

Default

from

Factory Definition

DQ15-

DQ5

FFFh Reserved

DQ41 VPB power-up / hardware reset state

0 = all protected

1 = all unprotected

DQ31 Reserved

DQ21 Password mode

0 = Password only mode

1 = Pass-Through mode

DQ11 Pass-Through mode

0 = Pass-Through only mode

1 = Pass-Through mode

DQ01 SEC ID Lock Out Bit

0 = locked

1 = unlocked

TABLE 4-6: VALID DQ2 AND DQ1

COMBINATIONS

Combination Definition

DQ2, DQ1 = 11 Pass-Through mode (factory

default)

DQ2, DQ1 = 10 Pass-Through only mode

DQ2, DQ1 = 01 Password only mode

DQ2, DQ1 = 00 Not Allowed

 2013 Microchip Technology Inc. Preliminary DS20005002D-page 15

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

SST38VF6403B/6404B devices, each of the two 4

KWord blocks in the 8 KWord boot area has it's own

VPB.

After using the Volatile Block Protection Mode Entry

command to enter the Volatile Block Protection mode,

individual VPBs can be set or reset with VPB Set/Clear,

or be read with VPB Status Read. If the VPB is ‘0’, then

the block is protected from Program and Erase. If the

VPB is ‘1’, then the block is unprotected. The Volatile

Block Protection Exit command must be issued to exit

Volatile Block Protection mode. See Table 5-2 for fur-

ther details on the commands and Figure 6-26 for a

flow chart.

If the device experiences a hardware reset or a power

cycle, all the VPBs return to their default state as deter-

mined by user-programmable bit DQ4 in the PSR. If

DQ4 is ‘0’, then all VPBs default to ‘0’ (protected). If

DQ4 is ‘1’, then all VPBs default to ‘1’ (unprotected).

4.15.2 NON-VOLATILE BLOCK PROTECTION

The Non-Volatile Block Protection feature provides

protection to individual blocks using Non-Volatile Pro-

tection Bits (NVPBs). Each block has it’s own Non-Vol-

atile Protection Bit. In the SST38VF6401B/2, the 32

KWord boot block also has a it's own NVPB. In the

SST38VF6403B/6404B, each 4 KWord block in the

8KWord boot area has it's own NVPB. All NVPBs come

from the factory set to ‘1’, the unprotected state.

Use the Non-Volatile Block Protection Mode Entry

command to enter the Non-Volatile Block Protection

mode. Once in this mode, the NVPB Program com-

mand can be used to protect individual blocks by set-

ting individual NVPBs to ‘0’. The time needed to

program an NVPB is two times TBP, which is a maxi-

mum of 20μs. The NVPB Status Read command can

be used to check the protection state of an individual

NVPB.

To change an NVPB to ‘1’, the unprotected state, the

NVPB must be erased using NVPBs Erase command.

This command erases all NVPBs to ‘1’ and can take up

to 25 ms to complete. NVPB Program should be used

to set the NVPBs of any blocks that are to be protected

before exiting the Non-Volatile Block Protection mode.

See Table 5-2 and Figure 6-27 for further details.

Upon a power cycle or hardware reset, the NVPBs

retain their states. Memory areas that are protected

using Non-Volatile Block Protection remain protected.

The NVPB Program and NVPBs Erase commands are

permanently disabled once the Irreversible Block Lock

command is issued. See “Irreversible Block Locking”

on page 16 for further information.

4.16 Advanced Protection

The SST38VF6401B/6402B/6403B/6404B provide

Advanced Protection features that allow users to imple-

ment conditional access to the NVPBs. Specifically,

Advanced Protection uses the Global Lock Bit to pro-

tect the NVPBs. If the Global Lock bit is ‘0’ then all the

NVPBs states are frozen and cannot be modified in any

mode. If the Global Lock bit is ‘1’, then all the NVPBs

can be modified in Non-Volatile Block Protection mode.

After using the Global Lock of NVPBs Entry command

to enter the Global Lock of NVPBs mode, the Global

Lock Bit can be activated by issuing a Set Global Lock

Bit command, which sets the Global Lock Bit to ‘0’. The

Global Lock bit cannot be set to ‘1’ with this command.

The status of the bit can be read with the Global Lock

Bit Status command. Use the Global Lock of NVPBs

Exit command to exit Global Lock of NVPBs mode. See

Table 5-2 and Figure 6-28 for further details.

The steps used to change the Global Lock Bit from '0'

to'1,' to allow access to the NVPBs, depend on whether

the device has been set to use Pass-Through or Pass-

word mode. When using Advanced Protection, select

either Pass-Through only mode or Password only

mode by programming the DQ2 and DQ1 bits in the

PSR. Although the factory default is Pass-Through

mode (DQ2 = 1, DQ1 = 1), the user should explicitly

chose either Pass-Through only mode (DQ2 = 1, DQ1

= 0), or Password only mode (DQ2 = 0, DQ1 = 1). Keep-

ing the SST38VF6401B/6402B/6403B/6404B in the

factory default Pass-Through mode leaves the device

open to unauthorized changes of DQ2 and DQ1 in the

PSR. See “Protection Settings Register (PSR)” on

page 14. for more information about the PSR.

4.16.1 PASS-THROUGH MODE (DQ2, DQ1 = 1,0)

The Pass-Through Mode allows the Global Lock Bit

state to be cleared to ‘1’ by a power-down power-up

sequence or a hardware reset (RST# pin = 0). No pass-

word is required in Pass-Through mode.

To set the Global Lock Bit to ‘0’, use the Set Global

Lock Bit command while in the Global Lock of NVPBs

mode. Select the Pass-Through only mode by pro-

gramming PSR bit DQ2 = 1 and DQ1 = 0.

4.16.2 PASSWORD MODE (DQ2, DQ1 = 0,1)

In the Password Mode, the Global Lock Bit is set to ‘0’

by the Set Global Lock Bit command, a power-down

power-up sequence, or a hardware reset (RST# pin =

0). Select the Password only mode by programming

PSR bit DQ2 = 0 and DQ1 = 1. Note that when the PSR

Program command is issued in Password mode, the

Global Lock bit is automatically set to ‘0’.

In contrast to the Pass-Through Mode, in the Password

mode, the only way to clear the Global Lock Bit to ‘1’ is

to submit the correct 64-bit password using the Submit

Password command in Password Commands Mode.

The words of the password can be submitted in any

order as long as each 16 bit section of the password is

matched with its correct address. After the entire 64 bit

password is submitted, the device takes approximately

1 μs to verify the password. A subsequent Submit

Password command cannot be issued until this verifi-

cation time has elapsed.

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

DS20005002D-page 16 Preliminary  2013 Microchip Technology Inc.

The 64-bit password must be chosen by the user

before programming the DQ2 and DQ1 OTP bits of the

PSR to choose Password Mode. The default 64 bit

password on the device from the factory is

FFFFFFFFFFFFFFFFh.

Enter the Password Commands mode by issuing the

Password Commands Entry command. Then, use the

Password Program command to program the desired

password. Use caution when programming the pass-

word because there is no method to reset the password

to FFFFFFFFFFFFFFFFh. Once a password bit has

been set to ‘0’, it cannot be changed back to ‘1’. See

Table 5-2 for further details about Password-related

commands.

The password can be read using the Password Read

command to verify the desired password has been pro-

grammed. Microchip recommends testing the pass-

word before permanently choosing Password Mode.

To test the password, do the following:

1. Enter the Global Lock of NVPBs mode.

2. Set the Global Lock Bit to ‘0’, and verify the

value.

3. Exit the Global Lock of NVPBs mode.

4. Enter the Password Commands mode.

5. Submit the 64-bit password with the Submit

Password command.

6. Wait 2 μs for the device to verify the password.

7. Exit the Password Commands mode.

8. Re-enter the Global Lock of NVPBs mode

9. Read the Global Lock Bit with the Global Lock

Bit Status Read command. The Global Lock bit

should now be ‘1’.

After verifying the password, program the DQ2 and

DQ1 OTP bits of the PSR to explicitly choose Password

mode. Once the Password mode has been selected,

the Password Read and Password Program com-

mands are permanently disabled. There is no longer

any method for reading or modifying the password. In

addition, Microchip is unable to read or modify the

password. If a Password Read command is issued

while in Password mode, the data presented for each

word of the password is FFFFh.

If the Password Mode is not explicitly chosen in the

PSR, then the password can still be read and modified.

Therefore, Microchip strongly recommends that users

explicitly choose Password Mode in the PSR.

4.17 Irreversible Block Locking

The SST38VF6401B/6402B/6403B/6404B provides

Irreversible Block Locking, a feature that allows users

to customize the size of Read-Only Memory (ROM) on

the device and provides more flexibility than One-Time

Programmable (OTP) memory.

Applying Irreversible Block Locking turns user-selected

memory areas into ROM by permanently disabling Pro-

gram and Erase operations to these chosen areas. Any

area that becomes ROM cannot be changed back to

Flash.

Any memory blocks in the main memory, including boot

blocks, can be irreversibly locked. In non-uniform boot

block devices (SST38VF6403B and SST38VF6404B)

each 4 KW block in the boot area can be irreversibly

locked. If desired, all blocks in the main memory can be

irreversibly locked.

To use Irreversible Block Locking do the following:

1. Global Lock Bit should be ‘1’. The Irreversible

Block Lock command is disabled when Global

Lock Bit is ‘0’.

2. Enter the Non-Volatile Block Protection mode.

3. Use the NVPB Program command to protect

only the blocks that are to be changed into

ROM.

4. Exit the Non-Volatile Block Protection mode.

5. Issue the Irreversible Block Lock command (see

Table 5-2 for details).

The Irreversible Block Lock command can only be used

once. Issuing the command after the first time has no

effect on the device.

Important: Once the Irreversible Block Lock command

is used, the state of the NVPBs can no longer be

changed or overridden. Therefore, the following fea-

tures no longer have any effect on the device:

• Global Lock of NVPBs feature

• Password feature

• NVPB Program command

• NVPB Erase command

• DQ2 and DQ1 of PSR

In addition, WP# has no effect on any memory in the

boot block area that has been irreversibly locked.

To verify whether the Irreversible Block Lock command

has already been issued, enter the Product ID mode

and read address 5FEH. If DQ0 = 0, then Irreversible

Block Lock has already been executed. When using

this feature to determine if a specific block is ROM, use

the NVPB Status Read.

 2013 Microchip Technology Inc. Preliminary DS20005002D-page 17

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

5.0 OPERATIONS

TABLE 5-1: OPERATION MODES SELECTION

Mode CE# OE# WE# RST# WP# DQ Address

Read VIL VIL VIH HXD

OUT AIN

Program VIL VIH VIL HV

IL/VIH1

1. WP# can be VIL when programming or erasing outside of the bootblock.

WP# must be VIH when programming or erasing inside the bootblock area.

DIN AIN

Erase VIL VIH VIL HV

IL/VIH1X2

2. X can be VIL or VIH, but no other value.

Block address,

XXH for Chip-Erase

Standby VIH XXV

IH X High Z X

Write Inhibit X VIL X X X High Z/ DOUT X

Product Identification X X VIH H X High Z/ DOUT X

Reset X X X L X High Z X

Software Mode VIL VIH VIL H X See Table 5-2 See Table 5-2

TABLE 5-2: SOFTWARE COMMAND SEQUENCE (SHEET 1 OF 3)

Command

Sequence

1st Bus

Cycle

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

7th Bus

Cycle

Addr1

Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2

Addr1

Data2

Read3WA Data

Page Read3WA0Data0WA1Data1WA2Data2WA3Data3

Word-Program 555H AAH 2AAH 55H 555H A0H WA Data

Reset XXH F0H

Write-Buffer Programming

Write-to-Buffer4555H AAH 2AAH 55H BA 25H BA WC WAXData WAXData WAXData

Program Buf-

fer-to- Flash

BAX29H

Write-to-Buffer

Abort-Reset

555H AAH 2AAH 55H 555H F0H

Bypass Mode5

Bypass Mode

Entry

555H AAH 2AAH 55H 555H 20H

Bypass Word-

Program

XXXH A0H WA Data

Bypass Block

Erase

XXXH 80H BA 30H

Bypass Chip

Erase

XXXH 80H 555H 10H

Bypass Mode

Exit

XXXH 90H XXXH 00H

Erase Related

Block-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H BAx 30H

Chip-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H

Erase Sus-

pend

XXXH B0H

Erase

Resume

XXXH 30H

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

DS20005002D-page 18 Preliminary  2013 Microchip Technology Inc.

Security ID

SEC ID Entry6555H AAH 2AAH 55H 555H 88H

SEC ID

Read3,7 WAXData

SEC ID Exit 555H AAH 2AAH 55H 555H 90H XXH 00H

Product Identification

Software ID

Entry8555H AAH 2AAH 55H 555H 90H

Manufac-

turer ID3,9 X00 BFH

Device ID3,9 X01 Data

Read Block

Protection

Status3

BAX0210

Data11

Read Irre-

versible

Block Lock

Status3

5FEH

Data12

Read Global

Lock Bit Sta-

tus3

9FFH

Data13

Software ID

Exit

/CFI Exit14

XXH F0H

Volatile Block Protection

Volatile Block

Protection

Mode Entry

555H AAH 2AAH 55H 555H E0H

Volatile Pro-

tection Bit

(VPB) Set/

Clear

XXH

A0H BAX15 Data16

VPB Status

Read3BAX

Data16

Volatile Block

Protection

Mode Exit

XXH 90H XXH 00H

Non-Volatile Block Protection

Non-Volatile

Block Protec-

tion Mode

Entry

555H AAH 2AAH 55H 555H C0H

Non-Volatile

Protect Bit

(NVPB)

Program

XXH A0H BAX15 00H

Non-Volatile

Protect Bits

(NVPB)

Erase17

XXH 80H 00H 30H

NVPB Status

Read3BAX15

Data16

Non-Volatile

Block Protec-

tion Mode Exit

XXH 90H XXH 00H

TABLE 5-2: SOFTWARE COMMAND SEQUENCE (CONTINUED) (SHEET 2 OF 3)

Command

Sequence

1st Bus

Cycle

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

7th Bus

Cycle

Addr1

Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2

Addr1

Data2

 2013 Microchip Technology Inc. Preliminary DS20005002D-page 19

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

Global Lock of NVPBs

Global Lock of

NVPBs Entry

555H AAH 2AAH 55H 555H 50H

Set Global

Lock Bit

XXH A0H XXH 00H

Global Lock

Bit Status

XXXH

Data13

Global Lock of

NVPBs Exit

XXH 90H XXH 00H

Password Commands

Password

Commands

Mode Entry

555H AAH 2AAH 55H 555H 60H

Password Pro-

gram18 XXH

A0H PWAXPWDX

Password

Read3PWAX

PWDX

Submit Pass-

word19 00H 25H 00H 03H 00H PWD001H PWD102H PWD203H PWD300H 29H

Password

Commands

Mode Exit

XXH 90H XXH 00H

Program and Settings Register (PSR)

PSR Entry 555H AAH 2AAH 55H 555H 40H

PSR Program XXH A0H XXXH Data

PSR Read3XXH Data

PSR Exit XXH 90H XXH 00H

CFI

CFI Query

Entry

55H 98H

Software ID

Exit/CFI Exit14 XXH F0H

Irreversible Block Lock

Irreversible

Block Lock20 555H AAH 2AAH 55H 555H 87H XXH 00H

1. Address format A10-A0(Hex). Addresses A11-A

21 can be VIL or VIH, but no other value, for the SST38VF6401B/6402B/

6403B/6404B command sequence.

2. DQ15-DQ8can be VIL or VIH, but no other value, for command sequence

3. All read commands are in Bold Italics.

4. Total number of cycles in this command sequence depends on the number of words to be written to the buffer.

Additional words are written by repeating Write Cycle 5. Address (WAX) values for Write Cycle 6 and later must have the

same A21-A4 values as WAXin Write Cycle 5.

WC = Word Count. The value of WC is the number of words to be written into the buffer, minus 1. Maximum WC value is 15

(i.e. F Hex)

5. Erase-Suspend and Erase-Resume commands are also available in Bypass Mode.

6. Once in SEC ID mode, the Word-Program, Write-Buffer Programming, and Bypass Word-Program features can be used to

program the SEC ID area.

7. Lock-out Status is read with A7-A0= FFH. Unlocked: DQ3= 1 / Locked: DQ3= 0. Lock status can also be checked by reading

Bit ‘0’ in the PSR.

8. The device does not remain in Software Product ID Mode if powered down.

9. With AMS-A1=0; Microchip Manufacturer ID = 00BFH, is read with A0=0,

SST38VF6401B/6402B/6403B/6404B Device IDs are read with the results shown in Table 4-3 on page 13.

10. BAX02:A

MS-A15 = Block Address; A14-A8= xxxxxx; A7-A0=02

TABLE 5-2: SOFTWARE COMMAND SEQUENCE (CONTINUED) (SHEET 3 OF 3)

Command

Sequence

1st Bus

Cycle

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

7th Bus

Cycle

Addr1

Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2

Addr1

Data2

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

DS20005002D-page 20 Preliminary  2013 Microchip Technology Inc.

Note: Table 5-2 uses the following abbreviations:

X = Don’t care (VIL or VIH, but no other value.

BAX= Block Address; uses AMS-A15 address lines

WA = Word Address

WC = Word Count

PWAX= Password Address; PWAX=PWA

0,PWA

1,PWA

2or PWA3; A1 and A0 are used to select each 16-bit portion of the

password

PWDX= Password Data; PWDX= PSWD0, PWD1, PWD2,orPWD

AMS = Most significant Address

11. Data = 00H unprotected block; Data = 01H protected block.

12. DQ0= 0 means the Irreversible Block Lock command has been previously used. DQ0= 1 means the Irreversible Block Lock

command has not yet been used.

13. DQ0= 0 means that the Global Lock Bit is locked. DQ0= 1 means that the Global Lock Bit is unlocked.

14. Both Software ID Exit operations are equivalent.

15. For Non-Uniform Boot Block devices (i.e. 8 KWord size), in the boot area, use BAX= Block Address.

16. DQ0= 0 means protected; DQ0= 1 means unprotected

17. Erases all NVPBs to ‘1’ (unprotected)

18. Entire two-bus cycle sequence must be entered for each portion of the password.

19. Entire password sequence required for validation. The word order doesn’t matter as long as the Address and Data pair

match.

20. Global Lock Bit must be ‘1’ before executing this command.

TABLE 5-3: PROTECTION PRIORITY FOR MAIN ARRAY

NVPB1

1. X = protect or unprotect

VPB1Protection State of Block

protect X protected

X protect protected

unprotect unprotect unprotected

TABLE 5-4: CFI QUERY IDENTIFICATION STRING1 FOR SST38VF6401B/6402B/6403B/6404B

1. Refer to CFI publication 100 for more details.

Address Data Description

10H 0051H Query Unique ASCII string “QRY”

11H 0052H

12H 0059H

13H 0002H Primary OEM command set

14H 0000H

15H 0040H Address for Primary Extended Table

16H 0000H

17H 0000H Alternate OEM command set (00H = none exists)

18H 0000H

19H 0000H Address for Alternate OEM Extended Table (00H = none exits)

1AH 0000H

 2013 Microchip Technology Inc. Preliminary DS20005002D-page 21

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

TABLE 5-5: SYSTEM INTERFACE INFORMATION FOR SST38VF6401B/6402B/6403B/6404B

Address Data Description

1BH 0027H VDD Min (Program/Erase)

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1CH 0036H VDD Max (Program/Erase)

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1DH 0000H VPP min. (00H = no VPP pin)

1EH 0000H VPP max. (00H = no VPP pin)

1FH 0003H Typical time out for Word-Program 2N μs (23 = 8 μs)

20H 0003H Typical time out for min. size buffer program 2N μs (00H = not supported)

21H 0004H Typical time out for individual Block-Erase 2N ms (24 = 16 ms)

22H 0005H Typical time out for Chip-Erase 2N ms (25 = 32 ms)

23H 0001H Maximum time out for Word-Program 2N times typical (21 x 23 = 16 μs)

24H 0003H Maximum time out for buffer program 2N times typical

25H 0001H Maximum time out for individual Block-Erase 2N times typical (21 x 24 = 32 ms)

26H 0001H Maximum time out for Chip-Erase 2N times typical (21 x 25 = 64 ms)

TABLE 5-6: DEVICE GEOMETRY INFORMATION FOR SST38VF6401B/6402B/6403B/6404B

Address Data Description

27H 0017H Device size = 2N Bytes (17H = 23; 223 = 8 MByte)

28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface

29H 0000H

2AH 0005H Maximum number of bytes in multi-byte write = 2N (00H = not supported)

2BH 0000H

2CH 000xH Number of Erase Block regions in the device (01H = uniform boot device, 02H = non-uniform boot

device.

2DH 00xxH Erase Block Region 1 Information

007FH, 0000H, 0000H, 0001H, for SST38VF6401B/6402B

0007H, 0000H, 0020H, 0000H for SST38VF6403B/6404B

2EH 000xH

2FH 00x0H

30H 000xH

31H Erase Block Region 2 Information

0000H, 0000H, 0000H, 0000H, for SST38VF6401B/6402B

007EH, 0000H, 0000H, 0001H for SST38VF6403B/6404B

32H

33H

34H

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

DS20005002D-page 22 Preliminary  2013 Microchip Technology Inc.

TABLE 5-7: PRIMARY VENDOR-SPECIFIC EXTENDED INFORMATION FOR SST38VF6401B/

6402B/6403B/6404B

Address Data Description

40H 0050H Query-unique ASCII string “PRI”

41H 0052H

42H 0049H

43H FFFFH Reserved

44H FFFFH Reserved

45H 0000H Reserved

46H 0002H Erase Suspend

0 = Not supported

1 = Only read during Erase Suspend, 2 = Read and Program during Erase Suspend.

47H 0001H Individual Block Protection

0 = Not supported

1 = Supported

48H 0000H Reserved

49H 0008H Protection

0008H = Advanced

4AH 0000H Simultaneous Operation

00 = Not supported

4BH 0000H Burst Mode

00 = Not supported

4CH 0002H Page Mode

00 = Not supported

02 = 8 Word page.

4DH 0000H Acceleration Supply Minimum

00 = Not supported

4EH 0000H Acceleration Supply Maximum

00 = Not supported

4FH 00XXH Top / Bottom Boot Block

02H = 8 KWord Bottom Boot

03H = 8 KWord Top Boot

04H = Uniform (32 KWord) Bottom Boot

05H = Uniform (32 KWord) Top Boot

50H 0000H Program Suspend

00H = Not Supported

01H = Supported

 2013 Microchip Technology Inc. Preliminary DS20005002D-page 23

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maxi-

mum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and func-

tional operation of the device at these conditions or conditions greater than those defined in the operational

sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may

affect device reliability.)

Temperature Under Bias ................................................. -55°C to +125°C

Storage Temperature .................................................... -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential ................................-0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential ......................-2.0V to VDD+2.0V

Voltage on A9Pin to Ground Potential .........................................-0.5V to 12.5V

Voltage on RST# Pin to Ground Potential ......................................-0.5V to 12.5V

Voltage on WP# Pin to Ground Potential .......................................-0.5V to 12.5V

Package Power Dissipation Capability (TA= 25°C) ...................................... 1.0W

Surface Mount Solder Reflow Temperature ...............................260°C for 10 seconds

Output Short Circuit Current1..................................................... 50mA

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

TABLE 5-8: OPERATING RANGE

Range Ambient Temp VDD

Commercial 0°C to +70°C 2.7-3.6V

Industrial -40°C to +85°C 2.7-3.6V

TABLE 5-9: AC CONDITIONS OF TEST1

1. See Figures 6-17 and 6-18

Input Rise/Fall Time Output Load

5ns CL = 30 pF

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

DS20005002D-page 24 Preliminary  2013 Microchip Technology Inc.

5.1 Power-Up Specifications

All functionalities and DC specifications are specified

for a VDD ramp rate faster than 1V per 100 ms (0V to

3V in less than 300 ms). If the VDD ramp rate is slower

than 1V per 100 ms, a hardware reset is required. The

recommended VDD power-up to RESET# high time

should be greater than 100 μs to ensure a proper reset.

See Table 5-10and Figure 5-1 for more information.

FIGURE 5-1: POWER-UP DIAGRAM

TABLE 5-10: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 μs

TPU-WRITE1Power-up to Erase/Program Operation 100 μs

25002 F37.0

VDD

RESET#

CE#

TPU-READ 100µs

VDD min

VIH

TRHR 5 0ns

 2013 Microchip Technology Inc. Preliminary DS20005002D-page 25

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

5.2 DC Characteristics

TABLE 5-11: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V1

1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C

(room temperature), and VDD = 3V. Not 100% tested.

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD Power Supply Current Address input=VILT/VIHT2, VDD=VDD Max

2. See Figure 6-22

3. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Typical VDD is 3V.

30 mA CE#=VIL, OE#=WE#=VIH at f= 5 MHz

Intra-Page Read @5 MHz

2.5 mA CE#=VIL, OE#=WE#=VIH

Intra-Page Read @40 MHz

20 mA CE#=VIL, OE#=WE#=VIH

Program and Erase 35 mA CE#=WE#=VIL, OE#=VIH

Program-Write-Buffer-

to-Flash

50 mA CE#=WE#=VIL, OE#=VIH

ISB Standby VDD Current 40 μA CE#=VIHC, VDD=VDD Max

IALP Auto Low Power 40 μA CE#=VILC, VDD=VDD Max

All inputs=VSS or VDD, WE#=VIHC

ILI Input Leakage Current 1 μAV

IN=GND to VDD, VDD=VDD Max

ILIW Input Leakage Current

on WP# pin and RST#

10 μA WP#=GND to VDD or RST#=GND to

VDD

ILO Output Leakage Current 10 μAV

OUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max

VIH Input High Voltage 0.7VDD VV

DD=VDD Max

VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max

VOL Output Low Voltage 0.2 V IOL=100 μA, VDD=VDD Min

VOH Output High Voltage VDD-0.2 V IOH=-100 μA, VDD=VDD Min

TABLE 5-12: CAPACITANCE (TA= 25°C, F=1 MHZ, OTHER PINS OPEN)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance VI/O = 0V 12 pF

CIN1Input Capacitance VIN = 0V 6 pF

TABLE 5-13: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

NEND1,2

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

2. NEND endurance rating is qualified as 100,000 cycles minimum per block.

Endurance 100,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

DS20005002D-page 26 Preliminary  2013 Microchip Technology Inc.

6.0 AC CHARACTERISTICS

TABLE 6-1: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V

Symbol Parameter Min Max Units

TRC Read Cycle Time 70 ns

TCE Chip Enable Access Time 70 ns

TAA Address Access Time 70 ns

TPACC Page Access Time 25 ns

TOE Output Enable Access Time 25 ns

TCLZ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

CE# Low to Active Output 0 ns

TOLZ1OE# Low to Active Output 0 ns

TCHZ1CE# High to High-Z Output 20 ns

TOHZ1OE# High to High-Z Output 20 ns

TOH1Output Hold from Address Change 0 ns

TRP1RST# Pulse Width 500 ns

TRHR1RST# High before Read 50 ns

TRYE1,2

2. This parameter applies to Block-Erase and Program operations.

This parameter does not apply to Chip-Erase operations.

RST# Pin Low to Read Mode 20 μs

TRY1RST# Pin Low to Read Mode – not during Program

or Erase algorithms.

500 ns

TRPD1RST# Input Low to Standby mode 20 μs

TRB1RY / BY# Output high to CE# / OE# pin Low 0 ns

TPWD Delay for each password check 1 μs

 2013 Microchip Technology Inc. Preliminary DS20005002D-page 27

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

FIGURE 6-1: READ CYCLE TIMING DIAGRAM

TABLE 6-2: PROGRAM/ERASE CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

TBP Word-Program Time 10 μs

TWBP1Program Buffer-to-Flash Time 40 μs

TAS Address Setup Time 0 ns

TAH Address Hold Time 30 ns

TCS WE# and CE# Setup Time 0 ns

TCH WE# and CE# Hold Time 0 ns

TOES OE# High Setup Time 0 ns

TOEH OE# High Hold Time 10 ns

TCP CE# Pulse Width 40 ns

TWP WE# Pulse Width 40 ns

TWPH2WE# Pulse Width High 30 ns

TCPH2CE# Pulse Width High 30 ns

TDS Data Setup Time 30 ns

TCEPH CE# Pulse Width High During Toggle Bit Polling 20 ns

TOEPH OE# Pulse Width High During Toggle bit Polling 20 ns

TDH2Data Hold Time 0 ns

TIDA2Software ID, Volatile Protect, Non-Volatile Protect, Global Lock

Bit, Password mode, Lock Bit, Bypass Entry, and Exit Times

150 ns

TBE Block-Erase 25 ms

TSCE Chip-Erase 50 ms

TBUSY2CE# High or WE# High to RY / BY# Low 90 ns

1. Effective programming time is 2.5 µs per word if 16-words are programmed during this operation.

2. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

25002 F03.1

ADDRESS AMS-0

DQ15-0

WE#

OE#

CE#

DATA VALIDDATA VALID

RY/BY#

HIGH-

VIH

HIGH-

TCH

TOH

TOL

TCL TOH

TOE

TCE

TRC TAA

TRB

Note: AMS = Most significant address

AMS = A21 for SST38VF6401B/6402B/6403B/6404B

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

DS20005002D-page 28 Preliminary  2013 Microchip Technology Inc.

FIGURE 6-2: PAGE READ TIMING DIAGRAM

FIGURE 6-3: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

ADDRESS AMS-3

A2 - A0

DQ15-0

CE#

OE#

Ax Ax Ax

DATA VALID

Same Page

RY/BY#

DATA VALID

TAA TPA C C TPA C C TPA C C

25002 F24.3

DATA VALID

Note: AMS = Most significant address

AMS = A21 for SST38VF6401B/6402B/6403B/6404B

AX = either 000, 001,... 111

TDH

WPH

TDS

TWP

TAH

TAS

TCH

TCS

TBUSY

25002 F04.1

ADDRESS AMS-0

DQ15-0

CE#

SW0 SW1 SW2

555 2AA 555 ADDR

XXAA XX55 XXA0 DATA

INTERNAL PROGRAM OPERATION STARTS

WORD

(ADDR/DATA)

OE#

WE#

TBP

RY/BY#

Note: AMS = Most significant address

AMS = A21 for SST38VF6401B/6402B/6403B/6404B

WP# must be held in proper logic state (VIL or VIH) 1 μs prior to and 1 μs after the command sequence.

X can be VIL or VIH, but no other value.

 2013 Microchip Technology Inc. Preliminary DS20005002D-page 29

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

FIGURE 6-4: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

FIGURE 6-5: WE# CONTROLLED WRITE-BUFFER CYCLE TIMING DIAGRAM

TDH

TCPH

TDS

TCP

TAH

TAS

TCH

TCS

TBUSY

25002 F05.1

ADDRESS AMS-0

DQ15-0

WE#

SW0 SW1 SW2

555 2AA 555 ADDR

XXAA XX55 XXA0 DATA

INTERNAL PROGRAM OPERATION STARTS

WORD

(ADDR/DATA)

OE#

CE#

TBP

RY/BY#

Note: AMS = Most significant address

AMS = A21 for SST38VF6401B/6402B/6403B/6404B

WP# must be held in proper logic state (VIL or VIH) 1 μs prior to and 1 μs after the command sequence.

X can be VIL or VIH, but no other value.

25002 F34.2

ADDRESS AMS-0

DQ15-0

WE#

SW0 SW1 SW2 SW3 SW4 SWn

555 2AA WAX

BA BA

DATA D ATA nXX55XXAA XX25 WC

WAX

OE#

CE#

RY/BY#

FILL WRITE BUFFER WITH DATA

TWP

Note: BA= Block Address

WAx = Word Address

WC = Word Count

DATAn = nth Data

X can be VIL or VIH, but no other value.

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

DS20005002D-page 30 Preliminary  2013 Microchip Technology Inc.

FIGURE 6-6: WE# CONTROLLED PROGRAM-WRITE-BUFFER-TO-FLASH CYCLE TIMING

DIAGRAM

FIGURE 6-7: DATA# POLLING TIMING DIAGRAM

25002 F35.1

ADDRESS AMS-0

DQ15-0

WE#

29H

OE#

CE#

TBusy

RY/BY#

TDH

TAS

TWBP

TWP

Note: BA= Block Address

25002 F06.1

ADDRESS AMS-0

DQ7DATA D ATA # DATA # D ATA

WE#

OE#

CE#

TOEH

TOE

TCE

TOES

Note: AMS = Most significant address

AMS = A21 for SST38VF6401B/6402B/6403B/6404B

 2013 Microchip Technology Inc. Preliminary DS20005002D-page 31

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

FIGURE 6-8: TOGGLE BITS TIMING DIAGRAM

FIGURE 6-9: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM

25002 F07.0

ADDRESS AMS-0

DQ6and DQ2

WE#

OE#

CE#

TOE

TOEH

TCE

TOES

TWO READ CYCLES

WITH SAME OUTPUTS

TCEPH

TOEPH

Note: AMS = Most significant address

AMS = A21 for SST38VF6401B/6402B/6403B/6404B

25002 F08.1

ADDRESS AMS-0

DQ15-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

555 2AA 2AA555 555

XX55 XX10XX55XXAA XX80 XXAA

555

OE#

CE#

RY/BY#

SIX-BYTE CODE FOR CHIP-ERASE

SCE

BUSY

Note: This device also supports CE# controlled Chip-Erase operation The WE# and CE# signals are

interchangeable as long as minimum timings are met. (See Table 6-2)

AMS = Most significant address

AMS = A21 for SST38VF6401B/6402B/6403B/6404B

WP# must be held in proper logic state (VIL or VIH) 1 μs prior to and 1 μs after the command sequence.

X can be VIL or VIH, but no other value.

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

DS20005002D-page 32 Preliminary  2013 Microchip Technology Inc.

FIGURE 6-10: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM

FIGURE 6-11: SOFTWARE ID ENTRY AND READ

25002 F09.1

ADDRESS AMS-0

DQ15-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

555 2AA 2AA555 555

XX55 XX30XX55XXAA XX80 XXAA

OE#

CE#

Busy

RY/BY#

SIX-BYTE CODE FOR BLOCK-ERASE

Note: This device also supports CE# controlled Block-Erase operation The WE# and CE# signals are inter-

changeable as long as minimum timings are met. (See Table 6-2)

BAX = Block Address

AMS = Most significant address

AMS = A21 for SST38VF6401B/6402B/6403B/6404B

WP# must be held in proper logic state (VIL or VIH) 1 μs prior to and 1 μs after the command sequence.

X can be VIL or VIH, but no other value.

25002 F11.0

ADDRESS AMS-0

TIDA

DQ15-0

WE#

SW0 SW1 SW2

555 2AA 555 0000 0001

OE#

CE#

Three-Byte Sequence for Software ID Entry

TWP

TWPH TAA

00BF

Device ID

XX55XXAA XX90

Note: Device ID = 536B for SST38VF6401B, 536A for SST38VF6402B, 536D for SST38VF6403B, 536C for

SST38VF6404B

AMS = Most significant address

AMS = A21 for SST38VF6401B/6402B/6403B/6404B

WP# must be held in proper logic state (VIL or VIH) 1 μs prior to and 1 μs after the command sequence.

X can be VIL or VIH, but no other value.

 2013 Microchip Technology Inc. Preliminary DS20005002D-page 33

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

FIGURE 6-12: CFI QUERY ENTRY AND READ

FIGURE 6-13: SOFTWARE ID EXIT/CFI EXIT

25002 F12.2

ADDRESS AMS-0

TIDA

DQ15-0

WE#

55H

OE#

CE#

TWP

TAA

98H

Note: WP# must be held in proper logic state (VIL or VIH) 1 μs prior to and 1 μs after the command sequence.

AMS = Most significant address

AMS = A21 for SST38VF6401B/6402B/6403B/6404B

X can be VIL or VIH, but no other value.

25002 F13.1

ADDRESS AMS-0

DQ15-0

TIDA

TWP

TWHP

WE#

SW0

ONE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

OE#

CE#

XXF0

Note: WP# must be held in proper logic state (VIL or VIH) 1 μs prior to and 1 μs after the command sequence.

AMS = Most significant address

AMS = A21 for SST38VF6401B/6402B/6403B/6404B

X can be VIL or VIH, but no other value.

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

DS20005002D-page 34 Preliminary  2013 Microchip Technology Inc.

FIGURE 6-14: SEC ID ENTRY

FIGURE 6-15: RST# TIMING DIAGRAM (WHEN NO INTERNAL OPERATION IS IN PROGRESS)

FIGURE 6-16: RST# TIMING DIAGRAM (DURING PROGRAM OR ERASE OPERATION)

25002 F14.1

ADDRESS AMS-0

TIDA

DQ15-0

WE#

SW0 SW1 SW2

555 2AA 555

OE#

CE#

THREE-BYTE SEQUENCE FOR

SEC ID ENTRY

TWP

TWPH TAA

XX55XXAA XX88

Note: AMS = Most significant address

AMS = A21 for SST38VF6401B/6402B/6403B/6404B

WP# must be held in proper logic state (VIL or VIH) 1 μs prior to and 1 μs after the command sequence.

X can be VIL or VIH, but no other value.

25002 F15.2

RST#

CE#/OE#

TRP

TRHR

TRY

RY/BY#

25002 F16.2

RST#

CE#/OE#

TRP

TRYE

RY/BY#

TRB

 2013 Microchip Technology Inc. Preliminary DS20005002D-page 35

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

FIGURE 6-17: AC INPUT/OUTPUT REFERENCE WAVEFORMS

FIGURE 6-18: A TEST LOAD EXAMPLE

25002 F17.0

REFERENCE POINTS OUTPUTINPUT VIT

VIHT

VILT

VOT

AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference

points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10%  90%) are <5 ns.

Note: VIT - VINPUT Test

VOT - VOUTPUT Test

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

25002 F18.1

TO TESTER

TO DUT

VDD

25KΩ

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

DS20005002D-page 36 Preliminary  2013 Microchip Technology Inc.

FIGURE 6-19: WORD-PROGRAM ALGORITHM

25002 F19.1

Start

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XXA0H

Address: 555H

Load

Word Address

Word Data

Wait for end of

Program

Complete

Note: X can be VIL or VIH, but no other value.

 2013 Microchip Technology Inc. Preliminary DS20005002D-page 37

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

FIGURE 6-20: WRITE-BUFFER PROGRAMMING

25002 F25.2

Start

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX25H

Address: BA

Wait for

end of Program

Program

Complete

Load data: WC

Address: BA

Load data: Data

Address: WA

Program Buffer

to Flash

Load data: XX29H

Address: BA

Is Data

Load

complete

Ye s

Keep writing

to buffer

Note: BA= Block Address

WC = Word Count

WA = Address of word to program

All subsequent Address values (WAX) in Write Cycle 6 and later must have the same A21-A4 as WAX in Write

Cycle 5.

X can be VIL or VIH, but no other value

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

DS20005002D-page 38 Preliminary  2013 Microchip Technology Inc.

FIGURE 6-21: WAIT OPTIONS

25002 F20.1

Wait TBP,

TWBP,T

SCE,

or TBE

Program/Erase

Initiated

Internal Timer Toggle Bit

Ye s

Program/Erase

Completed

Does DQ6

match

Read same

word

Data# Polling

Program/Erase

Completed

Program/Erase

Completed

Read word

Is DQ7=

true data

Read DQ7

Program/Erase

Initiated

Program/Erase

Initiated

Ye s

RY/BY#

Program/Erase

Completed

RY/BY# = 1

Read RY/BY#

Program/Erase

Initiated

Note: For a Program Buffer-to-Flash Operation, the valid DQ7 is from the last word loaded in the buffer using the Write-

to-Program Buffer command.

 2013 Microchip Technology Inc. Preliminary DS20005002D-page 39

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

FIGURE 6-22: CFI/SEC ID/SOFTWARE ID ENTRY COMMAND FLOWCHARTS

25002 F21.0

Load data: XXAAH

Address: 555H

Soft are Pr oduct ID Entry

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX90H

Address: 555H

Wait TIDA

Read Software ID

CFI Query Entry

Command Sequence

Load data: XX98H

Address: 555H

Wait TIDA

Read CFI data

Load data: XXAAH

Address: 555H

Sec ID Entry

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX88H

Address: 555H

Wait TIDA

Read Sec ID

Note: X can be VIL or VIH, but no other value.

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

DS20005002D-page 40 Preliminary  2013 Microchip Technology Inc.

FIGURE 6-23: SOFTWARE ID/CFI/SEC ID EXIT COMMAND FLOWCHARTS

25002 F26.2

SEC ID Exit

Command Sequence

CFI Exit

Command Sequence

Load data: XXF0H

Address: XXH

Wait TIDA

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX90H

Address: 555H

Load data: XX00H

Address: XXXH

Wait TIDA

Return to normal

operation

Return to normal

operation

Note: X can be VIL or VIH, but no other value.

 2013 Microchip Technology Inc. Preliminary DS20005002D-page 41

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

FIGURE 6-24: ERASE COMMAND SEQUENCE

25002 F23.0

Load data: XXAAH

Address: 555H

Chip-Erase

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX10H

Address: 555H

Load data: XXAAH

Address: 555H

Wait TSCE

Chip erased

to FFFFH

Load data: XXAAH

Address: 555H

Block-Erase

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX30H

Address: BAX

Load data: XXAAH

Address: 555H

Wait TBE

Block erased

to FFFFH

Note: X can be VIL or VIH, but no other value.

BA= Block Address

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

DS20005002D-page 42 Preliminary  2013 Microchip Technology Inc.

FIGURE 6-25: ERASE SUSPEND/RESUME

25002 F27.0

Start

Erase Operation

Load data: XXB0H

Address: XXXH

Wait Time (20

s max

)

Erase Suspend

Active

Execute valid

operations while in

Erase Suspend mode

Load data: XX30H

Address: XXXH

Resume

Erase Operation

Note: X can be VIL or VIH, but no other value.

 2013 Microchip Technology Inc. Preliminary DS20005002D-page 43

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

FIGURE 6-26: VOLATILE BLOCK PROTECTION

25003 F28.3

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XXE0H

Address: 555H

Wait T

IDA

Load data: XXA0H

Address: 555H

Load data: Data

Address: BA

Load data: XX90H

Address: XXXH

Load data: XX00H

Address: XXXH

Read data: Data

Address: BA

More Blocks

to protect/unprotect

or Read status

Ye s

Read Protect Status

Protect / Unprotect

Note: Data = 00H (unprotect);

Data = 01H (protect).

BA = Block Address

X can be VIL or VIH, but no other value.

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

DS20005002D-page 44 Preliminary  2013 Microchip Technology Inc.

FIGURE 6-27: NON-VOLATILE BLOCK PROTECT MODE

Program

(Protect Block)

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XXC0H

Address: 555H

Wait TIDA

Load data: XX80H

Address: XXH

Read data: Data

Address: BA

Load data: XXA0H

Address: XXH

Load data: XX30H

Address: 00H

Wait for end of

Program, Erase,

or Read

Load data: XX90H

Address: XXH

Load data: XX00H

Address: XXH

Load data: XX00H

Address: BA

More to

Program,Erase,

or Read

Erase

Read Protect

Status

Ye s

25002 F30.1

Program, Erase or Read

Note: Data = 00H (unprotect);

Data = 01H (protect).

X can be VIL or VIH, but no other value.

Programming NVPB requires 2x TBP

, which results in a 20μs maximum programming time

 2013 Microchip Technology Inc. Preliminary DS20005002D-page 45

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

FIGURE 6-28: GLOBAL LOCK OF NVPBS

Set

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX50H

Address: 555H

Wait TIDA

Read data:

Status Data

Address: XXXH

Load data: XXA0H

Address: XXH

Load data: XX90H

Address: XXH

Load data: XX00H

Address: XXH

Load data: XX00H

Address: XXH

Read Status

25002 F31.0

Note: Status Data: DQ0 = 0 (locked); DQ0 = 1 (unlocked).

X can be VIL or VIH, but no other value.

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

DS20005002D-page 46 Preliminary  2013 Microchip Technology Inc.

FIGURE 6-29: PASSWORD OPERATIONS (PROGRAM, READ, SUBMIT)

Program

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX60H

Address: 555H

Wait TIDA

Read data:

Status Data

Address: PWAX

Load data: XXA0H

Address: XXH

Load data: XX90H

Address: XXH

Load data: XX00H

Address: XXH

Load data: PWDX

Address: PWAX

Read

25002 F32.0

More to

Program or

Read

Ye s

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX60H

Address: 555H

Load data: XX25H

Address: 00H

Load data: XX03H

Address: 00H

Load data: PWD0

Address: PWA0

Load data: XX29H

Address: 00H

Wait TPWD

Wait TIDA

Load data: PWD1

Address: PWA1

Load data: PWD2

Address: PWA2

Load data: PWD3

Address: PWA3

Load data: XX90H

Address: XXH

Load data: XX00H

Address: XXH

Exit Password

Command Mode

Submit Pass ordProgram / Read Pass ord

Note: The PWDX and PWAX data and address pairs can be submitted in any order.

PWDX = PWD0, PWD1, PWD2, PWD3

PWAX = PWA0, PWA1,PWA2, PWA3

X can be VIL or VIH, but no other value.

 2013 Microchip Technology Inc. Preliminary DS20005002D-page 47

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

FIGURE 6-30: IRREVERSIBLE BLOCK LOCK IN MAIN ARRAY

Load data: AAH

Address: 555H

Load data: 55H

Address: 2AAH

Load data: 87H

Address: 555H

Load data: 00H

Address: XXH

25002 F33.0

Note: Global Lock Bit must be ‘1’ before executing this command.

X can be VIL or VIH, but no other value.

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

DS20005002D-page 48 Preliminary  2013 Microchip Technology Inc.

7.0 PACKAGING DIAGRAMS

 2013 Microchip Technology Inc. Preliminary DS20005002D-page 49

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

DS20005002D-page 50 Preliminary  2013 Microchip Technology Inc.

 2013 Microchip Technology Inc. Preliminary DS20005002D-page 51

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

DS20005002D-page 52 Preliminary  2013 Microchip Technology Inc.

TABLE 7-1: REVISION HISTORY

Number Description Date

A•Initial release Aug 2011

B•Applied new document format

•Revised Table 5-7 and Table 6-2

•Updated “Packaging Diagrams” on page 48

•Migrated to new package drawing style

Jan 2013

C•Updated part markings in Table 8-1 on page 54

•Revised part numbers in “Product Identification System” on page 54

Jul 2013

D•Corrected a part number in “Product Identification System” on page 54 Nov 2013

 2013 Microchip Technology Inc. Preliminary DS20005002D-page 53

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

THE MICROCHIP WEB SITE

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following informa-

tion:

•Product Support – Data sheets and errata, appli-

cation notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

•General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

•Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of Micro-

chip sales offices, distributors and factory repre-

sentatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a spec-

ified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com. Under “Support”, click on “Cus-

tomer Change Notification” and follow the registration

instructions.

CUSTOMER SUPPORT

Users of Microchip products can receive assistanc

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

Customers should contact their distributor, representa

tive or Field Application Engineer (FAE) for support

Local sales offices are also available to help custom

ers. A listing of sales offices and locations is included i

the back of this document.

Technical support is available through the web sit

at: http://microchip.com/support

SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B

DS20005002D-page 54 Preliminary  2013 Microchip Technology Inc.

8.0 PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

TABLE 8-1: PART MARKING

Ordering Number Marking On Part

SST38VF6401B-70I/TV 38VF6401B-I/TV

SST38VF6401B-70I/CD 38VF6401B-I/CD

SST38VF6402B-70I/TV 38VF6402B-I/TV

SST38VF6402B-70I/CD 38VF6402B-I/CD

SST38VF6403B-70I/TV 38VF6403B-I/TV

SST38VF6403B-70I/CD 38VF6403B-I/CD

SST38VF6404B-70I/TV 38VF6404B-I/TV

SST38VF6404B-70I/CD 38VF6404B-I/CD

PART NO. XX

XXX

PackageEndurance/

Device

Device: SST38VF6401B = 64 Mbit, 2.7-3.6V, Advanced Multi-

Purpose Flash Plus

Bottom Boot-Block Uniform (32 KWord)

SST38VF6402B = 64 Mbit, 2.7-3.6V, Advanced Multi-

Purpose Flash Plus

Top Boot-Block Uniform (32 KWord)

SST38VF6403B = 64 Mbit, 2.7-3.6V, Advanced Multi-

Purpose Flash Plus

Bottom Boot-Block Non- Uniform

(8 KWord)

SST38VF6404B = 64 Mbit, 2.7-3.6V, Advanced Multi-

Purpose Flash Plus

Top Boot-Block Non- Uniform

(8 KWord)

Tape and

Reel Flag:

T = Tape and Reel

Read Access

Speed:

70 = 70 ns

Temperature: I = -40°C to +85°C

Package: TV = TSOP (12mm x 20mm), 48-lead

CD = TFBGA (6mm x 8mm), 48-lead

Valid Combinations:

SST38VF6401B-70I/TV

SST38VF6401BT-70I/TV

SST38VF6401B-70I/CD

SST38VF6401BT-70I/CD

SST38VF6402B-70I/TV

SST38VF6402BT-70I/TV

SST38VF6402B-70I/CD

SST38VF6402BT-70I/CD

SST38VF6403B-70I/TV

SST38VF6403BT-70I/TV

SST38VF6403B-70I/CD

SST38VF6403BT-70I/CD

SST38VF6404B-70I/TV

SST38VF6404BT-70I/TV

SST38VF6404B-70I/CD

SST38VF6404BT-70I/CD

XXX

Read

Temperature

Tape/Reel

Indicator

Access

Speed

 2013 Microchip Technology Inc. Preliminary DS20005002D-page 55

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash

and UNI/O are registered trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MTP, SEEVAL and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of

Microchip Technology Inc. in other countries.

Analog-for-the-Digital Age, Application Maestro, BodyCom,

chipKIT, chipKIT logo, CodeGuard, dsPICDEM,

dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial

Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB

Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,

Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA

and Z-Scale are trademarks of Microchip Technology

Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

GestIC and ULPP are registered trademarks of Microchip

Technology Germany II GmbH & Co. & KG, a subsidiary of

Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN:978-1-62077-613-1

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

 2013 Microchip Technology Inc. Preliminary DS20005002D-page 56

AMERICAS

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Web Address:

www.microchip.com

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Cleveland

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

ASIA/PACIFIC

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

China - Beijing

Tel: 86-10-8569-7000

Fax: 86-10-8528-2104

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

China - Chongqing

Tel: 86-23-8980-9588

Fax: 86-23-8980-9500

China - Hangzhou

Tel: 86-571-2819-3187

Fax: 86-571-2819-3189

China - Hong Kong SAR

Tel: 852-2943-5100

Fax: 852-2401-3431

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

China - Shenzhen

Tel: 86-755-8864-2200

Fax: 86-755-8203-1760

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

ASIA/PACIFIC

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

India - Pune

Tel: 91-20-3019-1500

Japan - Osaka

Tel: 81-6-6152-7160

Fax: 81-6-6152-9310

Japan - Tokyo

Tel: 81-3-6880- 3770

Fax: 81-3-6880-3771

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Korea - Seoul

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Taiwan - Hsin Chu

Tel: 886-3-5778-366

Fax: 886-3-5770-955

Taiwan - Kaohsiung

Tel: 886-7-213-7828

Fax: 886-7-330-9305

Taiwan - Taipei

Tel: 886-2-2508-8600

Fax: 886-2-2508-0102

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

EUROPE

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

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