VNP35N07 "OMNIFET": FULLY AUTOPROTECTED POWER MOSFET TYPE VNP35N07 V clamp R DS(on) I lim 70 V 0.028 35 A LINEAR CURRENT LIMITATION THERMAL SHUT DOWN SHORT CIRCUIT PROTECTION INTEGRATED CLAMP LOW CURRENT DRAWN FROM INPUT PIN DIAGNOSTIC FEEDBACK THROUGH INPUT PIN ESD PROTECTION DIRECT ACCESS TO THE GATE OF THE POWER MOSFET (ANALOG DRIVING) COMPATIBLE WITH STANDARD POWER MOSFET STANDARD TO-220 PACKAGE ) s ( ct u d o let r P e o s b 3 1 2 TO-220 O ) DESCRIPTION The VNP35N07 is a monolithic device made using STMicroelectronics VIPower Technology, intended for replacement of standard power MOSFETS in DC to 50 KHz applications. Built-in thermal shut-down, linear current limi- s ( t c u d o tation and overvoltage clamp protect the chip in harsh enviroments. Fault feedback can be detected by monitoring the voltage at the input pin. r P e BLOCK DIAGRAM t e l o s b O March 2004 1/11 VNP35N07 ABSOLUTE MAXIMUM RATING Symbol Parameter Value Unit Internally Clamped V Input Voltage 18 V ID Drain Current Internally Limited A IR Reverse DC Output Current -50 A 2000 V V DS Drain-source Voltage (V in = 0) V in V esd Electrostatic Discharge (C= 100 pF, R=1.5 K) o Ptot Total Dissipation at T c = 25 C Tj 125 Operating Junction Temperature Tc Internally Limited Case Operating Temperature T stg -55 to 150 THERMAL DATA Thermal Resistance Junction-case Thermal Resistance Junction-ambient P e t e l o o t c u d o r Max Max C (s) Internally Limited Storage Temperature R thj-case R thj-amb W o 1 62.5 o o o C o C C/W C/W ELECTRICAL CHARACTERISTICS (Tcase = 25 C unless otherwise specified) OFF Symbol Parameter s b O Test Conditions V CLAMP Drain-source Clamp Voltage I D = 200 mA V CLTH Drain-source Clamp Threshold Voltage I D = 2 mA V INCL Input-Source Reverse Clamp Voltage I in = -1 mA I DSS Zero Input Voltage Drain Current (V in = 0) V DS = 13 V V DS = 25 V V in = 0 V in = 0 II SS Supply Current from Input Pin V DS = 0 V V in = 10 V ON () t e l o s b O Symbol V in = 0 t c u od r P e ) (s Parameter V in = 0 Min. Typ. Max. Unit 60 70 80 V 55 -1 Test Conditions Min. ID + I in = 1 mA 0.8 V IN(th) Input Threshold Voltage V DS = Vin R DS(on) Static Drain-source On Resistance V in = 10 V I D = 18 A V in = 5 V I D = 18 A V -0.3 V 50 200 A A 250 500 A Typ. Max. Unit 3 V 0.028 0.035 Max. Unit DYNAMIC Symbol g fs () C oss 2/11 Parameter Test Conditions Forward Transconductance V DS = 13 V I D = 18 A Output Capacitance V DS = 13 V f = 1 MHz V in = 0 Min. Typ. 20 25 980 S 1400 pF VNP35N07 ELECTRICAL CHARACTERISTICS (continued) SWITCHING () Symbol Parameter Test Conditions Min. Typ. Max. Unit t d(on) tr t d(off) tf Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time V DD = 28 V V gen = 10 V (see figure 3) I d = 18 A R gen = 10 100 350 650 200 200 600 1000 350 ns ns ns ns t d(on) tr t d(off) tf Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time V DD = 28 V V gen = 10 V (see figure 3) I d = 18 A R gen = 1000 500 2.7 10 4.3 800 4.2 16 6.5 ns s s s Turn-on Current Slope V DD = 28 V V in = 10 V Total Input Charge V DD = 12 V (di/dt) on Qi I D = 18 A R gen = 10 I D = 18 A V in = 10 V 100 SOURCE DRAIN DIODE Symbol V SD () Parameter t rr () Q rr () I RRM () Forward On Voltage I SD = 18 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 18 A di/dt = 100 A/s V DD = 30 V T j = 25 o C (see test circuit, figure 5) Parameter Drain Current Limit I lim t dlim () let T jsh () so T jrs () Ob r P e Step Response Current Limit t e l o bs ) s ( ct u d o Symbol V in = 0 Min. V in = 10 V V in = 5 V -O A/s nC u d o r P e Test Conditions PROTECTION ) s ( ct 60 Typ. Max. Unit 1.6 V 250 ns 1 C 8 A Test Conditions Min. Typ. Max. Unit V DS = 13 V V DS = 13 V 25 25 35 35 45 45 A A 35 70 60 140 s s V in = 10 V V in = 5 V Overtemperature Shutdown 150 o C Overtemperature Reset 135 o C I gf () Fault Sink Current V in = 10 V V in = 5 V E as () Single Pulse Avalanche Energy starting T j = 25 o C V DD = 20 V V in = 10 V R gen = 1 K L = 10 mH V DS = 13 V V DS = 13 V 50 20 2.5 mA mA J () Pulsed: Pulse duration = 300 s, duty cycle 1.5 % () Parameters guaranteed by design/characterization 3/11 VNP35N07 PROTECTION FEATURES During normal operation, the Input pin is electrically connected to the gate of the internal power MOSFET. The device then behaves like a standard power MOSFET and can be used as a switch from DC to 50 KHz. The only difference from the user's standpoint is that a small DC current (Iiss) flows into the Input pin in order to supply the internal circuitry. The device integrates: - OVERVOLTAGE CLAMP PROTECTION: internally set at 70V, along with the rugged avalanche characteristics of the Power MOSFET stage give this device unrivalled ruggedness and energy handling capability. This feature is mainly important when driving inductive loads. - LINEAR CURRENT LIMITER CIRCUIT: limits the drain current Id to Ilim whatever the Input pin voltage. When the current limiter is active, the device operates in the linear region, so power dissipation may exceed the capability of the heatsink. Both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the overtemperature threshold Tjsh. ) (s t c u d o r P e t e l o s b O 4/11 - OVERTEMPERATURE AND SHORT CIRCUIT PROTECTION: these are based on sensing the chip temperature and are not dependent on the input voltage. The location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. Overtemperature cutout occurs at minimum 150oC. The device is automatically restarted when the chip temperature falls below 135oC. ) s ( ct - STATUS FEEDBACK: In the case of an overtemperature fault condition, a Status Feedback is provided through the Input pin. The internal protection circuit disconnects the input from the gate and connects it instead to ground via an equivalent resistance of 100 . The failure can be detected by monitoring the voltage at the Input pin, which will be close to ground potential. Additional features of this device are ESD protection according to the Human Body model and the ability to be driven from a TTL Logic circuit (with a small increase in RDS(on)). u d o r P e s b O t e l o VNP35N07 Thermal Impedance Derating Curve ) s ( ct u d o r P e Output Characteristics Transconductance t e l o ) (s s b O t c u d o r P e t e l o bs Static Drain-Source On Resistance vs Input Voltage Static Drain-Source On Resistance O 5/11 VNP35N07 Input Charge vs Input Voltage Static Drain-Source On Resistance ) s ( ct u d o r P e Normalized Input Threshold Voltage vs Temperature Capacitance Variations t e l o ) (s s b O t c u d o r P e t e l o bs Normalized On Resistance vs Temperature O 6/11 Normalized On Resistance vs Temperature VNP35N07 Turn-on Current Slope Turn-on Current Slope ) s ( ct u d o r P e Turn-off Drain-Source Voltage Slope Turn-off Drain-Source Voltage Slope t e l o ) (s s b O t c u d o r P e t e l o bs Switching Time Resistive Load Switching Time Resistive Load O 7/11 VNP35N07 Switching Time Resistive Load Current Limit vs Junction Temperature ) s ( ct u d o r P e Step Response Current Limit Source Drain Diode Forward Characteristics t e l o ) (s t c u d o r P e t e l o s b O 8/11 s b O VNP35N07 Fig. 1: Unclamped Inductive Load Test Circuits Fig. 2: Unclamped Inductive Waveforms ) s ( ct Fig. 3: Switching Times Test Circuits For Resistive Load ) (s u d o r P e Fig. 4: Input Charge Test Circuit t e l o s b O t c u d o r P e t e l o bs Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times Fig. 6: Waveforms O 9/11 VNP35N07 TO-220 MECHANICAL DATA mm. DIM. MIN. 4.40 4.60 b 0.61 0.88 b1 1.15 1.70 c 0.49 0.70 D 15.25 15.75 E 10 e 2.40 e1 4.95 F 1.23 H1 6.20 J1 2.40 L 13 L1 3.50 ) (s t c u L30 P Q e t e ol od Pr Package Weight 10/11 MAX. A L20 s b O TYP ) s ( ct u d o 10.40 e t e ol s b O Pr 2.70 5.15 1.32 6.60 2.72 14 3.93 16.40 28.90 3.75 3.85 2.65 2.95 1.9Gr. (Typ.) VNP35N07 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics 2004 STMicroelectronics - Printed in ITALY- All Rights Reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 11/11