© 2010-2011 Microchip Technology Inc. DS22230D-page 1
MCP2003/4/3A/4A
Features
The MCP2003/2003A and MCP2004/2004A are
compliant with Local Interconnect Network (LIN)
Bus Specifications 1.3, 2.0 and 2.1 and are
compliant to SAE J2602
Support Baud Rates up to 20 Kbaud with
LIN-compatible output driver
43V load dump protected
Very low EMI meet s stri ng ent OEM requi rements
Very high ESD immuni ty:
- >20kV on VBB (IEC 61000-4-2)
- >14kV on LBUS (IEC 61000-4-2)
Very high immunity to RF disturbances meets
stringent OEM requirements
Wide supply voltage, 6.0V-27.0V continuous
Extended Temperature Range: -40 to +125°C
Interface to PIC® MCU EUSART and standard
USARTs
LIN bus pin:
- Internal pull-up resistor and diode
- Protected again st batt ery sh ort s
- Protected again st los s of groun d
- High current drive
Automatic thermal shutdown
Low-power mode:
- Receiver monitoring bus and transmitter off,
(A)
Description
This device provides a bidirectional, half-duplex
communication, physical interface to automotive and
industri al LIN systems to meet the LIN bus specification
Revision 2.1 and SAE J2602. The device is short-
circuit and over-temperature protected by internal
circuitry. The device has been specifically designed to
operate in the automotive operating environment and
will survive all specified transient conditions while
meeting all of the stringent quiescent current
requirements.
MCP200X family members:
8-pin PDIP, DFN and SOIC packages:
- MCP2003, LIN-c ompatible driv er , with WAKE
pins, wake up on falling edge of LBUS
- MCP2003A, LIN-compatible driver, with
WAKE pins, wake up on rising edge of LBUS
- MCP2004, LIN-compatible driver, with
FAULT/TXE pins, wake up on falling edge of
LBUS
- MCP2004A, LIN-compatible driver, with
FAULT/TXE pins, wake up on rising edge of
LBUS
Package Types
MCP2004/
2004A
PDIP, SOIC
FAULT/TXE
CS/WAKE
TXD
VBB
LBUS
1
2
3
4
8
7
6
5
VSS
VRENRXD
MCP2003/
2003A
PDIP, SOIC
WAKE
CS
TXD
VBB
LBUS
1
2
3
4
8
7
6
5
VSS
VRENRXD
MCP2003/
2003A
4x4 DFN*
WAKE
CS
TXD
VBB
LBUS
1
2
3
4
8
7
6
5VSS
VRENRXD
EP
9
MCP2004/
2004A
4x4 DFN*
FAULT/TXE
CS/WAKE
TXD
VBB
LBUS
1
2
3
4
8
7
6
5VSS
VRENRXD
EP
9
* Includes Exposed Thermal Pad (EP); see Table 1-1.
LIN J2602 Transceiver
MCP2003/4/3A/4A
DS22230D-page 2 © 2010-2011 Microchip Technology Inc.
MCP2003/2003A Block Diagram
MCP2004/2004A Block Diagram
Ratiometric
Reference
OC
Thermal
Protection
VREN
RXD
TXD
VBB
LBUS
VSS
~30 kΩ
CS
Wake-Up
Logic and
Power Control
Short Circuit
Protection
4.3V WAKE
Ratiometric
Reference
OC
Thermal
Protection
VREN
FAULT/TXE
RXD
TXD
VBB
LBUS
VSS
~30 kΩ
CS/WAKE
Wake-Up
Logic and
Power Control
Short Circuit
Protection
4.3V 4.3V
© 2010-2011 Microchip Technology Inc. DS22230D-page 3
MCP2003/4/3A/4A
1.0 DEVICE OVERVIEW
The MCP2003/4/3A/4A devices provide a physical
interface between a microcontroller and a LIN bus.
These de vices wi ll translate th e CMOS/TTL logic level s
to LIN logic level, and vice versa. It is intended for
automotive and industrial applications with serial bus
speeds up to 20 Kbaud.
LIN spec if ica tio n 2.1 requires that the transceiver of all
nodes in the syste m is conn ected via the LIN pin, ref er-
enced to ground and with a maximum external
termination resistance load of 510Ω from LIN bus to
battery supply. The 510Ω corres pon ds to 1 master an d
15 slave node s.
The VREN pin can be used to driv e t he l ogi c i npu t of an
external voltage regulator. This pin is high in all modes
except for Power-Down mode.
1.1 External Protection
1.1.1 REVERSE BATTERY PR OTECTION
An external reverse-battery-blocking diode should be
used to provide polarity protection (see Example 1-1).
1.1.2 TRANSIENT VOLTAGE
PROTECTION (LOAD DUMP)
An external 43V transient suppressor (TVS) diode,
between VBB and ground, with a 50Ω transient
protection resistor (RTP) in series with the battery
supply and the VBB pi n serve to p rotect the d evice from
power transients (see Example 1-1) and ESD events.
While this protection is optional, it is considered good
engineering practice.
1.2 Internal Protection
1.2.1 ESD PROTECTION
For component-level ESD ratings, please refer to the
maximum operation specifications.
1.2.2 GROUND LOSS PROTECTION
The LI N Bu s spe cifi cat ion s tates that th e LIN pin mu st
transition to the recessive state when ground is
disconnected. Therefore, a loss of ground effectively
forces the LIN line to a high-impedance level.
1.2.3 THERMAL PROTECTION
The thermal protection circuit monitors the die
temperature and is able to shut down the LIN
transmitter.
There are two causes for a thermal overload. A thermal
shut down can be triggered by either, or both, of the
following thermal overload conditions.
LIN bus out put overload
Increase in die temperature due to increase in
environment temperature
Driving the TXD and checking the RXD pin makes it
possib le to determine whether there is a bus co ntention
(Rx = low, Tx = high) or a thermal overload condition
(Rx = high, Tx = low). After a thermal overload event,
the device will automatically recover once the die
temperat ure has fallen below the recov ery temperature
threshold. See Figure 1-1.
FIGURE 1-1: THERMAL SHUTDOWN
STATE DIAGRAM
Operation
Mode
Transmitter
Shutdown
LIN bus
Shorted
to VBB
Temp < SHUTDOWNTEMP
MCP2003/4/3A/4A
DS22230D-page 4 © 2010-2011 Microchip Technology Inc.
1.3 Modes of Operation
For an overview of all operational modes, refer to
Table 1-1.
1.3.1 POWER-DOWN MODE
In Power-Down mode, everything is off except the
wake-up section. This is the lowest power mode. The
receiver is off, thus its output is open-drain.
On CS go ing to a h igh lev el or a fal li ng ed ge on WAKE
(MCP2003/MCP2003A only), the device will enter
Ready Mode as soon as internal voltage stabilizes.
Refer to the AC Spec tabl e. In additi on, LIN bu s activity
will c hange the de vice from po wer-dow n mode to read y
mode; MCP2003/4 wakes up on a falling edge of LIN
bus and M CP20 03/4A on a risi ng edge , followi ng a low
level lasting at least 20 µS of time. Refer to Figure 1-2
Figure 1-5 about remote wake up. If CS is held high
as the device transitions from Power-Down to Ready
mode, the device will transition to either Operation or
Transmitter Off mode, depending on TXD input, as
soon as internal voltages stabilize.
1.3.2 READY MODE
Upon entering the Ready mode, VREN is enabled and
the receiver detect circuit is powered up. The transmit-
ter rema ins disabled and th e device i s read y to rec eiv e
data but not to transmit.
Upon VBB supply pin power-on, the device will remain
in Ready mode as long as CS is low. When CS transi-
tions hi gh, the device wil l e ithe r en ter Operation mod e,
if TXD pin is held high, or the device will enter Trans-
mitter Off mode, if TXD pin is held low.
1.3.3 OPERATION MODE
In this mode, all internal modules are operational.
The device will go into the Power-Down mode on the
falling edge of CS. For the MCP2003/4 device, a
specific process should be followed to put all nodes into
Power-down mode. Refer to Section 1.6 “Enter
Power-Down Mode” and Figure 1-6. The device will
enter Transmitter Off mode in the event of a Fault
condition. These include: thermal overload, bus
contention and TXD timer expiration.
The MCP2004/2004A device can also enter
Transmitter Off mode if the FAULT/TXE pin is pulled
low. The VBB-LBUS pull-up resistor is connected only
in Operation mode.
1.3.4 TRANSMITTER OFF MODE
Transmitter Off mode is reached whenever the
transmi tter is disable d either du e to a Fault co ndition or
pulling the nFAULT/TXE pin low on the MCP2004/
2004A. The fault conditions include: thermal overload,
bus contention or TXD timer expiration.
The device will go into Power-Down mode on the falling
edge of CS, or r eturn to Opera tion m ode if all fa ult s ar e
resolved and the FAULT/TXE pin on the MCP2004/
2004A is high.
FIGURE 1-2: OPERATIONAL MODES STATE DIAGRAM – MCP2003
POR
VREN OFF
RX OFF
TX OFF
VBAT>5.5V
Ready
VREN ON
RX ON
TX OFF
TOFF
Mode
VREN ON
RX ON
TX OFF
Operation
Mode
VREN ON
RX ON
TX ON
POWER
DOWN
VREN OFF
RX OFF
TX OFF
CS=1 & TXD=0
CS=1 & TXD=1
CS=1 & TXD=1 & No Fault
Fault (thermal or timer)
CS=0
Falling edge on LIN
or CS=1
or falling edge on WAKE PIN
CS=0
© 2010-2011 Microchip Technology Inc. DS22230D-page 5
MCP2003/4/3A/4A
FIGURE 1-3: OPERATIONAL MODES STATE DIAGRAM – MCP2003A
FIGURE 1-4: OPERATIONAL MODES STATE DIAGRAM – MCP2004
POR
VREN OFF
RX OFF
TX OFF
VBAT>5.5V
Ready
VREN ON
RX OFF
TX OFF
TOFF
Mode
VREN ON
RX ON
TX OFF
Operation
Mode
VREN ON
RX ON
TX ON
POWER
DOWN
VREN OFF
RX OFF
TX OFF
CS=1 & TXD=0
CS=1 & TXD=1
CS=1 & TXD=1 & No Fault
Fault (thermal or timer)
CS=0
Rising edge on LIN
or CS=1
Or falling edge on WAKE PIN
CS=0
POR
VREN OFF
RX OFF
TX OFF
VBAT>5.5V
Ready
VREN ON
RX ON
TX OFF
TOFF
Mode
VREN ON
RX ON
TX OFF
Operation
Mode
VREN ON
RX ON
TX ON
POWER
DOWN
VREN OFF
RX OFF
TX OFF
CS=1 & (TXE=0 or TXD=0)
CS=1 & TXD=1 & TXE=1
CS=1 & TXD=1 &TXE=1 &
No Fault
Fault (thermal or timeout)
or FAULT/TXE=0
CS=0
Falling edge on LIN
or CS=1
CS=0
MCP2003/4/3A/4A
DS22230D-page 6 © 2010-2011 Microchip Technology Inc.
FIGURE 1-5: OPERATIONAL MODES STATE DIAGRAM – MCP2004A
TABLE 1-1: OVERVIEW OF OPERATIONAL MODES
State Transmitter Receiver Vren Operation Comments
POR OFF OFF OFF Check CS, if low then Ready;
If high tr ansitions to eith er TOFF o r Operation
mode, depending on TXD (2003/A), or TXD
and FAULT/TXE (2004/A).
VBB > VBB (min)
and Internal
Supply stable
Ready OFF ON ON If CS high level, then either Operation or
TXOFF mode. Bus Off state
Operation ON ON ON If CS low level, then Power-Down;
If FAU LT/TXE low level, then Transmitter Off
mode.
Normal Operation
mode
Power-Down OFF Activity
Detect OFF On CS high level, go to READY then either
Operation mode or TXOFF.
MCP2003/20 03A: Fa lli ng ed ge on WAKE wil l
put the device into READY mode.
MCP2003 /MCP2 004: fal ling ed ge on LIN bus
will put the device into READY mode.
MCP2003A/MCP2004A: rising edge on LIN
bus will put the device into READY mode.
Low Power mode
Transmitter Off OFF ON ON If CS low level, then Power-Down;
If FAULT/TXE and TXD high, then Operation
mode
FAULT/TXE only
available on
MCP2004/2004A
POR
VREN OFF
RX OFF
TX OFF
VBAT>5.5V
Ready
VREN ON
RX ON
TX OFF
TOFF
Mode
VREN ON
RX ON
TX OFF
Operation
Mode
VREN ON
RX ON
TX ON
POWER
DOWN
VREN OFF
RX OFF
TX OFF
CS=1 & (TXE=0 or TXD=0)
CS=1 & TXD=1 & TXE=1
CS=1 & TXD=1 &TXE=1 &
No Fault
Fault (thermal or timeout)
or FAULT/TXE=0
CS=0
Rising edge on LIN
or CS=1
CS=0
© 2010-2011 Microchip Technology Inc. DS22230D-page 7
MCP2003/4/3A/4A
1.4 Typical Applications
EXAMPLE 1-1: TYPICAL MCP2003/2003A APPLICATION
EXAMPLE 1-2: TYPICAL MCP2004/2004A APPLICATION
LIN Bus
43V
Vbb
Lbus
Vren
Txd
Rxd
Vss
Vdd
Txd
Rxd
+12
1.0
µ
F
CS
I/O
WAKE
50W
43V
1KW
+12
Maste r No de Only
+12
3.9KW
Wake-up
Voltage Reg
(See Note)
Note: For applications with current requirements of less than 20 mA, the connection to +12V can be
deleted, and voltage to the regulator supplied directly from the VREN pin.
4.7KW
optional resistor and transient suppressor
LIN Bus
43V
Vbb
Lbus
Vren
Txd
Rxd
Vss
Vdd
Txd
Rxd
1.0
µ
F
CS/WAKE
I/O
FAULT/TXE
I/O
50W
43V
1KW
+12
Master Node Only
+12
220 KW
Wake-up
V oltage Reg
100 pF
4.7KW
ZD1
+12
optional resistor and transient suppressor
MCP2003/4/3A/4A
DS22230D-page 8 © 2010-2011 Microchip Technology Inc.
EXAMPLE 1-3: TYPICAL LIN NETWORK CONFIGURATION
Master
µC
1kΩ
VBB
Slave 1
µC Slave 2
µC Slave n <23
µC
40m
+ Return
LIN bus
LIN bus
MCP200X
LIN bus
MCP200X LIN bus
MCP200X LIN bus
MCP200X
© 2010-2011 Microchip Technology Inc. DS22230D-page 9
MCP2003/4/3A/4A
1.5 Pin Descriptions
TABLE 1-2: PINOUT DESCRIPTIONS
1.5.1 RECEIVE DATA OUTPUT (RXD)
The Receive Data Output pin is an open drain (OD)
output and follows the state of the LIN pin, except in
Power Down mode.
1.5.2 CS (C HIP SE LEC T )
This is the Chip Select Input pin. An internal pull-down
resisto r will ke ep the CS p in low. Thi s is done to ensure
that no disruptive data will be present on t he bus wh ile
the microcontroller is executing a Power-on Reset and
an I/O initialization sequence. The pin must detect a
high level to activate the transmitter. An internal Low-
Pass filter, with a typical time constant of 10 µS,
prevents unwanted wake-up (or transition to Power
Down mode) on glitches.
If CS = 0 when the VBB supply is turned on, the device
goes to Ready mode as soon as internal voltages sta-
bilize , a nd st ays t here a s lon g as the C S pin i s hel d low
(0). In Ready mode, the receiver is on, and the LIN
transmitter driv er is off.
If CS = 1 when the VBB supply is turne d on, the dev ic e
will proceed to Operation mode, or TXOFF (refer to
Figure 1-2 – Figure 1-5), as soon as internal voltages
stabilize.
This pin may also be used as a local wake-up input
(refer to Example 1-1). In this implementation, the
microcontroller I/O controlling the CS should be
converted to a high-impedance input allowing the
internal pull-down resistor to keep CS low. An external
switch, or other source, can then wake-up both the
transceiver and the microcontroller (if powered). Refer
to Section 1.3 “Modes of Operation”, for detailed
operation of CS.
1.5.3 WAKE UP INPUT (WAKE)
This pin is only available on the MCP2003/2003A.
The WAKE pin has an internal 800K pull up to VBB. A
falling edge on the WAKE pin causes the device to
wake from Power-Down mode. Upon waking, the
MCP2003/3A will enter Ready mode.
1.5.4 FAULT/TXE
This pin is on ly ava ilabl e on the MCP2 004/20 04A. Thi s
pin is bidirectional and allows disabling of the
transmitter, as well as fault reporting related to
disabling the transmitter. This pin is an open-drain
output, with states as defined in TABLE 1-3: “FAULT/
TXE Truth Table”. The transmitter is disabled
whenever this pin is low (‘0’), either from an internal
Pin Name 8-Pin
PDIP,
SOIC
8-Pin
DFN
MCP2003/2003A MCP2004/2004A
Normal Operation Normal Operation
RXD 1 1 Receive Data Output (OD), HV
tolerant Receive Data Output (OD), HV tol-
erant
CS 2 2 Chip Select (TTL), HV tolerant Chip Select/Local WAKE (TTL),
HV tolerant
WAKE
(MCP2003/2003A only)
FAULT/TXE
(MCP2004/2004A only)
3 3 Wake up, HV tolerant Fault Detect Output (OD)
Transmitter Enable (TTL)
HV tolerant
TXD 4 4 Transmit Data Input (TTL), HV
tolerant Transmit Data Input (TTL), HV tol-
erant
VSS 5 5 Ground Ground
LBUS 6 6 LIN Bus (bidirectional) LIN Bus (bidirectional)
VBB 7 7 Battery Positive Battery Positive
VREN 8 8 Voltage Regulator Enable Output Voltage Regulator Enable Output
EP 9 Exposed Thermal Pad. Do not
electrically connect or connect to
Vss
Exposed Thermal Pad. Do not
electrically connect or connect to
Vss
Legend: TTL = TTL Input Buffer; OD = Open-Drain Output
Note: It is not recommended to tie CS high as
this can result in the device entering
Operation mode before the
microc ontroller is initialize d and may result
in unintentional LIN traffic.
MCP2003/4/3A/4A
DS22230D-page 10 © 2010-2011 Microchip Technology Inc.
Fault condition or by an external drive. While the
transmitter is disabled, the internal 30 kΩ pull-up
resi sto r on the LBUS p in is als o disconne cte d to reduce
current.
TABLE 1-3: FAULT/TXE TRUTH TABLE
1.5.5 TRANSMIT DATA INPUT (TXD)
The Transmit Data Input pin has an internal pull-up.
The LIN pin is low (dominant) when TXD is low , and high
(recessive) when TXD is high.
For extra bus security, TXD is internally forced to ‘1
whenever the transmitter is disabled regardless of
external TXD voltage.
1.5.5.1 TXD Dominant Timeout
If TXD is driven low for longer than approximately 25
mS, the LBUS pin is switched to recessive mode and
the part enters TOFF Mode. This is to prevent the LIN
node from permanently driving the LIN Bus dominant.
The transmitter is reenabled on TXD risi ng edge.
1.5.6 GROUND (VSS)
This is the Ground pin.
1.5.7 LIN BUS (LBUS)
The bid irectional L IN Bus pin (LBUS) is controll ed by the
TXD input. LBUS has a current limited open collector
output. To reduce EMI, the edges during the signal
changes are slope controlled and include corner
rounding control for both falling and rising edges.
The intern al LIN rec ei ver observ es the ac tiv iti es on th e
LIN bus, and matches the output signal RXD to follow
the state of the LBUS pin.
1.5.7.1 Bus Dominant Timer
The Bus Dominant Timer is an internal timer that
deactivates the LBUS transmitter after approximately
25 millisecond s of dom inant st ate on the LBUS pin. The
timer is reset on any recessive LBUS state.
The LIN bus transmitter will be reenabled after a
recessive state on the LBUS pin as long as CS is high.
Disabling can be caused by the LIN bus being
externally held dominant, or by TXD being driven low.
Additionally, on the MCP2004/2004A, the FAULT pin
will be driven low to indicate the Transmitter Off state.
1.5.8 BATTERY (VBB)
This is the Battery Positive Supply Voltage pin.
1.5.9 VOLTAGE REGULATOR ENABLE
OUTPUT (VREN)
This is the External Voltage Regulator Enable pin.
Open source output is pulled high to VBB in all modes,
except Power-Do w n.
1.5.10 EXPOSED THERMAL PAD (EP)
Do not electrically connect, or connect to Vss.
Note: The FAULT/TXE pin is true (‘0’) whenever
the internal circuits have detected a short
or thermal excursion and have disabled
the LBUS output driver.
TXD
In RXD
Out LINBUS
I/O Thermal
Override
FAULT/TXE
Definition
External
Input Driven
Output
LHV
BB OFF H L F A U LT, TXD driven low, LIN BUS shorted to VBB
(Note 1)
HHV
BB OFF H H OK
L L GND OFF H H OK
H L GND OFF H H OK, data is being received from the LINBUS
xxVBB ON H L FAULT, Transceiver in thermal shutdown
xxV
BB x L x NO FAULT, the CPU is commanding the
transceiver to turn off the transmitter driver
Legend: x = don’t care
Note 1: The FAULT/TXE is valid after approximately 25 µs after TXD falling edge. This is to eliminate false fault
reporting during bus propagation delays.
© 2010-2011 Microchip Technology Inc. DS22230D-page 11
MCP2003/4/3A/4A
1.6 MCP2003/4 and MCP2003A/4A
Difference Details
The differences between the MCP2003/4 and the
MCP2003/4A devices are isolated to the wake-up
functio nal ity . The cha nges were i mp lem en ted to make
the device more robust to LIN bus conditions, outside
of the normal operating conditions. The MCP2003/4
will wake-up from Power Down Mode during any LIN
falling edge held low longer than 20us.
In the case where a LIN system is designed to
minimize stand-by current by disconnecting all bus
pull-ups resistors (including the external master pull-
up resistor to VBB), the original MCP2003/4 could
wake up, if the floating bus drifted to a valid low level.
The MCP2003/4A revisions were modified to require a
rising edge after a valid low level. This will prevent an
undesired system wake-up in this scenari o, while
maintaining functional capability with the original
version.
It should be noted that the original MCP2003/4 meets
all LIN transceiver specification requirements and
modules can be designed to pass all LIN system
requirem ent s. H owev er, whe n all bus pu ll-u p res istors
are disconnected, the MCP2003/4 requires the
module designer to write firmware to monitor the LIN
Bus after any wake-up e vent to prevent th e transceiver
from automat ically transitioning fr om Ready mode to
Operational mode.
If the MCP2003 /4 is pla ce d into Operation al mo de,
VBB-LBUS pull-u p resistor is automatically connected,
which will raise the LIN bus to a recessive level; then
putting the device to Power-Down mode may cause
LBUS to be floating, and thus wake up all bus nodes.
To prevent this, the designer should insure TXD
(MCP2003) or TXE (MCP2004) is held low until valid
bus activity is verified (see Figure 1-6). This will
ensure th e transce iver transitio ns from Ready mode to
Transmi tter Off mode , until bu s activi ty can b e verified .
In the case of valid bus activity, the transceiver can
shift to Operation mode, while if there is no bus
activity, the device can be again placed into Power
Down. Th e design practices neede d to accomp lish this
are fully detailed in Tech Brief TB3067 - “MCP2003
Power-Down Mode a nd Wak e-Up Handling in Case
of LIN Bus Loss” (DS93067).
The revised MCP2003/4A devices now eliminate the
need for firmware to prevent system wide wake-up.
The revised devices now require a longer valid bus
low (see updated tBDB value in the Specification
tables and FIGURE 2-7: “MCP2003A/4A Remote
Wake-up”), which enable s a rising ed ge detect ci rcuit.
The device will now only wake up after a rising edge,
following a low longer than tBDB. While the module
designer can still hold TXD (MCP2003) or TXE
(MCP2004) low during wake-up, to enter Transmitter
Off mode from Ready mode, it is not required to
prevent an advertent system wake-up.
In addition to the longer tBDB value, the time from
wake-up detect to VREN enable is shortened as
documented in the Specification table.
FIGURE 1-6: MCP2003/2004 Switching Timing Diagram for the Forced Power-Down Mode
Sequence
TXD
VREN
CS
Ready
Mode
Transmitter OFF
Mode
Power Down
Mode after Master
Sleep instruction
Power Down
Mode
tTx2CS >= 100ns tCSactive >= 100µs
TXD to 0
forced
externally
TXD state depending
on how the Slave
Microcontroller is
powered
LBUS
State
LIN bus
disconnected
MCP2003/4/3A/4A
DS22230D-page 12 © 2010-2011 Microchip Technology Inc.
2.0 ELECTRICAL CHARACTERISTICS
2.1 Absolute Maximum Ratings†
VIN DC Voltage on RXD, TXD, FAULT/TXE, CS.............................................................................................-0.3 to +43V
VIN DC Voltage on WAKE and VREN .............................................................................................................-0.3 to +VBB
VBB Battery Voltage, continuous, non-operating (Note 1)............................................................................. -0.3 to +40V
VBB Battery Voltage, non-operating (LIN bus recessive) (Note 2)................................................................ -0.3 to +43V
VBB Battery Voltage, transient ISO 7637 Test 1 ..................................................................................................... -200V
VBB Battery Voltage, transient ISO 7637 Test 2a ...................................................................................................+150V
VBB Battery Voltage, transient ISO 7637 Test 3a ................................................................................................... -300V
VBB Battery Voltage, transient ISO 7637 Test 3b ...................................................................................................+200V
VLBUS Bus Voltage, continuous......................................................................................................................-18 to +40V
VLBUS Bus Voltage, transient (Note 3)...........................................................................................................-27 to +43V
ILBUS Bus Short Circuit Current Limit....................................................................................................................200 mA
ESD protection on LIN, VBB, W AKE (IEC 61000-4-2) (Note 4)...............................................................................±8 KV
ESD protection on LIN, VBB (Human Body Model) (Note 5)................................................................................... ±8 KV
ESD protection on all other pins (Human Body Model) (Note 5) ............................................................................ ±4 KV
ESD protection on all pins (Charge Device Model) (Note 6) ...................................................................................±2 KV
ESD protection on all pins (Machine Model) (Note 7).............................................................................................±200V
Maximum Junction Temperature.............................................................................................................................150°C
Storage Temperature...................................................................................................................................-65 to +150°C
Note 1: LIN 2.x compliant specification.
2: SAE J2602 complia nt spe ci fic ati on.
3: ISO 7637/1 load dump compliant (t < 500 ms).
4: According to IEC 61 000-4-2, 330 ohm, 150 pF and T ransceiver EMC Test S pecificati ons [2] to [4]. For WAKE
pin to meet the specification, series resistor must be in place (refer to Example 1-2).
5: According to AEC-Q100-002 / JESD22-A114.
6: According to AEC-Q100-011B.
7: According to AEC-Q100-003 / JESD22-A115.
2.2 Nomenclature used in this document
Some terms and names used in this data sheet deviate from those referred to in the LIN specifications. Equivalent
values are shown below.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device . This is a stress rati ng only an d functio nal operati on of the dev ice, at tho se or any o ther condi tions abov e those
indicated in the operational listings of this specification, is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
LIN 2.1 Name Term used in the following tables Definition
VBAT not used ECU operating voltage
VSUP VBB Supply voltage at device pin
IBUS_LIM ISC Curr ent Limit of Driver
VBUSREC VIH(LBUS) Recessive state
VBUSDOM VIL(LBUS) Dominant state
© 2010-2011 Microchip Technology Inc. DS22230D-page 13
MCP2003/4/3A/4A
2.3 DC Specifications
DC Specifications
Electrical Charact eris tics:
Unless otherwise indicated, all limits are specified for:
VBB = 6.0V to 30.0V
TA = -40°C to +125°C
Parameter Sym Min. Typ. Max. Units Conditions
Power
VBB Quiesce nt Op erat ing
Current IBBQ 90 150 µA Oper ating Mode,
bus recess ive (Note 1)
VBB Transmitte r-off Current IBBTO 75 120 µA Transmitter off,
bus recess ive (Note 1)
VBB Power-Down Current IBBPD —515µA
VBB Current
with VSS Floatin g IBBNOGND -1 1 mA VBB = 12V, GND to VBB,
VLIN =0-27V
Microcontroller Interface
High Level Input Voltage
(TXD, FAULT/TXE) VIH 2.0 — 30 V
Low Level Input Voltage
(TXD, FAULT/TXE) VIL -0.3 0.8 V
High Level Input Current
(TXD, FAULT/TXE) IIH -2.5 µA Input voltage = 4.0V
Low Level Input Current
(TXD, FAULT/TXE) IIL -10 µA Input voltage = 0.5V
High Level Voltage (VREN)VHVREN -0.3 VBB+0.3
High Level Output Current
(VREN)IHVREN -20 -10 mA Output voltage = VBB-
0.5V
High Level Input Voltage
(CS)VIH 2.0 30 V Through a curr ent limiti ng
resistor
Low Level Input Voltage
(CS) VIL -0.3 0.8 V
High Level Input Current
(CS) IIH 10.0 µA Input voltage = 4.0V
Low Level Input Current
(CS) IIL 5.0 µA Input voltage = 0.5V
Low Level Input Voltage
(WAKE)VIL VBB – 4.0V V
Low Level Output Voltage
(RXD)VOL ——0.4 VIIN = 2 mA
High Level Output Current
(RXD)IOH -1 -1 µA VLIN = VBB, VRXD = 5.5V
Note 1: Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0Ω, TX = 0.4 VREG, VLBUS = VBB).
2: Node has to sustain the current that can flow under this condition; bus must be operational under this
condition.
MCP2003/4/3A/4A
DS22230D-page 14 © 2010-2011 Microchip Technology Inc.
Bus Interface
High Level Input Voltage VIH(LBUS) 0.6 VBB V Recessi ve state
Low Level Input Voltage VIL(LBUS)-80.4 VBB V Dominant state
Input Hysteresis VHYS 0.175 VBB VVIH(LBUS) – VIL(LBUS)
Low Level Output Current IOL(LBUS) 40 200 mA Output voltage = 0.1 VBB,
VBB = 12V
High Level Output Current IOH(LBUS)—20µA
Pull-up Current on Input IPU(LBUS)5180µA~30kΩ internal pull-up
@ VIH (LBUS) = 0.7 VBB
Short Circuit Current Limit ISC 50 200 mA (Note 1)
High Level Output Voltage VOH(LBUS) 0.9 VBB —VBB V
Driver Dominant Voltage V_LOSUP ——1.2 VVBB = 7V, RLOAD = 500Ω
Driver Dominant Voltage V_HISUP ——2.0 VVBB = 1 8V, RLOAD = 500Ω
Driver Dominant Voltage V_LOSUP-1K0.6 V VBB = 7V, RLOAD = 1 kΩ
Driver Dominant Voltage V_HISUP-1K0.8 V VBB = 18V, RLOAD = 1 kΩ
Input Leakage Current
(at the receiver during
dominant bus level)
IBUS_PAS_DOM -1 -0.4 mA Driver off,
VBUS = 0V,
VBB = 12V
Input Leakage Current
(at the receiver during
recessive bus level)
IBUS_PAS_REC 12 20 µA Driver off,
8V < VBB < 18V
8V < VBUs < 18V
VBUS VBB
Leakage Current
(disconnected from ground) IBUS_NO_GND -10 1.0 +10 µA GNDDEVICE = VBB,
0V < VBUS < 18V,
VBB = 12V
Leakage Current
(disconnected from VBB)IBUS_NO_VBB —— 10µAVBB = GND,
0 < VBUS < 18V,
(Note 2)
Receiver Center Voltage VBUS_CNT 0.475 VBB 0.5
VBB 0.525 VBB VVBUS_CNT = (VIL (LBUS) +
VIH (LBUS))/2
Slave Termination RSLAVE 20 30 47 kΩ
Capacitance of Slave N ode CSLAVE 50 pF
2.3 DC Specifications (Contin ued)
DC Specifications
Electrical Charact eris tics:
Unless otherwise indicated, all limits are specified for:
VBB = 6.0V to 30.0V
TA = -40°C to +125°C
Parameter Sym Min. Typ. Max. Units Conditions
Note 1: Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0Ω, TX = 0.4 VREG, VLBUS = VBB).
2: Node has to sustain the current that can flow under this condition; bus must be operational under this
condition.
© 2010-2011 Microchip Technology Inc. DS22230D-page 15
MCP2003/4/3A/4A
2.4 AC Specifications
AC CHARACTERISTICS VBB = 6.0V to 27.0V; TA = -40°C to +125°C
Parameter Sym Min. Typ. Max. Units Test Conditions
Bus Interface – Constant Slope Time Parameters
Slope Rising and Falling Edges tslope 3.5 22.5 µs 7.3V <= VBB <= 18V
Propagation Delay of
Transmitter ttranspd 4.0 µs ttranspd = max (ttranspdr or ttranspdf)
Propagation Delay of Receiver trecpd 6.0 µs trecpd = max (trecpdr or trecpdf)
Sym m etry of Propagation
Delay of Receiver Rising Edge
w.r.t. Falling Edge
trecsym -2.0 2.0 µs trecsym = max (trecpdf – trecpdr)
RRXD 2.4Ω TO VCC, CRXD 20 PF
Sym m etry of Propagation
Delay of Transmitter Rising
Edge w.r.t. Falling Edge
ttrans-
sym -2.0 2.0 µs ttranssym = max (ttranspdf - ttranspdr)
Time to Sample of FAULT/TXE
for Bus Conflict Reporting tfault 32.5 µs tfault = max (ttranspd + tslope + trecpd)
Duty Cycle 1 @20.0 kbit/sec .396 Cbus; Rbus conditions:
1nF; 1kΩ | 6.8 nF; 660Ω | 10 nF; 500Ω
THrec(max) = 0.744 x VBB,
THdom(max) = 0.581 x VBB,
VBB =7.0V – 18V; tbit = 50 µs
D1 = tbus_rec(min)/2 x tbit)
Duty Cycle 2 @20.0 kbit/sec .581 Cbus; Rbus conditions:
1nF; 1kΩ | 6.8 nF; 660Ω | 10 nF; 500Ω
THrec(max) = 0.284 x VBB,
THdom(max) = 0.422 x VBB,
VBB =7.6V – 18V; tbit = 50 µs
D2 = tbus_rec(max)/2 x tbit)
Duty Cycle 3 @10.4 kbit/sec .417 Cbus; Rbus conditions:
1nF; 1kΩ | 6.8 nF; 660Ω | 10 nF; 500Ω
THrec(max) = 0.778 x VBB,
THdom(max) = 0.616 x VBB,
VBB =7.0V – 18V; tbit = 96 µs
D3 = tbus_rec(min)/2 x tbit)
Duty Cycle 4 @10.4 kbit/sec .590 Cbus; Rbus conditions:
1nF; 1kΩ | 6.8 nF; 660Ω | 10 nF; 500Ω
THrec(max) = 0.251 x VBB,
THdom(max) = 0.389 x VBB,
VBB =7.6V – 18V; tbit = 96 µs
D4 = tbus_rec(max)/2 x tbit)
Wake-up Timing
Bus Activity Debounce time tBDB 5 20 µs MCP2003/2004
30 70 125 µs MCP2003A/2004A
Bus Activity to Vren on tBACTVE 35 150 µs MCP2003/2004
10 30 90 µs MCP2003A/2004A
WAKE to Vren on tWAKE 150 µs
Chip Select to Vren on tCSOR 150 µs Vren floating
Chip Select to Vren off tCSPD 80 µs Vren floating
MCP2003/4/3A/4A
DS22230D-page 16 © 2010-2011 Microchip Technology Inc.
2.5 Thermal S pecifications
THERMAL CHARACTERISTICS
Parameter Symbol Typ Max Units Test Conditions
Recovery Temperature θRECOVERY +140 °C
Shutdown Temperature θSHUTDOWN +150 °C
Short Circuit Recovery Time tTHERM 1.5 5.0 ms
Thermal Package Resistances
Thermal Resistance, 8L-DFN θJA 35.7 °C/W
Thermal Resistance, 8L-PDIP θJA 89.3 °C/W
Thermal Resistance, 8L-SOIC θJA 149.5 °C/W
Note 1: The maximum power dissipation is a function of TJMAX, ΘJA and ambient temperature TA. The maximum
allowable power dissipation at an ambient temperature is PD = (TJMAX - TA) ΘJA. If this dissipation is
exceeded, the die temperature will rise above 150°C and the device will go into thermal shutdown.
© 2010-2011 Microchip Technology Inc. DS22230D-page 17
MCP2003/4/3A/4A
2.6 Typical Performance Curves
Note: Unless otherwise indicated, VBB = 6.0V to 18.0V, TA = - 40°C to +125° C.
FIGURE 2-1: TYPICAL IBBQ
FIGURE 2-2: TYPICAL IBBPD
FIGURE 2-3: TYPICAL IBBTO
Note: The g r ap hs and t ables prov id ed followi ng thi s n ote are a sta tis tic al s umm ar y b as ed on a limite d n um ber of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
6 7.3 12 14.4 18
VBB (V)
Current (mA)
-40C
25C
85C
125C
0
0.001
0.002
0.003
0.004
0.005
0.006
0.007
0.008
6 7.3 12 14.4 18
VBB (V)
Current (mA)
-40C
25C
85C
125C
0
0.02
0.04
0.06
0.08
0.1
0.12
6V 7.3V 12V 14.4V 18V
VBB (V)
Current (mA)
-40C
25C
85C
125C
MCP2003/4/3A/4A
DS22230D-page 18 © 2010-2011 Microchip Technology Inc.
2.7 Timing Diagrams and Specifications
FIGURE 2-4: BUS TIMING DIAGRAM
FIGURE 2-5: CS TO VREN TIMING DIAGRAM
.95VLBUS
0.05VLBUS
TTRANSPDR
TRECPDR
TTRANSPDF
TRECPDF
TXD
LBUS
RXD
Internal TXD/RXD
Compare
FAULT Sampling
TFAULT TFAULT
FAULT/TXE Output Stable Stable
Stable
Match Match
Match Match Match
Hold
Value
Hold
Value
50%
50%
.50VBB
50%
50%
0.0V
TCSPD
TCSOR
CS
VREN
VBB
OFF
© 2010-2011 Microchip Technology Inc. DS22230D-page 19
MCP2003/4/3A/4A
FIGURE 2-6: MCP2003/4 REMOTE WAKE-UP
FIGURE 2-7: MCP2003A/4A REMOTE WAKE-UP
MCP2003/4/3A/4A
DS22230D-page 20 © 2010-2011 Microchip Technology Inc.
3.0 PACKAGING INFORMATION
3.1 Package Marking Information
8-Lead PDIP (300 mil) Examples:
8-Lead SOIC (150 mil) Examples:
E/P^^256
1148
MCP2003E
SN^^1148
256
MCP2003A
3
e
3
e
Examples:
2004A
1148
256
E/MD^^
3
e
8-Lead DFN (4x4)
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In th e event the full Mi croch ip p art numb er canno t be marked on one l ine, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
E/P^^256
0948
2003AE
SN^^0948
256
MCP2003
3
e
3
e
2004
0948
256
E/MD
^^
3
e
XXXX
NNN
YYWW
PIN 1
XXXXXXXX
XXXXXNNN
YYWW
NNN