18-Bit Registered Transceiver
f
ax id: 7046
CY74FCT16500T
CY74FCT162500T
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Au
g
ust 1994 - Revised Oc tober 30
,
1997
2
500T
Features
• Lo w pow er, pin compatible replacement f or ABT
functions
• FCT-C speed at 4.6 ns
• Power-off disable outputs permits live inser tion
• Edge-rate control circuitry for si gnificantly improved
noise characteristics
• Typical out put skew < 250 ps
• ESD > 2000V
• TSSOP (19.6 -mil pit ch) and SSOP (25-mil pitch)
packages
• Industrial temperature range of −40°C to +85°C
•V
CC = 5V ± 10%
CY74FCT16500T Features:
• 64 mA sink current, 32 mA source current
• Typical VOLP (ground bounce) <1.0V at VCC = 5V,
TA = 25°C
CY74FCT162500T Features:
• Balanced 24 mA output dri vers
• Red uced system swit ching noise
• Typical VOLP (ground bounce) <0.6V at VCC = 5V,
TA= 2 5° C
Functional Descripti on
These 18-bit universal bus transceivers can be operated in
transparent, latched, or clock modes by combining D-type
latches and D-type flip-flops. Data flow in each direction is con-
trolled by output-enable (OEAB and OEBA), latch enable
(LEAB and LEBA), and clock inputs (CLKAB and CLKBA) in-
puts. For A-to-B data flow, the device operates in transparent
mode when LEAB is HIGH. When LEAB is LO W , the A data is
la tch ed if CLK AB is held at a HIGH or LOW logic level. If LEAB
is LOW, the A bus data is stored in the latch/flip-flop on the
HIGH-to-LOW tra nsition o f CLKAB . OEAB per forms the ou tput
enable function on the B port. Data flow from B-to-A is similar
to that of A-to-B and is controlled by OEBA, LEBA, and
CLKBA. The output buffers are designed with power-off
disable feature that allows live insertion of boards.
The CY74FCT16500T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.
The CY74FCT162500T has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The
CY74FCT162500T is ideal for driving transmission lines.
GND
LogicBlockDiagram Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
33
32
31
30
29
36
35
OEAB
34
SSOP/TSSOP
Top Vie w
13
14
15
16
17
18
19
20
21
22
23
24
45
44
43
42
41
37
38
39
40
48
47
46
LEAB
A1
A2
A3
B1
B2
B3
GND
GND
GND
VCC
A6
A7
A4
A5
B4
B5
B6
B7
VCC
GND
A10
A11
A8
A9
B8
B9
B11
B12
GND
A12
VCC
A16
GND
A14
VCC
A15
A17
FCT16500-1
TO 17 OTHER CHANNELS
LEAB
OEBA
LEBA
CLKAB
CLKBA
OEAB
C
D
C
D
C
D
C
D
A1B1
25
26
27
28
49
52
51
50
A13
OEBA
LEBA
GND
A18
CLKAB
53
56
55
54
B10
GND
B14
B15
B13
B16
B17
GND
B18
CLKBA
FCT16500-2
CY74FCT16500T
CY74FCT162500T
2
Maximum Ratings[5, 6]
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Storage Temperature ....................... Com’l −55°C to +125°C
Ambient Temperature with
Power Applied....................................Com’l −55°C to +125°C
DC Input Voltage.................................................−0.5V to +7.0V
DC Output Voltage..............................................−0.5V to +7.0V
DC Output Current
(Maximum Sink Current /Pin)...........................−60 to +120 mA
Power Dissipation.......................................................... 1.0W
Static Discharge Voltage ...........................................>2001V
(per MIL- STD-883, Method 3015)
Pin Summary
Name Description
OEAB A- to-B Output En a ble Input
OEBA B-to-A Output Enable Input (Acti ve LOW)
LEAB A-to-B Latch Enable Input
LEBA B-to-A Latch Enable Input
CLKAB A-to-B Clock Input (Active LOW)
CLKBA B-to-A Clock Input (Active LOW)
AA-to -B Data Inputs or B-to-A Three-State Output s
BB-to -A Data Inputs or A-to-B Three-State Output s
Function Table[1, 2]
Inputs Outputs
OEAB LEAB CLKAB A B
L X X X Z
H H X L L
H H X H H
H L L L
H L H H
H L H X B[3]
H L L X B[4]
Operating Range
Range Ambient
Temperature VCC
Industrial −40°C to +85°C 5V ± 10%
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Typ.[7] Max. Unit
VIH Input HIGH Voltage 2.0 V
VIL Input LO W Voltage 0.8 V
VHInput Hysteresis[8] 100 mV
VIK Input Clamp Diode Voltage VCC=Min., IIN=−18 m A −0.7 −1.2 V
IIH Input HIGH Current VCC=Max., VI=VCC ±1µA
IIL Input LO W Cur rent VCC=Max., VI=GND. ±1µA
IOZH High Impedance Output Current
(Three-State Output pi ns) VCC=Max., V OUT=2.7V ±1µA
IOZL High Impedance Output Current
(Three-State Output pi ns) VCC=Max., V OUT=0.5V ±1µA
IOS Short Circuit Current[9] VCC=Max., VOUT=GND −80 −140 −200 mA
IOOutput Drive Current[9] VCC=Max., V OUT=2.5V −50 −180 mA
IOFF Power-Off Disable VCC=0V, VOUT≤4.5V[10] ±1µA
Notes:
1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Z = HIGH Impedance. = HIGH-to-LOW Transition.
2. A-to-B data flow is shown, B-to-A data flow is similar but uses OE BA , LEBA, and CLKBA.
3. Output level before the indicated steady-state input conditions were established.
4. Output level before the indicated steady-state input conditions were established, provided that CLKAB was LO W bef ore LEAB went LOW.
5. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature
range.
6. Unused inputs must always be connected to an appropriate logic voltage level, pref erably either VCC or g round.
7. Typical values are at VCC= 5.0 V, TA= + 25°C ambient .
8. This parameter is guaranteed but not tested.
9. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests shou ld be per formed last .
10. Tested at +25°C.
CY74FCT16500T
CY74FCT162500T
3
Output D rive Characteristics for CY74FCT16500T
Parameter Description Te st Conditions Min. Typ.[7] Max. Unit
VOH Output HIGH Voltage VCC=Min., IOH=−3 mA 2.5 3.5 V
VCC=Min., IOH=−15 mA 2.4 3.5
VCC=Min., IOH=−32 mA 2.0 3.0
VOL Output LOW Voltage VCC=Min., IOL=64 mA 0.2 0.55 V
Output D rive Characteristics for CY74FCT162500T
Parameter Description Te st Conditions Min. Typ.[7] Max. Unit
IODL Output LOW Current[9] VCC=5V, VIN=VIH or VIL, VOUT=1.5V 60 115 150 mA
IODH Output HIGH Current[9] VCC=5V, VIN=VIH or VIL, VOUT=1.5V −60 −115 −150 mA
VOH Output HIGH Voltage VCC=Min., IOH=−24 mA 2.4 3.3 V
VOL Output LOW Voltage VCC=Min., IOL=24 mA 0.3 0.55 V
Capacitance[8] (TA = +25°C , f = 1.0 MHz)
Parameter Description Test Conditions Typ.[7] Max. Unit
CIN Input Capacitance VIN = 0V 4.5 6.0 pF
COUT Output Capacitance VOUT = 0V 5.5 8.0 pF
Power Supply Characteristics
Parameter Description Test Conditi ons Typ.[7] Max. Unit
ICC Quiesc ent P ower S upply Curr ent VCC=Max. VIN≤0.2V,
VIN≥VCC−0.2V 5500 µA
∆ICC Quiescent Power Supply Current
(TTL in puts HIGH) VCC=Max. VIN=3.4V[11] 0.5 1.5 mA
ICCD Dynamic Power Supply
Current[12] VCC=Max., One Input Toggling,
50% Duty Cycle, Outputs Open,
OEAB=OEBA=VCC or GND
VIN=VCC or
VIN=GND 75 120 µA/MHz
ICTotal Power Supply Current[13] VCC=Max., f0=10 MHz
(CLKAB), f1=5 MHz, 50% Duty
Cycle, Outputs Open,
One Bit Toggling,
OEAB=OEBA=VCC
LEAB=GND
VIN=VCC or
VIN=GND 0.8 1.7 mA
VIN=3 . 4V o r
VIN=GND 1.3 3.2 mA
VCC=Max., f0=10 MHz,
f1=2.5 M Hz, 50 % Duty
Cycle, Outputs Open,
Eighteen Bits Toggling,
OEAB=OEBA=VCC
LEAB=GND
VIN=VCC or
VIN=GND 3.8 6.5[14] mA
VIN=3 . 4V o r
VIN=GND 8.5 20.8[14] mA
Notes:
11. Per TTL driven input (VIN=3.4V) ; all oth er inputs at VCC or GND .
12. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
13. IC=I
QUIESCENT + IINPUTS + IDYNAMIC
IC=I
CC+∆ICCDHNT+ICCD(f0/2 + f1N1)
ICC = Quiescent Current with CMOS input levels
∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V)
DH = Duty Cycle for TTL inputs HIGH
NT = Number of TTL inputs at DH
ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)
f0= Clock frequency for registered devices, otherwise zero
f1= Input signal frequency
N1= Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
14. Values for these conditions are examples of the ICC f ormula. These l imits are gu aranteed but not tes ted.
CY74FCT16500T
CY74FCT162500T
4
Document #: 38−00381-B
Swi tch i ng C h ara cter i sti cs Over the Operating Range[15]
CY74FCT16500AT/
CY74FCT162500AT CY74FCT16500CT/
CY74FCT162500CT Fig.
No.[16]
Parameter Description Min. Max. Min. Max. Unit
fMAX CLKAB or CLKBA fr equency 150 150 MHz
tPLH
tPHL Propagation Delay
A to B or B to A 1.5 5.1 1.5 4.6 ns 1, 3
tPLH
tPHL Propagation Delay
LEBA to A, LEAB to B 1.5 5.6 1.5 5.3 ns 1, 5
tPLH
tPHL Propagation Delay
CLKBA to A, C LKAB to B 1.5 5.6 1.5 5.3 ns 1, 5
tPZH
tPZL Output Enable Time
OEBA to A, O EAB to B 1.5 6.0 1.5 5.4 ns 1, 7, 8
tPHZ
tPLZ O utp ut Disable T i m e
OEBA to A, O EAB to B 1.5 5.6 1.5 5.2 ns 1, 7, 8
tSU Set-Up Time, HIGH or LOW
A to CLKAB, B to CLKBA 3.0 3.0 ns 9
tHHold Time, HIGH or LOW
A to CLKAB, B to CLKBA 0 0 ns 9
tSU Set-Up Time, HIGH or LOW
A to LEAB, B to LEBA Clock HIGH 3.0 3.0 ns 4
Clock LOW 1.5 1.5 ns 4
tHHold Time, HIGH or LOW
A to LEAB, B to LEBA 1.5 1.5 ns 4
tWLEAB or LEBA Pulse Width HIGH 3.0 2.5 ns 5
tWCLKAB or CLKBA Pulse Width HIGH or LOW 3.0 3.0 ns 5
tSK(O) Output Skew[17] 0.5 0.5 ns
Ordering Information CY74FCT16500T
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
4.6 CY74FCT16500CTPAC Z56 56-Lead (240-Mil ) TSSOP Industrial
CY74FCT16500CTPVC O56 56-Lead (300-Mi l) SSOP
5.1 CY74FCT16500ATPAC Z56 56-Lead (240-Mil ) TSSOP Industrial
CY74FCT16500ATPVC O56 56-Lead (300-Mil) SSOP
Ordering Information CY74FCT162500T
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
4.6 CY74FCT162500CTPAC Z56 56-Lead (24 0-Mil) TSSOP Industrial
CY74FCT162500CTPVC O56 56-Lead (300-Mi l) SSOP
5.1 CY74FCT162500ATPA C Z56 56-Lead (240-Mil ) TSSOP Industrial
CY74FCT162500ATPVC O56 56-Lead (300-Mil) SSOP
Notes:
15. Minimum limits are guaranteed but not tested on Propagation Delays.
16. See “Parameter Measurement Information” in the General Information section.
17. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
CY74FCT16500T
CY74FCT162500T
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circui try other than circuitry embodied in a Cypress Semiconduc tor produc t. Nor does it conv ey or imply any license under patent or other rights. Cypress Semi conductor does not author ize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Di ag ra ms
56-Lead Shrunk Small Outline Package O56
56-Lead Thin Shrunk Small Outline Package Z56
