Dual-Channel Ultralow Noise Amplifier with
Selectable Gain and Input Impedance
Data Sheet
AD8432
Rev. C
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FEATURES
Low noise
Input voltage noise: 0.85 nV/√Hz
Current noise: 2.0 pA/√Hz
High speed
200 MHz bandwidth (G = 12.04 dB)
295 V/µs slew rate
Selectable gain
G = 12.04 dB (×4)
G = 18.06 dB (×8)
G = 21.58 dB (×12)
G = 24.08 dB (×16)
Active input impedance matching
Integrated input clamp diodes
Single-ended input, differential output
Supply range: 4.5 V to 5.5 V
Low power: 60 mW/channel
APPLICATIONS
CW Doppler ultrasound front ends
Low noise preamplification
Predriver for I/Q demodulators and phase shifters
Wideband analog-to-digital drivers
FUNCTIONAL BLOCK DIAGRAM
BIAS
ENB COMM
INH1
IND1
INL1
INH2
IND2
INL2
VPS1 VPS2
OPH1
OPL1
GMH1
GOH1
GOL1
GML1
OPH2
OPL2
GMH2
GOH2
GOL2
GML2
LNA1
LNA2
AD8432
08341-001
Figure 1.
GENERAL DESCRIPTION
The AD8432 is a dual-channel, low power, ultralow noise
amplifier with selectable gain and active impedance matching.
Each channel has a single-ended input, differential output, and
integrated input clamps. By pin strapping the gain setting pins, four
accurate gains of G = 12.04 dB, 18.06 dB, 21.58 dB, and 24.08 dB
(×4, ×8, ×12, and ×16, respectively) are possible. A bandwidth of
200 MHz at G = 12.04 dB makes this amplifier well suited for many
high speed applications.
The exceptional noise performance of the AD8432 is made
possible by the active impedance matching. Using a feedback
network, the input impedance of the amplifiers can be adjusted
to match the signal source impedance without compromising
the noise performance. Impedance matching and low noise in
the AD8432 allow designers to create wider dynamic range
systems that are able to detect even very low level signals.
The AD8432 achieves 0.85 nV/√Hz input-referred voltage noise for
a gain of 12.04 dB. The AD8432’s ultralow noise, low distortion,
gain accuracy, and channel-to-channel matching are ideal for
high performance ultrasound systems and for processing I/Q
demodulator signals.
The AD8432 operates on a single supply of 5 V at 24 mA. It is
available in a 4 mm × 4 mm, 24-lead LFSCP. The LFCSP features
an exposed paddle that provides a low thermal resistance path to
the PCB, which enables more efficient heat transfer and increases
reliability. The operating temperature range is −40°C to +85°C.
AD8432 Data Sheet
Rev. C | Page 2 of 32
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
Maximum Power Dissipation ..................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Test Circuits ..................................................................................... 16
Theory of Operation ...................................................................... 18
Low Noise Amplifier (LNA) ..................................................... 18
Gain Setting Technique ............................................................. 18
Active Input Resistance Matching............................................ 19
Applications Information .............................................................. 21
Typical Setup ............................................................................... 21
I/Q Demodulation Front End ................................................... 23
Differential-to-Single-Ended Conversion ............................... 24
Evaluation Board ............................................................................ 25
Connection and Operation ....................................................... 25
Schematic..................................................................................... 28
Outline Dimensions ....................................................................... 29
Ordering Guide .......................................................................... 29
REVISION HISTORY
7/12—Rev. B to Rev. C
Changes to Figure 1 .......................................................................... 1
Changes to Figure 65 ...................................................................... 18
Change to Figure 69 ....................................................................... 21
Changes to Table 7 .......................................................................... 22
Deleted Gain Settings Section and Table 8.................................. 25
Changes to Evaluation Board Section and Figure 73; Added
Connection and Operation Section and Table 8 ........................ 25
Added Figure 74 to Figure 78, Renumbered Sequentially ........ 26
Added Figure 79 .............................................................................. 27
Changes to Figure 80 ...................................................................... 28
Updated Outline Dimensions ....................................................... 29
3/11—Rev. A to Rev. B
Changes to Format ......................................................................... 21
2/10—Rev. 0 to Rev. A
Changes to General Description ..................................................... 1
Changes to Figure 5, Figure 6, Figure 7, Figure 8 .......................... 7
Added Figure 27, Figure 29, and Figure 31, Renumbered
Sequentially ..................................................................................... 11
Added Figure 33 and Figure 35 .................................................... 12
Changes to Figure 58 ...................................................................... 16
10/09—Revision 0: Initial Version
Data Sheet AD8432
Rev. C | Page 3 of 32
SPECIFICATIONS
VS = 5 V, T A = 25°C, RS = RIN = 50 Ω, RFB =150 Ω, CSH = 47 pF, RSH = 15 Ω, RL = 500 Ω (per SE output), CL = 5 pF (per SE output),
G = 12.04 dB (single-ended input to differential output), f = 1 MHz, unless otherwise specified.
Table 1.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
Gain Range Input to differential output (selectable gain) 12.04 24.08 dB
Input to single output (selectable gain) 6.02 18.06 dB
Gain Error 0.1 1 dB
−3 dB Small Signal Bandwidth R
IN
unterminated, R
FB
= ∞, C
SH
= 0 pF, R
SH
= 0 Ω
G = 12.04 dB
200
MHz
G = 18.06 dB 90 MHz
G = 21.58 dB 50 MHz
G = 24.08 dB 32 MHz
−3 dB Large Signal Bandwidth V
OUT
= 2 V p-p 42 MHz
Slew Rate (Rising Edge) V
OUT
= 2 V p-p, f = 10 MHz 295 V/µs
Slew Rate (Falling Edge) V
OUT
= 2 V p-p, f = 10 MHz 170 V/µs
Overdrive Recovery Time 10 ns
DISTORTION/NOISE PERFORMANCE
Input Voltage Noise
RFB = ∞
0.85
nV/√Hz
Input Current Noise R
FB
= ∞ 2.0 pA/√Hz
Noise Figure
Unterminated R
S
= 50 Ω, R
FB
= ∞ 2.8 dB
Active Termination R
S
= R
IN
= 50 Ω, R
FB
= 150 Ω 4.8 dB
RS = 50 Ω, RFB = 226 Ω, RIN = 75 Ω
4.2
dB
R
S
= 50 Ω, R
FB
= 301 Ω, R
IN
= 100 Ω 3.2 dB
R
S
= 50 Ω, R
FB
= 619 Ω, R
IN
= 200 Ω 2.1 dB
R
S
= 50 Ω, R
FB
= 3.57 kΩ, R
IN
= 1 kΩ 2.3 dB
Output Referred Noise G = 12.04 dB, R
FB
= ∞ 3.4 nV/√Hz
G = 18.06 dB, R
FB
= ∞ 6.8 nV/√Hz
G = 21.58 dB, R
FB
= ∞ 10.2 nV/√Hz
G = 24.08 dB, R
FB
= ∞ 13.6 nV/√Hz
Harmonic Distortion
1 MHz (V
OUT
= 1 V p-p) HD2 −67 dBc
HD2, R
S
= 50 Ω, R
IN
unterminated −74 dBc
HD3 −103 dBc
HD3, R
S
= 50 Ω, R
IN
unterminated −106 dBc
1 MHz (V
OUT
= 2 V p-p) HD2 −65 dBc
HD2, R
S
= 50 Ω, R
IN
unterminated −72 dBc
HD3 −103 dBc
HD3, R
S
= 50 Ω, R
IN
unterminated −92 dBc
10 MHz (VOUT = 1 V p-p)
HD2
−66
dBc
HD2, R
S
= 50 Ω, R
IN
unterminated −62 dBc
HD3 −78 dBc
HD3, R
S
= 50 Ω, R
IN
unterminated −73 dBc
10 MHz (V
OUT
= 2 V p-p) HD2 −60 dBc
HD2, R
S
= 50 Ω, R
IN
unterminated −56 dBc
HD3 −72 dBc
HD3, R
S
= 50 Ω, R
IN
unterminated −65 dBc
AD8432 Data Sheet
Rev. C | Page 4 of 32
Parameter Conditions Min Typ Max Unit
Two-Tone IMD3 Distortion R
S
= 50 Ω, R
IN
unterminated
10 MHz V
OUT
= 1 V p-p, f1 = 9.5 MHz, f2 = 10.5 MHz −89.1 dBc
V
OUT
= 2 V p-p, f1 = 9.5 MHz, f2 = 10.5 MHz −66.0 dBc
1 MHz V
OUT
= 1 V p-p, f1 = 0.9 MHz, f2 = 1.1 MHz −88.9 dBc
VOUT = 2 V p-p, f1 = 0.9 MHz, f2 = 1.1 MHz
−73.7
dBc
Input 1dB Compression Point f = 1 MHz 7.5 dBm
f = 10 MHz 7.7 dBm
Output Third-Order Intercept
1 MHz V
OUT
= 1 V p-p of composite tones 29.7 dBV rms
V
OUT
= 2 V p-p of composite tones 28.2 dBV rms
10 MHz V
OUT
= 1 V p-p of composite tones 23.2 dBV rms
V
OUT
= 2 V p-p of composite tones 24.2 dBV rms
1 MHz V
OUT
= 1 V p-p of composite tones, reference to 50 Ω 42.7 dBm
V
OUT
= 2 V p-p of composite tones, reference to 50 Ω 41.2 dBm
10 MHz V
OUT
= 1 V p-p of composite tones, reference to 50 Ω 36.2 dBm
V
OUT
= 2 V p-p of composite tones, reference to 50 Ω 37.2 dBm
Crosstalk
V
OUT
= 1 V p-p, f = 1 MHz 102 dB
DC PERFORMANCE
Input Offset Voltage
−6.25
+1
+6.25
mV
Input Offset Voltage Drift 300 µV/°C
INPUT CHARACTERISTICS
Input Voltage Range AC-coupled 1.2 V p-p
Input Resistance R
FB
= 150 Ω 50 Ω
R
FB
= 226 Ω 75 Ω
R
FB
= 301 Ω 100 Ω
R
FB
= 619 Ω 200 Ω
R
FB
= 3.57 kΩ 1 kΩ
R
FB
= ∞, f = 100 kHz 6.2 kΩ
Input Capacitance 6 pF
Input Common-Mode Voltage 3.25 V
OUTPUT CHARACTERISTCS
Output Common-Mode Voltage 2.5 V
Output Offset Voltage −25 +4 +25 mV
Output Voltage Swing 4.8 V p-p
Output Resistance Single-ended, either output <0.1 Ω
Output Resistance in Shutdown Mode Single-ended, either output 2.5 kΩ
Output Short-Circuit Current R
L
= 10 Ω differential 77 mA
Enable Response Time ENB
ON
(enable high to output on) 200 µs
ENB
OFF
(enable low to output off) 200 µs
POWER SUPPLY
Supply Voltage 4.5 5 5.5 V
Quiescent Current ENB = 5 V 24 mA
Over Temperature T
A
= −40°C 21 mA
TA = +85°C
27
mA
Supply Current in Shutdown Mode ENB = GND 50 100 µA
Power Dissipation 120 mW
PSRR G = 24.08 dB, f = 100 kHz, no bypass capacitors −82 dB
Data Sheet AD8432
Rev. C | Page 5 of 32
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Voltage
Supply Voltage 5.5 V
Input Voltage 0 V to VPS
Power Dissipation 120 mW
Temperature
Operating Temperature –40°C to +85°C
Storage Temperature –65°C to +150°C
Package Glass Transition Temperature (TG)
150°C
Lead Temperature (Soldering, 60 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages. The θJA
value in Table 3 assumes a 4-layer JEDEC standard board with
zero airflow.
Table 3. Thermal Resistance1
Parameter θ
JA
θ
JC
θ
JB
Ψ
JT
Unit
40-Lead LFCSP 57.9 11.2 35.9 1.1 °C/W
1 4-layer JEDEC board (2S2P).
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation for the AD8432 is limited
by the associated rise in junction temperature (TJ) on the die. At
approximately 150°C, which is the glass transition temperature,
the properties of the plastic change. Even temporarily exceeding
this temperature limit may change the stresses that the package
exerts on the die, permanently shifting the parametric performance
of the amplifiers. Exceeding a temperature of 150°C for an
extended period can cause changes in silicon devices, potentially
resulting in a loss of functionality.
ESD CAUTION
AD8432 Data Sheet
Rev. C | Page 6 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
08341-002
2
1
3
4
5
6
18
17
16
15
14
13
INH2
INL2
COMM
IND1
INL1
INH1
GOL2
OPL2
COM2
COM1
OPL1
GOL1
8
9
10
11
7
VPS2
OPH2
GOH2
GMH2
12GML2
IND2
20
19
21
GMH1
GML1
GOH1
22 OPH1
23 VPS1
24 ENB
AD8432
TOP VIEW
(No t t o Scal e)
NOTES
1. EXPOSED PAD MUST BE CONNECT E D
TO GROUND.
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 INH1 LNA1 Noninverting Input.
2 INL1 LNA1 Inverting Input (AC-Coupled to Ground).
3, 7 IND1, IND2 Integrated Input Clamping Back-to-Back Diodes.
4
COMM
Input Ground.
5 INL2 LNA2 Inverting Input (AC-Coupled to Ground).
6 INH2 LNA2 Noninverting Input.
8 VPS2 5 V Supply.
9 OPH2 Noninverting Output of LNA2.
10
GOH2
Gain Setting Pin for LNA2.
11 GMH2 Gain Setting Pin for LNA2.
12 GML2 Gain Setting Pin for LNA2.
13 GOL2 Gain Setting Pin for LNA2.
14 OPL2 Inverting Output of LNA2.
15 COM2 LNA2 Output Ground.
16 COM1 LNA1 Output Ground.
17 OPL1 Inverting Output of LNA1.
18 GOL1 Gain Setting Pin for LNA1.
19 GML1 Gain Setting Pin for LNA1.
20 GMH1 Gain Setting Pin for LNA1.
21 GOH1 Gain Setting Pin for LNA1.
22 OPH1 Noninverting Output of LNA1.
23 VPS1 5 V Supply.
24 ENB Enable.
EPAD Exposed pad must be connected to ground.
Data Sheet AD8432
Rev. C | Page 7 of 32
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25°C, RS = RIN = 50 Ω, RFB =150 Ω, CSH = 47 pF, RSH = 15 Ω, RL =500 Ω (per SE output), CL = 5 pF (per SE output),
G = 12.04 dB (single-ended input to differential output), f = 1 MHz, unless otherwise specified.
08341-003
–30
–24
–12
0
12
6
–6
18
–18
30
24
1 10 100 1k
GAIN (d B)
FREQUENCY (MHz)
G = 24.08d B
G = 21.58d B
G = 18.06d B
G = 12.04d B
Figure 3. Small Signal Differential Gain vs. Frequency, RIN Unterminated
–12
–9
–6
–3
0
12
24
110 100 500
GAIN (d B)
FREQUENCY (MHz)
RIN UNTERMI NATED
RIN = 200Ω
RIN = 100Ω
RIN = 50Ω
08341-004
3
6
9
15
18
21
Figure 4. Small Signal Frequency Response vs. RIN, G = 12.04 dB
–24
–18
–12
–6
0
6
12
18
24
110 100 1k
GAIN (d B)
FREQUENCY (MHz)
R
IN
UNTE RM INATE D
R
IN
= 200Ω
R
IN
= 100Ω
R
IN
= 50Ω
08341-055
Figure 5. Small Signal Frequency Response vs. RIN, G = 18.06 dB
–24
–18
–12
–6
0
6
12
18
24
110 100 1k
GAIN (d B)
FREQUENCY (MHz)
R
IN
UNTE RM INATE D
R
IN
= 200Ω
R
IN
= 100Ω
R
IN
= 50Ω
08341-056
Figure 6. Small Signal Frequency Response vs. RIN, G = 21.58 dB
08341-057
–18
–24
–12
–6
0
6
12
18
24
30
110 100 1k
GAIN (d B)
FREQUENCY (MHz)
R
IN
UNTE RM INATE D
R
IN
= 200Ω
R
IN
= 100Ω
R
IN
= 50Ω
Figure 7. Small Signal Frequency Response vs. RIN, G = 24.08 dB
–18
–24
–12
–6
0
6
12
18
24
30
110 100 1k
GAIN (d B)
FREQUENCY (MHz)
08341-058
G = 24.08d B
G = 21.58d B
G = 18.06d B
G = 12.04d B
Figure 8. Differential Gain vs. Frequency, VOUT = 1 V p-p, RIN = 50 Ω
AD8432 Data Sheet
Rev. C | Page 8 of 32
–24
–12
–6
–18
0
12
30
24
18
6
110 100 1k
GAIN (d B)
FREQUENCY (MHz)
08341-011
G = 24.08d B
G = 21.58d B
G = 18.06d B
G = 12.04d B
Figure 9. Differential Gain vs. Frequency, VOUT = 2 V p-p, RIN = 50 Ω
45
46
47
48
49
51
52
53
54
50
55
0.1 110
FREQUENCY (MHz)
INP UT IM P E DANCE (Ω)
G = 24.08d B
G = 21.58d B
G = 18.06d B
G = 12.04d B
08341-029
Figure 10. Input Impedance RIN vs. Frequency, 50 Ω Active Termination
85
90
95
100
105
110
115
0.1 110
INPUT IMPEDANCE (Ω)
FREQUENCY (MHz)
G = 24.08d B
G = 21.58d B
G = 18.06d B
G = 12.04d B
08341-030
Figure 11. Input Impedance RIN vs. Frequency, 100 Ω Active Termination
0.1 110
FREQUENCY (MHz)
160
170
180
190
200
210
220
230
240
G = 24.08d B
G = 21.58d B
G = 18.06d B
G = 12.04d B
INPUT IMPEDANCE (Ω)
08341-031
Figure 12. Input Impedance RIN vs. Frequency, 200 Ω Active Termination
0.1 110
FREQUENCY (MHz)
0.1
1
10
INPUT IMPEDANCE (kΩ)
G = 24.08d B
G = 21.58d B
G = 18.06d B
G = 12.04d B
08341-032
Figure 13. Input Impedance RIN vs. Frequency, Unterminated
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.1 110 100
OUTPUT IMPEDANCE (Ω)
FREQUENCY (MHz)
08341-033
Figure 14. Output Impedance vs. Frequency
Data Sheet AD8432
Rev. C | Page 9 of 32
0.1 110 100
FREQUENCY (MHz)
0.1
1
10
100
OUTPUT IMPEDANCE (kΩ)
08341-034
Figure 15. Output Impedance vs. Frequency in Disable Mode
0.1
1
10
110 100 1k
INPUT-REFERRED VOLTAGE NOISE (nV/√Hz)
f = 1MHz
SO URCE RE S ISTANCE (Ω)
R
S
THE RM AL
NOISE ALONE
08341-036
Figure 16. Input-Referred Voltage Noise vs. Source Resistance (RS)
1
10
100
110 100 1k
OUTPUT-REFERRED VOLTAGE NOISE (nV/√Hz)
f = 1MHz
SO URCE RE S ISTANCE (Ω)
G = 12.04dB
G = 18.06dB
G = 21.58dB
08341-035
G = 24.08d B
Figure 17. Output-Referred Voltage Noise vs. Source Resistance (RS)
0.70
0.75
0.80
0.85
0.90
0.95
1.00
–50 –30 –10 10 30 50 70 90
INP UT VOLTAGE NOISE (nV/√Hz)
TEMPERAT URE ( °C)
08341-037
Figure 18. Input Voltage Noise vs. Temperature
2
4
6
8
10
12
14
16
–50 –30 –10 10 30 50 70 90
OUTPUT VOLTAGE NOISE (nV/√Hz)
TEMPERAT URE ( °C)
G = 12.04d B
G = 18.06d B
G = 21.58d B
G = 24.08d B
08341-038
Figure 19. Output Voltage Noise vs. Temperature
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.01 0.1 110 100
INP UT VOLTAGE NOISE (nV/√Hz)
FREQUENCY (MHz)
08341-221
G = 24.08d B
G = 21.58d B
G = 18.06d B
G = 12.04d B
Figure 20. Input Voltage Noise vs. Frequency
AD8432 Data Sheet
Rev. C | Page 10 of 32
0
2
4
6
8
10
12
14
16
18
20
0.01 0.1 110 100
OUTPUT VOLTAGE NOISE (nV/√Hz)
FREQUENCY (MHz)
08341-222
G = 24.08d B
G = 21.58d B
G = 18.06d B
G = 12.04d B
Figure 21. Output Voltage Noise vs. Frequency
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
110 100
IM D3 ( dBc)
FREQUENCY (MHz)
LOW TONE
HIGH TONE
08341-223
Figure 22. IMD3 vs. Frequency
0
5
10
15
20
25
30
35
40
45
50
110 100
OIP3 (dBm)
G = 24.08d B
G = 12.04d B
FREQUENCY (MHz)
08341-224
Figure 23. Output Third-Order Intercept vs. Frequency
–110
–100
–90
–80
–70
–60
–50
–40
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
DISTORTION (dBc)
V
OUT
(V p-p)
HD2, 10M Hz
HD2, 1M Hz
HD3, 10M Hz
HD3, 1M Hz
MEASUREMENT
LIMIT
08341-225
Figure 24. Harmonic Distortion vs. Differential Output Voltage, G = 12.04 dB
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
–110
–100
–90
–80
–70
–60
–50
–40
DISTORTION (dBc)
V
OUT
(V p-p)
HD2, 10M Hz
HD2, 1M Hz
HD3, 10M Hz
HD3, 1M Hz
MEASUREMENT
LIMIT
08341-226
Figure 25. Harmonic Distortion vs. Differential Output Voltage, G = 24.08 dB
–90
–80
–70
–60
–50
0 5 10 15 20 25
DISTORTION (dBc)
C
L
(pF)
08341-227
HD2, 10M Hz , 2V p - p
HD2, 10M Hz , 1V p - p
HD3, 10M Hz , 2V p - p
HD3, 10M Hz , 1V p - p
Figure 26. Harmonic Distortion at 10 MHz vs. Capacitive Load (CL),
G = 12.04 dB
Data Sheet AD8432
Rev. C | Page 11 of 32
–110
–100
–90
–80
–70
–60
–50
0 5 10 15 20 25
DISTORTION (dBc)
C
L
(pF)
08341-269
HD2, 1M Hz , 2V p - p
HD2, 1M Hz , 1V p - p
HD3, 1M Hz , 2V p - p
HD3, 1M Hz , 1V p - p
Figure 27. Harmonic Distortion at 1 MHz vs. Capacitive Load (CL),
G = 12.04 dB
–100
–90
–80
–70
–60
–50
–40
0 5 10 15 20 25 30 35
DISTORTION (dBc)
C
L
(pF)
08341-228
HD2, 10M Hz , 2V p - p
HD2, 10M Hz , 1V p - p
HD3, 10M Hz , 2V p - p
HD3, 10M Hz , 1V p - p
Figure 28. Harmonic Distortion at 10 MHz vs. Capacitive Load (CL),
G = 24.08 dB
–120
–110
–100
–90
–80
–70
–60
0 5 10 15 20 25 30 35
DISTORTION (dBc)
C
L
(pF)
08341-270
HD2, 1M Hz , 1V p - p
HD2, 1M Hz , 2V p - p
HD3, 1M Hz , 2V p - p
HD3, 1M Hz , 1V p - p
Figure 29. Harmonic Distortion at 1 MHz vs. Capacitive Load (CL),
G = 24.08 dB
–75
–70
–65
–60
–55
–50
0200 400 600 800 1000 1200 1400 1600 1800 2000
DISTORTION (dBc)
RL (Ω)
08341-229
HD2, 10M Hz , 2V p - p
HD2, 10M Hz , 1V p - p
HD3, 10M Hz , 2V p - p
HD3, 10M Hz , 1V p - p
Figure 30. Harmonic Distortion at 10 MHz vs. Resistive Load (RL),
G = 12.04 dB
–95
–90
–85
–80
–75
–70
–65
–60
0200 400 600 800 1000 1200 1400 1600 1800 2000
DISTORTION (dBc)
RL (Ω)
08341-271
HD2, 1M Hz , 1V p - p
HD2, 1M Hz , 2V p - p
HD3, 1M Hz , 2V p - p
HD3, 1M Hz , 1V p - p
Figure 31. Harmonic Distortion at 1 MHz vs. Resistive Load (RL),
G = 12.04 dB
–95
–90
–85
–80
–75
–70
–65
–60
–55
–50
0200 400 600 800 1000 1200 1400 1600 1800 2000
DISTORTION (dBc)
R
L
(Ω)
HD2, 10M Hz , 2V p - p
HD2, 10M Hz , 1V p - p
HD3, 10M Hz , 2V p - p
HD3, 10M Hz , 1V p - p
08341-230
Figure 32. Harmonic Distortion at 10 MHz vs. Resistive Load (RL),
G = 24.08 dB
AD8432 Data Sheet
Rev. C | Page 12 of 32
–95
–90
–85
–80
–75
–70
–65
–60
0200 400 600 800 1000 1200 1400 1600 1800 2000
DISTORTION (dBc)
R
L
(Ω)
HD2, 1M Hz , 1V p - p
HD2, 1M Hz , 2V p - p
HD3, 1M Hz , 2V p - p
HD3, 1M Hz , 1V p - p
08341-272
Figure 33. Harmonic Distortion at 1 MHz vs. Resistive Load (RL),
G = 24.08 dB
–100
–90
–80
–70
–60
–50
246810 12 14 16 18
DISTORTION (dBc)
GAIN (V/V)
HD2, 10M Hz , 2V p - p
HD2, 10M Hz , 1V p - p
HD3, 10M Hz , 2V p - p
HD3, 10M Hz , 1V p - p
08341-231
Figure 34. Harmonic Distortion at 10 MHz vs. Gain
–110
–100
–90
–80
–70
–60
–50
246810 12 14 16 18
DISTORTION (dBc)
GAIN (V/V)
08341-273
HD2, 1M Hz , 2V p - p
HD2, 1M Hz , 1V p - p
HD3, 1M Hz , 2V p - p
HD3, 1M Hz , 1V p - p
Figure 35. Harmonic Distortion at 1 MHz vs. Gain
–120
–115
–110
–105
–100
–95
–90
–85
–80
–75
–70
0.1 110 100
CROSSTALK (dB)
FREQUENCY (MHz)
08341-232
Figure 36. Channel Crosstalk vs. Frequency
1V/DIV
08341-132
100ns/DIV
Figure 37. Overdrive Recovery, G = 12.04 dB
1V/DIV
08341-013
100ns/DIV
Figure 38. Overdrive Recovery, G = 24.08 dB
Data Sheet AD8432
Rev. C | Page 13 of 32
200mV/DIV
10ns/DIV
G = 12.04d B
G = 18.06d B
G = 21.58d B
G = 24.08d B
08341-014
Figure 39. Small Signal Transient Response vs. Gain, VIN = 100 mV p-p
100mV/DIV
10ns/DIV
08341-015
Figure 40. Small Signal Transient Response, G = 12.04 dB
50mV/DIV
10ns/DIV
C
L
= 15pF
C
L
= 10pF
C
L
= 5pF
08341-016
Figure 41. Small Signal Transient Response vs. Capacitive Load (CL),
G = 12.04 dB
50mV/DIV
10ns/DIV
C
L
= 5pF
C
L
= 10pF
C
L
= 15pF
C
L
= 20pF
C
L
= 30pF
08341-017
Figure 42. Small Signal Transient Response vs. Capacitive Load (CL),
G = 24.08 dB
50mV/DIV
10ns/DIV
R
L
= 499Ω
R
L
= 249Ω
R
L
= 24.9 Ω
R
L
= 15Ω
R
L
= 10Ω
08341-018
Figure 43. Small Signal Transient Response vs. Resistive Load (RL),
G = 12.04 dB
50mV/DIV
10ns/DIV
RL = 499Ω
RL = 249Ω
RL = 24.9Ω
RL = 15Ω
RL = 10Ω
08341-019
Figure 44. Small Signal Transient Response vs. Resistive Load (RL),
G = 24.08 dB
AD8432 Data Sheet
Rev. C | Page 14 of 32
50mV/DIV
10ns/DIV
G = 12.04d B G = 18.06d B
G = 21.58d B
G = 24.08d B
08341-020
Figure 45. Small Signal Transient Response vs. Gain, VOUT = 200 mV p-p
500mV/DIV
10ns/DIV
G = 12.04d B
G = 21.58d B
G = 18.06d B
08341-021
G = 24.08d B
Figure 46. Large Signal Transient Response vs. Gain, VIN = 125 mV p-p
500mV/DIV
10ns/DIV
CL = 20pF
CL = 15pF
CL = 10pF
CL = 5pF
08341-022
Figure 47. Large Signal Transient Response vs. Capacitive Load (CL),
G = 12.04 dB
500mV/DIV
10ns/DIV
C
L
= 30pF
C
L
= 20pF
C
L
= 15pF
C
L
= 10pF
C
L
= 5pF
08341-023
Figure 48. Large Signal Transient Response vs. Capacitive Load (CL),
G = 24.08 dB
500mV/DIV
10ns/DIV
RL = 499Ω
RL = 249Ω
RL = 24.9Ω
RL = 15Ω
08341-024
Figure 49. Large Signal Transient Response vs. Resistive Load (RL),
G = 12.04 dB
500mV/DIV
10ns/DIV
R
L
= 499Ω
R
L
= 249Ω
R
L
= 24.9 Ω
R
L
= 15Ω
R
L
= 10Ω
08341-025
Figure 50. Large Signal Transient Response vs. Resistive Load (RL),
G = 24.08 dB
Data Sheet AD8432
Rev. C | Page 15 of 32
500mV/DIV
10ns/DIV
G = 12.04d B G = 21.58dB
G = 24.08d B
08341-026
G = 18.06d B
Figure 51. Large Signal Transient Response vs. Gain, VOUT = 2 V p-p
–100
–90
–80
–70
–60
–50
–40
–20
–30
0.01 0.1110 100
PSRR ( dB)
FREQUENCY (MHz)
G = 24.08d B
NO BY P AS S CAP S
08341-248
Figure 52. PSRR vs. Frequency
20
22
24
26
28
30
–60 –40 –20 020 40 60 80 100
SUPPLY CURRENT ( mA)
TEMPERAT URE ( °C)
08341-027
Figure 53. Supply Current vs. Temperature
0
20
40
60
80
100
120
140
–60 –40 –20 020 40 60 80 100
SUPPLY CURRENT (µA)
TEMPERAT URE ( °C)
08341-028
Figure 54. Supply Current vs. Temperature in Disable Mode
08341-252
TIME (100µs/DIV)
2
1
ENB
5V/DIV
OUTPUT
50mV/DIV
Figure 55. Small Signal Enable Response
08341-251
TIME (100µs/DIV)
2
1
ENB
5V/DIV
OUTPUT
500mV/DIV
Figure 56. Large Signal Enable Response
AD8432 Data Sheet
Rev. C | Page 16 of 32
TEST CIRCUITS
R
SH
C
SH
R
FB
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
1MHz
(10MHz)
1MHz
(10MHz LPF)
OPL
OPH
SPECTRUM
ANALZYER
R
L
R
L
AD8130
G = 1
475Ω
08341-046
56.2Ω
DUAL FILTER
HP
LP
50Ω
1.7MHz
(10.7MHz)
50Ω
INH
INL
AD8432
LNA1
INH
INL
Figure 57. Harmonic Distortion vs. Resistive Load (RL) Measurements
08341-049
DUAL FILTER
1.7MHz
(10.7MHz)
RSH
CSH
RFB 0.1µF
0.1µF
0.1µF
0.1µF
1MHz
(10MHz)
1MHz
(10MHz LPF)
OPL
OPH
RL
0.1µF 487Ω
487Ω26.1Ω
1:1
26.1Ω
CL
CL
LP
HP IN
50Ω
50Ω
SPECTRUM
ANALYZER
AD8432
LNA1
INH
INL
Figure 58. Harmonic Distortion vs. Capacitive Load (CL) Measurements
08341-047
R
SH
C
SH
R
FB
0.1µF
0.1µF
INH OPL
OPH
INL
0.1µF
0.1µF
0.1µF 499Ω
5pF
499Ω
5pF
DIFF
PROBE
NETWORK
ANALYZER
IN
OUT 50Ω
50Ω
AD8432
LNA1
Figure 59. Frequency Response Measurements
08341-048
0.1µF
0.1µF
OPL
OPH
0.1µF
0.1µF
AD8129
G = 10
1kΩ 50Ω
1kΩ
SPECTRUM
ANALYZER
AD8432
LNA1
INH
INL
Figure 60. Voltage Noise Measurements
Data Sheet AD8432
Rev. C | Page 17 of 32
08341-050
DIFF
PROBE
RSH
RFB
CSH
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF 499Ω
5pF
499Ω
5pF
X
Y
1MHz
MULTIPLIER
CH1
10MHz
OSCILLOSCOPE
INH
INL
AD8432
LNA1
OPL
OPH
Figure 61. Overdrive Recovery Measurements
08341-051
50Ω
0.1µF
INH OPL
OPH 0.1µF
INL
0.1µF 499Ω5pF
0.1µF
5pF499Ω
NETWORK
ANALYZER
OUT 0.1µF
RSH
CSH
RFB
AD8432
LNA1
Figure 62. Input Impedance vs. Frequency Measurements
08341-052
50Ω
0.1µF
INH OPL
OPH 0.1µF
INL
0.1µF 499Ω
0.1µF
NETWORK
ANALYZER
0.1µF
R
SH
C
SH
R
FB
AD8432
LNA1
Figure 63. Output Impedance vs. Frequency Measurements
08341-054
0.1µF
0.1µF
OPL1
OPH1
INH1
INL1
0.1µF
0.1µF AD8129
G = 10
1kΩ 50Ω
1kΩ
–IN
+IN
OUT
SPECTRUM
ANALYZER
0.1µF
R
FB
R
S
AD8432
LNA1
Figure 64. Noise Figure Measurements
AD8432 Data Sheet
Rev. C | Page 18 of 32
THEORY OF OPERATION
LOW NOISE AMPLIFIER (LNA)
The AD8432 is a dual-channel, ultralow noise amplifier with
integrated pin-strappable, gain-setting resistors. The resistors
can be externally connected to achieve differential gains of
12.04 dB, 18.06 dB, 21.58 dB, and 24.08 dB (×4, ×8, ×12, and
×16, respectively). A simplified schematic of an LNA is shown
in Figure 65.
The LNA is driven with a single-ended input and measured
differentially at the output. The inverting input INL must be
ac-coupled to ground through a capacitor for proper operation.
The LNA cannot be driven differentially due to the asymmetry
of the internal gain setting resistors. The gain from the inverting
input INL to the single-ended output (OPH or OPL) does not
match the gain from the noninverting input INH to the single-
ended output.
The AD8432 inputs have a dc bias voltage of 3.25 V, which is
generated internally. The inputs must be ac-coupled through a
series capacitor to maintain the dc bias level of the inputs. Likewise,
the AD8432 outputs have a dc bias voltage of 2.5 V. An ac coupling
capacitor in series with each single-ended output is recommended
to prevent improper loading of the outputs. The AD8432 inputs
have a dc bias voltage of 3.25 V, which is generated internally.
The inputs must be ac-coupled through a series capacitor to
maintain the dc bias level of the inputs (see CINL and CINH
in Figure 65).
The AD8432 supports a differential output voltage of 4.8 V p-p
for the common-mode output voltage of 2.5 V. Therefore, for a
differential gain of G = 12.04 dB, the maximum input voltage
allowed is 1.2 V p-p.
Clamping the inputs ensures quick recovery from large input
voltages. The input back-to-back diodes, which are integrated
inside the die (IND1 and IND2), should be used for the lowest gain
configuration (12.04 dB) to protect the input from overdriving.
They should be connected after the source resistance or before
the INH coupling capacitor.
The use of a fully differential topology and negative feedback
minimizes distortion. A differential signal enables smaller swings at
each output, which results in reduction of third-order distortion.
The AD8432 is a voltage feedback amplifier. Due to gain band-
width product (GBW), a decrease in bandwidth should be
expected as the gain increases. Table 5 displays the values of the
−3 dB bandwidth for each gain with unterminated input
impedance.
GAIN SETTING TECHNIQUE
Pin strapping is used to set the gain of the amplifier. Gain setting
resistors are integrated in the LNA and are accessible externally
through the GOH, GMH, GML, and GOL pins. By externally
shorting these pins, and thereby shorting or connecting the
internal resistors, the AD8432 can be configured for four different
gains. Table 5 shows which pins must be connected to achieve
the desired gain.
RG2
12Ω
RG3
24Ω
RG4
48Ω RG7
48Ω
RG6
24Ω
RG5
24Ω
RG1
12Ω
I I
I I
CINH
INH
OPH
VPS
OPL
INL
R
FB
C
FB
Q2
Q1
GMHGOH GML GOL
CINL
GND
GND
GND
R
SH
R
S
C
SH
V
S
08341-065
Figure 65. Simplified Schematic of a Single LNA Channel, Including External Shunt and Feedback Components
Data Sheet AD8432
Rev. C | Page 19 of 32
Table 5. Gain Setting Using a Pin-Strapping Technique and −3 dB Bandwidth for Each Gain Configuration
Differential
Gain (dB)
Single
Gain (dB)
−3 dB
BW (MHz) RG1 (Ω) RG2 (Ω) RG3 (Ω) RG4 (Ω) RG5 (Ω) RG6 (Ω) RG7 (Ω)
12.04 6.02 200 12 12 Connect
GMH to GOH
Connect
GOH to OPH
24 Connect
GML to GOL
Connect
GOL to OPL
18.06 12.04 90 12 12 24 Connect
GOH to OPH
24 24 Connect
GOL to OPL
21.58 15.56 50 12 12 Connect
GMH to GOH
48 24 Connect
GML to GOL
48
24.08 18.06 32 12 12 24 48 24 24 48
The single-ended gain from INH to OPH (see Figure 65) is
defined as
G1
G4G3G2G1
INHOPH
R
RRRR
G+++
=
−
The single-ended gain from INH to OPL is defined as
G1
G7G6G5
INHOPL
R
RRR
G++
−=
−
The values of the seven gain resistors were chosen so that both
single-ended gains are equal. For example, to set a gain of
12.04 dB (G = ×4) differentially, the gain from INH to each
output (OPH, OPL) should be 6.02 dB (G = ×2).
INH to OPH: For RG1 = RG2 = RG, then
2
2=
×
=
+
=
−
G
G
G1
G2G1
INHOPH
R
R
R
RR
G
INH to OPL: For RG1 = RG and RG5 = 2 × RG, then
2
2−=
×
−=−=
−
G
G
G1
G5
INHOPL
R
R
R
R
G
ACTIVE INPUT RESISTANCE MATCHING
The AD8432 reduces noise and optimizes signal power transfer
by using active input termination to perform signal source
resistance matching.
The primary purpose of input impedance matching is to optimize
the input signal power transfer. With resistive termination, the
input noise increases due to the thermal noise of the terminating
resistor and the increased contribution of the input voltage
noise generator of the LNA. With active impedance matching,
however, the contributions of both are smaller than they are for
resistive termination by a factor of 1/(1 + ½ LNA) gain. The
noise figure (NF) for the three terminating schemes is shown in
Figure 67.
LNA
R
IN
V
IN
V
OUT
R
S
INH
UNTERMINATED
LNA
R
IN
V
IN
V
OUT
R
S
R
S
INH
RESISTIVE
TERMINATION
LNA
R
IN
V
IN
V
OUT
R
S
R
FB
INH
ACTIVE
IM P E DANCE MATCH
08341-009
Figure 66. Input Resistance Matching
To achieve this active impedance match, connect a feedback
resistor, RFB, between the INH and OPL (see Figure 66). RIN is
given in Equation 1, where G/2 is the single-ended gain.
2
1G
R
RFB
IN
+
=
(1)
In addition, to further reduce the input resistance, there is an
internal resistance of 6.2 kΩ in parallel with the source resistance,
such that
INTERNAL
FB
IN R
G
R
R
2
1+
=
(2)
Equation 3 should be used to calculate RFB accurately for a desired
input resistance and single-ended gain. Refer to Table 6 for
calculated results for RFB for several input resistance and gain
combinations.
kΩ2.6,
1
2
1
=
−
+
=⇒ INTERNAL
INTERNAL
IN
IN
FB R
R
R
G
R
R (3)
AD8432 Data Sheet
Rev. C | Page 20 of 32
08341-267
0
1
2
3
4
5
6
7
8
10050 1k
NOISE FIGURE (dB)
R
S
(Ω)
(SIMULATED RESULTS)
ACTIVE IMPE DANCE
MATCH
UNTERMINATED
RESISTIVE TERMINATION
(R
S
= R
IN
)
Figure 67. Noise Figure vs. RS for Resistive, Active Match, and
Unterminated Inputs
08341-268
0
2
6
4
8
10
12
14
16
18
10050 1k
NOISE FIGURE (dB)
RS (Ω)
(SIMULATED RESULTS)
R
IN
= UNTE RM INAT E D
R
IN
= 50Ω
R
IN
= 75Ω
R
IN
= 100Ω
R
IN
= 200Ω
R
IN
= 1kΩ
Figure 68. Noise Figure vs. RS for Various Values of RIN, Actively Matched
The user must determine the level of matching accuracy desired
and adjust RFB accordingly. The RFB and CFB network presents a
load to OPL that OPH does not see. The user can add an identical
load on OPH to improve slightly the distortion caused by this
imbalance.
There is a feedback capacitor (CFB) in series with RFB (see
Figure 65) because the dc levels of the positive output and the
positive input are different. At higher frequencies, the value
of the feedback capacitor must be considered.
The unterminated bandwidth (RFB = ∞) is 200 MHz. The AD8432
has a low input-referred voltage noise of 0.85 nV/√Hz at the
lowest gain, 12.04 dB (unterminated configuration). To achieve
such low noise, the dual amplifier consumes 24 mA, resulting in
a power consumption of 120 mW.
Table 6. Feedback Resistance for Several RIN and Gain Combinations
Desired R
IN
(Ω) Differential Gain (V/V)
Single-Ended Gain,
G/2 (V/V)
Exact RFB (Ω),
Equation 2 R
FB
(Ω), 1% Standard Value
Actual RIN (Ω),
Equation 2
50 4 2 151.2 150 49.6
75 4 2 227.8 226 74.4
100 4 2 304.9 301 98.7
200 4 2 620 619 199.7
1 k 4 2 3.58 k 3.57 k 998.4
50 8 4 252 250 49.6
100 8 4 508.2 511 100.5
50 12 6 352.9 357 50.6
100 12 6 711.5 715 100.5
50 16 8 453.7 453 49.9
100 16 8 914.8 909 99.4
Data Sheet AD8432
Rev. C | Page 21 of 32
APPLICATIONS INFORMATION
The AD8432 LNA provides precision gain and ultralow noise
performance with minimal external components. Because it is
a high performance part, care must be taken to ensure that it is
configured optimally to attain the best performance and dynamic
range for the system.
TYPICAL SETUP
The internal bias circuitry of the AD8432 sets the input bias
voltage at 3.25 V and the output bias voltage at 2.5 V. It is important
to ac couple the inputs through a capacitor to maintain the internal
dc bias levels. When active input termination is used (RFB), a
decoupling capacitor (CFB) is required to isolate the input and
output bias voltages of the LNA. A typical value for CFB is 0.1 µF, but
a smaller value capacitor is more appropriate at higher frequencies.
The unterminated input impedance of the AD8432 is 6.2 kΩ.
Any input resistance between 50 Ω and 6.2 kΩ can be synthesized
using active impedance matching.
At the lowest gain (12.04 dB), the gain response exhibits some
peaking at higher frequencies. A resistor-capacitor shunt net-
work (RC) at the input (see RSHx and CSHx in Figure 69) is
recommended to reduce gain peaking and enhance stability at
higher frequencies.
Table 7 shows the recommended values of RFB, CSH, and RSH for
all four gains and several input impedance combinations. The
values for the CSH and RSH network are determined empirically
and can be customized as needed to optimize performance. As
RIN increases, the value of CSH diminishes, and for higher input
impedance values, no capacitor may be required.
08341-040
R
L
R
SH2
15Ω
C
SH2
47pF
C
L
OUT2+
OUT2–
LNA2
0.1µF
0.1µF
0.1µF
0.1µF
FB
120nH
IN2
INL2
IND2
INH2 OPH2
OPL2
GMH2
GOH2
GOL2
GML2
R
FB2
C
FB2
0.1µF
C
FB1
0.1µF
AD8432
R
L
R
SH1
15Ω
C
SH1
47pF
C
L
OUT1+
OUT1–
LNA1
BIAS
0.1µF
0.1µF
0.1µF
0.1µF 0.1µF
0.1µF
FB
120nH
IN1
INL1
IND1
INH1 OPH1
OPL1
GMH1
GOH1
GOL1
GML1
FB
120nH
R
FB1
G = 12dB
COMM
VPS2
VPS1ENB
Figure 69. Typical AD8432 Setup, G = 12.04 dB
AD8432 Data Sheet
Rev. C | Page 22 of 32
Table 7. External Component Selections for Common Input Impedance
R
IN
(Ω) Gain (dB) R
FB1, 2
(Ω) C
SH1, 2
(pF) R
SH1, 2
(Ω) −3 dB BW (MHz)
50 12 150 47 15 176
18 249 30 15 116
21 357 None None 117
24 453 None None 87
75 12 226 36 15 167
18 383 None None 144
21 536 None None 100
24 681 None None 72
100 12 301 30 15 164
18
511
None
None
134
21 715 None None 90
24 909 None None 63
200
12
619
18
15
164
18 1.02 k None None 116
21 1.43 k None None 74
24 1.87 k None None 51
1 k 12 3.57 k 10 10 160
18 5.9 k None None 99
21 8.25 k None None 61
24 10.7 k None None 43
Unterminated, R
S
= 50 Ω 12 ∞ None None 178
18 ∞ None None 95
21
∞
None
None
59
24
∞
None
None
40
Unterminated, R
S
= 0 Ω 12 ∞ None None 210
18 ∞ None None 96
21 ∞ None None 55
24 ∞ None None 38
Data Sheet AD8432
Rev. C | Page 23 of 32
I/Q DEMODULATION FRONT END
The AD8432 low noise amplifiers can be used to drive the
differential RF inputs of the dual AD8333 or the quad AD8339
I/Q demodulators. The primary application for the AD8339 is
phased array beamforming in medical ultrasound, specifically
in CW Doppler processing. Other applications include phased
array radar and smart antennas for mobile communications.
08341-041
AD8021
AD8021
20Ω787Ω
787Ω
2.2nF
2.2nF
RF1N
RF1P
I1OP
Q1OP
4LO
20Ω
0.1µF
0.1µF
0.1µF
AD8432 AD8339
Q1
I1
Figure 70. Block Diagram of AD8432 and AD8339 Application for
Ultrasound Beamforming
Because of its low output noise and low distortion, the AD8432
ensures minimal degradation in dynamic range while amplifying
the RF input signal. At the lowest gain of 12.04 dB, the AD8432
contributes only 3.4 nV/√Hz output voltage noise.
Figure 70 shows a simplified block diagram of one channel of
the AD8432 driving the AD8339. The AD8432 outputs can be
connected directly to the AD8339 RF inputs through 20 Ω
resistors. A differential clock signal, 4LO, which is applied to the
4LOP and 4LON pins of the AD8339, has a frequency 4× that of
the RF inputs. The AD8339 downconverts the RF signals,
generates quadrature, and phase-shifts the resultant I and Q
signals.
The I and Q outputs of the AD8339 are current outputs. A
transimpedance amplifier, such as the AD8021, processes the
outputs and performs several functions, including the following:
• Current-to-voltage conversion
• Summation amplifier for multiple channels
• Active low-pass filter
In beamforming applications, the I and Q outputs of a number
of receiver channels are summed, which increases the system
dynamic range by 10 log10 (N), where N is the number of
channels being summed. The external RC feedback network of
the AD8021 is a 100 kHz low-pass filter as shown in Figure 70.
See the AD8333 and AD8339 datasheets for more details on
implementing I/Q demodulators.
Evaluation boards are available for the AD8432 and the AD8339
to facilitate system level design and testing. A detailed reference
schematic of the setup is shown in Figure 71. The AD8432 is
shown in this configuration with a gain of 12.04 dB, with
unterminated inputs. If active termination is preferred, use an
RFB and CFB network as discussed in the Theory of Operation
section. The IND1/IND2 clamping diodes can be connected to
IN1/IN2 to protect the LNA input from being overdriven.
08341-043
BIAS
AD8432
INL2
IND2
INH2
INL1
IND1
INH1
ENB VPS1 VPS2 COMM
OPH2
LNA1
LNA2
IN2
IN1
0.1µF
AD8339
RF1P
RF1N
20Ω
20Ω
20Ω
20Ω
RF2P
RF2N
Q1 + Q2
787Ω
0Ω
2 7
34
6
+
–
Q1OP AD8021
VPOS VNEG 4LOP
RSH1
15Ω
G = 12dB
G = –1.3d B
LPF
fC = 100kHz
4LO
CSH1
47
pF
RSH2
15Ω
CSH2
47
pF
0.1µF
0.1µF
0.1µF 0.1µF 0.1µF
0.1µF
0.1µF OPL2
OPH1
OPL1
GMH2
GOH2
GOL2
GML2
GMH1
GOH1
GOL1
GML1
−5V
−5V
+5V
0.1µF
0.1µF
+5V
I1OP
Q2OP
I2OP
2.2nF
I1 + I2
787Ω
0Ω
2 7
34
6
+
–
AD8021
−5V
0.1µF
0.1µF
+5V
2.2nF
Figure 71. Schematic of the AD8432 (G = 12.04 dB) and AD8339 Application for Ultrasound Beamforming
AD8432 Data Sheet
Rev. C | Page 24 of 32
DIFFERENTIAL-TO-SINGLE-ENDED CONVERSION
Some applications require the low noise and high dynamic
range of the AD8432; however, they may also require a single-
ended output, rather than a differential output. The AD8129
or AD8130 differential receiver amplifier can be used for the
differential-to-single-ended conversion of the AD8432 output,
as shown in Figure 72.
The AD8129 is a low noise, high gain (10 or greater) amplifier
intended for applications over very long cables, where signal
attenuation is significant. The AD8130 is stable at a gain of 1
and can be used for applications where lower gains are required.
The AD8129 and AD8130 have user-adjustable gain, set by the
ratio of two resistors, to help compensate for losses in the
transmission line.
A transformer or balun can also be used to convert the differential
output of the AD8432 to a single-ended output. Transformers
have lower distortion; however, care must be taken to properly
match the impedance of the transformer. The test circuit for
distortion measurements in Figure 58 uses an ADTT1-1
transformer to perform differential-to-single-ended conversion.
08341-044
–
–
+
+
1
8
4
5
6
7
2
–V
S
+V
S
V
OUT1
BIAS
INL1
IND1
INH1
ENB VPS1 VPS2 COMM
OPH1
OPL1
LNA1
IN1 20Ω
499Ω 499Ω
20Ω
R
SH1
15Ω
C
SH1
47
pF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
GMH1
GOH1
GOL1
GML1
SERIES 20Ω
RESI STORS IF DRI V ING
HIGH CAP LOAD
AC-COUPLING CAPS
(AD8432 HAS 2.5V
OUT PUT BIAS)
AD8130
499Ω RESISTORS PROVIDE
BIAS CURRE NT PAT H AND
TERM INATI ON I F NECES SARY
G = 12 dB
Figure 72. AD8432 Differential-to-Single-Ended Conversion Using the AD8129/AD8130 with Unity Gain
Data Sheet AD8432
Rev. C | Page 25 of 32
EVALUATION BOARD
Figure 73 is a photo of the AD8432 evaluation board. Completely
assembled and pretested, the board provides convenient and fast
verification of system design and to assess the performance of
the AD8432 under user-specific operating conditions. The
remainder of this section describes the operation and construction
of the board.
Figure 74 through Figure 79 are various artwork and assembly
views and Figure 80 shows the schematic diagram. The board
provides access to the inputs, the outputs, and the gain settings.
As shipped, the board is configured for a gain of 21 dB and 50 Ω
input termination. Multiple combinations of gain and impedance
matching are available to the user.
08341-073
Figure 73. Evaluation Board
CONNECTION AND OPERATION
Power Supply
The AD8432 requires only a single 5 V supply connected to the
+5V red test loop and black test loop GND next to it. Separate
power pins are provided for the two LNA channels, but the two
amplifier sections are wired together and rf-decoupled by small
inductors as a precaution. The remaining red test loops are for
pin probing as necessary. Should the need for amplifier isolation
arise, simply un-power the unneeded amplifier by removing L3
or L4. (Refer to Figure 74 and Figure 80.
Input Termination
The AD8432 features active input termination and boards are
shipped for 50 Ω. The input impedance is determined by the LNA
gain, and the feedback resistors RFB1 and RFB2 (see the schematic in
Figure 80) and source impedance (refer to the Theory of Operation
section and Table 7). CFB provides the necessary ac coupling
between the input and output when using active termination; a
0.1 µF capacitor is recommended. The RFB and CFB network
presents a load to the OPL; if needed, an equivalent load at OPH
balances the differential output.
Switches CLAMP1 and CLAMP2 connect the input clamping
diodes (IND1 and IND2) across the signal path. The diodes provide
input overvoltage protection in applications where fast transient
pulses exceeding 5.5 V or less than –0.6 V are present. Clamping
diodes enable faster overdrive recovery times, especially at the
lowest gain (12.04 dB). Fast transients are usually not fatal to
the device, which features ESD protection in any event.
Setting the Amplifier Gain
The violet test loops OPnn, GOnn and GMnn and Resistors
R1–R4 and Resistors R9–R12 are provided for gain adjustment.
Install 0 Ω resistors to reduce gain, leaving the positions open to
increase gain. As shipped, the evaluation board is configured for
G = 21 dB (12×). Table 8 lists the configuration for the four
available LNA gain values.
Table 8. Gain Setting Configuration
LNA1 LNA2 GAIN dB(×)
8(4) 18(8) 21(12) 24(16)
R1 R9 Y
1
Y
1
open open
R2 R10 Y
1
open Y
1
open
R3 R11 Y1 open Y1 open
R4 R12 Y1 Y1 open open
1 Y = Install 0 Ω.
Output
The 4-pin headers PR1OUT and PR2OUT are placed close to
the AD8432, and provide a way for monitoring the differential
output or the single-ended output using a high impedance
differential probe. The two inner pins of the headers are connected
to OPL/OPH, and the two outer pins of the headers are connected
to ground.
AD8432 Data Sheet
Rev. C | Page 26 of 32
08341-074
Figure 74. Evaluation Board Assembly
08341-075
Figure 75. AD8432 Primary Side Copper
08341-076
Figure 76. AD8432-EVALZ Secondary Side Copper
08341-077
Figure 77. AD8432-EVALZ Power Plane Copper
08341-078
Figure 78. AD8432-EVALZ Ground Plane Copper
Data Sheet AD8432
Rev. C | Page 27 of 32
SIGNAL
GENERATOR
33250A OR E QUIV
DIFFERENTIAL
PROBE
P6247 O R E QUIV
OSCILLOSCOPE
POWER SUPPLY
08341-079
Figure 79. Bench Setup for Testing the AD8432-EVALZ
AD8432 Data Sheet
Rev. C | Page 28 of 32
SCHEMATIC
PIN 1 IDENTIFIER
PIN 0
EXPOSED PADDLE
CONNECTED TO GROUND
INH1
INL1
IND1
COMM
INL2
INH2
G0L1
OPL1
COM1
COM2
OPL2
G0L2
ENB VPS1 OPH1 GOH1
GOH2
GMH1 GML1
IND2 VPS2 OPH2 GMH2 GML2
1
2
3
4
5
6
24 23 22 21 20 19
7 8 9 10 11 12
18
17
16
15
14
13
C1
0.1µF
C2
0.1µF
C6
0.1µF
C3
0.1 µF
L3
120nH FB
C4
0.1µF
C5
0.1µF
IN1
CSH1
47pF
L1
120nH FB
PR1
PR2
RSH1
15Ω
IN2 L2
120nH FB
CLAMP1
CLAMP2
RFB1
357Ω
CFB1
0.1µF
RFB2
357Ω
CFB2
0.1µF
PRB3
PRB4
ON
OFF
INH1
INL1
INL2
INH2
TPENB
OPH1
G0H1 GMH1 GML1
G0L1
OPL1
OPL2
G0L2
GML2
G0H2 GMH2
R1
0Ω
DNI R2
0ΩR3
0Ω
R4
0Ω
DNI
R12
0Ω
R11
0Ω
+5V
L4
120nH FB
+VCH2
VPOS
COM1
COM2
COMM
ENB
CSH2
47pF
RSH2
15Ω
R9
0ΩR10
0Ω
GND1 GND2 GND3 GND5 GND6GND4
OPH2
GND C11
10µF
10V
VPOS
VPOS
VPOS +VCH1
08341-080
Figure 80. AD8432-EVALZ Schematic
Data Sheet AD8432
Rev. C | Page 29 of 32
OUTLINE DIMENSIONS
0.50
BSC
0.50
0.40
0.30
0.30
0.25
0.18
COMPLIANT
TO
JEDEC S TANDARDS MO-220-WGGD.
04-12-2012-A
BOTTOM VIEWTOP VI EW
EXPOSED
PAD
PI N 1
INDICATOR
4.10
4.00 S Q
3.90
SEATING
PLANE
0.80
0.75
0.70
0.20 RE F
0.25 M IN
COPLANARITY
0.08
PI N 1
INDICATOR
2.65
2.50 S Q
2.45
1
24
7
12
13
1819
6
FOR PRO P E R CONNECT ION OF
THE EXPOSED PAD, REFER TO
THE P IN CONFIGURATION AND
FUNCTION DESCRIPT IONS
SECTION OF THIS DATA SHEET.
0.05 M AX
0.02 NOM
Figure 81. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm, Very Very Thin Quad
(CP-24-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Temperature Range Package Description Package Option
AD8432ACPZ-R7 −40°C to +85°C 24-Lead LFCSP_WQ, 7” Tape and Reel CP-24-7
AD8432ACPZ-RL −40°C to +85°C 24-Lead LFCSP_WQ, 13” Tape and Reel CP-24-7
AD8432ACPZ-WP −40°C to +85°C 24-Lead LFCSP_WQ, Waffle Pack CP-24-7
AD8432-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
AD8432 Data Sheet
Rev. C | Page 30 of 32
NOTES
Data Sheet AD8432
Rev. C | Page 31 of 32
NOTES
