5-552
FAST AND LS TTL DATA
SN74LS395
LOGIC DIAGRAM
S
Ds
CP
MR
OE
P0P1P2P3
O0O1O2O3Q3
CP D
CD Q
CP D
CD Q
CP D
CD Q
CP D
CD Q
FUNCTION DESCRIPTION
The SN74LS395 contains four D-type edge-triggered
flip-flops and auxiliary gating to select a D input either from a
Parallel (Pn) input or from the preceding stage. When the
Select input is HIGH, the Pn inputs are enabled. A LOW signal
on the S input enables the serial inputs for shift-right opera-
tions, as indicated in the Truth Table.
State changes are initiated by HIGH-to-LOW transitions on
the Clock Pulse (CP) input. Signals on the Pn, Ds and S inputs
can change when the Clock is in either state, provided that the
recommended set-up and hold times are observed. When the
S input is LOW, a CP HIGH-LOW transition transfers data in
Q0 to Q1, Q1 to Q2, and Q2 to Q3. A left-shift is accomplished
by connecting the outputs back to the Pn inputs, but offset one
place to the left, i.e., O3 to P2, O2 to P1 and O1 to P0, with P3
acting as the linking input from another package.
When the OE input is HIGH, the output buffers are disabled
and the Q0–Q3 outputs are in a high impedance condition.
The shifting, parallel loading or resetting operations can still be
accomplished, however.
MODE SELECT — TRUTH TABLE
Inputs @ tnOutputs @ tn+1
Operating Mode MR CP S DsPnO0O1O2O3
Asynchronous Reset L X X X X L L L L
Shift, SET First Stage H L H X H O0n O1n O2n
Shift, RESET First Stage H L L X L O0n O1n O2n
Parallel Load H H X PnP0P1P2P3
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
tn, n + 1 = time before and after CP HIGH-to-LOW transition
NOTE:
When OE is HIGH, outputs O0–O3 are in the high impedance state; however , this does not affect other operations or the Q3 output.
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 4.75 5.0 5.25 V
TAOperating Ambient Temperature Range 0 25 70 °C
IOH Output Current — High –0.4 mA
IOL Output Current — Low 8.0 mA