DM2200 EDRAM 4Mb x 1 Enhanced Dynamic RAM Enhanced Memory Systems Inc. Product Specification Features 2Kbit SRAM Cache Memory for 12ns Random Reads Within a Page Fast 4Mbit DRAM Array for 30ns Access to Any New Page Write Posting Register for 12ns Random Writes and Burst Writes Within a Page (Hit or Miss) 256-byte Wide DRAM to SRAM Bus for 14.2 Gigabytes/Sec Cache Fill On-chip Cache Hit/Miss Comparators Maintain Cache Coherency on Writes Description Architecture The 4Mb Enhanced DRAM (EDRAM) combines raw speed with innovative architecture to offer the optimum cost-performance solution for high performance local or system main memory. In most high speed applications, no-wait-state performance can be achieved without secondary SRAM cache and without interleaving main memory banks at system clock speeds through 50MHz. Two-way interleave will allow nowait-state operation at clock speeds greater than 100MHz without the need of secondary SRAM cache. The EDRAM outperforms conventional SRAM cache plus DRAM memory systems by minimizing processor wait states for all possible bus events, not just cache hits. The combination of data and address latching, 2K of fast on-chip SRAM cache, and simplified on-chip cache control allows system level flexibility, performance, and overall memory cost reduction not available with any other high density memory component. Architectural similarity with JEDEC DRAMs allows a single memory controller design to support either slow JEDEC DRAMs or high speed EDRAMs. A system designed in this manner can provide a simple upgrade path to higher system performance. The EDRAM architecture has a simple integrated SRAM cache which allows it to operate much like a page mode or static column DRAM. The EDRAM's SRAM cache is integrated into the DRAM array as tightly coupled row registers. Memory reads always occur from the cache row register. When the internal comparator detects a page hit, only the SRAM is accessed and data is available in 12ns from column address. When a page read miss is detected, the new DRAM row is loaded into the cache and data is available at the output all within 30ns from row enable. Subsequent reads within the page (burst reads or random reads) can continue at 12ns cycle time. Since reads occur from the SRAM cache, the DRAM precharge can occur simultaneously without degrading performance. The on-chip refresh counter with independent refresh bus allows the EDRAM to be refreshed during cache reads. Memory writes are internally posted in 12ns and directed to the DRAM array. During a write hit, the on-chip address comparator activates a parallel write path to the SRAM cache to maintain coherency. The EDRAM delivers 12ns cycle page mode memory Hidden Precharge and Refresh Cycles Extended 64ms Refresh Period for Low Standby Power 300 Mil Plastic SOJ and TSOP-II Package Options +5 and +3.3 Volt Power Supply Voltage Options Low Power, Self Refresh Mode Option Industrial Temperature Range Option TSOP-II Pin Configuration Functional Diagram Column Add Latch /CAL A0-10 Column Decoder Q 2048 X 1 Cache (Row Register) 11 Bit Comp D Sense Amps & Column Write Select Last Row Read Add Latch Row Add Latch /F W/R /RE Memory Array (2048 X 2048) A0-9 Row Add and Refresh Control I/O Control and Data Latches /S Row Decoder A0-10 /G Refresh Counter /WE VCC VSS SOJ Pin Configuration NC 1 44 VSS * A0 2 43 VSS NC 3 42 VSS A1 4 41 Q NC 5 40 D 6 39 NC A0 A1 1 2 28 27 VSS A3 A4 7 38 NC A3 8 37 NC A4 26 25 D NC 3 4 A5 9 36 /G A5 5 24 NC 6 23 7 22 /G VCC Q NC /RE 10 35 VCC VCC 11 34 VCC VSS 12 33 VSS /RE VCC VSS 13 32 VSS VSS 8 21 VSS A6 14 31 /WE 9 20 A7 15 30 /S A8 16 29 /F A6 A7 10 19 /WE /S NC 17 28 NC A8 11 18 A2 18 27 W/R A2 12 17 NC 19 26 NC A9 13 16 A9 20 25 /CAL VCC 14 15 VCC 21 24 A10 VCC* 22 23 NC /F W/R /CAL A 10 * Reserved for future use The information contained herein is subject to change without notice. Enhanced reserves the right to change or discontinue this product without notice. (c) 1996 Enhanced Memory Systems Inc., 1850 Ramtron Drive, Colorado Springs, CO Telephone (800) 545-DRAM; Fax (719) 488-9095; http://www.csn.net/ramtron/enhanced 80921 38-2108-001 clocked to latch the column address. In page mode, data valid time is determined by either tAC or tCQV. writes. Memory writes do not affect the contents of the cache row register except during a cache hit. By integrating the SRAM cache as row registers in the DRAM array and keeping the on-chip control simple, the EDRAM is able to provide superior performance over standard slow 4Mb DRAMs. By eliminating the need for SRAMs and cache controllers, system cost, board space, and power can all be reduced. Functional Description The EDRAM is designed to provide optimum memory performance with high speed microprocessors. As a result, it is possible to perform simultaneous operations to the DRAM and SRAM cache sections of the EDRAM. This feature allows the EDRAM to hide precharge and refresh operation during SRAM cache reads and maximize SRAM cache hit rate by maintaining valid cache contents during write operations even if data is written to another memory page. These new functions, in conjunction with the faster basic DRAM and cache speeds of the EDRAM, minimize processor wait states. EDRAM Basic Operating Modes The EDRAM operating modes are specified in the table below. Hit and Miss Terminology In this datasheet, "hit" and "miss" always refer to a hit or miss to the page of data contained in the SRAM cache row register. This is always equal to the contents of the last row that was read from (as modified by any write hit data). Writing to a new page does not cause the cache to be modified. DRAM Read Miss A DRAM read request is initiated by clocking /RE with W/R low and /F & /CAL high. The EDRAM compares the new row address to the LRR address latch (an 11-bit latch loaded on each /RE active read miss cycle). If the row address does not match the LRR, the requested data is not in SRAM cache and a new row must be fetched from the DRAM. The EDRAM will load the new row data into the SRAM cache and update the LRR latch. The data at the specified column address is available at the output pins at the greater of times tRAC, tAC, and tGQV. It is possible to bring /RE high after time tRE since the new row data is safely latched into SRAM cache. This allows the EDRAM to precharge the DRAM array while data is accessed from SRAM cache. It is possible to access additional SRAM cache locations by providing new column addresses to the multiplex address inputs. New data is available at the output at time tAC after each column address change. During read cycles, it is possible to operate in either static column mode with /CAL=high or page mode with /CAL clocked to latch the column address. In page mode, data valid time is determined by either tAC or tCQV. DRAM Write Hit If a DRAM write request is initiated by clocking /RE while W/R, /CAL, /WE, and /F are high, the EDRAM will compare the new row address to the LRR address latch (an 11-bit address latch loaded on each /RE active read miss cycle). If the row address matches, the EDRAM will write data to both the DRAM array and selected SRAM cache simultaneously to maintain coherency. The write DRAM Read Hit address and data are posted to the DRAM as soon as the column A DRAM read request is initiated by clocking /RE with W/R low address is latched by bringing /CAL low and the write data is and /F & /CAL high. The EDRAM compares the new row address to latched by bringing /WE low. The write address and data can be the last row read address latch (LRR - an 11-bit latch loaded on latched very quickly after the fall of /RE (tRAH + tASC for the column each /RE active read miss cycle). If the row address matches the address and tDS for the data). During a write burst sequence, the LRR, the requested data is already in the SRAM cache and no second write data can be posted at time tRSW after /RE. Subsequent DRAM memory reference is initiated. The data specified by the writes within a page can occur with write cycle time tPC. With /G column address is available at the output pins at the greater of enabled and /WE disabled, it is possible to perform cache read times tAC or tGQV. Since no DRAM activity is initiated, /RE can be operations while the /RE is activated in write hit mode. This allows brought high after time tRE1, and a shorter precharge time, tRP1, is read-modify-write, write-verify, or random read-write sequences allowed. It is possible to access additional SRAM cache locations by within the page with 12ns cycle times (the first read cannot providing new column addresses to the multiplex address inputs. complete until after time tRAC2). At the end of a write sequence New data is available at the output at time tAC after each column (after /CAL and /WE are brought high and tRE is satisfied), /RE can address change. During read cycles, it is possible to operate in be brought high to precharge the memory. It is possible to perform either static column mode with /CAL=high or page mode with /CAL EDRAM Basic Operating Modes Function /S /RE W/R /F /CAL /WE A0-10 Read Hit L L H H X Row = LRR No DRAM Reference, Data in Cache Read Miss L L H H X Row LRR DRAM Row to Cache Write Hit L H H H H Row = LRR Write to DRAM and Cache, Reads Enabled Write Miss L H H H H Row LRR Write to DRAM, Cache Not Updated, Reads Disabled Internal Refresh X X L X X X Cache Reads Enabled Low Power Standby H H X X H H X 1mA Standby Current Unallowed Mode H L X H X X X Unallowed Mode (Except -L Option) Low Power Self-Refresh Option H H H L H X Standby Current, Internal Refresh Clock (-L Option) H = High; L = Low; X = Don't Care; = High-to-Low Transition; LRR = Last Row Read 1-2 Comment cache reads concurrently with precharge. During write sequences, a write operation is not performed unless both /CAL and /WE are low. As a result, the /CAL input can be used as a byte write select in multi-chip systems. the output pin Q (as shown below). The specific databit selected to the output is determined by column addresses A9 and A10. System operation is consistent with the standard "Functional Description" and timing diagrams shown in this specification. See the note in the read timing diagrams and "Switching Characteristics" chart for the DRAM Write Miss faster access and data hold times. If a DRAM write request is initiated by clocking /RE while W/R, /CAL, /WE, and /F are high, the EDRAM will compare the new row Internal Refresh If /F is active (low) on the assertion of /RE, an internal refresh address to the LRR address latch (an 11-bit latch loaded on each /RE active read miss cycle). If the row address does not match, the cycle is executed. This cycle refreshes the row address supplied by EDRAM will write data to the DRAM array only and contents of the an internal refresh counter. This counter is incremented at the end of the cycle in preparation for the next /F refresh cycle. At least current cache are not modified. The write address and data are 1,024 /F cycles must be executed every 64ms. /F refresh cycles can posted to the DRAM as soon as the column address is latched by be hidden because cache memory can be read under column bringing /CAL low and the write data is latched by bringing /WE address control throughout the entire /F cycle. low. The write address and data can be latched very quickly after the fall of /RE (tRAH + tASC for the column address and tDS for the data). During a write burst sequence, the second write data can be DM2200 Datapath Architecture posted at time tRSW after /RE. Subsequent writes within a page can occur with write cycle time tPC. During a write miss sequence, EDRAM Row Address 4M DRAM Array cache reads are inhibited and the output buffers are disabled A0-10 (independently of /G) until time tWRR after /RE goes high. At the 2,048 Bits end of a write sequence (after /CAL and /WE are brought high and tRE is satisfied), /RE can be brought high to precharge the memory. EDRAM Column Address It is possible to perform cache reads concurrently with the 2K SRAM Cache A2-10 precharge. During write sequences, a write operation is not 128 Bits performed unless both /CAL and /WE are low. As a result, /CAL can be used as a byte write select in multi-chip systems. /RE Inactive Operation It is possible to read data from the SRAM cache without clocking /RE. This option is desirable when the external control logic is capable of fast hit/miss comparison. In this case, the controller can avoid the time required to perform row/column multiplexing on hit cycles. This capability also allows the EDRAM to perform cache read operations during precharge and refresh cycles to minimize wait states and reduce power. It is only necessary to select /S and /G and provide the appropriate column address to read data as shown in the table below. The row address of the SRAM cache accessed without clocking /RE will be specified by the LRR address latch loaded during the last /RE active read cycle. To perform a cache read in static column mode, /CAL is held high, and the cache contents at the specified column address will be valid at time tAC after address is stable. To perform a cache read in page mode, /CAL is clocked to latch the column address. The cache data is valid at time tAC after the column address is setup to /CAL. On-Chip SRAM Interleave The DM2200 has an on-chip interleave of its SRAM cache which allows 8ns random accesses (tAC1) for up to three data words (burst reads) following an initial read access (hit or miss). The SRAM cache is integrated into the DRAM arrays in a 512 x 4 organization. It is converted into a 2K x 1 page organization by using an on-chip address multiplexer to select one of four bits to Function /S /G /CAL A0-8 Cache Read (Static Column) L L H Column Address Cache Read (Page Mode) L L Column Address H = High; L = Low; X = Don't Care; = Transitioning Column Address A9,A10 4 to 1 Output Selector 1 Bit Q Low Power Mode The EDRAM enters its low power mode when /S is high. In this mode, the internal DRAM circuitry is powered down to reduce standby current to 1mA. Low Power, Self-Refresh Option When the low power, self-refresh option is specified when ordering the EDRAM, the EDRAM enters this mode when /RE is clocked while /S, W/R, /F, and /WE are high; and /CAL is low. In this mode, the power is turned off to all I/O pins except /RE to minimize chip power, and an on-board refresh clock is enabled to perform self-refresh cycles using the on-board refresh counter. The EDRAM remains in this low power mode until /RE is brought high again to terminate the mode. The EDRAM /RE input must remain high for tRP2 following exit from self-refresh mode to allow any ongoing internal refresh to terminate prior to the next memory operation. +3.3 Volt Power Supply Operation If the +3.3 volt power supply option is specified, the EDRAM will operate from a +3.3 volt 0.3 volt power supply and all inputs and outputs will have LVTTL/LVCMOS compatible signal levels. The +3.3 volt EDRAM will not accept input levels which exceed the power supply voltage. If mixed I/O levels are expected in your system, please specify the +5 volt version of the EDRAM. /CAL Before /RE Refresh ("/CAS Before /RAS") /CAL before /RE refresh, a special case of internal refresh, is discussed in the "Reduced Pin Count Operation" section below. 1-3 /RE Only Refresh Operation Although /F refresh using the internal refresh counter is the recommended method of EDRAM refresh, it is possible to perform an /RE only refresh using an externally supplied row address. /RE refresh is performed by executing a write cycle (W/R and /F are high) where /CAL is not clocked. This is necessary so that the current cache contents and LRR are not modified by the refresh operation. All combinations of addresses A0-9 must be sequenced every 64ms refresh period. A10 does not need to be cycled. Read refresh cycles are not allowed because a DRAM refresh cycle does not occur when a read refresh address matches the LRR address latch. Initialization Cycles A minimum of 10 initialization (start-up) cycles are required before normal operation is guaranteed. At least eight /F refresh cycles and two read cycles to different row addresses are necessary to complete initialization. /RE must be high for at least 300ns prior to initialization. Unallowed Mode Read, write, or /RE only refresh operations must not be performed to unselected memory banks by clocking /RE when /S is high. Reduced Pin Count Operation Although it is desirable to use all EDRAM control pins to optimize system performance, it is possible to simplify the interface to the EDRAM by either tying pins to ground or by tying one or more control inputs together. The /S input can be tied to ground if the low power standby modes are not required. The /CAL and /F pins can be tied together if hidden refresh operation is not required. In this case, a CBR refresh (/CAL before /RE) can be performed by holding the combined input low prior to /RE. A CBR refresh does not require that a row address be supplied when /RE is asserted. The timing is identical to /F refresh cycle timing. The /WE input can be tied to /CAL if independent posting of column addresses and data are not required during write operations. In this case, both column address and write data will be latched by the combined input during writes. W/R and /G can be tied together if reads are not performed during write hit cycles. If these techniques are used, the EDRAM will require only three control lines for operation (/RE, /CAS [combined /CAL, /F, and /WE], and W/R [combined W/R and /G]). The simplified control interface still allows the fast page read/write cycle times, fast random read/write times, and hidden precharge functions available with the EDRAM. Pin Descriptions /RE -- Row Enable This input is used to initiate DRAM read and write operations and latch a row address. It is not necessary to clock /RE to read data from the EDRAM SRAM row registers. On read operations, /RE can be brought high as soon as data is loaded into cache to allow early precharge. /CAL -- Column Address Latch This input is used to latch the column address and in combination with /WE to trigger write operations. When /CAL is high, the column address latch is transparent. When /CAL is low, the column address latch is closed and the output of the latch contains the address present while /CAL was high. W/R -- Write/Read This input along with /F specifies the type of DRAM operation initiated on the low going edge of /RE. When /F is high, W/R specifies either a write (logic high) or read operation (logic low). /F -- Refresh This input will initiate a DRAM refresh operation using the internal refresh counter as an address source when it is low on the low going edge of /RE. /WE -- Write Enable This input controls the latching of write data on the input data pins. A write operation is initiated when both /CAL and /WE are low. /G -- Output Enable This input controls the gating of read data to the output data pins during read operations. /S -- Chip Select This input is used to power up the I/O and clock circuitry. When /S is high, the EDRAM remains in its low power mode. /S must remain active throughout any read or write operation. With the exception of /F refresh cycles, /RE should never be clocked when /S is inactive. D -- Data Input This input pin is used to write data to the EDRAM. Q -- Data Output This output pin is used to read data from the EDRAM. A0-10 -- Multiplex Address These inputs are used to specify the row and column addresses of the EDRAM data. The 11-bit row address is latched on the falling edge of /RE. The11-bit column address can be specified at any other time to select read data from the SRAM cache or to specify the write column address during write cycles. VCC Power Supply These inputs are connected to the +5 or +3.3 volt power supply. VSS Ground These inputs are connected to the power supply ground connection. Pin Names Pin Names Function Pin Names Function A0-10 Address Inputs VSS Ground /RE Row Enable /WE Write Enable D Data In /G Output Enable Q Data Out /F Refresh Control /CAL Column Address Latch /S Chip Select - Active/Standby Control W/R Write/Read Control NC No Connection VCC Power (+5V or +3.3V) 1-4 AC Test Load and Waveforms Load Circuit VIN Timing Reference Point at VIL and VIH Input Waveforms + 5.0 (+3.3 Volt Option) Output VIH (5.0 volt) R1 = 828 R1 = 1178 VIH (3.3 Volt Option) CL = 50pf R2 = 295 (5.0 volt) VIL GND VIL 5ns R2 = 868 (3.3 Volt Option) Absolute Maximum Ratings 5ns Capacitance (Beyond Which Permanent Damage Could Result) Description 3.3V Option Rating Ratings Input Voltage (VIN) - .5 ~ 4.6v - 1 ~ 7v Output Voltage (VOUT) - .5 ~ 4.6v - 1 ~ 7v Power Supply Voltage (VCC) - .5 ~ 4.6v - 1 ~ 7v Ambient Operating Temperature (TA) -40 ~ 85C -40 ~ 85C -55 ~ 150C -55 ~ 150C Static Discharge Voltage (Per MIL-STD-883 Method 3015) Class 1 Class 1 Short Circuit O/P Current (IOUT) 20mA 50mA Description Storage Temperature (TS) Input Capacitance Input Capacitance (1) 7pf, 10pf A0-9 A10, /CAL, /RE, W/R, /WE, /F, /S /G Input Capacitance 6pf D Output Capacitance 6pf Q (1) +5 V, DM2200-15 only. TA = 0 to 70C (Commercial); -40 to 85C (Industrial) 3.3V Option Parameters Min Max Min Max Supply Voltage 3.0V 3.6V 4.75V 5.25V VIH Input High Voltage 2.0V VCC+0.3V 2.4V Vcc+0.5V VIL Input Low Voltage Vss-0.3V 0.8V Vss-0.5V 0.8V VOH Output High Level 2.4V VOL Output Low Level Ii(L) Input Leakage Current -5A 5A IO(L) Output Leakage Current -5A 5A Operating Current 6pf, 7pf 2pf VCC Symbol Pins (1) Input Capacitance Electrical Characteristics Symbol Max Test Conditions All Voltages Referenced to VSS IOUT = - 5mA (-2ma For 3.3 Volt Option) 2.4V 0.4V IOUT = 4.2mA (2ma For 3.3 Volt Option) -10A 10A OV VIN Vcc + 0.5 Volts -10A 10A O VI/O Vcc 0.4V 33MHz Typ (1) -12 Max -15 Max Test Condition Notes ICC1 Random Read 110mA 225mA 180mA /RE, /CAL, and Addresses Cycling: tC = tC Minimum 2, 3, 5 ICC2 Fast Page Mode Read 65mA 145mA 115mA /CAL and Addresses Cycling: tPC = tPC Minimum 2, 4, 5 ICC3 Static Column Read 55mA 110mA 90mA Addresses Cycling: tSC = tSC Minimum 2, 4, 5 ICC4 Random Write 135mA 190mA 150mA /RE, /CAL, /WE, and Addresses Cycling: tC = tC Minimum 2, 3 ICC5 Fast Page Mode Write 50mA 135mA 105mA /CAL, /WE, and Addresses Cycling: tPC = tPC Minimum 2, 4 ICC6 Standby 1mA 1mA 1mA All Control Inputs Stable VCC - 0.2V, Output Driven ICC7 Self-Refresh Option (-L) 200 A 200 A 200 A 30mA -- -- ICCT Average Typical Operating Current /S, /F, W/R, /WE, and A0-10 at VCC - 0.2V /RE and /CAL at VSS + 0.2V, I/O Open See "Estimating EDRAM Operating Power" Application Note 1 (1) "33MHz Typ" refers to worst case ICC expected in a system operating with a 33MHz memory bus. See power applications note for further details. This parameter is not 100% tested or guaranteed. (2) ICC is dependent on cycle rates and is measured with CMOS levels and the outputs open. (3) ICC is measured with a maximum of one address change while /RE = VIL. (4) ICC is measured with a maximum of one address change while /CAL = VIH. (5) /G is high. 1-5 Switching Characteristics VCC = 5V 5% (+5 Volt Option), VCC = 3.3V 0.3V (+3.3 Volt Option), CL = 50pf, TA = 0 to 70C (Commercial) ,TA = -40 to 85C (Industrial) -12 Symbol tAC(1) Description Min Column Address Access Time for Addresses A0-8 (1) tAC1 Column Address Access Time for Addresses A9 and A10 tACH Column Address Valid to /CAL Inactive (Write Cycle) tAQX -15 Max Min Max Units 12 15 ns 8 8 ns 12 15 ns Column Address Change to Output Data Invalid for Addresses A0-8 5 5 ns tAQX1 Column Address Change to Output Data Invalid for Addresses A9 and A10 1 1 ns tASC Column Address Setup Time 5 5 ns tASR Row Address Setup Time 5 5 ns tC Row Enable Cycle Time 55 65 ns tC1 Row Enable Cycle Time, Cache Hit (Row=LRR), Read Cycle Only 20 25 ns tCAE Column Address Latch Active Time 5 6 ns tCAH Column Address Hold Time 0 0 ns tCH Column Address Latch High Time (Latch Transparent) 5 5 ns tCHR /CAL Inactive Lead Time to /RE Inactive (Write Cycles Only) -2 -2 ns tCHW Column Address Latch High to Write Enable Low (Multiple Writes) 0 0 ns tCQV Column Address Latch High to Data Valid tCQX Column Address Latch Inactive to Data Invalid for Addresses A0-8 5 5 ns tCQX1 Column Address Latch Inactive to Data Invalid for Addresses A9 and A10 1 1 ns tCRP Column Address Latch Setup Time to Row Enable 5 5 ns tCWL /WE Low to /CAL Inactive 5 5 ns tDH Data Input Hold Time 0 0 ns Data Input Setup Time 5 5 ns tDS 15 17 ns (1) Output Enable Access Time tGQX (2,3) Output Enable to Output Drive Time 0 5 tGQZ(4,5) Output Turn-Off Delay From Output Disabled (/G) 0 5 tMH /F and W/R Mode Select Hold Time 0 0 ns tMSU /F and W/R Mode Select Setup Time 5 5 ns tNRH /CAL, /G, /WE, and W/R Hold Time For /RE-Only Refresh 0 0 ns tNRS /CAL, /G, /WE, and W/R Setup Time For /RE-Only Refresh, 5 5 ns tPC Column Address Latch Cycle Time 12 15 ns tGQV tRAC(1) 5 ns 0 5 ns 0 5 ns 5 Row Enable Access Time, On a Cache Miss 30 35 ns tRAC1 Row Enable Access Time, On a Cache Hit (Limit Becomes tAC) 15 17 ns tRAC2(1,6) Row Enable Access Time for a Cache Write Hit 30 35 ns tRAH Row Address Hold Time 1 tRE Row Enable Active Time 30 (1) 1-6 1.5 100000 35 ns 100000 ns Switching Characteristics (continued) VCC = 5V 5% (+5 Volt Option), VCC = 3.3V 0.3V% (+3.3 Volt Option), CL = 50pf, TA = 0 to 70C (Commercial) ,TA = -40 to 85C (Industrial) -12 Symbol Description Min tRE1 Row Enable Active Time, Cache Hit (Row=LRR) Read Cycle tREF Refresh Period tRGX Max 8 Min 9 tRQX1 Row Enable High to Output Turn-On After Write Miss 0 tRP Row Precharge Time tRP1 Row Precharge Time, Cache Hit (Row=LRR) Read Cycle tRP2 Row Precharge Time, Self-Refresh Mode tRRH Read Hold Time From Row Enable (Write Only) tRSH Max 10 64 Output Enable Don't Care From Row Enable (Write, Cache Miss), O/P Hi Z (2,6) -15 ns 64 0 ms ns 10 12 Units 15 ns 20 25 ns 8 10 ns 100 100 ns 0 0 ns Last Write Address Latch to End of Write 12 15 ns t RSW Row Enable to Column Address Latch Low For Second Write 35 40 ns tRWL Last Write Enable to End of Write 12 15 ns tSC Column Address Cycle Time 12 15 ns Select Hold From Row Enable 0 0 ns tSHR tSQV (1) Chip Select Access Time 12 15 ns tSQX(2,3) Output Turn-On From Select Low 0 12 0 15 ns tSQZ (4,5) Output Turn-Off From Chip Select 0 8 0 10 ns tSSR Select Setup Time to Row Enable 5 tT Transition Time (Rise and Fall) 1 tWC Write Enable Cycle Time tWCH 5 10 1 ns 10 ns 12 15 ns Column Address Latch Low to Write Enable Inactive Time 5 5 ns tWHR Write Enable Hold After /RE 0 0 ns tWI Write Enable Inactive Time 5 5 ns Write Enable Active Time 5 5 ns tWP (1) tWQV Data Valid From Write Enable High tWQX(2,5) Data Output Turn-On From Write Enable High 0 12 tWQZ Data Turn-Off From Write Enable Low 0 12 tWRP Write Enable Setup Time to Row Enable 5 tWRR Write to Read Recovery (Following Write Miss) (3,4) 12 1-7 ns 0 15 ns 0 15 ns 5 16 (1) VOUT Timing Reference Point at 1.5V (2) Parameter Defines Time When Output is Enabled (Sourcing or Sinking Current) and is Not Referenced to VOH or VOL (3) Minimum Specification is Referenced from VIH and Maximum Specification is Referenced from VIL on Input Control Signal (4) Parameter Defines Time When Output Achieves Open-Circuit Condition and is Not Referenced to VOH or VOL (5) Minimum Specification is Referenced from VIL and Maximum Specification is Referenced from VIH on Input Control Signal (6) Access Parameter Applies When /CAL Has Not Been Asserted Prior to tRAC2 15 ns 18 ns /RE Inactive Cache Read Hit (Static Column Mode) /RE /F W/R A0-10 Column 1 Column 2 Column 3 t SC t SC t SC Column 4 /CAL /WE t AC t AC t AQX t AQX Q Open Data 1 t AC t AC t AQX Data 2 Data 3 Data 4 t GQZ t GQX t GQV /G t SQX t SQV t SQZ /S Don't Care or Indeterminate NOTES: 1. Data accessed during /RE inactive read is from the row address specified during the last /RE active read cycle. 2. If column address 2, 3, or 4 modifies only address pin A9 or A10, then tAC becomes tAC1 for data 2, 3, and 4, and tAQX becomes tAQX1for data 1, 2, and 3. 1-8 /RE Inactive Cache Read Hit (Page Mode) /RE /F W/R t CAH A0-10 Column 1 Column 2 t ASC t CAH t CAE /CAL Row t ASC t CH t PC t CQV /WE t AC t CQX Q Open Data 1 Data 2 t AC t GQX t GQZ t GQV /G t SQX t SQV t SQZ /S Don't Care or Indeterminate NOTES: 1. Data accessed during /RE inactive read is from the row address specified during the last /RE active read cycle. 2. If column address 2 modifies only address pin A9 or A10, then tAC becomes tAC1 for data 2 and tCQX becomes tCQX1for data 1. 1-9 /RE Active Cache Read Hit (Static Column Mode) t C1 t RE1 /RE t RP1 t MSU t MH /F t MSU t MH W/R t ASR t RAH A0-10 Row Column 1 Column 2 Column 3 t SC t SC t SC Column 4 t CRP /CAL /WE t AC t RAC1 Q t AC t AQX t AQX Open Data 1 t AC t AQX Data 2 t GQX t AC Data 3 Data 4 t GQZ t GQV /G t SHR t SSR t SQZ /S Don't Care or Indeterminate NOTES: 1. If column address 2, 3, or 4 modifies only address pin A9 or A10, then tAC becomes tAC1 for data 2, 3, and 4, and tAQX becomes tAQX for data 1, 2, and 3. 1-10 /RE Active Cache Read Hit (Page Mode) t C1 t RE1 /RE t RP1 t MSU t MH /F t MSU t MH W/R t ASR t CAH t RAH A0-10 Row Column 1 Column 2 t ASC t CRP t CAH t CAE /CAL Row t ASC t CH t PC t CQV /WE t AC t CQX t RAC1 Q Open Data 1 Data 2 t AC t GQX t GQZ t GQV /G t SHR t SSR t SQZ /S Don't Care or Indeterminate NOTES: 1. If column address 2 modifies only address pin A9 or A10, then tAC becomes tAC1 for data 2 and tCQX becomes tCQX1 for data 1. 1-11 /RE Active Cache Read Miss (Static Column Mode) tC t RE /RE t RP t MSU t MH /F t MSU t MH W/R t ASR t RAH A0-10 t SC Row Column 1 Column 2 Row t CRP /CAL t AQX /WE t AC t AC t RAC Q t AQX Open Data 1 Data 2 t GQX t GQV t GQZ /G t SHR t SSR t SQZ /S Don't Care or Indeterminate NOTES: 1. If column address 2 modifies only address pin A9 or A10, then tAC becomes tAC1 for data 2, and tAQX becomes tAQX1 for data 1. 1-12 /RE Active Cache Read Miss (Page Mode) tC t RE /RE t RP t MSU t MH /F t MSU t MH W/R t ASR t RAH A0-10 Row t CAH Column 1 Column 2 t ASC Row t ASC t CRP t CAH t CAE /CAL t CH t PC t CQV /WE t AC t CQX t RAC Open Q Data 1 Data 2 t AC t GQZ /G t SSR t GQX t SHR t GQV t SQZ /S Don't Care or Indeterminate NOTES: 1. If column address 2 modifies only address pin A9 or A10, then tAC becomes tAC1 for data 2, and tCQX becomes tCQX1 for data 1. 1-13 Burst Write (Hit or Miss) Followed By /RE Inactive Cache Reads t RE /RE t MSU t RP t MH t CHR /F t MSU t MH W/R t ASR t RAH A 0-10 Row t CAH t RSW Column 1 Column 2 t ACH t ACH t ASC t CAH t CAE t CRP /CAL t WCH t WRP t RSH t CWL t CHW D t CWL t WCH t RRH t WP /WE t DS t CAE t CH t PC t WP t WHR Column n t CHR t WC t DH t WI t RWL t DH t DS Data 1 Data 2 t RQX1 Q Open t WRR t AC Cache (Column n) tGQX t GQV /G t SSR /S Don't Care or Indeterminate NOTES: 1. /G becomes a don't care after tRGX during a write miss. 1-14 Read/Write During Write Hit Cycle (Can Include Read-Modify-Write) tC t RE /RE t RP t MSU t CHR t MH /F t MSU t MH W/R t CHR t ASR t RAH A0-10 Row Column 1 t CRP t AC t CAH Column 2 t ACH t ASC Column 3 t RSH t CAE /CAL t WCH t CQV t CWL t WRP /WE t WHR t RAC2 t AQX t RWL t AC t CQX D t RRH t WP t WQV Read Data Read Data t DH t WQX t DS Q Write Data t GQX t GQZ t GQZ /G t GQV t GQV t SSR /S Don't Care or Indeterminate NOTES: 1. If column address 2 modifies only address pin A9 or A10, then tAQX becomes tAQX1. 1-15 /F Refresh Cycle t RE /RE t MSU t RP t MH /F Don't Care or Indeterminate NOTES: 1. During /F refresh cycles, the status of W/R, /WE, A0-10, /CAL, /S, and /G is a don't care. 2. /RE inactive cache reads may be performed in parallel with /F refresh cycles. /RE-Only Refresh t RE /RE tC t RP t ASR t RAH A 0-10 Row t NRS /CAL, /WE, /G, W/R t NRH t MSU t MH /F t SSR t SHR /S Don't Care or Indeterminate NOTES: 1. All binary combinations of A0-9 must be refreshed every 64ms interval. A10 does not have to be cycled, but must remain valid during row address setup and hold times. 2. /RE refresh is write cycle with no /CAL active cycle. 1-16 Low Power Self-Refresh Mode Option /RE t RP2 A 0-10 t MSU t MH /CAL t MSU /F, W/R, /WE, /S t MH Don't Care or Indeterminate NOTES: 1. EDRAM self refreshes as long as /RE remains low. (Low Power Self-Refresh parts only). 2. When using the Low Power Self Refresh mode the following operations must be performed: If row addresses are being refreshed in an evenly distributed manner over the refresh interval using /F refresh cycles, then at least one /F refresh cycle must be performed immediately after exit from the Low Power Self Refresh Mode. If row addresses are being refreshed in any other manner (/F burst or /RE distributed or burst), then all rows must be refresh immediately before entry to and immediately after exit from the Low Power Self Refresh. Part Numbering System DM2200J 1 - 12I Temperature Range No Designator = 0 to 70oC (Commercial) I = -40 to 85oC (Industrial) L = 0 to 70oC, Low Power Self-Refresh Access Time from Cache in Nanoseconds 12ns 15ns Power Supply Voltage No Designator = +5 Volts 1 = +3.3 Volts Packaging System J = 300 Mil, Plastic SOJ T = 300 Mil, Plastic TSOP-II I/O Width i.e., Power to Which 2 is Raised for I/O Width (x1) Capacity in Bits i.e., Power to Which 2 is Raised for Total Capacity (4Mbit) Dynamic Memory 1-17 Mechanical Data 28 Pin 300 Mil Plastic SOJ Package Inches (mm) Optional Pin 1 Indicator 3 2 1 0.295 (7.493) 0.305 (7.747) 0.330 (8.382) 0.340 (8.636) 0.094 (2.39) 0.102 (2.59) 0.720 (18.288) 0.730 (18.542) 0.128 (3.251) 0.148 (3.759) 0.088 (2.24) 0.098 (2.48) 0.050 (1.27) 0.014 (.36) 0.019 (.48) 0.035 (0.89) 0.045 (1.14) 0.260 (6.604) 0.275 (6.985) 0.0091 (.23) 0.0125 (.32) Seating Plane Mechanical Data 44 Pin 300 Mil Plastic TSOP-II Package Inches (mm) 0.741 (18.81) MAX. 0.0315 (0.80) TYP. 0.040 (1.02) TYP. 0.040 (1.02) TYP. 0.040 (1.02) TYP. 7 TYP. 0.044 (1.13) MAX. 0.308 (7.82) 0.292 (7.42) 0.004 (0.10) 0.000 (0.00) 0.016 (0.40) 0.008 (0.20) 0.371 (9.42) 0.355 (9.02) 0.039 (1.00) TYP. 0.039 (1.00) 0.023 (0.60) 0.024 (0.60) 0.016 (0.40) 0.010 (0.24) 0.004 (0.09) The information contained herein is subject to change without notice. Enhanced Memory Systems Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in an Enhanced product, nor does it convey or imply any license under patent or other rights. 1-18