DM2200 EDRAM
4Mb x 1 Enhanced Dynamic RAM
Product Specification
© 1996 Enhanced Memory Systems Inc., 1850 Ramtron Drive, Colorado Springs, CO 80921
Telephone (800) 545-DRAM; Fax (719) 488-9095; http://www.csn.net/ramtron/enhanced 38-2108-001
The information contained herein is subject to change without notice.
Enhanced reserves the right to change or discontinue this product without notice.
Features
■2Kbit SRAM Cache Memory for 12ns Random Reads Within a Page
■Fast 4Mbit DRAM Array for 30ns Access to Any New Page
■Write Posting Register for 12ns Random Writes and Burst Writes
Within a Page (Hit or Miss)
■256-byte Wide DRAM to SRAM Bus for 14.2 Gigabytes/Sec Cache
Fill
■On-chip Cache Hit/Miss Comparators Maintain Cache Coherency
on Writes
■Hidden Precharge and Refresh Cycles
■Extended 64ms Refresh Period for Low Standby Power
■300 Mil Plastic SOJ and TSOP-II Package Options
■+5 and +3.3 Volt Power Supply Voltage Options
■Low Power, Self Refresh Mode Option
■Industrial Temperature Range Option
Description
The 4Mb Enhanced DRAM (EDRAM) combines raw speed with
innovative architecture to offer the optimum cost-performance solution
for high performance local or system main memory. In most high
speed applications, no-wait-state performance can be achieved without
secondary SRAM cache and without interleaving main memory banks at
system clock speeds through 50MHz. Two-way interleave will allow no-
wait-state operation at clock speeds greater than 100MHz without the
need of secondary SRAM cache. The EDRAM outperforms conventional
SRAM cache plus DRAM memory systems by minimizing processor wait
states for all possible bus events, not just cache hits. The combination
of data and address latching, 2K of fast on-chip SRAM cache, and
simplified on-chip cache control allows system level flexibility,
performance, and overall memory cost reduction not available with any
other high density memory component. Architectural similarity with
JEDEC DRAMs allows a single memory controller design to support
either slow JEDEC DRAMs or high speed EDRAMs. A system designed in
this manner can provide a simple upgrade path to higher system
performance.
Architecture
The EDRAM architecture has a simple integrated SRAM cache
which allows it to operate much like a page mode or static column
DRAM.
The EDRAM’s SRAM cache is integrated into the DRAM array as
tightly coupled row registers. Memory reads always occur from the
cache row register. When the internal comparator detects a page hit,
only the SRAM is accessed and data is available in 12ns from column
address. When a page read miss is detected, the new DRAM row is
loaded into the cache and data is available at the output all within
30ns from row enable. Subsequent reads within the page (burst reads
or random reads) can continue at 12ns cycle time. Since reads occur
from the SRAM cache, the DRAM precharge can occur simultaneously
without degrading performance. The on-chip refresh counter with
independent refresh bus allows the EDRAM to be refreshed during
cache reads.
Memory writes are internally posted in 12ns and directed to the
DRAM array. During a write hit, the on-chip address comparator
activates a parallel write path to the SRAM cache to maintain
coherency. The EDRAM delivers 12ns cycle page mode memory
/CAL
A0-10
W/R
/F
/RE
V
V
Sense Amps
& Column Write Select
Column Decoder
Row
Add
Latch
CC
SS
2048 X 1 Cache (Row Register)
Memory
Array
(2048 X 2048)
A0-10
/G
/S
/WE
Column
Add
Latch
11 Bit
Comp
Last
Row
Read
Add
Latch
I/O
Control
and
Data
Latches
Refresh
Counter
Row Decoder
Row Add
and
Refresh
Control
A0-9
D
Q
Functional Diagram SOJ Pin
Configuration
TSOP-II Pin
Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
VSS *
VSS
VSS
Q
D
NC
NC
NC
/G
VCC
VCC
VSS
VSS
/WE
/S
/F
NC
W/R
NC
/CAL
A10
NC
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
A0
NC
A1
NC
A3
A4
NC
A5
/RE
VCC
VSS
VSS
A6
A7
A8
NC
A2
NC
A9
VCC
VCC*
* Reserved for future use
1
2
3
4
5
9
10
11
12
13
26
25
24
23
22
18
17
16
15
14
A
6
21
8
19
7
20
27
28
0
A1
A3
A4
A5
/RE
VCC
VSS
A6
A7
A8
A2
A9
VCC
VSS
Q
/WE
/S
/F
W/R
/CAL
/G
VCC
VSS
A10
D
NC
NC
Enhanced
M emory S y stems I nc.
writes. Memory writes do not affect the contents of the cache row
register except during a cache hit.
By integrating the SRAM cache as row registers in the DRAM
array and keeping the on-chip control simple, the EDRAM is able
to provide superior performance over standard slow 4Mb DRAMs.
By eliminating the need for SRAMs and cache controllers, system
cost, board space, and power can all be reduced.
Functional Description
T
he EDRAM is designed to provide optimum memory
performance with high speed microprocessors. As a result, it is
possible to perform simultaneous operations to the DRAM and SRAM
cache sections of the EDRAM. This feature allows the EDRAM to hide
precharge and refresh operation during SRAM cache reads and
maximize SRAM cache hit rate by maintaining valid cache contents
during write operations even if data is written to another memory
page. These new functions, in conjunction with the faster basic DRAM
and cache speeds of the EDRAM, minimize processor wait states.
EDRAM Basic Operating Modes
The EDRAM operating modes are specified in the table below.
Hit and Miss Terminology
In this datasheet, “hit” and “miss” always refer to a hit or miss
to the page of data contained in the SRAM cache row register. This
is always equal to the contents of the last row that was read from
(as modified by any write hit data). Writing to a new page does not
cause the cache to be modified.
DRAM Read Hit
A DRAM read request is initiated by clocking /RE with W/R low
and /F & /CAL high. The EDRAM compares the new row address to
the last row read address latch (LRR - an 11-bit latch loaded on
each /RE active read miss cycle). If the row address matches the
LRR, the requested data is already in the SRAM cache and no
DRAM memory reference is initiated. The data specified by the
column address is available at the output pins at the greater of
times tAC or tGQV. Since no DRAM activity is initiated, /RE can be
brought high after time tRE1, and a shorter precharge time, tRP1, is
allowed. It is possible to access additional SRAM cache locations by
providing new column addresses to the multiplex address inputs.
New data is available at the output at time tAC after each column
address change. During read cycles, it is possible to operate in
either static column mode with /CAL=high or page mode with /CAL
clocked to latch the column address. In page mode, data valid
time is determined by either tAC or tCQV.
DRAM Read Miss
A DRAM read request is initiated by clocking /RE with W/R low
and /F & /CAL high. The EDRAM compares the new row address to
the LRR address latch (an 11-bit latch loaded on each /RE active
read miss cycle). If the row address does not match the LRR, the
requested data is not in SRAM cache and a new row must be
fetched from the DRAM. The EDRAM will load the new row data
into the SRAM cache and update the LRR latch. The data at the
specified column address is available at the output pins at the
greater of times tRAC, tAC, and tGQV. It is possible to bring /RE high
after time tRE since the new row data is safely latched into SRAM
cache. This allows the EDRAM to precharge the DRAM array while
data is accessed from SRAM cache. It is possible to access additional
SRAM cache locations by providing new column addresses to the
multiplex address inputs. New data is available at the output at time
tAC after each column address change. During read cycles, it is
possible to operate in either static column mode with /CAL=high or
page mode with /CAL clocked to latch the column address. In page
mode, data valid time is determined by either tAC or tCQV.
DRAM Write Hit
If a DRAM write request is initiated by clocking /RE while W/R,
/CAL, /WE, and /F are high, the EDRAM will compare the new row
address to the LRR address latch (an 11-bit address latch loaded
on each /RE active read miss cycle). If the row address matches,
the EDRAM will write data to both the DRAM array and selected
SRAM cache simultaneously to maintain coherency. The write
address and data are posted to the DRAM as soon as the column
address is latched by bringing /CAL low and the write data is
latched by bringing /WE low. The write address and data can be
latched very quickly after the fall of /RE (tRAH + tASC for the column
address and tDS for the data). During a write burst sequence, the
second write data can be posted at time tRSW after /RE. Subsequent
writes within a page can occur with write cycle time tPC. With /G
enabled and /WE disabled, it is possible to perform cache read
operations while the /RE is activated in write hit mode. This allows
read-modify-write, write-verify, or random read-write sequences
within the page with 12ns cycle times (the first read cannot
complete until after time tRAC2). At the end of a write sequence
(after /CAL and /WE are brought high and tRE is satisfied), /RE can
be brought high to precharge the memory. It is possible to perform
1-2
Function /S
Unallowed Mode H
/RE W/R /F A
0-10
Comment
L X H X Unallowed Mode (Except -L Option)
Standby Current, Internal Refresh Clock (-L Option)
Low Power Self-Refresh
Option H↓H H X
Internal Refresh X X L X Cache Reads Enabled
Read Miss L L H Row ≠ LRR DRAM Row to Cache
Write Hit L H H Row = LRR Write to DRAM and Cache, Reads Enabled
Write Miss L H H Row ≠ LRR Write to DRAM, Cache Not Updated, Reads Disabled
↓
↓
↓
↓
Read Hit L L H
/CAL
X
L
X
H
H
H
H
/WE
X
Low Power Standby H H X X X 1mA Standby CurrentH H
H
X
X
H
H
X Row = LRR No DRAM Reference, Data in Cache↓
H = High; L = Low; X = Don’t Care; ↓ = High-to-Low Transition; LRR = Last Row Read
EDRAM Basic Operating Modes
1-3
cache reads concurrently with precharge. During write sequences,
a write operation is not performed unless both /CAL and /WE are
low. As a result, the /CAL input can be used as a byte write select in
multi-chip systems.
DRAM Write Miss
If a DRAM write request is initiated by clocking /RE while W/R,
/CAL, /WE, and /F are high, the EDRAM will compare the new row
address to the LRR address latch (an 11-bit latch loaded on each
/RE active read miss cycle). If the row address does not match, the
EDRAM will write data to the DRAM array only and contents of the
current cache are not modified. The write address and data are
posted to the DRAM as soon as the column address is latched by
bringing /CAL low and the write data is latched by bringing /WE
low. The write address and data can be latched very quickly after
the fall of /RE (tRAH + tASC for the column address and tDS for the
data). During a write burst sequence, the second write data can be
posted at time tRSW after /RE. Subsequent writes within a page can
occur with write cycle time tPC. During a write miss sequence,
cache reads are inhibited and the output buffers are disabled
(independently of /G) until time tWRR after /RE goes high. At the
end of a write sequence (after /CAL and /WE are brought high and
tRE is satisfied), /RE can be brought high to precharge the memory.
It is possible to perform cache reads concurrently with the
precharge. During write sequences, a write operation is not
performed unless both /CAL and /WE are low. As a result, /CAL can
be used as a byte write select in multi-chip systems.
/RE Inactive Operation
It is possible to read data from the SRAM cache without
clocking /RE. This option is desirable when the external control
logic is capable of fast hit/miss comparison. In this case, the
controller can avoid the time required to perform row/column
multiplexing on hit cycles. This capability also allows the EDRAM to
perform cache read operations during precharge and refresh
cycles to minimize wait states and reduce power. It is only
necessary to select /S and /G and provide the appropriate column
address to read data as shown in the table below. The row address
of the SRAM cache accessed without clocking /RE will be specified
by the LRR address latch loaded during the last /RE active read
cycle. To perform a cache read in static column mode, /CAL is held
high, and the cache contents at the specified column address will
be valid at time tAC after address is stable. To perform a cache read
in page mode, /CAL is clocked to latch the column address. The
cache data is valid at time tAC after the column address is setup to
/CAL.
On-Chip SRAM Interleave
The DM2200 has an on-chip interleave of its SRAM cache
which allows 8ns random accesses (tAC1) for up to three data
words (burst reads) following an initial read access (hit or miss).
The SRAM cache is integrated into the DRAM arrays in a 512 x 4
organization. It is converted into a 2K x 1 page organization by
using an on-chip address multiplexer to select one of four bits
to
the output pin Q (as shown below). The specific databit selected to
the output is determined by column addresses A9and A10. System
operation is consistent with the standard “Functional Description”
and timing diagrams shown in this specification. See the note in the
read timing diagrams and “Switching Characteristics” chart for the
faster access and data hold times.
Internal Refresh
If /F is active (low) on the assertion of /RE, an internal refresh
cycle is executed. This cycle refreshes the row address supplied by
an internal refresh counter. This counter is incremented at the end
of the cycle in preparation for the next /F refresh cycle. At least
1,024 /F cycles must be executed every 64ms. /F refresh cycles can
be hidden because cache memory can be read under column
address control throughout the entire /F cycle.
Low Power Mode
The EDRAM enters its low power mode when /S is high. In this
mode, the internal DRAM circuitry is powered down to reduce
standby current to 1mA.
Low Power, Self-Refresh Option
When the low power, self-refresh option is specified when
ordering the EDRAM, the EDRAM enters this mode when /RE is
clocked while /S, W/R, /F, and /WE are high; and /CAL is low. In this
mode, the power is turned off to all I/O pins except /RE to
minimize chip power, and an on-board refresh clock is enabled to
perform self-refresh cycles using the on-board refresh counter. The
EDRAM remains in this low power mode until /RE is brought high
again to terminate the mode. The EDRAM /RE input must remain
high for tRP2 following exit from self-refresh mode to allow any on-
going internal refresh to terminate prior to the next memory
operation.
+3.3 Volt Power Supply Operation
If the +3.3 volt power supply option is specified, the EDRAM
will operate from a +3.3 volt ±0.3 volt power supply and all inputs
and outputs will have LVTTL/LVCMOS compatible signal levels. The
+3.3 volt EDRAM will not accept input levels which exceed the
power supply voltage. If mixed I/O levels are expected in your
system, please specify the +5 volt version of the EDRAM.
/CAL Before /RE Refresh (“/CAS Before /RAS”)
/CAL before /RE refresh, a special case of internal refresh, is
discussed in the “Reduced Pin Count Operation” section below.
Function /S /G /CAL A
0-8
Cache Read (Static Column) L H Column Address
Cache Read (Page Mode) L Column Address
H = High; L = Low; X = Don’t Care; ↓ = Transitioning
L
L↓
2,048 Bits
128 Bits
1 Bit
Q
Row Address
A0-10
Column Address
A2-10
Column Address
A9,A10
EDRAM
4M DRAM Array
EDRAM
2K SRAM Cache
4 to 1
Output Selector
DM2200 Datapath Architecture
/RE Only Refresh Operation
Although /F refresh using the internal refresh counter is the
recommended method of EDRAM refresh, it is possible to perform
an /RE only refresh using an externally supplied row address. /RE
refresh is performed by executing a write cycle (W/R and /F are
high) where /CAL is not clocked. This is necessary so that the
current cache contents and LRR are not modified by the refresh
operation. All combinations of addresses A0-9 must be sequenced
e
ver
y 64ms refresh period. A10 does not need to be cycled. Read
refresh cycles are not allowed because a DRAM refresh cycle does not
occur when a read refresh address matches the LRR address latch.
Initialization Cycles
A minimum of 10 initialization (start-up) cycles are required
before normal operation is guaranteed. At least eight /F refresh
cycles and two read cycles to different row addresses are necessary
to complete initialization. /RE must be high for at least 300ns prior
to initialization.
Unallowed Mode
Read, write, or /RE only refresh operations must not be performed
to unselected memory banks by clocking /RE when /S is high.
Reduced Pin Count Operation
Although it is desirable to use all EDRAM control pins to
optimize system performance, it is possible to simplify the interface
to the EDRAM by either tying pins to ground or by tying one or
more control inputs together. The /S input can be tied to ground if
the low power standby modes are not required. The /CAL and /F
pins can be tied together if hidden refresh operation is not
required. In this case, a CBR refresh (/CAL before /RE) can be
performed by holding the combined input low prior to /RE. A CBR
refresh does not require that a row address be supplied when /RE
is asserted. The timing is identical to /F refresh cycle timing. The
/WE input can be tied to /CAL if independent posting of column
addresses and data are not required during write operations. In
this case, both column address and write data will be latched by
the combined input during writes. W/R and /G can be tied together
if reads are not performed during write hit cycles. If these
techniques are used, the EDRAM will require only three control
lines for operation (/RE, /CAS [combined /CAL, /F, and /WE], and
W/R [combined W/R and /G]). The simplified control interface still
allows the fast page read/write cycle times, fast random read/write
times, and hidden precharge functions available with the EDRAM.
Pin Descriptions
/RE — Row Enable
This input is used to initiate DRAM read and write operations
and latch a row address. It is not necessary to clock /RE to read
data from the EDRAM SRAM row registers. On read operations, /RE
can be brought high as soon as data is loaded into cache to allow
early precharge.
/CAL — Column Address Latch
This input is used to latch the column address and in
combination with /WE to trigger write operations. When /CAL is
high, the column address latch is transparent. When /CAL is low,
the column address latch is closed and the output of the latch
contains the address present while /CAL was high.
W/R — Write/Read
This input along with /F specifies the type of DRAM operation
initiated on the low going edge of /RE. When /F is high, W/R
specifies either a write (logic high) or read operation (logic low).
/F — Refresh
This input will initiate a DRAM refresh operation using the
internal refresh counter as an address source when it is low on the
low going edge of /RE.
/WE — Write Enable
This input controls the latching of write data on the input data
pins. A write operation is initiated when both /CAL and /WE are low.
/G — Output Enable
This input controls the gating of read data to the output data
pins during read operations.
/S — Chip Select
This input is used to power up the I/O and clock circuitry.
When /S is high, the EDRAM remains in its low power mode. /S
must remain active throughout any read or write operation. With
the exception of /F refresh cycles, /RE should never be clocked
when /S is inactive.
D — Data Input
This input pin is used to write data to the EDRAM.
Q — Data Output
This output pin is used to read data from the EDRAM.
A
0-10
— Multiplex Address
These inputs are used to specify the row and column
addresses of the EDRAM data. The 11-bit row address is latched on
the falling edge of /RE. The11-bit column address can be specified
at any other time to select read data from the SRAM cache or to
specify the write column address during write cycles.
V
CC
Power Supply
These inputs are connected to the +5 or +3.3 volt power supply.
V
SS
Ground
These inputs are connected to the power
supply ground
connection.
1-4
Pin Names
Electrical Characteristics
TA= 0 to 70°C (Commercial); -40 to 85°C (Industrial)
1-5
Symbol Parameters Min Max Test Conditions
VCC Supply Voltage 4.75V All Voltages Referenced to VSS
VIH
VIL
Ii(L)
IO(L)
VOH
VOL
OV ≤ VIN ≤ Vcc + 0.5 Volts
O ≤ VI/O ≤ Vcc
IOUT = - 5mA (-2ma For 3.3 Volt Option)
IOUT = 4.2mA (2ma For 3.3 Volt Option)
0.8V
10µA
0.4V
10µA
2.4V
Vss-0.5V
-10µA
-10µA
2.4V
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
Output High Level
Output Low Level
5.25V
Min Max
3.3V Option
3.0V
VCC+0.3V
0.8V
5µA
0.4V
5µA
2.0V
Vss-0
.3V
-5µA
-5µA
2.4V
3.6V
Vcc+0.5V
Symbol Operating Current -15 Max Test Condition
ICC1 Random Read /RE, /CAL, and Addresses Cycling: tC = tC Minimum
All Control Inputs Stable ≥ VCC - 0.2V, Output Driven
/RE, /CAL, /WE, and Addresses Cycling: tC = tC Minimum
/CAL, /WE, and Addresses Cycling: tPC = tPC Minimum
115mA
90mA
105mA
Fast Page Mode Read
Static Column Read
Standby
Random Write
Fast Page Mode Write
180mA
ICC2
ICC3
ICC4
ICC5
ICC6
150mA
33MHz Typ
(1)
65mA
55mA
1mA
200 µA
1mA 1mA
50mA
110mA
135mA
Notes
2, 3, 5
2, 4, 5
2, 4, 5
2, 3
2, 4
/CAL and Addresses Cycling: tPC = tPC Minimum
Addresses Cycling: tSC = tSC Minimum
(1) “33MHz Typ” refers to worst case ICC expected in a system operating with a 33MHz memory bus. See power applications note for further details. This parameter is not 100% tested
or guaranteed. (2) ICC is dependent on cycle rates and is measured with CMOS levels and the outputs open. (3) ICC is measured with a maximum of one address change while
/RE = VIL. (4) ICC is measured with a maximum of one address change while /CAL = VIH. (5) /G is high.
-12 Max
225mA
145mA
110mA
/S, /F, W/R, /WE, and A0-10 at ≥ VCC - 0.2V
/RE and /CAL at ≤ VSS + 0.2V, I/O Open
Self-Refresh
Option (-L)
ICC7
190mA
135mA
See “Estimating EDRAM Operating Power” Application Note—Average Typical
Operating Current
ICCT 30mA — 1
200 µA 200 µA
R1 = 828Ω
≤5ns ≤5ns
VIL VIL
GND
+ 5.0 (+3.3 Volt Option)
Output
CL = 50pf
R2 = 295Ω
Load Circuit Input Waveforms
VIH VIH
(5.0 volt)
R1 = 1178Ω(3.3 Volt Option)
R2 = 868Ω
(5.0 volt)
(3.3 Volt Option)
AC Test Load and Waveforms
VIN Timing Reference Point at VIL and VIH
Ambient Operating Temperature (TA)
Description Ratings
Output Voltage (VOUT)
Power Supply Voltage (VCC)
Storage Temperature (TS)
Static Discharge Voltage
(Per MIL-STD-883 Method 3015)
Short Circuit O/P Current (IOUT)
- 1 ~ 7v
- 1 ~ 7v
Input Voltage (VIN)
- 1 ~ 7v
-40 ~ 85°C
-55 ~ 150°C
Class 1
50mA
3.3V Option
Rating
- .5 ~ 4.6v
- .5 ~ 4.6v
- .5 ~ 4.6v
-40 ~ 85°C
-55 ~ 150°C
Class 1
20mA
Absolute Maximum Ratings
(Beyond Which Permanent Damage Could Result)
Description Max Pins
Input Capacitance
Input Capacitance
Input Capacitance
2pf
A0-9
/G
Input Capacitance 7pf, 10pf(1)
6pf, 7pf(1)
A10, /CAL, /RE, W/R, /WE, /F, /S
6pf D
Output Capacitance 6pf Q
Capacitance
(1) +5 V, DM2200-15 only.
Symbol Description
tAC(1)
tASC
tASR
tC
tC1
tCAE
tCAH
tCH
tCQV
tCRP
tCWL
tDH
tDS
tGQV(1)
tGQX(2,3)
Column Address Access Time for Addresses A0-8
Column Address Setup Time
Row Enable Cycle Time
Row Enable Cycle Time, Cache Hit (Row=LRR), Read Cycle Only
Row Address Setup Time
Column Address Latch Active Time
Column Address Hold Time
Column Address Latch High Time (Latch Transparent)
Column Address Latch High to Data Valid
Column Address Latch Inactive to Data Invalid for Addresses A0-8
Column Address Latch Setup Time to Row Enable
/WE Low to /CAL Inactive
Data Input Hold Time
Data Input Setup Time
Output Enable Access Time
Output Enable to Output Drive Time
5
5
55
20
5
5
5
5
0
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min Max Units
12
5
0
15
0
5
tAQX1 Column Address Change to Output Data Invalid for Addresses A9 and A10 ns
1
tACH Column Address Valid to /CAL Inactive (Write Cycle) ns12
8
5
5
5
65
25
5
5
5
5
0
5
Min Max
15
6
0
17
0
5
1
tAQX Column Address Change to Output Data Invalid for Addresses A0-8 ns
5 5
15
8
tAC1(1) Column Address Access Time for Addresses A9 and A10 ns
5
-12 -15
tCQX
Column Address Latch Inactive to Data Invalid for Addresses A9 and A10 1 ns1
tCQX1
tNRS
tPC
tRAC(1)
tRAC1(1)
tRAH
Output Turn-Off Delay From Output Disabled (/G↑)
/CAL, /G, /WE, and W/R Setup Time For /RE-Only Refresh,
Column Address Latch Cycle Time
Row Address Hold Time
Row Enable Access Time, On a Cache Miss
tNRH /CAL, /G, /WE, and W/R Hold Time For /RE-Only Refresh
tMSU /F and W/R Mode Select Setup Time
tMH /F and W/R Mode Select Hold Time
ns
0 5 0 5
ns0 0
ns5 5
ns0 0
ns5 5
ns12 15
ns30 35
ns1.5
tGQZ(4,5)
tRAC2(1,6) Row Enable Access Time for a Cache Write Hit ns30 35
1
tCHR /CAL Inactive Lead Time to /RE Inactive (Write Cycles Only) -2 ns
-2
tCHW Column Address Latch High to Write Enable Low (Multiple Writes) 0ns
0
Row Enable Access Time, On a Cache Hit (Limit Becomes tAC)15 17 ns
tRE Row Enable Active Time ns30 35100000 100000
Switching Characteristics
VCC = 5V ± 5% (+5 Volt Option), VCC = 3.3V ± 0.3V (+3.3 Volt Option), CL= 50pf, TA= 0 to 70°C (Commercial) ,TA= -40 to 85°C (Industrial)
1-6
1-7
Switching Characteristics (continued)
VCC = 5V ± 5% (+5 Volt Option), VCC = 3.3V ± 0.3V% (+3.3 Volt Option), CL= 50pf, TA= 0 to 70°C (Commercial) ,TA= -40 to 85°C (Industrial)
Symbol Description
tRGX
tRP
tRP1
tRRH
tRSH
t
Output Enable Don't Care From Row Enable (Write, Cache Miss), O/P Hi Z
Row Precharge Time
Row Precharge Time, Cache Hit (Row=LRR) Read Cycle
Read Hold Time From Row Enable (Write Only)
Last Write Address Latch to End of Write
Row Enable to Column Address Latch Low For Second Write
9
20
8
0
ns
ns
ns
ns
ns
ns
Min Max Units
35
25
10
tRP2 Row Precharge Time, Self-Refresh Mode 100 ns
100
0
Min Max
10
tRQX1(2,6) Row Enable High to Output Turn-On After Write Miss 0 ns
40
-12 -15
12 15
RSW ns
tRWL Last Write Enable to End of Write ns
12 15
tSC Column Address Cycle Time ns
12 15
tSHR Select Hold From Row Enable ns
00
tSQV(1) Chip Select Access Time ns12 15
tSQX(2,3) Output Turn-On From Select Low ns12 15
00
Output Turn-Off From Chip Select ns8 10
00
tSSR Select Setup Time to Row Enable ns
55
tTTransition Time (Rise and Fall) ns10 10
11
tWC Write Enable Cycle Time ns
12 15
tWCH Column Address Latch Low to Write Enable Inactive Time ns
55
tWI Write Enable Inactive Time ns
55
(1) VOUT Timing Reference Point at 1.5V
(2) Parameter Defines Time When Output is Enabled (Sourcing or Sinking Current) and is Not Referenced to VOH or VOL
(3) Minimum Specification is Referenced from VIH and Maximum Specification is Referenced from VIL on Input Control Signal
(4) Parameter Defines Time When Output Achieves Open-Circuit Condition and is Not Referenced to VOH or VOL
(5) Minimum Specification is Referenced from VIL and Maximum Specification is Referenced from VIH on Input Control Signal
(6) Access Parameter Applies When /CAL Has Not Been Asserted Prior to tRAC2
tWP
tWRP
tWRR
Write Enable Active Time
Write Enable Setup Time to Row Enable
Write to Read Recovery (Following Write Miss) 16
ns
ns
ns5
Data Turn-Off From Write Enable Low ns
tWQX(2,5) Data Output Turn-On From Write Enable High ns0
tWQV(1) Data Valid From Write Enable High ns
18
5
0
12
5 5
15
12 15
0 012 15
tRE1
tREF
Row Enable Active Time, Cache Hit (Row=LRR) Read Cycle
Refresh Period ms64 64
8 10 ns
tWHR Write Enable Hold After /RE ns
00
tSQZ(4,5)
tWQZ(3,4)
12 0 15
1-8
/RE
/F
W/R
A0-10
/CAL
/G
/S
Column 1
tSC tSC
Data 1Open tGQZ
tGQX tGQV
tSQV
tSQX tSQZ
Q
Don’t Care or Indeterminate
/WE
Column 2 Column 3 Column 4
Data 2 Data 3 Data 4
AC
t
tAQX
tAQX
AC
t
tAQX
AC
t
AC
t
tSC
NOTES: 1.
2. Data accessed during /RE inactive read is from the row address specified during the last /RE active read cycle.
If column address 2, 3, or 4 modifies only address pin A9 or A10, then tAC becomes tAC1 for data 2, 3, and 4,
and tAQX becomes tAQX1for data 1, 2, and 3.
/RE Inactive Cache Read Hit (Static Column Mode)
1-9
/RE
/F
W/R
A0-10
/CAL
/G
/S
tCAH
Column 1 Column 2
tASC t
CAH
tCH
tCAE
tPC tCQV
tAC
tCQX
Data 1Open Data 2
tGQZ
tGQX tGQV
tAC
tSQZ
tSQV
tSQX
Row
tASC
Q
/WE
Don’t Care or Indeterminate
NOTES: 1.
2. Data accessed during /RE inactive read is from the row address specified during the last /RE active read cycle.
If column address 2 modifies only address pin A9 or A10, then tAC becomes tAC1 for data 2 and tCQX becomes tCQX1for data 1.
/RE Inactive Cache Read Hit (Page Mode)
1-10
/RE
tC1
Row
/F
W/R
A0-10
/CAL
/G
/S
tRE1
tMSU tMH
tRP1
tASR
tRAH
Column 1
tCRP
tSC tSC
tRAC1
Data 1Open
tGQZ
tGQX tGQV
tSSR tSQZ
tSHR
tMH
tMSU
Q
Don’t Care or Indeterminate
/WE
Column 2 Column 3 Column 4
Data 2 Data 3 Data 4
AC
t
tAQX
tAQX
AC
t
tAQX
AC
t
AC
t
tSC
If column address 2, 3, or 4 modifies only address pin A9 or A10, then tAC becomes tAC1 for data 2, 3, and 4, and tAQX becomes
tAQX for data 1, 2, and 3.
1.
NOTES:
/RE Active Cache Read Hit (Static Column Mode)
1-11
/RE
tC1
Row
/F
W/R
A0-10
/CAL
/G
/S
tRE1
tMSU tMH
tRP1
tASR tRAH tCAH
Column 1 Column 2
tCRP
tASC t
CAH
tCH
tCAE
tPC tCQV
tAC
tRAC1 tCQX
Data 1Open Data 2
tGQZ
tGQX tGQV
tAC
tSSR tSQZ
tSHR
tMH
tMSU
Row
tASC
Q
/WE
Don’t Care or Indeterminate
If column address 2 modifies only address pin A9 or A10, then tAC becomes tAC1 for data 2 and tCQX becomes
tCQX1 for data 1.
NOTES: 1.
/RE Active Cache Read Hit (Page Mode)
1-12
/RE
/F
W/R
A0-10
/CAL
/G
tC
Column 1
/S
tRE tRP
tMSU
tMSU
tASR
tMH
tMH
tRAH tSC
tCRP
tAQX
tAC tAC
tRAC tAQX
Row Column 2 Row
Open Data 1 Data 2
tGQX tGQV tGQZ
tSSR tSQZ
tSHR
Q
/WE
Don’t Care or Indeterminate
If column address 2 modifies only address pin A9 or A10, then tAC becomes tAC1 for data 2, and tAQX becomes
tAQX1 for data 1.
NOTES: 1.
/RE Active Cache Read Miss (Static Column Mode)
1-13
/RE
/F
W/R
A0-10
/CAL
/G
/S
tMSU
tC
tRE tRP
tMH
tMH
tRAH
tMSU
tASR
tCRP
tCAH
tASC tASC
tCAH tCH
tCAE
tPC tCQV
tRAC tCQX
tAC
Open tAC tGQZ
tSSR
tGQX tGQV
tSHR tSQZ
Row Column 1 Column 2 Row
Data 1 Data 2
Q
/WE
Don’t Care or Indeterminate
If column address 2 modifies only address pin A9 or A10, then tAC becomes tAC1 for data 2, and tCQX becomes
tCQX1 for data 1.
NOTES: 1.
/RE Active Cache Read Miss (Page Mode)
1-14
W/R
tRE
Column 1
tMSU
tMSU
tASR
tMH
tRAH tRSW
Column 2Row Column n
tCRP tCAH
tASC tCWL
tCAE
tCWL
tRSH
tCAE
tWRP tWP tRRH
tWCH
tWCH tPC
tWP
tRWL
tDH
tDH tDS
tDS
tAC
tWRR
tGQX
tRQX1
tGQV
tSSR
Data 1 Data 2
tACH tACH tCHR
tCH
tWHR tWI
tWC
Cache (Column n)Open
Q
D
/RE
/F
/CAL
/G
/S
/WE
tCHW
tRP
tCHR
A0-10
tCAH
Don’t Care or Indeterminate
NOTES: 1. /G becomes a don’t care after tRGX during a write miss.
tMH
Burst Write (Hit or Miss) Followed By /RE Inactive Cache Reads
1-15
/RE
/F
W/R
A0-10
/CAL
/WE
/G
tRE
/S
Column 1
tMSU
tMSU
tASR
tMH
tRAH
Column 2Row Column 3
tWRP
tCQX
tGQX
tSSR
DRead Data
tWHR
tC
tRP
tCRP tCAE
tACH
tASC tRSH
tWCH
tRRH
tCQV
tWP
tCWL
Read Data
tRAC2 tAC
tAQX
tDS
tRWL tWQV
tGQV
tGQZ
tDH
tGQZ
tGQV
tWQX
Write Data
Q
tCHR
Don’t Care or Indeterminate
tCAH tAC
tMH
tCHR
NOTES: 1. If column address 2 modifies only address pin A9 or A10, then tAQX becomes tAQX1.
Read/Write During Write Hit Cycle (Can Include Read-Modify-Write)
1-16
/RE
/F
tRE
tMSU tMH
Don’t Care or Indeterminate
NOTES: 1.
2.
During /F refresh cycles, the status of W/R, /WE, A0-10, /CAL, /S, and /G is a don’t care.
/RE inactive cache reads may be performed in parallel with /F refresh cycles.
tRP
/F Refresh Cycle
tC
/F
tRE tRP
tASR tRAH
Row
tNRS tNRH
tSSR tSHR
tMSU tMH
/RE
A0-10
/CAL, /WE, /G,
W/R
/S
Don’t Care or Indeterminate
NOTES: 1. All binary combinations of A0-9 must be refreshed every 64ms interval. A10 does not have to be cycled, but must remain valid
during row address setup and hold times.
2. /RE refresh is write cycle with no /CAL active cycle.
/RE-Only Refresh
1-17
/F, W/R,
/WE, /S
tRP2
tMSU tMH
tMSU tMH
/RE
Don’t Care or Indeterminate
NOTES: 1. EDRAM self refreshes as long as /RE remains low. (Low Power Self-Refresh parts only).
2. When using the Low Power Self Refresh mode the following operations must be performed:
If row addresses are being refreshed in an evenly distributed manner over the refresh interval using /F refresh cycles, then at
least one /F refresh cycle must be performed immediately after exit from the Low Power Self Refresh Mode. If row addresses
are being refreshed in any other manner (/F burst or /RE distributed or burst), then all rows must be refresh immediately before
entry to and immediately after exit from the Low Power Self Refresh.
A0-10
/CAL
Low Power Self-Refresh Mode Option
DM2200J 1 - 12I
Dynamic Memory
Capacity in Bits
I/O Width
Packaging System
Access Time from Cache in Nanoseconds
12ns
15ns
Temperature Range
I = -40 to 85oC (Industrial)
L = 0 to 70oC, Low Power Self-Refresh
Power Supply Voltage
No Designator = +5 Volts
1 = +3.3 Volts
J = 300 Mil, Plastic SOJ
T = 300 Mil, Plastic TSOP-II
i.e., Power to Which 2 is Raised for I/O Width (x1)
No Designator = 0 to 70oC (Commercial)
i.e., Power to Which 2 is Raised for Total Capacity (4Mbit)
Part Numbering System
1-18
Optional
Pin 1
Indicator
Inches (mm)
123
0.050 (1.27) Seating
Plane
0.295 (7.493)
0.305 (7.747)
0.330 (8.382)
0.340 (8.636)
0.0091 (.23)
0.0125 (.32)
0.094 (2.39)
0.102 (2.59)
0.260 (6.604)
0.275 (6.985)
0.014 (.36)
0.019 (.48)
0.128 (3.251)
0.148 (3.759)
0.035 (0.89)
0.045 (1.14)
0.720 (18.288)
0.730 (18.542)
0.088 (2.24)
0.098 (2.48)
Mechanical Data
28 Pin 300 Mil Plastic SOJ Package
0.040 (1.02) TYP.
Inches (mm)
0.741 (18.81) MAX.
0.0315 (0.80) TYP.
0.040 (1.02) TYP.
0.016 (0.40)
0.008 (0.20)
0.040 (1.02) TYP.
0.039 (1.00) TYP.
0.004 (0.10)
0.000 (0.00)
0.044 (1.13) MAX.
0.010 (0.24)
0.004 (0.09)
0.308 (7.82)
0.292 (7.42)
0.371 (9.42)
0.355 (9.02)
0.024 (0.60)
0.016 (0.40)
0.039 (1.00)
0.023 (0.60)
7° TYP.
Mechanical Data
44 Pin 300 Mil Plastic TSOP-II Package
The information contained herein is subject to change without notice. Enhanced Memory Systems Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in
an Enhanced product, nor does it convey or imply any license under patent or other rights.