ISP1504C1ETTM - ST-Ericsson Inc - Datasheet.Directory

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1. General description

The ISP1504A1; ISP1504C1 (ISP1504x1) is a Universal Serial Bus (USB) On-The-Go

(OTG) transceiver that is fully compliant with

Universal Serial Bus Speciﬁcation Rev. 2.0

On-The-Go Supplement to the USB 2.0 Speciﬁcation Rev. 1.2

and

UTMI+ Low Pin

Interface (ULPI) Speciﬁcation Rev. 1.1

The ISP1504x1 can transmit and receive USB data at high-speed (480 Mbit/s), full-speed

(12 Mbit/s) and low-speed (1.5 Mbit/s), and provides a pin-optimized, physical layer

front-end attachment to the USB host, peripheral and OTG devices.

It is ideal for use in portable electronic devices, such as mobile phones, digital still

cameras, digital video cameras, Personal Digital Assistants (PDAs) and digital audio

players. It allows USB Application-Speciﬁc Integrated Circuits (ASICs), Programmable

Logic Devices (PLDs) and any system chip set to interface with the physical layer of the

USB through a 12-pin interface.

The ISP1504x1 can interface to devices with digital I/O voltages in the range of 1.65 V to

3.6 V.

The ISP1504x1 is available in TFBGA36 package.

2. Features

nFully complies with:

Universal Serial Bus Speciﬁcation Rev. 2.0

On-The-Go Supplement to the USB 2.0 Speciﬁcation Rev. 1.2

UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev 1.1

nInterfaces to host, peripheral and OTG device cores; optimized for portable devices or

system ASICs with built-in USB OTG device core

nComplete Hi-Speed USB physical front-end solution that supports high-speed

(480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)

uIntegrated 45 Ω± 10 % high-speed termination resistors, 1.5 kΩ± 5 % full-speed

device pull-up resistor, and 15 kΩ± 5 % host termination resistors

uIntegrated parallel-to-serial and serial-to-parallel converters to transmit and receive

uUSB clock and data recovery to receive USB data at ±500 ppm

uUSB data synchronization from 60 MHz input to 480 MHz output during transmit

uInsertion of stuff bits during transmit and discarding of stuff bits during receive

uNon-Return-to-Zero Inverted (NRZI) encoding and decoding

uSupports bus reset, suspend, resume and high-speed detection handshake (chirp)

nComplete USB OTG physical front-end that supports Host Negotiation Protocol (HNP)

and Session Request Protocol (SRP)

ISP1504A1; ISP1504C1

ULPI Hi-Speed Universal Serial Bus On-The-Go transceiver

Rev. 01 — 6 August 2007 Product data sheet

Product data sheet Rev. 01 — 6 August 2007 2 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

uSupports external charge pump or 5 V VBUS switch

uComplete control over bus resistors

uData line and VBUS pulsing session request methods

uIntegrated VBUS voltage comparators

uIntegrated cable (ID) detector

nHighly optimized ULPI-compliant interface

u60 MHz, 8-bit interface between the core and the transceiver

uIntegrated Phase-Locked Loop (PLL) supporting input clock frequency of 19.2 MHz

for ISP1504A1, and 26 MHz for ISP1504C1

uFully programmable ULPI-compliant register set

uInternal Power-On Reset (POR) circuit

nFlexible system integration and very low current consumption, optimized for portable

devices

uPower-supply input range is 3.0 V to 4.5 V

uInternal voltage regulator supplies 3.3 V and 1.8 V

uSupports external VBUS charge pump or 5 V supply:

External VBUS source is controlled using the PSW_N pin; open-drain PSW_N

allows per-port or ganged power control

Digital FAULT input to monitor the external VBUS supply status

uPin CS_N/PWRDN 3-states the ULPI interface, allowing bus reuse for other

applications

uSupports power-down mode when VCC(I/O) is not present or when

pin CS_N/PWRDN is HIGH

uSupports wide range interfacing I/O voltage of 1.65 V to 3.6 V; separate I/O voltage

pins minimize crosstalk

uTypical operating current of 10 mA to 48 mA, depending on the USB speed and

bus utilization

uTypical suspend current of 50 µA

uTypical power-down current of 0.5 µA

nFull industrial grade operating temperature range from −40 °C to +85 °C

nElectroStatic Discharge (ESD) compliance

uJESD22-A114D 2 kV contact Human Body Model (HBM)

uJESD22-A115-A 200 V Machine Model (MM)

uJESD22-C101-C 500 V Charge Device Model (CDM)

nAvailable in a small TFBGA36 (3.5 mm × 3.5 mm) Restriction of Hazardous

Substances (RoHS) compliant, halogen-free and lead-free package

3. Applications

nDigital still camera

nDigital TV

nDigital Versatile Disc (DVD) recorder

nExternal storage device, for example:

uZip drive

uMagneto-Optical (MO) drive

uOptical drive: CD-ROM, CD-RW, CD-DVD

Product data sheet Rev. 01 — 6 August 2007 3 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

nMobile phone

nMP3 player

nPDA

nPrinter

nScanner

nSet-Top Box (STB)

nVideo camera

4. Ordering information

[1] The package marking is the ﬁrst line of text on the IC package and can be used for IC identiﬁcation.

Table 1. Ordering information

Part Package

Type number Marking Crystalorclock

frequency Name Description Version

ISP1504A1ET 504M[1] 19.2 MHz TFBGA36 plastic thin ﬁne-pitch ball grid array package;

36 balls; body 3.5 × 3.5 × 0.8 mm SOT912-1

ISP1504C1ET 504P[1] 26 MHz

Product data sheet Rev. 01 — 6 August 2007 4 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

5. Block diagram

Fig 1. Block diagram

MAP

ULPI

INTERFACE

CONTROLLER

USB DATA

SERIALIZER

USB DATA

DESERIALIZER

HI-SPEED USB ATX

STP

DIR

NXT

DATA

[7:0]

B1, A1,

A2, A3,

A5, A6,

B6, C6

004aaa942

CLOCK A4

TERMINATION

RESISTORS

DETECTOR

VBUS

COMPARATORS

ON-THE-GO MODULE

SRP CHARGE

AND DISCHARGE

RESISTORS

POWER-ON

RESET

PLL

CRYSTAL

OSCILLATOR

VOLTAGE

REGULATOR

BAND GAP

REFERENCE

VOLTAGE RREF

internal power

VCC F3

REG3V3

REG1V8

RESET_N

global

reset

global clocks

XTAL2

XTAL1 F5

VCC(I/O)

B2, B3,

B5 interface voltage PSW_N

Drive VBUS external

VBUS

FAULT

ISP1504x1

ULPI

interface

USB

cable

VREF

CS_N/PWRDN C3

VBUS valid external

B4, C5,

D2, E1, E4

GND

Product data sheet Rev. 01 — 6 August 2007 5 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

6. Pinning information

6.1 Pinning

6.2 Pin description

Fig 2. Pin conﬁguration TFBGA36; top view

004aaa943

ISP1504x1

Transparent top view

246135

ball A1

index area

Table 2. Pin description

Symbol[1][2] Pin Type[3] Description[4]

DATA1 A1 I/O pin 1 of the bidirectional ULPI data bus

slew rate controlled output (1 ns); plain input; programmable pull down

DATA2 A2 I/O pin 2 of the bidirectional ULPI data bus

slew rate controlled output (1 ns); plain input; programmable pull down

DATA3 A3 I/O pin 3 of the bidirectional ULPI data bus

slew rate controlled output (1 ns); plain input; programmable pull down

CLOCK A4 O 60 MHz clock output for ULPI

slew rate controlled output (1 ns)

DATA4 A5 I/O pin 4 of the bidirectional ULPI data bus

slew rate controlled output (1 ns); plain input; programmable pull down

DATA5 A6 I/O pin 5 of the bidirectional ULPI data bus

slew rate controlled output (1 ns); plain input; programmable pull down

DATA0 B1 I/O pin 0 of the bidirectional ULPI data bus

slew rate controlled output (1 ns); plain input; programmable pull down

VCC(I/O) B2, B3, B5 P input I/O supply voltage; allowable range 1.65 V to 3.6 V; a 0.1 µF decoupling

capacitor is recommended

GND B4, C5, D2,

E1, E4 P ground supply

DATA6 B6 I/O pin 6 of the bidirectional ULPI data bus

slew rate controlled output (1 ns); plain input; programmable pull down

DM C1 AI/O data minus (D−) pin of the USB cable

RREF C2 AI/O resistor reference; connect through 12 kΩ± 1 % to GND

Product data sheet Rev. 01 — 6 August 2007 6 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

[1] Symbol names ending with underscore N, for example, NAME_N, indicate active LOW signals.

[2] For details on external components required on each pin, see bill of materials and application diagrams in Section 15.

[3] I = input; O = output; I/O = digital input/output; OD = open-drain output; AI/O = analog input/output; P = power or ground pin.

[4] A detailed description of these pins can be found in Section 7.9.

CS_N/

PWRDN C3 I active LOW chip select

•When this pin is HIGH, ULPI pins will be 3-stated and the chip is in power-down

mode.

•When this pin is LOW, ULPI pins will operate normally.

plain input

RESET_N C4 I active LOW, asynchronous reset input

If this pin is not used, it must directly be connected to VCC(I/O).

plain input

DATA7 C6 I/O pin 7 of the bidirectional ULPI data bus

slew rate controlled output (1 ns); plain input; programmable pull down

DP D1 AI/O data plus (D+) pin of the USB cable

ID D3 I identiﬁcation (ID) pin of the micro-USB cable; see Section 7.6.1

If this pin is not used, it is recommended to connect it to REG3V3.

plain input; TTL level

PSW_N D4 OD active LOW external VBUS power switch or external charge pump enable

open-drain output; 5 V tolerant

NXT D5 O ULPI next signal

slew rate controlled output (1 ns)

STP D6 I ULPI stop signal

plain input; programmable pull up

FAULT E2 I input pin for the external VBUS digital overcurrent or the fault detector signal

If this pin is not used, it must be connected to ground.

plain input; 5 V tolerant

REG3V3 E3 P 3.3 V regulator output requiring parallel 0.1 µF and 4.7 µF capacitors; internally

powers OTG, analog core and ATX; cannot be externally used as a power source

DIR E5 O ULPI direction signal

slew rate controlled output (1 ns)

REG1V8 E6 P 1.8 V regulator output requiring parallel 0.1 µF and 4.7 µF capacitors; internally

powers digital core and analog core; cannot be externally used as a power source

n.c. F1, F2 - not connected

VCC F3 P input supply voltage or battery source; 3.0 V to 4.5 V

VBUS F4 AI/O must be connected to the VBUS pin of the USB cable; required in all conﬁgurations,

except when the ISP1504x1 is used as a host-only with an external 5 V source

XTAL1 F5 AI/O crystal oscillator or clock input; 1.8 V peak input allowed; frequency is 19.2 MHz for

ISP1504A1, and 26 MHz for ISP1504C1

XTAL2 F6 AI/O crystal oscillator output; if crystal is not in use, leave this pin open

Table 2. Pin description

…continued

Symbol[1][2] Pin Type[3] Description[4]

Product data sheet Rev. 01 — 6 August 2007 7 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

7. Functional description

7.1 ULPI interface controller

The ISP1504x1 provides a 12-pin interface that is compliant with

UTMI+ Low Pin Interface

(ULPI) Speciﬁcation Rev. 1.1

. This interface must be connected to the USB link.

The ULPI interface controller provides the following functions:

•ULPI-compliant interface and register set

•Allows full control over the USB peripheral, host and OTG functionality

•Parses the USB transmit and receive data

•Prioritizes the USB receive data, USB transmit data, interrupts and register operations

•Low-power mode

•Control of the VBUS external power source

•VBUS monitoring, charging and discharging

•6-pin serial mode and 3-pin serial mode

•Generates RXCMDs; status updates

•Maskable interrupts

•Control over the ULPI bus state, allowing pins to 3-state or attach active weak

pull-down resistors

For more information on the ULPI protocol, see Section 9.

7.2 USB data serializer and deserializer

The USB data serializer prepares data to transmit on the USB bus. To transmit data, the

USB link sends a transmit command and data on the ULPI bus. The serializer performs

parallel-to-serial conversion, bit stufﬁng and NRZI encoding. For packets with a PID, the

serializer adds a SYNC pattern to the start of the packet, and an EOP pattern to the end

of the packet. When the serializer is busy and cannot accept any more data, the ULPI

interface controller de-asserts NXT.

The USB data deserializer decodes data received from the USB bus. When data is

received, the deserializer strips the SYNC and EOP patterns, and then performs

serial-to-parallel conversion, NRZI decoding and discarding of stuff bits on the data

payload. The ULPI interface controller sends data to the USB link by asserting DIR, and

then asserting NXT whenever a byte is ready. The deserializer also detects various

receive errors, including bit stuff errors, elasticity buffer underrun or overrun, and

byte-alignment errors.

7.3 Hi-Speed USB (USB 2.0) ATX

The Hi-Speed USB ATX block is an analog front-end containing the circuitry needed to

transmit, receive and terminate the USB bus in high-speed, full-speed and low-speed, for

USB peripheral, host and OTG implementations. The following circuitry is included:

•Differential drivers to transmit data at high-speed, full-speed and low-speed

Product data sheet Rev. 01 — 6 August 2007 8 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

•Differential and single-ended receivers to receive data at high-speed, full-speed and

low-speed

•Squelch circuit to detect high-speed bus activity

•High-speed disconnect detector

•45 Ω high-speed bus terminations on DP and DM

•1.5 kΩ pull-up resistor on DP

•15 kΩ pull-down resistor on DP and DM

For details on controlling resistor settings, see Table 8.

7.4 Voltage regulator

The ISP1504x1 contains a built-in voltage regulator that conditions the VCC supply for use

inside the ISP1504x1. The voltage regulator:

•Supports input supply range of 3.0 V < VCC < 4.5 V

•Can be supplied from a battery with a voltage range of 3.0 V to 4.5 V

•Supplies internal circuitry with 1.8 V and 3.3 V

•Automatically bypasses the internal 3.3 V regulator when VCC < 3.5 V, drawing power

directly from the VCC pin

To save current, the voltage regulator will be shut down, if VCC(I/O) is not present or if

pin CS_N/PWRDN is at a HIGH level.

Remark: The REG1V8 and REG3V3 pins require an external 0.1 µF capacitor in parallel

with a 4.7 µF capacitor. For details, see Section 15.

7.5 Crystal oscillator and PLL

The ISP1504x1 has a built-in crystal oscillator and a Phase-Locked Loop (PLL) for clock

generation.

The crystal oscillator takes a sine-wave input from an external crystal, on the XTAL1 pin,

and converts it to a square wave clock for internal use. Alternatively, a square wave clock

of the same frequency can also be directly driven into the XTAL1 pin. Using an existing

square wave clock can save the cost of the crystal and also reduce the board size. The

input clock or crystal frequency supported is 19.2 MHz or 26 MHz.

The PLL produces the following frequencies, irrespective of the clock source:

•60 MHz clock for the ULPI interface controller

•1.5 MHz for the low-speed USB data

•12 MHz for the full-speed USB data

•480 MHz for the high-speed USB data

•Other internal frequencies for data conversion and data recovery

7.6 OTG module

This module contains several sub-blocks that provide all the functionality required by the

USB OTG speciﬁcation. Speciﬁcally, it provides the following circuits:

Product data sheet Rev. 01 — 6 August 2007 9 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

•The ID detector to sense the ID pin of the micro-USB cable. The ID pin dictates which

device is initially conﬁgured as the host and which as the peripheral.

•VBUS comparators to determine the VBUS voltage level. This is required for the VBUS

detection, SRP and HNP.

•Resistors to temporarily charge and discharge VBUS. This is required for SRP.

Remark: The ISP1504x1 does not include the 5 V charge pump to power VBUS.

7.6.1 ID detector

The ID detector detects which end of the micro-USB cable is plugged in. The detector

must ﬁrst be enabled by setting the ID_PULLUP register bit to logic 1. If the ISP1504x1

senses a value on ID that is different from the previously reported value, an RXCMD

status update will be sent to the USB link, or an interrupt will be asserted.

•If the micro-B end of the cable is plugged in, the ISP1504x1 will report that ID_GND is

logic 1. The USB link must change to peripheral mode.

•If the micro-A end of the cable is plugged in, the ISP1504x1 will report that ID_GND is

logic 0. The USB link must change to host mode.

7.6.2 VBUS comparators

The ISP1504x1 provides three comparators, VBUS valid comparator, session valid

comparator and session end comparator, to detect the VBUS voltage level.

7.6.2.1 VBUS valid comparator

This comparator is used by hosts and OTG A-devices to determine whether the voltage on

VBUS is at a valid level for operation. The ISP1504x1 threshold for the VBUS valid

comparator is VA_VBUS_VLD. Any voltage on VBUS below VA_VBUS_VLD is considered a fault.

During power-up, it is expected that the comparator output will be ignored.

7.6.2.2 Session valid comparator

The session valid comparator is a TTL-level input that determines when VBUS is high

enough for a session to start. Peripherals, A-devices and B-devices use this comparator to

detect when a session is started. The A-device also uses this comparator to determine

when a session is completed. The session valid threshold of the ISP1504x1 is

VA_SESS_VLD, with a hysteresis of Vhys(A_SESS_VLD).

7.6.2.3 Session end comparator

The ISP1504x1 session end comparator determines when VBUS is below the B-device

session end threshold. The B-device uses this threshold to determine when a session has

ended. The session end threshold of the ISP1504x1 is VB_SESS_END.

7.6.3 SRP charge and discharge resistors

The ISP1504x1 provides on-chip resistors for short-term charging and discharging of

VBUS. These are used by the B-device to request a session, prompting the A-device to

restore the VBUS power. First, the B-device makes sure that VBUS is fully discharged from

the previous session by setting the DISCHRG_VBUS register bit to logic 1 and waiting for

SESS_END to be logic 1. Then the B-device charges VBUS by setting the CHRG_VBUS

threshold and starts a session by turning on the VBUS power.

Product data sheet Rev. 01 — 6 August 2007 10 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

7.7 Band gap reference voltage

The band gap circuit provides a stable internal voltage reference to bias analog circuitry.

The band gap requires an accurate external reference resistor. Connect a 12 kΩ± 1%

resistor between the RREF pin and GND.

7.8 Power-On Reset (POR)

The ISP1504x1 has an internal POR circuit that resets all internal logic on power-up. The

ULPI interface is also reset on power-up.

Remark: When CLOCK starts toggling after power-up, the USB link must issue a reset

command over the ULPI bus to ensure correct operation of the ISP1504x1.

7.9 Detailed description of pins

7.9.1 DATA[7:0]

Bidirectional data bus. The USB link must drive DATA[7:0] to LOW when the ULPI bus is

idle. When the link has data to transmit to the PHY, it drives a nonzero value.

The data bus can be reconﬁgured to carry various data types, as given in Section 8 and

Section 9.

The DATA[7:0] pins can be 3-stated by driving pin CS_N/PWRDN to HIGH. Weak

pull-down resistors are incorporated into the DATA[7:0] pins as part of the interface protect

feature. For details, see Section 9.3.1.

7.9.2 VCC(I/O)

The input voltage that sets the I/O voltage level. The ISP1504x1 supports nominal I/O

voltages in the range of 1.8 V to 3.3 V. A 0.1 µF decoupling capacitor is recommended.

VCC(I/O) provides power to on-chip pads of the following pins:

•CLOCK

•CS_N/PWRDN

•DATA[7:0]

•DIR

•NXT

•RESET_N

•STP

If VCC(I/O) is not present while VCC is present, the chip is put in power-down mode.

7.9.3 RREF

Resistor reference analog I/O pin. A 12 kΩ± 1 % resistor must be connected between

RREF and GND, as shown in Section 15. This provides an accurate voltage reference that

biases internal analog circuitry. Less accurate resistors cannot be used and will render the

ISP1504x1 unusable.

Product data sheet Rev. 01 — 6 August 2007 11 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

7.9.4 DP and DM

DP (data plus) and DM (data minus) are USB differential data pins. These must be

connected to the D+ and D− pins of the USB receptacle.

7.9.5 FAULT

If an external VBUS overcurrent or fault circuit is used, the output fault indicator of that

circuit can be connected to the ISP1504x1 FAULT input pin. The ISP1504x1 will inform the

link of VBUS fault events by sending RXCMDs on the ULPI bus. To use the FAULT pin, the

link must set the USE_EXT_VBUS_IND register bit to logic 1, and the polarity of the

external fault signal must be set using the IND_COMPL register bit.

7.9.6 ID

For OTG implementations, the ID (identiﬁcation) pin is connected to the ID pin of the

micro-USB receptacle. As deﬁned in

On-The-Go Supplement to the USB 2.0 Speciﬁcation

Rev. 1.2

, the ID pin dictates the initial role of the link. If ID is detected as HIGH, the link

must assume the role of a peripheral. If ID is detected as LOW, the link must assume a

host role. Roles can be swapped at a later time by using HNP.

If the ISP1504x1 is not used as an OTG PHY, but as a standard USB host or peripheral

PHY, it is recommended to connect the ID pin to REG3V3.

7.9.7 VCC

VCC is the main input supply voltage for the ISP1504x1. A 0.1 µF decoupling capacitor is

recommended. For details, see Section 15.

7.9.8 PSW_N

PSW_N is an active LOW, open-drain output pin. This pin can be connected to an active

LOW, external VBUS switch or charge pump enable circuit to control the external VBUS

power source.

If the link is in host mode, it can enable the external power switch by setting the

DRV_VBUS_EXT bit in the OTG Control register to logic 1. The ISP1504x1 will drive

PSW_N to LOW to enable the external switch. If the link detects an overcurrent condition

(the VBUS state in RXCMD is not 11b), it must disable the external VBUS supply by setting

DRV_VBUS_EXT to logic 0.

An external pull-up resistor, Rpullup, is required when PSW_N is used. This pin is

open-drain, allowing ganged mode power control for multiple USB ports.

7.9.9 VBUS

This pin acts as an input to VBUS comparators, and also as a power pin for SRP charge

and discharge resistors.

The VBUS pin requires a capacitive load. Table 3 provides the recommended capacitor for

various applications.

Product data sheet Rev. 01 — 6 August 2007 12 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

7.9.10 REG3V3 and REG1V8

Regulator output voltage. These supplies are used to power the ISP1504x1 internal digital

and analog circuits, and must not be used to power external circuits.

For correct operation of the regulator, it is recommended that you connect REG3V3 and

REG1V8 to a 0.1 µF capacitor in parallel with a 4.7 µF capacitor. For examples, see

Section 15.

7.9.11 XTAL1 and XTAL2

XTAL1 is the crystal input, and XTAL2 is the crystal output. The allowed frequency on the

XTAL1 pin is 19.2 MHz or 26 MHz.

Either a crystal must be attached, or a clock of the same frequency must be driven into

XTAL1, with XTAL2 left ﬂoating.

If a crystal is attached, it requires capacitors to GND on each terminal of the crystal. For

details, see Section 15.

7.9.12 RESET_N

An active LOW asynchronous reset pin that resets all circuits in the ISP1504x1. The

RESET_N pin must be connected to VCC(I/O), if not used. The ISP1504x1 contains an

internal power-on reset circuit, and therefore using the RESET_N pin is optional.

For details on using RESET_N, see Section 9.3.2.

Table 3. Recommended VBUS capacitor value

Application VBUS capacitor (CVBUS)

OTG 1 µF to 6.5 µF, 10 V

Standard host 120 µF± 20 %, 10 V

Standard peripheral 1 µF to 10 µF, 10 V

Fig 3. Application circuit components

004aaa871

RUP(VBUS)

RDN(VBUS) RI(idle)(VBUS)

VBUS

comparators

DISCHRG_

VBUS

CHRG_VBUS

VBUS

REG3V3

Product data sheet Rev. 01 — 6 August 2007 13 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

7.9.13 DIR

ULPI direction output pin. Controls the direction of the data bus. By default, the

ISP1504x1 holds DIR at LOW, causing the data bus to be an input. When DIR is LOW, the

ISP1504x1 listens for data from the link. The ISP1504x1 pulls DIR to HIGH only when it

has data to send to the link, which is for one of two reasons:

•To send the USB receive data, RXCMD status updates and register read data to the

link.

•To block the link from driving the data bus during power-up, reset and low-power

mode (suspend).

For details on DIR usage, refer to

UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1

7.9.14 STP

ULPI stop input pin. The link must assert STP to signal the end of a USB transmit packet

or a register write operation. When DIR is asserted, the link can optionally assert STP to

abort the ISP1504x1, causing it to de-assert DIR in the next clock cycle. A weak pull-up

resistor is incorporated into the STP pin as part of the interface protect feature. For details,

see Section 9.3.1.

For details on STP usage, refer to

UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1

7.9.15 NXT

ULPI next data output pin. The ISP1504x1 holds NXT at LOW, by default. When DIR is

LOW and the link is sending data to the ISP1504x1, NXT will be asserted to notify the link

to provide the next data byte. When DIR is HIGH and the ISP1504x1 is sending data to

the link, NXT will be asserted to notify the link that another valid byte is on the bus. NXT is

not used for register read data or the RXCMD status update.

For details on NXT usage, refer to

UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1

7.9.16 CLOCK

A 60 MHz interface clock to synchronize the ULPI bus.

7.9.17 CS_N/PWRDN

Active LOW chip select pin. When CS_N/PWRDN is HIGH, ULPI output pins DATA[7:0],

CLOCK, DIR and NXT are 3-stated and ignored. All internal circuits, including the internal

regulator, are powered down. When CS_N/PWRDN is LOW, the ISP1504x1 will wake up

and the ULPI bus will operate normally.

If CS_N/PWRDN is not used, it must be connected to LOW. For more information on using

CS_N/PWRDN, see Section 9.3.3.

7.9.18 GND

Power and signal ground. To ensure correct operation of the ISP1504x1, GND must be

soldered to the cleanest ground available.

Product data sheet Rev. 01 — 6 August 2007 14 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

8. Modes of operation

8.1 ULPI modes

The ISP1504x1 ULPI bus can be programmed to operate in ﬁve modes. Each mode

reconﬁgures the signals on the data bus as described in the following subsections. Setting

more than one mode will lead to undeﬁned behavior.

8.1.1 Synchronous mode

This is default mode. At power-up, and when CLOCK is stable, the ISP1504x1 will enter

synchronous mode. The link must synchronize all ULPI signals to CLOCK, meeting the

set-up and hold times as deﬁned in Section 14. A description of the ULPI pin behavior in

synchronous mode is given in Table 4.

This mode is used by the link to perform the following tasks:

•High-speed detection handshake (chirp)

•Transmit and receive USB packets

•Read and write to registers

•Receive USB status updates (RXCMDs)

For more information on various synchronous mode protocols, see Section 9.

Table 4. ULPI signal description

Signal

name Directionon

ISP1504x1 Signal description

CLOCK O 60 MHz interface clock: During low-power and serial modes, the

clock can be turned off to save power.

DATA[7:0] I/O 8-bit data bus: In synchronous mode, the link drives DATA[7:0] to

LOW by default. The link initiates transfers by sending a nonzero data

pattern called TXCMD (transmit command). In synchronous mode, the

direction of DATA[7:0] is controlled by DIR. Contents of DATA[7:0] lines

must be ignored for exactly one clock cycle whenever DIR changes

value. This is called the turnaround cycle.

Data lines have ﬁxed direction and different meaning in low-power and

serial modes.

Product data sheet Rev. 01 — 6 August 2007 15 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

8.1.2 Low-power mode

When the USB is idle, the link can place the ISP1504x1 into low-power mode (also called

suspend mode). In low-power mode, the data bus deﬁnition changes to that shown in

Table 5. To enter low-power mode, the link sets the SUSPENDM bit in the Function

Control register to logic 0. To exit low-power mode, the link asserts the STP signal. The

ISP1504x1 will draw only suspend current from the VCC supply (see Table 46).

During low-power mode, the clock on XTAL1 may be stopped. The clock must be started

again before asserting STP to exit low-power mode. After exiting low-power mode, the

ISP1504x1 will send an RXCMD to the link if a change was detected in any interrupt

source, and the change still exists. An RXCMD may not be sent if the interrupt condition is

removed before exiting.

For more information on low-power mode enter and exit protocols, refer to

UTMI+ Low Pin

Interface (ULPI) Speciﬁcation Rev. 1.1

DIR O Direction: Controls the direction of data bus DATA[7:0]. In

synchronous mode, the ISP1504x1 drives DIR to LOW by default,

making the data bus an input so that the ISP1504x1 can listen for

TXCMDs from the link. The ISP1504x1 drives DIR to HIGH only when

it has data for the link. When DIR and NXT are HIGH, the byte on the

data bus contains decoded USB data. When DIR is HIGH and NXT is

LOW, the byte contains status information called RXCMD (receive

command). The only exception to this rule is when the PHY returns

RXCMD byte. Every change in DIR causes a turnaround cycle on the

data bus, during which DATA[7:0] is not valid and must be ignored by

the link.

DIR is always asserted during low-power and serial modes.

STP I Stop: In synchronous mode, the link drives STP to HIGH for one cycle

after the last byte of data is sent to the ISP1504x1. The link can

optionally assert STP to force DIR to be de-asserted.

In low-power and serial modes, the link holds STP at HIGH to wake up

the ISP1504x1, causing the ULPI bus to return to synchronous mode.

NXT O Next: In synchronous mode, the ISP1504x1 drives NXT to HIGH to

throttle data. If DIR is LOW, the ISP1504x1 asserts NXT to notify the

link to place the next data byte on DATA[7:0] in the following clock

cycle. If DIR is HIGH, the ISP1504x1 asserts NXT to notify the link that

a valid USB data byte is on DATA[7:0] in the current cycle. The

ISP1504x1 always drives an RXCMD when DIR is HIGH and NXT is

LOW, unless register read data is to be returned to the link in the

current cycle.

NXT is not used in low-power or serial mode.

Table 4. ULPI signal description

…continued

Signal

name Directionon

ISP1504x1 Signal description

Product data sheet Rev. 01 — 6 August 2007 16 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

8.1.3 6-pin full-speed or low-speed serial mode

If the link requires a 6-pin serial interface to transmit and receive full-speed or low-speed

USB data, it can set the ISP1504x1 to 6-pin serial mode. In 6-pin serial mode, the data

bus deﬁnition changes to that shown in Table 6. To enter 6-pin serial mode, the link sets

the 6PIN_FSLS_SERIAL bit in the Interface Control register to logic 1. To exit 6-pin serial

mode, the link asserts STP. This is provided primarily for links that contain legacy

full-speed or low-speed functionality, providing a more cost-effective upgrade path to

high-speed. An interrupt pin is also provided to inform the link of USB events. If the link

requires CLOCK to be running during 6-pin serial mode, the CLOCK_SUSPENDM

For more information on 6-pin serial mode enter and exit protocols, refer to

UTMI+ Low

Pin Interface (ULPI) Speciﬁcation Rev. 1.1

8.1.4 3-pin full-speed or low-speed serial mode

If the link requires a 3-pin serial interface to transmit and receive full-speed or low-speed

USB data, it can set the ISP1504x1 to 3-pin serial mode. In 3-pin serial mode, the data

bus deﬁnition changes to that shown in Table 7. To enter 3-pin serial mode, the link sets

the 3PIN_FSLS_SERIAL bit in the Interface Control register to logic 1. To exit 3-pin serial

mode, the link asserts STP. This is provided primarily for links that contain legacy

full-speed or low-speed functionality, providing a more cost-effective upgrade path to

high-speed. An interrupt pin is also provided to inform the link of USB events. If the link

requires CLOCK to be running during 3-pin serial mode, the CLOCK_SUSPENDM

For more information on 3-pin serial mode enter and exit protocols, refer to

UTMI+ Low

Pin Interface (ULPI) Speciﬁcation Rev. 1.1

Table 5. Signal mapping during low-power mode

Signal Maps to Direction Description

LINESTATE0 DATA0 O combinatorial LINESTATE0 directly driven by the analog receiver

LINESTATE1 DATA1 O combinatorial LINESTATE1 directly driven by the analog receiver

Reserved DATA2 O reserved; the ISP1504x1 will drive this pin to LOW

INT DATA3 O active HIGH interrupt indication; will be asserted whenever any

unmasked interrupt occurs

Table 6. Signal mapping for 6-pin serial mode

Signal Maps to Direction Description

TX_ENABLE DATA0 I active HIGH transmit enable

TX_DAT DATA1 I transmit differential data on DP and DM

TX_SE0 DATA2 I transmit single-ended zero on DP and DM

INT DATA3 O active HIGH interrupt indication; will be asserted whenever any

unmasked interrupt occurs

RX_DP DATA4 O single-ended receive data from DP

RX_DM DATA5 O single-ended receive data from DM

RX_RCV DATA6 O differential receive data from DP and DM

Reserved DATA7 O reserved; the ISP1504x1 will drive this pin to LOW

Product data sheet Rev. 01 — 6 August 2007 17 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

8.1.5 Power-down mode

In this mode, the PHY will 3-state the DATA[7:0], CLOCK, NXT and DIR pins. The link can

reuse the 3-stated pins for other purposes. To enter power-down mode, the link must drive

the CS_N/PWRDN pin to HIGH. To exit power-down mode, the link must drive the

CS_N/PWRDN pin to LOW.

In this mode, the ISP1504x1 will do the following:

•All internal circuits, including the internal regulator, are powered down. The total

current from VCC is less than 10 µA.

•The DATA[7:0], NXT, CLOCK and DIR pins are 3-stated and ignored. The STP pin is

ignored.

•The pull-down resistors on DATA[7:0] are disabled.

•USB wake-up events cannot be detected. The link must ﬁrst wake up the ISP1504x1

by driving CS_N/PWRDN to LOW.

Table 7. Signal mapping for 3-pin serial mode

Signal Maps to Direction Description

TX_ENABLE DATA0 I active HIGH transmit enable

DAT DATA1 I/O transmit differential data on DP and DM when TX_ENABLE is HIGH

receive differential data from DP and DM when TX_ENABLE is LOW

SE0 DATA2 I/O transmit single-ended zero on DP and DM when TX_ENABLE is HIGH

receive single-ended zero from DP and DM when TX_ENABLE is LOW

INT DATA3 O active HIGH interrupt indication; will be asserted whenever any

unmasked interrupt occurs

Reserved DATA[7:4] O reserved; the ISP1504x1 will drive these pins to LOW

Product data sheet Rev. 01 — 6 August 2007 18 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

8.2 USB state transitions

A Hi-Speed USB host or an OTG device handles more than one electrical state as deﬁned

Universal Serial Bus Speciﬁcation Rev. 2.0

and

On-The-Go Supplement to the USB 2.0

Speciﬁcation Rev. 1.2

. The ISP1504x1 accommodates various states through the register

bit settings of XCVRSELECT[1:0], TERMSELECT, OPMODE[1:0], DP_PULLDOWN and

DM_PULLDOWN.

Table 8 summarizes operating states. The values of register settings in Table 8 will force

resistor settings as also given in Table 8. Resistor setting signals are deﬁned as follows:

•RPU_DP_EN enables the 1.5 kΩ pull-up resistor on DP

•RPD_DP_EN enables the 15 kΩ pull-down resistor on DP

•RPD_DM_EN enables the 15 kΩ pull-down resistor on DM

•HSTERM_EN enables the 45 Ω termination resistors on DP and DM

It is up to the link to set the desired register settings.

Fig 4. Entering and exiting 3-state in normal mode

CLOCK

004aaa733

CS_N/PWRDN

entering power-down mode exiting power-down mode

3-stated pins

DATA[7:0]

DIR

NXT

STP

tPWRUP

tPWRDN

Product data sheet Rev. 01 — 6 August 2007 19 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

Table 8. Operating states and corresponding resistor settings

Signaling mode Register settings Internal resistor settings

XCVR

SELECT

[1:0]

TERM

SELECT OPMODE

[1:0] DP_

PULL

DOWN

DM_

PULL

DOWN

RPU_DP

_EN RPD_DP

_EN RPD_

DM_EN HSTERM_

General settings

3-state drivers XXb Xb 01b Xb Xb 0b 0b 0b 0b

Power up or VBUS <

VB_SESS_END

01b 0b 00b 1b 1b 0b 1b 1b 0b

Host settings

Host chirp 00b 0b 10b 1b 1b 0b 1b 1b 1b

Host high-speed 00b 0b 00b 1b 1b 0b 1b 1b 1b

Host full-speed X1b 1b 00b 1b 1b 0b 1b 1b 0b

Host high-speed or

full-speed suspend 01b 1b 00b 1b 1b 0b 1b 1b 0b

Host high-speed or

full-speed resume 01b 1b 10b 1b 1b 0b 1b 1b 0b

Host low-speed 10b 1b 00b 1b 1b 0b 1b 1b 0b

Host low-speed

suspend 10b 1b 00b 1b 1b 0b 1b 1b 0b

Host low-speed

resume 10b 1b 10b 1b 1b 0b 1b 1b 0b

Host Test J or Test K 00b 0b 10b 1b 1b 0b 1b 1b 1b

Peripheral settings

Peripheral chirp 00b 1b 10b 0b 0b 1b 0b 0b 0b

Peripheral

high-speed 00b 0b 00b 0b 0b 0b 0b 0b 1b

Peripheral full-speed 01b 1b 00b 0b 0b 1b 0b 0b 0b

Peripheral

high-speed or

full-speed suspend

01b 1b 00b 0b 0b 1b 0b 0b 0b

Peripheral

high-speed or

full-speed resume

01b 1b 10b 0b 0b 1b 0b 0b 0b

Peripheral Test J or

Test K 00b 0b 10b 0b 0b 0b 0b 0b 1b

OTG settings

OTG device

peripheral chirp 00b 1b 10b 0b 1b 1b 0b 1b 0b

OTG device

peripheral

high-speed

00b 0b 00b 0b 1b 0b 0b 1b 1b

OTG device

peripheral full-speed 01b 1b 00b 0b 1b 1b 0b 1b 0b

Product data sheet Rev. 01 — 6 August 2007 20 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

OTG device

peripheral

high-speed and

full-speed suspend

01b 1b 00b 0b 1b 1b 0b 1b 0b

OTG device

peripheral

high-speed and

full-speed resume

01b 1b 10b 0b 1b 1b 0b 1b 0b

OTG device

peripheral Test J or

Test K

00b 0b 10b 0b 1b 0b 0b 1b 1b

Table 8. Operating states and corresponding resistor settings

…continued

Signaling mode Register settings Internal resistor settings

XCVR

SELECT

[1:0]

TERM

SELECT OPMODE

[1:0] DP_

PULL

DOWN

DM_

PULL

DOWN

RPU_DP

_EN RPD_DP

_EN RPD_

DM_EN HSTERM_

Product data sheet Rev. 01 — 6 August 2007 21 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

9. Protocol description

This following subsections describe the protocol for using the ISP1504x1.

9.1 ULPI references

The ISP1504x1 provides a 12-pin ULPI interface to communicate with the link. It is highly

recommended that you read

UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1

and

UTMI+ Speciﬁcation Rev. 1.0

9.2 Power-On Reset (POR)

An internal POR is generated when REG1V8 rises above VPOR(trip) for at least

tw(REG1V8_H). The internal POR pulse will also be generated whenever REG1V8 drops

below VPOR(trip) for more than tw(REG1V8_L), and then rises above VPOR(trip) again. The

voltage on REG1V8 is generated from VCC.

To give a better view of the functionality, Figure 5 shows a possible curve of REG1V8. The

internal POR starts with logic 0 at t0. At t1, the detector will see the passing of the trip

level so that POR turns to logic 1 and a delay element will add another tPORP before it

drops to logic 0. If REG1V8 dips from t2 to t3 for > tw(REG1V8_L), another POR pulse is

generated. If the dip at t4 to t5 is too short, that is, < tw(REG1V8_L), the internal POR pulse

will not react and will remain LOW.

9.3 Power-up, reset and bus idle sequence

Figure 6 shows a typical start-up sequence.

On power-up, the ISP1504x1 performs an internal power-on reset and asserts DIR to

indicate to the link that the ULPI bus cannot be used. When the internal PLL is stable, the

ISP1504x1 de-asserts DIR and outputs 60 MHz on the CLOCK pin. The power-up time

depends on the VCC supply rise time, the crystal start-up time, and the PLL start-up time

(tstartup(o)(CLOCK)). Whenever DIR is asserted, the ISP1504x1 drives the NXT pin to LOW

and drives DATA[7:0] with RXCMD values. When DIR is de-asserted, the link must drive

the data bus to a valid level. By default, the link must drive data to LOW. When the

ISP1504x1 initially de-asserts DIR on power-up, the link must ignore all RXCMDs until it

resets the ISP1504x1. Before beginning USB packets, the link must set the RESET bit in

the Function Control register to reset the ISP1504x1. After the RESET bit is set, the

ISP1504x1 will assert DIR until the internal reset completes. The ISP1504x1 will

automatically de-assert DIR and clear the RESET bit when reset has completed. After

every reset, an RXCMD is sent to the link to update USB status information. After this

sequence, the ULPI bus is ready for use and the link can start USB operations.

Fig 5. Internal power-on reset timing

004aaa751

REG1V8

t0 t1 t2 t3 t4 t5

VPOR(trip)

tPORP POR

tPORP

Product data sheet Rev. 01 — 6 August 2007 22 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

The recommended power-up sequence for the link is:

1. The CS_N/PWRDN pin transitions from HIGH to LOW.

2. The link waits for 1 ms, ignoring all the ULPI pin status.

3. The link may start to detect DIR status level. If DIR is detected LOW for three clock

cycles, the link may send a RESET command.

4. The ULPI interface is ready for use.

For details on power-up sequence, see Figure 6.

Product data sheet Rev. 01 — 6 August 2007 23 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

t1 = VCC is applied to the ISP1504x1.

t2 = VCC(I/O) is turned on. ULPI interface pins (CLOCK, DATA[7:0], DIR and NXT) are in 3-state as long as CS_N/PWRDN is

HIGH.

t3 = CS_N/PWRDN turns from HIGH to LOW. The ISP1504x1 regulator starts to turn on.

t4 = ULPI pads detect REG1V8 rising above the REG1V8 regulator threshold and are not in 3-state. These pads may drive

either LOW or HIGH. It is recommended that the link ignores the ULPI pins status during tPWRUP.

t5 = The POR threshold is reached and a POR pulse is generated. After the POR pulse, ULPI pins are driven to a deﬁned

level. DIR is driven to HIGH and the other pins are driven to LOW.

t6 = The 19.2 MHz or 26 MHz input clock starts. This clock may be started any time.

t7 = The internal PLL is stabilized after tstartup(PLL). If the 19.2 MHz or 26 MHz clock is started before POR, the internal PLL

will be stabilized after tstartup(PLL) from POR. The CLOCK pin starts to output 60 MHz. The DIR pin will transition from HIGH

to LOW. The link is expected to issue a RESET command to initialize the ISP1504x1.

t8 = The power-up sequence is completed and the ULPI bus interface is ready for use.

Fig 6. Power-up and reset sequence required before the ULPI bus is ready for use

CS_N/

PWRDN

CLOCK

TXCMD

DIR

DATA[7:0]

STP

NXT

004aaa768

RESET command

internal clocks stable

internal reset RXCMD

update

bus idle

VCC

VCC(I/O)

REG1V8

internal

REG1V8

detector

internal

POR

XTAL1

tstartup(PLL)

t1 t2 t3 t4 t5 t6 t7 t8

tPWRUP

Product data sheet Rev. 01 — 6 August 2007 24 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

9.3.1 Interface protection

By default, the ISP1504x1 enables a weak pull-up resistor on STP. If the STP pin is

unexpectedly HIGH at any time, the ISP1504x1 will protect the ULPI interface by enabling

weak pull-down resistors on DATA[7:0].

The interface protect feature prevents unwanted activity of the ISP1504x1 whenever the

ULPI interface is not correctly driven by the link. For example, when the link powers up

more slowly than the ISP1504x1.

The interface protect feature can be disabled by setting the INTF_PROT_DIS bit to logic 1.

If the interface protect feature is not needed, it must be disabled to reduce power

consumption.

9.3.2 Interface behavior with respect to RESET_N

The use of the RESET_N pin is optional. When RESET_N is asserted (LOW), the

ISP1504x1 will assert DIR. All logic in the ISP1504x1 will be reset, including the analog

circuitry and ULPI registers. During reset, the link must drive DATA[7:0] and STP to LOW;

otherwise undeﬁned behavior may result. When RESET_N is de-asserted (HIGH), the

DIR output will de-assert (LOW) four or ﬁve clock cycles later. Figure 7 shows the ULPI

interface behavior when RESET_N is asserted (LOW), and when RESET_N is

subsequently de-asserted (HIGH). The behavior of Figure 7 applies only when

CS_N/PWRDN is asserted (LOW). If RESET_N is not used, it must be tied to VCC(I/O).

9.3.3 Interface behavior with respect to CS_N/PWRDN

The use of the CS_N/PWRDN pin is optional. When de-asserted (HIGH), the

CS_N/PWRDN pin will 3-state ULPI pins and power down internal circuitry. If

CS_N/PWRDN is not used, it must be tied to LOW. Figure 8 shows the ULPI interface

behavior when CS_N/PWRDN is asserted (LOW) and when CS_N/PWRDN is

subsequently de-asserted (HIGH). The behavior of Figure 8 assumes that RESET_N is

de-asserted (HIGH).

Fig 7. Interface behavior with respect to RESET_N

CLOCK

004aaa720

STP

RESET_N

DATA[7:0]

DIR

NXT

Hi-Z (input)

Hi-Z (link must drive)

Product data sheet Rev. 01 — 6 August 2007 25 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

9.4 VBUS power and overcurrent detection

9.4.1 Driving 5 V on VBUS

The ISP1504x1 supports external 5 V supplies. The ISP1504x1 can control the external

supply using the active-LOW PSW_N open-drain output pin. To enable the external supply

by driving PSW_N to LOW, the link must set the DRV_VBUS_EXT bit in the OTG Control

Table 9 summarizes settings to drive 5 V on VBUS.

9.4.2 Fault detection

The ISP1504x1 supports external VBUS fault detector circuits that output a digital fault

indicator signal. The indicator signal must be connected to the FAULT pin. To enable the

ISP1504x1 to monitor the digital fault input, the link must set the USE_EXT_VBUS_IND

bit in the OTG Control register and the IND_PASSTHRU bit in the Interface Control

The FAULT input pin is mapped to the A_VBUS_VLD bit in RXCMD. Any changes for the

FAULT input will trigger RXCMD carrying the FAULT condition with A_VBUS_VLD.

9.5 TXCMD and RXCMD

Commands between the ISP1504x1 and the link are described in the following

subsections.

Fig 8. Interface behavior with respect to CS_N/PWRDN

CLOCK

004aaa734

STP

CS_N/PWRDN

DATA[7:0]

DIR

NXT

Hi-Z (input)

Hi-Z (ignored)

tPWRDN

Table 9. OTG Control register power control bits

DRV_VBUS_EXT Power source used

0 external 5 V VBUS power source disabled (PSW_N = HIGH)

1 external 5 V VBUS power source enabled (PSW_N = LOW)

Product data sheet Rev. 01 — 6 August 2007 26 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

9.5.1 TXCMD

By default, the link must drive the ULPI bus to its idle state of 00h. To send commands and

USB packets, the link drives a nonzero value on DATA[7:0] to the ISP1504x1 by sending a

byte called TXCMD. Commands include USB packet transmissions, and register reads

and writes. Once the TXCMD is interpreted and accepted by the ISP1504x1, the NXT

signal is asserted and the link can follow up with the required number of data bytes. The

TXCMD byte format is given in Table 10. Any values other than those in Table 10 are

illegal and will result in undeﬁned behavior.

Various TXCMD packet and register sequences are shown in later sections.

9.5.2 RXCMD

The ISP1504x1 communicates status information to the link by asserting DIR and sending

an RXCMD byte on the DATA bus. The RXCMD data byte format follows

UTMI+ Low Pin

Interface (ULPI) Speciﬁcation Rev. 1.1

and is given in Table 11.

The ISP1504x1 will automatically send an RXCMD whenever there is a change in any of

the RXCMD data ﬁelds. The link must be able to accept an RXCMD at any time; including

single RXCMDs, back-to-back RXCMDs, and RXCMDs at any time during USB receive

packets when NXT is LOW. An example is shown in Figure 9. For details and diagrams,

refer to

UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1

An RXCMD may not be sent when exiting low-power mode or serial mode, if the interrupt

condition is removed before exiting.

Table 10. TXCMD byte format

Command

type name Command code

DATA[7:6] Command

payload DATA[5:0] Command

name Command description

Idle 00b 00 0000b NOOP No operation. 00h is the idle value of the data bus.

The link must drive NOOP by default.

Packet

transmit 01b 00 0000b NOPID Transmit USB data that does not havea PID, such as

chirp and resume signaling. The ISP1504x1 starts

transmitting only after accepting the next data byte.

00 XXXXb PID Transmit USB packet. DATA[3:0] indicates USB

packet identiﬁer PID[3:0].

write 10b 10 1111b EXTW Extended register write command (optional). The

8-bit address must be provided after the command is

accepted.

XX XXXXb REGW Register write command with 6-bit immediate

address.

read 11b 10 1111b EXTR Extended register read command (optional). The

8-bit address must be provided after the command is

accepted.

XX XXXXb REGR Register read command with 6-bit immediate

address.

Product data sheet Rev. 01 — 6 August 2007 27 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

9.5.2.1 Linestate encoding

LINESTATE[1:0] reﬂects the current state of DP and DM. Whenever the ISP1504x1

detects a change in DP or DM, an RXCMD will be sent to the link with the new

LINESTATE[1:0] value. The value given on LINESTATE[1:0] depends on the setting of

various registers. Table 12 shows the LINESTATE[1:0] encoding for upstream facing ports,

which applies to peripherals. Table 13 shows the LINESTATE[1:0] encoding for

downstream facing ports, which applies to Host Controllers. Dual-role devices must

choose the correct table, depending on whether it is in peripheral or host mode.

[1] !squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates inactive HS_Differential_Receiver_Output.

Table 11. RXCMD byte format

DATA Name Description and value

1 to 0 LINESTATE LINESTATE signals: For a deﬁnition of LINESTATE, see Section 9.5.2.1.

DATA0 — LINESTATE[0]

DATA1 — LINESTATE[1]

3to2 V

BUS state Encoded VBUS voltage state: For an explanation of the VBUS state, see Section 9.5.2.2.

5 to 4 RxEvent Encoded USB event signals: For an explanation of RxEvent, see Section 9.5.2.4.

6 ID Set to the value of the ID pin.

7 ALT_INT By default, this signal is not used and is not needed in typical designs. Optionally, the link can

enable the BVALID_RISE and/or BVALID_FALL bits in the Power Control register. Corresponding

changes in BVALID will cause an RXCMD to be sent to the link with the ALT_INT bit asserted.

Fig 9. Single and back-to-back RXCMDs from the ISP1504x1 to the link

CLOCK

RXCMD

DATA[7:0]RXCMD RXCMD

004aaa695

DIR

STP

NXT

Single RXCMD Back-to-back RXCMDs

turnaround turnaround turnaround turnaround

Table 12. LINESTATE[1:0] encoding for upstream facing ports: peripheral

DP_PULLDOWN = 0.

[1]

Mode Full-speed High-speed Chirp

XCVRSELECT[1:0] 01, 11 00 00

TERMSELECT 1 0 1

LINESTATE[1:0] 00 SE0 squelch squelch

01 FS-J !squelch !squelch and HS_Differential_Receiver_Output

10 FS-K invalid !squelch and !HS_Differential_Receiver_Output

11 SE1 invalid invalid

Product data sheet Rev. 01 — 6 August 2007 28 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

[1] !squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates inactive HS_Differential_Receiver_Output.

9.5.2.2 VBUS state encoding

USB devices must monitor the VBUS voltage for purposes such as overcurrent detection,

starting a session and SRP. The VBUS state ﬁeld in the RXCMD is an encoding of the

voltage level on VBUS.

The SESS_END and SESS_VLD indicators in the VBUS state are directly taken from

internal comparators built-in to the ISP1504x1, and encoded as shown in Table 11 and

Table 14.

The A_VBUS_VLD indicator in the VBUS state provides several options and must be

conﬁgured based on current draw requirements. A_VBUS_VLD can input from one or

more VBUS voltage indicators, as shown in Figure 10.

A description on how to use and select the VBUS state encoding is given in

Section 9.5.2.3.

Table 13. LINESTATE[1:0] encoding for downstream facing ports: host

DP_PULLDOWN and DM_PULLDOWN = 1.

[1]

Mode Low-speed Full-speed High-speed Chirp

XCVRSELECT[1:0] 10 01, 11 00 00

TERMSELECT 1 1 0 0

OPMODE[1:0] X X 00, 01 or 11 10

LINESTATE[1:0] 00 SE0 SE0 squelch squelch

01 LS-K FS-J !squelch !squelch and HS_Differential_Receiver_Output

10 LS-J FS-K invalid !squelch and !HS_Differential_Receiver_Output

11 SE1 SE1 invalid invalid

Table 14. Encoded VBUS voltage state

Value VBUS voltage SESS_END SESS_VLD A_VBUS_VLD

00 VBUS < VB_SESS_END 100

01 VB_SESS_END ≤ VBUS < VA_SESS_VLD 000

10 VA_SESS_VLD ≤ VBUS < VA_VBUS_VLD X1 0

11 VBUS ≥ VA_VBUS_VLD XX1

Product data sheet Rev. 01 — 6 August 2007 29 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

9.5.2.3 Using and selecting the VBUS state encoding

The VBUS state encoding is shown in Table 11. The ISP1504x1 will send an RXCMD to the

link whenever there is a change in the VBUS state. To receive VBUS state updates, the link

must ﬁrst enable corresponding interrupts in the USB Interrupt Enable Rising Edge and

USB Interrupt Enable Falling Edge registers.

The link can use the VBUS state to monitor VBUS and take appropriate action. Table 15

shows the recommended usage for typical applications.

Standard USB Host Controllers: For standard hosts, the system must be able to provide

500 mA on VBUS in the range of 4.75 V to 5.25 V. An external circuit must be used to

detect overcurrent conditions. If the external overcurrent detector provides a digital fault

signal, then the fault signal must be connected to the ISP1504x1 FAULT input pin, and the

link must do the following:

1. Set the IND_COMPL bit in the Interface Control register to logic 0 or logic 1,

depending on the polarity of the external fault signal.

2. Set the USE_EXT_VBUS_IND bit in the OTG Control register to logic 1.

3. If it is not necessary to qualify the fault indicator with the internal A_VBUS_VLD

comparator, set the IND_PASSTHRU bit in the Interface Control register to logic 1.

Standard USB Peripheral Controllers: Standard peripherals must be able to detect

when VBUS is at a sufﬁcient level for operation. SESS_VLD must be enabled to detect the

start and end of USB peripheral operations. Detection of A_VBUS_VLD and SESS_END

thresholds is not needed for standard peripherals.

Fig 10. RXCMD A_VBUS_VLD indicator source

004aaa698

VBUS (0, X)

(1, 0)

FAULT

IND_COMPL

(1, 1)

USE_EXT_VBUS_IND,

IND_PASSTHRU

RXCMD

A_VBUS_VLD

A_VBUS_VLD comparator

internal A_VBUS_VLD

complement

output

FAULT indicator

Table 15. VBUS indicators in RXCMD required for typical applications

Application A_VBUS_VLD SESS_VLD SESS_END

Standard host yes no no

Standard peripheral no yes no

OTG A-device yes yes no

OTG B-device no yes yes

Product data sheet Rev. 01 — 6 August 2007 30 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

OTG devices: When an OTG device is conﬁgured as an OTG A-device, it must be able to

provide a minimum of 8 mA on VBUS. If the OTG A-device provides less than 100 mA, then

there is no need for an overcurrent detection circuit because the internal A_VBUS_VLD

comparator is sufﬁcient. If the OTG A-device provides more than 100 mA on VBUS, an

overcurrent detector must be used and Section “Standard USB Host Controllers” applies.

The OTG A-device also uses SESS_VLD to detect when an OTG A-device is initiating

VBUS pulsing SRP.

When an OTG device is conﬁgured as an OTG B-device, SESS_VLD must be used to

detect when VBUS is at a sufﬁcient level for operation. SESS_END must be used to detect

when VBUS has dropped to a LOW level, allowing the B-device to safely initiate VBUS

pulsing SRP.

9.5.2.4 RxEvent encoding

The RxEvent ﬁeld (see Table 16) of the RXCMD informs the link of information related

packets received on the USB bus. RxActive and RxError are deﬁned in

USB 2.0

Transceiver Macrocell Interface (UTMI) Speciﬁcation Ver. 1.05

. HostDisconnect is deﬁned

UTMI+ Speciﬁcation Rev. 1.0

. A short deﬁnition is also given in the following

subsections.

RxActive: When the ISP1504x1 has detected a SYNC pattern on the USB bus, it signals

an RxActive event to the link. An RxActive event can be communicated using two

methods. The ﬁrst method is for the ISP1504x1 to simultaneously assert DIR and NXT.

The second method is for the ISP1504x1 to send an RXCMD to the link with the RxActive

ﬁeld in RxEvent bits set to logic 1. The link must be able to detect both methods. RxActive

frames the receive packet from the ﬁrst byte to the last byte.

The link must assume that RxActive is set to logic 0 when indicated in an RXCMD or when

DIR is de-asserted, whichever occurs ﬁrst.

The link uses RxActive to time high-speed packets and ensure that bus turnaround times

are met. For more information on the USB packet timing, see Section 9.8.1.

RxError: When the ISP1504x1 has detected an error while receiving a USB packet, it

de-asserts NXT and sends an RXCMD with the RxError ﬁeld set to logic 1. The received

packet is no longer valid and must be dropped by the link.

HostDisconnect: HostDisconnect is encoded into the RxEvent ﬁeld of the RXCMD.

HostDisconnect is valid only when the ISP1504x1 is conﬁgured as a host (both

DP_PULLDOWN and DM_PULLDOWN are set to logic 1), and indicates to the Host

Controller when a peripheral is connected or disconnected. The Host Controller must

enable HostDisconnect by setting the HOST_DISCON_R and HOST_DISCON_F bits in

the USB Interrupt Enable Rising Edge and USB Interrupt Enable Falling Edge registers,

respectively. Changes in HostDisconnect will cause the PHY to send an RXCMD to the

link with the updated value.

Table 16. Encoded USB event signals

Value RxActive RxError HostDisconnect

00000

01100

11110

10XX1

Product data sheet Rev. 01 — 6 August 2007 31 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

9.6 Register read and write operations

Figure 11 shows register read and write sequences. The ISP1504x1 supports immediate

addressing and extended addressing register operations. Extended register addressing is

optional for links. Note that register operations will be aborted if the ISP1504x1 asserts

DIR during the operation. When a register operation is aborted, the link must retry until

successful. For more information on register operations, refer to

UTMI+ Low Pin Interface

(ULPI) Speciﬁcation Rev. 1.1

9.7 USB reset and high-speed detection handshake (chirp)

Figure 12 shows the sequence of events for USB reset and high-speed detection

handshake (chirp). The sequence is shown for hosts and peripherals. Figure 12 does not

show all RXCMD updates, and timing is not to scale. The sequence is as follows:

1. USB reset: The host detects a peripheral attachment as low-speed if DM is HIGH and

as full-speed if DP is HIGH. If a host detects a low-speed peripheral, it does not follow

the remainder of this protocol. If a host detects a full-speed peripheral, it resets the

peripheral by writing to the Function Control register and setting XCVRSELECT[1:0] =

00b (high-speed) and TERMSELECT = 0b, which drives SE0 on the bus (DP and DM

are connected to ground through 45 Ω). The host also sets OPMODE[1:0] = 10b for

correct chirp transmit and receive. The start of SE0 is labeled T0.

Remark: To receive chirp signaling, the host must also consider the high-speed

differential receiver output. The Host Controller must interpret LINESTATE as shown

in Table 13.

2. High-speed detection handshake (chirp)

a. Peripheral chirp: After detecting SE0 for no less than 2.5 µs, if the peripheral is

capable of high-speed, it sets XCVRSELECT[1:0] to 00b (high-speed) and

OPMODE[1:0] to 10b (chirp). The peripheral immediately follows this with a

TXCMD (NOPID), transmitting a Chirp K for no less than 1 ms and ending no more

AD indicates the address byte, and D indicates the data byte.

Fig 11. Example of register write, register read, extended register write and extended register read

CLOCK

DIR

DATA[7:0]

NXT

004aaa710

DTXCMD

(EXTW) AD D

immediate

TXCMD

(REGW) TXCMD

(REGR) DAD

TXCMD

(EXTW) D

STP

extended

Product data sheet Rev. 01 — 6 August 2007 32 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

than 7 ms after reset time T0. If the peripheral is in low-power mode, it must wake

up its clock within 5.6 ms, leaving 200 µs for the link to start transmitting the

Chirp K, and 1.2 ms for the Chirp K to complete (worst case with 10 % slow clock).

b. Host chirp: If the host does not detect the peripheral chirp, it must continue

asserting SE0 until the end of reset. If the host detects the peripheral Chirp K for

no less than 2.5 µs, then no more than 100 µs after the bus leaves the Chirp K

state, the host sends a TXCMD (NOPID) with an alternating sequence of Chirp Ks

and Js. Each Chirp K or Chirp J must last no less than 40 µs and no longer than

60 µs.

c. High-speed idle: The peripheral must detect a minimum of Chirp K-J-K-J-K-J. Each

Chirp K and Chirp J must be detected for at least 2.5 µs. After seeing that

minimum sequence, the peripheral sets TERMSELECT = 0b and OPMODE[1:0] =

00b. The peripheral is now in high-speed mode and sees !squelch (01b on

LINESTATE). When the peripheral sees squelch (10b on LINESTATE), it knows

that the host has completed chirp and waits for high-speed USB trafﬁc to begin.

After transmitting the chirp sequence, the host changes OPMODE[1:0] to 00b and

begins sending USB packets.

For more information, refer to

UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1

Product data sheet Rev. 01 — 6 August 2007 33 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

Timing is not to scale.

Fig 12. USB reset and high-speed detection handshake (chirp) sequence

004aaa711

DATA

[7:0]

TXCMD

NOPID J ... TXCMD

(REGW)

TXCMD

(REGW) SE0 K

DIR

STP

NXT

XCVR

SELECT

TERM

SELECT

01 (FS) 00 (HS)

MODE

00 (normal) 01 (chirp) 00 (normal)

LINE

STATE

J (01b) SE0 (00b) peripheral chirp K (10b) squelch (00b)

host chirp K (10b) or chirp J (01b)

squelch

(00b)

ULPI host

DATA

[7:0]

TXCMD

NOPID K...

SE0 TXCMD

(REGW) 00 KJKJKJTXCMD

(REGW) 00

DIR

STP

NXT

XCVR

SELECT

01 (FS) 00 (HS)

TERM

SELECT

MODE

00 (normal) 10 (chirp) 00 (normal)

LINE

STATE

J (01b) SE0 (00b) peripheral chirp K (10b) !squelch

(01b)

host chirp K or J (10b or 01b)

squelch

(00b) squelch (00b)

ULPI peripheral

USB signals

USB reset high-speed detection handshake (chirp)

peripheral chirp host chirp HS idle

RXCMDs

Product data sheet Rev. 01 — 6 August 2007 34 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

9.8 USB packet transmit and receive

An example of a packet transmit and receive is shown in Figure 13. For details on USB

packets, refer to

UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1

9.8.1 USB packet timing

9.8.1.1 ISP1504x1 pipeline delays

The ISP1504x1 delays are shown in Table 17. For detailed description, refer to

UTMI+

Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1, Section 3.8.2.6.2

9.8.1.2 Allowed link decision time

The amount of clock cycles allocated to the link to respond to a received packet and

correctly receive back-to-back packets is given in Table 18. Link designs must follow

values given in Table 18 for correct USB system operation. Examples of high-speed

packet sequences and timing are shown in Figure 14 and Figure 15. For details, refer to

UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1, Section 3.8.2.6.3

Fig 13. Example of using the ISP1504x1 to transmit and receive USB data

CLOCK

TXCMD DATA

DATA[7:0]RXCMD DATA

DIR

STP

NXT

004aaa944

link sends

TXCMD

ISP1504x1

accepts

TXCMD

link sends

the next data;

ISP1504x1

accepts link signals

end of data ULPI bus

is idle

ISP1504x1

asserts DIR,

causing

turnaround

cycle

ISP1504x1

sends

RXCMD

(NXT LOW)

ISP1504x1

sends

USB data

(NXT HIGH)

ISP1504x1

deasserts

DIR, causing

turnaround

cycle

turnaround turnaround

Table 17. PHY pipeline delays

Parameter name High-speed PHY delay Full-speed PHY delay Low-speed PHY delay

RXCMD delay (J and K) 4 4 4

RXCMD delay (SE0) 4 4 to 6 16 to 18

TX start delay 1 to 2 6 to 10 74 to 75

TX end delay (packets) 3 to 4 not applicable not applicable

TX end delay (SOF) 6 to 9 not applicable not applicable

RX start delay 5 to 6 not applicable not applicable

RX end delay 5 to 6 17 to 18 122 to 123

Product data sheet Rev. 01 — 6 August 2007 35 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

Table 18. Link decision times

Packet sequence High-speed

link delay Full-speed

link delay Low-speed

link delay Deﬁnition

Transmit-Transmit

(host only) 15 to 24 7 to 18 77 to 247 Number of clocks a host link must wait before driving the

TXCMD for the second packet.

In high-speed, the link starts counting from the assertion of

STP for the ﬁrst packet.

In full-speed, the link starts counting from the RXCMD,

indicating LINESTATE has changed from SE0 to J for the

ﬁrst packet. The timing given ensures inter-packet delays of

2 bit times to 6.5 bit times.

Receive-Transmit

(host or

peripheral)

1 to 14 7 to 18 77 to 247 Number of clocks the link must wait before driving the

TXCMD for the transmit packet.

In high-speed, the link starts counting from the end of the

receive packet; de-assertion of DIR or an RXCMD

indicating RxActive is LOW.

In full-speed or low-speed, the link starts counting from the

RXCMD, indicating LINESTATE has changed from SE0 to J

for the receive packet. The timing given ensures

inter-packet delays of 2 bit times to 6.5 bit times.

Receive-Receive

(peripheral only) 1 1 1 Minimum number of clocks between consecutive receive

packets. The link must be capable of receiving both

packets.

Transmit-Receive

(host or

peripheral)

92 80 718 Host or peripheral transmits a packet and will time-out after

this amount of clock cycles if a response is not received.

Any subsequent transmission can occur after this time.

Fig 14. High-speed transmit-to-transmit packet timing

004aaa712

DP or

DM DATA EOP IDLE SYNC

CLOCK

DN−1DN

DATA

[7:0]

TXCMD D1

DIR

STP

NXT

TX end delay (two to five clocks) link decision time (15 to 24 clocks) TX start delay

(one to two clocks)

USB interpacket delay (88 to 192 high-speed bit times)

Product data sheet Rev. 01 — 6 August 2007 36 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

9.9 Preamble

Preamble packets are headers to low-speed packets that must travel over a full-speed

bus, between a host and a hub. To enter preamble mode, the link sets

XCVRSELECT[1:0] = 11b in the Function Control register. When in preamble mode, the

ISP1504x1 operates just as in full-speed mode, and sends all data with full-speed rise and

fall times. Whenever the link transmits a USB packet in preamble mode, the ISP1504x1

will automatically send a preamble header at full-speed bit rate before sending the link

packet at low-speed bit rate. The ISP1504x1 will ensure a minimum gap of four full-speed

bit times between the last bit of the full-speed PRE PID and the ﬁrst bit of the low-speed

packet SYNC. The ISP1504x1 will drive a J for at least one full-speed bit time after

sending the PRE PID, after which the pull-up resistor can hold the J state on the bus. An

example transmit packet is shown in Figure 16.

In preamble mode, the ISP1504x1 can also receive low-speed packets from the full-speed

bus.

Fig 15. High-speed receive-to-transmit packet timing

004aaa713

DP or

DM DATA EOP IDLE SYNC

CLOCK

DN−4

DN−3

DATA

[7:0]

TXCMD D1

DIR

STP

NXT

RX end delay

(three to eight clocks) link decision time (1 to 14 clocks) TX start delay

(one to two clocks)

USB interpacket delay (8 to 192 high-speed bit times)

DN−2

DN−1

turnaround

Product data sheet Rev. 01 — 6 August 2007 37 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

9.10 USB suspend and resume

9.10.1 Full-speed or low-speed host-initiated suspend and resume

Figure 17 illustrates how a host or a hub places a full-speed or low-speed peripheral into

suspend and sometime later initiates resume signaling to wake up the downstream

peripheral. Note that Figure 17 timing is not to scale, and does not show all RXCMD

LINESTATE updates.

The sequence of events for a host and a peripheral, both with ISP1504x1, is as follows:

1. Idle: Initially, the host and the peripheral are idle. The host has its 15 kΩ pull-down

resistors enabled (DP_PULLDOWN and DM_PULLDOWN are set to 1b) and 45 Ω

terminations disabled (TERMSELECT is set to 1b). The peripheral has the 1.5 kΩ

pull-up resistor connected to DP for full-speed or DM for low-speed (TERMSELECT is

set to 1b).

2. Suspend: When the peripheral sees no bus activity for 3 ms, it enters the suspend

state. The peripheral link places the PHY into low-power mode by setting the

SUSPENDM bit in the Function Control register, causing the PHY to draw only

suspend current. The host may or may not be powered down.

3. Resume K: When the host wants to wake up the peripheral, it sets OPMODE[1:0] to

10b and transmits a K for at least 20 ms. The peripheral link sees the resume K on

LINESTATE, and asserts STP to wake up the PHY.

4. EOP: When STP is asserted, the ISP1504x1 on the host side automatically appends

an EOP of two bits of SE0 at low-speed bit rate, followed by one bit of J. The

ISP1504x1 on the host side knows to add the EOP because DP_PULLDOWN and

DM_PULLDOWN are set to 1b for a host. After the EOP is completed, the host link

sets OPMODE[1:0] to 00b for normal operation. The peripheral link sees the EOP and

also resumes normal operation.

DP and DM timing is not to scale.

Fig 16. Preamble sequence

CLOCK

TXCMD (low-speed packet ID) D1

DATA[7:0]

DIR

STP

NXT

004aaa714

DP or DM FS SYNC FS

PRE ID IDLE (min

4 FS bits) LS SYNC LS PID LS D0 LS D1

Product data sheet Rev. 01 — 6 August 2007 38 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

9.10.2 High-speed suspend and resume

Figure 18 illustrates how a host or a hub places a high-speed enabled peripheral into

suspend and then initiates resume signaling. The high-speed peripheral will wake up and

return to high-speed operations. Note that Figure 18 timing is not to scale, and does not

show all RXCMD LINESTATE updates.

Timing is not to scale.

Fig 17. Full-speed suspend and resume

DATA

[7:0]

TXCMD

NOPID K...

TXCMD

(REGW)

DIR

STP

NXT

OPMODE 00b 10b 00b

KTXCMD

LINE

STATE JKSE0 J

CLOCK

DATA

[7:0]

TXCMD

(REGW) LINESTATE J LINESTATE K SE0 J

DIR

STP

NXT

OPMODE 00b 10b 00b

SUSPEND

LINE

STATE J KSE0 J

004aaa715

FS or LS host (XCVRSELECT = 01b (FS)

or 10b (LS), DPPULLDOWN = 1b,

DMPULLDOWN = 1b, TERMSELECT = 1b)

FS or LS peripheral (XCVRSELECT = 01b (FS)

or 10b (LS), DPPULLDOWN = 0b, TERMSELECT = 1b)

USB signals

(only FS is shown)

idle suspend resume K EOP idle

Product data sheet Rev. 01 — 6 August 2007 39 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

The sequence of events related to a host and a peripheral, both with ISP1504x1, is as

follows.

1. High-speed idle: Initially, the host and the peripheral are idle. The host has its 15 kΩ

pull-down resistors enabled (DP_PULLDOWN and DM_PULLDOWN are set to 1b)

and 45 Ω terminations enabled (TERMSELECT is set to 0b). The peripheral has its

45 Ω terminations enabled (TERMSELECT is set to 0b).

2. Full-speed suspend: When the peripheral sees no bus activity for 3 ms, it enters the

suspend state. The peripheral link places the ISP1504x1 into full-speed mode

(XCVRSELECT is set to 01b), removes 45 Ω terminations, and enables the 1.5 kΩ

pull-up resistor on DP (TERMSELECT is set to 1b). The peripheral link then places

the ISP1504x1 into low-power mode by setting SUSPENDM, causing the ISP1504x1

to draw only suspend current. The host also changes the ISP1504x1 to full-speed

(XCVRSELECT is set to 01b), removes 45 Ω terminations (TERMSELECT is set to

1b), and then may or may not be powered down.

3. Resume K: When the host wants to wake up the peripheral, it sets OPMODE to 10b

and transmits a full-speed K for at least 20 ms. The peripheral link sees the resume K

(10b) on LINESTATE, and asserts STP to wake up the ISP1504x1.

4. High-speed trafﬁc: The host link sets high-speed (XCVRSELECT is set to 00b) and

enables its 45 Ω terminations (TERMSELECT is set to 0b). The peripheral link sees

SE0 on LINESTATE and also sets high-speed (XCVRSELECT is set to 00b), and

enables its 45 Ω terminations (TERMSELECT is set to 0b). The host link sets

OPMODE to 00b for normal high-speed operation.

Product data sheet Rev. 01 — 6 August 2007 40 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

Timing is not to scale.

Fig 18. High-speed suspend and resume

DATA

[7:0]

TXCMD

NOPID K...

TXCMD

(REGW)

DIR

STP

NXT

MODE 00b 10b 00b

KTXCMD

(REGW)

CLOCK

DATA

[7:0]

TXCMD

(REGW) LINESTATE J LINESTATE K SE0 TXCMD

(REGW)

DIR

STP

NXT

MODE 00b 10b 00b

SUSPEND

LINE

STATE

004aaa717

ULPI HS host (DPPULLDOWN = 1b,

DMPULLDOWN = 1b)

ULPI HS peripheral (DPPULLDOWN = 0b)

USB signals

HS idle FS suspend resume K

TXCMD

(REGW)

HS idle

XCVR

SELECT 00b 01b 00b

TERM

SELECT

LINE

STATE

!SQUELCH

(01b) FS J (01b) !SQUELCH

(01b)

SQUELCH (00b)

FS K (10b)

XCVR

SELECT 00b 01b 00b

TERM

SELECT

!SQUELCH

(01b) SQUELCH

(00b) FS J (01b) !SQUELCH

(01b)

SQUELCH (00b)

FS K (10b)

SQUELCH

(00b)

Product data sheet Rev. 01 — 6 August 2007 41 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

9.10.3 Remote wake-up

The ISP1504x1 supports peripherals that initiate remote wake-up resume. When placed

into USB suspend, the peripheral link remembers what speed it was originally operating.

Depending on the original speed, the link follows one of the protocols detailed here. In

Figure 19, timing is not to scale, and not all RXCMD LINESTATE updates are shown.

The sequence of events related to a host and a peripheral, both with ISP1504x1, is as

follows.

1. Both the host and the peripheral are assumed to be in low-power mode.

2. The peripheral begins remote wake-up by re-enabling its clock and setting its

SUSPENDM bit to 1b.

3. The peripheral begins driving K on the bus to signal resume. Note that the peripheral

link must assume that LINESTATE is K (01b) while transmitting because it will not

receive any RXCMDs.

4. The host recognizes the resume, re-enables its clock and sets its SUSPENDM bit.

5. The host takes over resume driving within 1 ms of detecting the remote wake-up.

6. The peripheral stops driving resume.

7. The peripheral sees the host continuing to drive the resume.

8. The host stops driving resume and the ISP1504x1 automatically adds the EOP to the

end of the resume. The peripheral recognizes the EOP as the end of resume.

9. Both the host and the peripheral revert to normal operation by writing 00b to

OPMODE. If the host or the peripheral was previously in high-speed mode, it must

revert to high-speed before the SE0 of the EOP is completed. This can be achieved

by writing XCVRSELECT = 00b and TERMSELECT = 0b after LINESTATE indicates

SE0.

Product data sheet Rev. 01 — 6 August 2007 42 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

9.11 No automatic SYNC and EOP generation (optional)

This setting allows the link to turn off the automatic SYNC and EOP generation, and must

be used for high-speed packets only. It is provided for backwards compatibility with legacy

controllers that include SYNC and EOP bytes in the data payload when transmitting

packets. The ISP1504x1 will not automatically generate the SYNC and EOP patterns

when OPMODE[1:0] is set to 11b. The ISP1504x1 will still NRZI encode data and perform

bit stufﬁng. An example of a sequence is shown in Figure 20. The link must always send

packets using the TXCMD (NOPID) type. The ISP1504x1 does not provide a mechanism

to control bit stufﬁng in individual bytes, but will automatically turn off bit stufﬁng for EOP

when STP is asserted with data set to FEh. If data is set to 00h when STP is asserted, the

Timing is not to scale.

Fig 19. Remote wake-up from low-power mode

DATA

[7:0]

LINESTATE TXCMD

REGW TXCMD

REGW

00h

TXCMD

NOPID

DIR

STP

NXT

XCVR

SELECT 01b (FS), 10b (LS) 00b (HS only)

TERM

SELECT

MODE 10b 00b

DATA

[7:0]

LINESTATE TXCMD

REGW RXCMD

00h

TXCMD

NOPID RXCMD RXCMD TXCMD

REGW

DIR

STP

NXT

XCVR

SELECT 00b (HS), 01b (FS), 10b (LS)

00b (HS only)

TERM

SELECT

MODE 10b 00b

ULPI host

ULPI peripheral

004aaa718

0b (HS only)

Product data sheet Rev. 01 — 6 August 2007 43 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

PHY will not transmit any EOP. The ISP1504x1 will also detect if the PID byte is A5h,

indicating an SOF packet and automatically send a long EOP when STP is asserted. To

transmit chirp and resume signaling, the link must set OPMODE to 10b.

9.12 On-The-Go operations

On-The-Go (OTG) is a supplement to

Universal Serial Bus Speciﬁcation Rev. 2.0

that

allows a portable USB device to assume the role of a limited USB host by deﬁning

improvements, such as a small connector and low power. Non-portable devices, such as

standard hosts and embedded hosts, can also beneﬁt from OTG features.

The ISP1504x1 OTG PHY is designed to support all the tasks speciﬁed in the OTG

supplement. The ISP1504x1 provides the front-end analog support for Host Negotiation

Protocol (HNP) and Session Request Protocol (SRP) for dual-role devices. The

supporting components include:

•Voltage comparators

–A_VBUS_VLD

–SESS_VLD (session valid, can be used for both A-session and B-session valid)

–SESS_END (session end)

•Pull-up and pull-down resistors on DP and DM

•ID detector indicates if micro-A or micro-B plug is inserted

•Charge and discharge resistors on VBUS

The following subsections describe how to use the ISP1504x1 OTG components.

Fig 20. Transmitting USB packets without automatic SYNC and EOP generation

CLOCK

DATA

[7:0] TXCMD 00h 00h 00h 80h PID D1 D2 D3 ... ... DN − 1 FEh

DIR

STP

NXT

ULPI signals

VALID

READY

TXBIT

STUFF

ENABLE

DP,

DM IDLE SYNC PID IDLE

EOP

DATA PAYLOAD

004aaa719

UTMI+ equivalent

signals

USB bus

Product data sheet Rev. 01 — 6 August 2007 44 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

9.12.1 OTG comparators

The ISP1504x1 provides comparators that conform to

On-The-Go Supplement to the

USB 2.0 Speciﬁcation Rev. 1.2

requirements of VA_VBUS_VLD, VA_SESS_VLD, VB_SESS_VLD

and VB_SESS_END. In this data sheet, VA_SESS_VLD and VB_SESS_VLD are combined into

VA_SESS_VLD. Comparators are described in Section 7.6.2. Changes in comparator values

are communicated to the link by RXCMDs as described in Section 9.5.2.2. Control over

comparators is described in Section 10.1.5 to Section 10.1.8.

9.12.2 Pull-up and pull-down resistors

The USB resistors on DP and DM can be used to initiate data-line pulsing SRP. The link

must set the required bus state using mode settings in Table 8.

9.12.3 ID detection

The ISP1504x1 provides an internal pull-up resistor to sense the value of the ID pin. The

pull-up resistor must ﬁrst be enabled by setting the ID_PULLUP register bit to logic 1. If

the value on ID has changed, the ISP1504x1 will send an RXCMD or interrupt to the link

by time tID. If the link does not receive any RXCMD or interrupt by tID, then the ID value

has not changed.

9.12.4 VBUS charge and discharge resistors

A pull-up resistor, RUP(VBUS), is provided to perform VBUS pulsing SRP. A B-device is

allowed to charge VBUS above the session valid threshold to request the host to turn on

the VBUS power.

A pull-down resistor, RDN(VBUS), is provided for a B-device to discharge VBUS. This is done

whenever the A-device turns off the VBUS power; the B-device can use the pull-down

resistor to ensure VBUS is below VB_SESS_END before starting a session.

For details, refer to

On-The-Go Supplement to the USB 2.0 Speciﬁcation Rev. 1.2

9.13 Serial modes

The ISP1504x1 supports both 6-pin serial mode and 3-pin serial mode, controlled by bits

6PIN_FSLS_SERIAL and 3PIN_FSLS_SERIAL of the Interface Control register. For

details, refer to

UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1, Section 3.10

Figure 21 and Figure 22 provide example of 6-pin serial mode and 3-pin serial mode,

respectively.

Product data sheet Rev. 01 — 6 August 2007 45 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

Fig 21. Example of transmit followed by receive in 6-pin serial mode

DATA0

(TX_ENABLE)

DATA1

(TX_DAT)

DATA2

(TX_SE0)

DATA4

(RX_DP)

DATA5

(RX_DM)

DATA6

(RX_RCV)

SYNC DATA EOP

TRANSMIT RECEIVE

SYNC DATA EOP

004aaa692

Fig 22. Example of transmit followed by receive in 3-pin serial mode

DATA0

(TX_ENABLE)

DATA1

(TX_DAT/

RX_RCV)

DATA2

(TX_SE0/

RX_SE0)

004aaa693

SYNC DATA EOP

TRANSMIT RECEIVE

SYNC DATA EOP

Product data sheet Rev. 01 — 6 August 2007 46 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

9.14 Aborting transfers

The ISP1504x1 supports aborting transfers on the ULPI bus. For details, refer to

UTMI+

Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1, Section 3.8.4

9.15 Avoiding contention on the ULPI data bus

Because the ULPI data bus is bidirectional, avoid situations in which both the link and the

PHY simultaneously drive the data bus.

The following points must be considered while implementing the data bus drive control on

the link.

After power-up and clock stabilization, default states are as follows:

•The ISP1504x1 drives DIR to LOW.

•The data bus is input to the ISP1504x1.

•The ULPI link data bus is output, with all data bus lines driven to LOW.

When the ISP1504x1 wants to take control of data bus to initiate a data transfer, it

changes the DIR value from LOW to HIGH.

At this point, the link must disable its output buffers. This must be as fast as possible so

the link must use a combinational path from DIR.

The ISP1504x1 will not immediately enable its output buffers, but will delay the enabling of

its buffers until the next clock edge, avoiding bus contention.

When the data transfer is no longer required by the ISP1504x1, it changes DIR from HIGH

to LOW and starts to immediately turn off its output drivers. The link senses the change of

DIR from HIGH to LOW, but delays enabling its output buffers for one CLOCK cycle,

avoiding data bus contention.

Product data sheet Rev. 01 — 6 August 2007 47 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

10. Register map

[1] Read (R): A register can be read. Read-only if this is the only mode given.

[2] Write (W): The pattern on the data bus will be written over all bits of a register.

[3] Set (S): The pattern on the data bus is OR-ed with and written to a register.

[4] Clear (C): The pattern on the data bus is a mask. If a bit in the mask is set, then the corresponding register bit will be set to zero

(cleared).

[1] Read (R): A register can be read. Read-only if this is the only mode given.

[2] Write (W): The pattern on the data bus will be written over all bits of a register.

[3] Set (S): The pattern on the data bus is OR-ed with and written to a register.

[4] Clear (C): The pattern on the data bus is a mask. If a bit in the mask is set, then the corresponding register bit will be set to zero

(cleared).

Table 19. Immediate register set overview

Field name Size

(bits) Address (6 bits) References

R[1] W[2] S[3] C[4]

Vendor ID Low register 8 00h - - - Section 10.1.1 on page 48

Vendor ID High register 8 01h - - -

Product ID Low register 8 02h - - -

Product ID High register 8 03h - - -

Function Control register 8 04h to 06h 04h 05h 06h Section 10.1.2 on page 48

Interface Control register 8 07h to 09h 07h 08h 09h Section 10.1.3 on page 49

OTG Control register 8 0Ah to 0Ch 0Ah 0Bh 0Ch Section 10.1.4 on page 50

USB Interrupt Enable Rising register 8 0Dh to 0Fh 0Dh 0Eh 0Fh Section 10.1.5 on page 51

USB Interrupt Enable Falling register 8 10h to 12h 10h 11h 12h Section 10.1.6 on page 52

USB Interrupt Status register 8 13h - - - Section 10.1.7 on page 52

USB Interrupt Latch register 8 14h - - - Section 10.1.8 on page 53

Debug register 8 15h - - - Section 10.1.9 on page 54

Scratch register 8 16h to 18h 16h 17h 18h Section 10.1.10 on page 54

Reserved (not used, not available) - 19h to 2Eh Section 10.1.11 on page 54

Access extended register set 8 - 2Fh - - Section 10.1.12 on page 54

Vendor-speciﬁc registers 8 30h to 3Ch Section 10.1.13 on page 54

Power Control register 8 3D to 3Fh Section 10.1.14 on page 54

Table 20. Extended register set overview

Field name Size

(bits) Address (6 bits) References

R[1] W[2] S[3] C[4]

Maps to immediate register set above 8 00h to 3Fh Section 10.2 on page 55

Reserved (do not use) 8 40h to FFh

Product data sheet Rev. 01 — 6 August 2007 48 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

10.1 Immediate register set

10.1.1 Vendor ID and Product ID registers

10.1.1.1 Vendor ID Low register

Table 21 shows the bit description of the register.

10.1.1.2 Vendor ID High register

The bit description of the register is given in Table 22.

10.1.1.3 Product ID Low register

The bit description of the Product ID Low register is given in Table 23.

10.1.1.4 Product ID High register

The bit description of the register is given in Table 24.

10.1.2 Function Control register

This register controls UTMI function settings of the PHY. The bit allocation of the register

is given in Table 25.

Table 21. Vendor ID Low register (address R = 00h) bit description

Bit Symbol Access Value Description

7 to 0 VENDOR_ID_

LOW[7:0] R CCh Vendor ID Low: Lower byte of the NXP vendor ID supplied by USB-IF;

has a ﬁxed value of CCh

Table 22. Vendor ID High register (address R = 01h) bit description

Bit Symbol Access Value Description

7 to 0 VENDOR_ID_

HIGH[7:0] R 04h Vendor ID High: Upper byte of the NXP vendor ID supplied by USB-IF;

has a ﬁxed value of 04h

Table 23. Product ID Low register (address R = 02h) bit description

Bit Symbol Access Value Description

7 to 0 PRODUCT_ID_

LOW[7:0] R 04h Product ID Low: Lower byte of the NXP product ID number; has a ﬁxed

value of 04h

Table 24. Product ID High register (address R = 03h) bit description

Bit Symbol Access Value Description

7 to 0 PRODUCT_ID_

HIGH[7:0] R 15h Product ID High: Upper byte of the NXP product ID number; has a

ﬁxed value of 15h

Table 25. Function Control register (address R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol reserved SUSPENDM RESET OPMODE[1:0] TERM

SELECT XCVRSELECT[1:0]

Reset 0 1000001

Access R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C

Product data sheet Rev. 01 — 6 August 2007 49 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

10.1.3 Interface Control register

The Interface Control register enables alternative interfaces. All of these modes are

optional features provided for legacy link cores. Setting more than one of these ﬁelds

results in undeﬁned behavior. Table 27 provides the bit allocation of the register.

Table 26. Function Control register (address R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit description

Bit Symbol Description

7 - reserved

6 SUSPENDM Suspend LOW: Active LOW PHY suspend.

Sets the PHY into low-power mode. The PHY will power down all blocks, except the full-speed

receiver, OTG comparators and ULPI interface pins.

To come out of low-power mode, the link must assert STP. The PHY will automatically clear this

bit when it exits low-power mode.

0b — Low-power mode

1b — Powered

5 RESET Reset: Active HIGH transceiver reset.

After the link sets this bit, the PHY will assert DIR and reset the digital core. This does not reset

the ULPI interface or the ULPI register set.

When the reset is completed, the PHY will de-assert DIR and automatically clear this bit,

followed by an RXCMD update to the link.

The link must wait for DIR to de-assert before using the ULPI bus.

0b — Do not reset

1b — Reset

4 to 3 OPMODE[1:0] Operation Mode: Selects the required bit-encoding style during transmit.

00b — Normal operation

01b — Non-driving

10b — Disable bit-stufﬁng and NRZI encoding

11b — Do not automatically add SYNC and EOP when transmitting; must be used only for

high-speed packets

2 TERMSELECT Termination Select: Controls the internal 1.5 kΩ full-speed pull-up resistor and 45 Ω

high-speed terminations. Control over bus resistors changes, depending on

XCVRSELECT[1:0], OPMODE[1:0], DP_PULLDOWN and DM_PULLDOWN, as shown in

Table 8.

1 to 0 XCVRSELECT

[1:0] Transceiver Select: Selects the required transceiver speed.

00b — Enable the high-speed transceiver

01b — Enable the full-speed transceiver

10b — Enable the low-speed transceiver

11b — Enable the full-speed transceiver for low-speed packets (full-speed preamble is

automatically preﬁxed)

Table 27. Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol INTF_

PROT_DIS IND_PASS

THRU IND_

COMPL reserved CLOCK_

SUSPENDM reserved 3PIN_

FSLS_

SERIAL

6PIN_

FSLS_

SERIAL

Reset 0000 0000

Access R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C

Product data sheet Rev. 01 — 6 August 2007 50 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

10.1.4 OTG Control register

This register controls various OTG functions of the ISP1504x1. The bit allocation of the

OTG Control register is given in Table 29.

Table 28. Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit description

Bit Symbol Description

7 INTF_PROT_DIS Interface Protect Disable: Controls circuitry built into the ISP1504x1 to protect the ULPI

interface when the link 3-states STP and DATA[7:0]. When this bit is enabled, the ISP1504x1

will automatically detect when the link stops driving STP.

0b — Enables the interface protect circuit (default). The ISP1504x1 attaches a weak pull-up

resistor on STP. If STP is unexpectedly HIGH, the ISP1504x1 attaches weak pull-down

resistors on DATA[7:0], protecting data inputs.

1b — Disables the interface protect circuit, detaches weak pull-down resistors on DATA[7:0],

and a weak pull-up resistor on STP.

6 IND_PASSTHRU Indicator Pass-through: Controls whether the complement output is qualiﬁed with the internal

A_VBUS_VLD comparator before being used in the VBUS state in RXCMD. For details, see

Section 9.5.2.2.

0b — The complement output signal is qualiﬁed with the internal A_VBUS_VLD comparator.

1b — The complement output signal is not qualiﬁed with the internal A_VBUS_VLD

comparator.

5 IND_COMPL Indicator Complement: Informs the PHY to invert the FAULT input signal, generating the

complement output. For details, see Section 9.5.2.2.

0b — The ISP1504x1 will not invert the FAULT signal (default).

1b — The ISP1504x1 will invert the FAULT signal.

4 - reserved

3 CLOCK_

SUSPENDM Clock Suspend LOW: Active LOW clock suspend.

Powers down the internal clock circuitry only. By default, the clock will not be powered in 6-pin

serial mode or 3-pin serial mode.

Valid only in 6-pin serial mode and 3-pin serial mode. Valid only when SUSPENDM is set to

logic 1, otherwise this bit is ignored.

0b — Clock will not be powered in 3-pin or 6-pin serial mode.

1b — Clock will be powered in 3-pin and 6-pin serial modes.

2 - reserved

1 3PIN_FSLS_

SERIAL 3-Pin Full-Speed Low-Speed Serial Mode: Changes the ULPI interface to a 3-bit serial

interface. The PHY will automatically clear this bit when 3-pin serial mode is exited.

0b — Full-speed or low-speed packets are sent using the parallel interface.

1b — Full-speed or low-speed packets are sent using the 3-pin serial interface.

0 6PIN_FSLS_

SERIAL 6-Pin Full-Speed Low-Speed Serial Mode: Changes the ULPI interface to a 6-bit serial

interface. The PHY will automatically clear this bit when 6-pin serial mode is exited.

0b — Full-speed or low-speed packets are sent using the parallel interface.

1b — Full-speed or low-speed packets are sent using the 6-pin serial interface.

Table 29. OTG Control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit allocation

Bit 76543210

Symbol USE_EXT_

VBUS_IND DRV_

VBUS_EXT reserved CHRG_

VBUS DISCHRG_

VBUS DM_PULL

DOWN DP_PULL

DOWN ID_PULL

Reset 00000110

Access R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C

Product data sheet Rev. 01 — 6 August 2007 51 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

10.1.5 USB Interrupt Enable Rising Edge register

The bits in this register enable interrupts and RXCMDs to be sent when the corresponding

bits in the USB Interrupt Status register change from logic 0 to logic 1. By default, all

transitions are enabled. Table 31 shows the bit allocation of the register.

Table 30. OTG Control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit description

Bit Symbol Description

7 USE_EXT_VBUS

_IND Use External VBUS Indicator: Informs the PHY to use an external VBUS overcurrent indicator.

0b — Use the internal OTG comparator.

1b — Use the external VBUS valid indicator signal input from the FAULT pin.

6 DRV_VBUS_EXT Drive VBUS External: Controls external charge pump or 5 V supply by the PSW_N pin.

0b — PSW_N is HIGH.

1b — PSW_N to LOW.

5 - reserved

4 CHRG_VBUS Charge VBUS: Charges VBUS through a resistor. Used for the VBUS pulsing of SRP. The link must

ﬁrst check that VBUS is discharged (see bit DISCHRG_VBUS), and that both the DP and DM

data lines have been LOW (SE0) for 2 ms.

0b — Do not charge VBUS.

1b — Charge VBUS.

3 DISCHRG_VBUS Discharge VBUS: Discharges VBUS through a resistor. If the link sets this bit to logic 1, it waits for

an RXCMD indicating that SESS_END has changed from 0 to 1, and then resets this bit to 0 to

stop the discharge.

0b — Do not discharge VBUS.

1b — Discharge VBUS.

2 DM_PULLDOWN DM Pull Down: Enables the 15 kΩ pull-down resistor on DM.

0b — Pull-down resistor is not connected to DM.

1b — Pull-down resistor is connected to DM.

1 DP_PULLDOWN DP Pull Down: Enables the 15 kΩ pull-down resistor on DP.

0b — Pull-down resistor is not connected to DP.

1b — Pull-down resistor is connected to DP.

0 ID_PULLUP ID Pull Up: Connects a pull-up to the ID line and enables sampling of the ID level. Disabling the

ID line sampler will reduce PHY power consumption.

0b — Disable sampling of the ID line.

1b — Enable sampling of the ID line.

Table 31. USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh, C = 0Fh) bit

allocation

Bit 76543210

Symbol reserved ID_GND_R SESS_

END_R SESS_

VALID_R VBUS_

VALID_R HOST_

DISCON_R

Reset 00011111

Access R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C

Product data sheet Rev. 01 — 6 August 2007 52 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

10.1.6 USB Interrupt Enable Falling Edge register

The bits in this register enable interrupts and RXCMDs to be sent when the corresponding

bits in the USB Interrupt Status register change from logic 1 to logic 0. By default, all

transitions are enabled. See Table 33.

10.1.7 USB Interrupt Status register

This register (see Table 35) indicates the current value of the interrupt source signal.

Table 32. USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh, C = 0Fh) bit

description

Bit Symbol Description

7 to 5 - reserved

4 ID_GND_R ID Ground Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on ID_GND.

3 SESS_END_R Session End Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on

SESS_END.

2 SESS_VALID_R Session Valid Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on

SESS_VLD.

1 VBUS_VALID_R VBUS Valid Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on

A_VBUS_VLD.

0 HOST_DISCON

_R Host Disconnect Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on

HOST_DISCON.

Table 33. USB Interrupt Enable Falling Edge register (address R = 10h to 12h, W = 10h, S = 11h, C = 12h) bit

allocation

Bit 76543210

Symbol reserved ID_GND_F SESS_

END_F SESS_

VALID_F VBUS_

VALID_F HOST_

DISCON_F

Reset 00011111

Access R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C

Table 34. USB Interrupt Enable Falling Edge register (address R = 10h to 12h, W = 10h, S = 11h, C = 12h) bit

description

Bit Symbol Description

7 to 5 - reserved

4 ID_GND_F ID Ground Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on ID_GND.

3 SESS_END_F Session End Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on

SESS_END.

2 SESS_VALID_F Session Valid Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on

SESS_VLD.

1 VBUS_VALID_F VBUS Valid Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on

A_VBUS_VLD.

0 HOST_DISCON

_F Host Disconnect Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on

HOST_DISCON.

Product data sheet Rev. 01 — 6 August 2007 53 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

10.1.8 USB Interrupt Latch register

The bits of the USB Interrupt Latch register are automatically set by the ISP1504x1 when

an unmasked change occurs on the corresponding interrupt source signal. The

ISP1504x1 will automatically clear all bits when the link reads this register, or when the

PHY enters low-power mode.

Remark: It is optional for the link to read this register when the clock is running because

all signal information will automatically be sent to the link through the RXCMD byte.

The bit allocation of this register is given in Table 37.

Table 35. USB Interrupt Status register (address R = 13h) bit allocation

Bit 76543210

Symbol reserved ID_GND SESS_

END SESS_

VALID VBUS_

VALID HOST_

DISCON

Reset XXX00000

Access RRRRRRRR

Table 36. USB Interrupt Status register (address R = 13h) bit description

Bit Symbol Description

7 to 5 - reserved

4 ID_GND ID Ground: Reﬂects the current value of the ID detector circuit.

3 SESS_END Session End: Reﬂects the current value of the session end voltage comparator.

2 SESS_VALID Session Valid: Reﬂects the current value of the session valid voltage comparator.

1 VBUS_VALID VBUS Valid: Reﬂects the current value of the VBUS valid voltage comparator.

0 HOST_DISCON Host Disconnect: Reﬂects the current value of the host disconnect detector.

Table 37. USB Interrupt Latch register (address R = 14h) bit allocation

Bit 76543210

Symbol reserved ID_GND_L SESS_

END_L SESS_

VALID_L VBUS_

VALID_L HOST_

DISCON_L

Reset 00000000

Access RRRRRRRR

Table 38. USB Interrupt Latch register (address R = 14h) bit description

Bit Symbol Description

7 to 5 - reserved

4 ID_GND_L ID Ground Latch: Automatically set when an unmasked event occurs on ID_GND. Cleared

when this register is read.

3 SESS_END_L Session End Latch: Automatically set when an unmasked event occurs on SESS_END.

Cleared when this register is read.

2 SESS_VALID_L Session Valid Latch: Automatically set when an unmasked event occurs on SESS_VLD.

Cleared when this register is read.

1 VBUS_VALID_L VBUS Valid Latch: Automatically set when an unmasked event occurs on A_VBUS_VLD.

Cleared when this register is read.

0 HOST_DISCON_L Host Disconnect Latch: Automatically set when an unmasked event occurs on

HOST_DISCON. Cleared when this register is read.

Product data sheet Rev. 01 — 6 August 2007 54 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

10.1.9 Debug register

The bit allocation of the Debug register is given in Table 39. This register indicates the

current value of signals useful for debugging.

10.1.10 Scratch register

This is an empty register for testing purposes, see Table 41.

10.1.11 Reserved

Registers 19h to 2Eh are not implemented. Operating on these addresses will have no

effect on the PHY.

10.1.12 Access extended register set

Address 2Fh does not contain register data. Instead it links to the extended register set.

The immediate register set maps to the lower end of the extended register set.

10.1.13 Vendor-speciﬁc registers

Address 30h to 3Fh contains vendor-speciﬁc registers.

10.1.14 Power Control register

This register controls various aspects of the ISP1504x1. Table 42 shows the bit allocation

of the register.

Table 39. Debug register (address R = 15h) bit allocation

Bit 76543210

Symbol reserved LINE

STATE1 LINE

STATE0

Reset 00000000

Access RRRRRRRR

Table 40. Debug register (address R = 15h) bit description

Bit Symbol Description

7 to 2 - reserved

1 LINESTATE1 Line State 1: Contains the current value of LINESTATE 1

0 LINESTATE0 Line State 0: Contains the current value of LINESTATE 0

Table 41. Scratch register (address R = 16h to 18h, W = 16h, S = 17h, C = 18h) bit description

Bit Symbol Access Value Description

7 to 0 SCRATCH[7:0] R/W/S/C 00h Scratch: This is an empty register byte for testing purposes. Software can

read, write, set and clear this register, and the functionality of the PHY will

not be affected.

Table 42. Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit allocation

Bit 76543210

Symbol reserved BVALID_

FALL BVALID_

RISE reserved

Reset 00000000

Access R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C

Product data sheet Rev. 01 — 6 August 2007 55 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

10.2 Extended register set

Addresses 00h to 3Fh of the extended register set directly map to the immediate set. This

means a read, write, set or clear operation to these extended addresses will operate on

the immediate register set.

Addresses 40h to FFh are not implemented. Operating on these addresses may result in

undeﬁned behavior of the PHY.

Table 43. Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit description

Bit Symbol Description

7 to 4 - reserved; the link must never write logic 1 to these bits.

3 BVALID_FALL BValid Fall: Enables RXCMDs for HIGH-to-LOW transitions on BVALID. When BVALID changes

from HIGH to LOW, the ISP1504x1 will send an RXCMD to the link with the ALT_INT bit set to

logic 1.

This bit is optional and is not necessary for OTG devices. The session valid comparator must be

used instead.

2 BVALID_RISE BValid Rise: Enables RXCMDs for LOW-to-HIGH transitions on BVALID. When BVALID changes

from LOW to HIGH, the ISP1504x1 will send an RXCMD to the link with the ALT_INT bit set to

logic 1.

This bit is optional and is not necessary for OTG devices. The session valid comparator must be

used instead.

1 to 0 - reserved; the link must never write logic 1 to this bit.

Product data sheet Rev. 01 — 6 August 2007 56 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

11. Limiting values

[1] The ISP1504x1 has been tested according to the additional requirements listed in

Universal Serial Bus Speciﬁcation Rev. 2.0,

Section 7.1.1

. The short circuit withstand test and the AC stress test were performed for 24 hours, and the ISP1504x1 was found to be

fully operational after the test completed.

[2] Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor (Human Body Model).

12. Recommended operating conditions

[1] VCC(I/O) must not exceed VCC.

Table 44. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage −0.5 +5.5 V

VCC(I/O) input/output supply voltage −0.5 +4.6 V

VIinput voltage on pins CLOCK, STP, DATA[7:0],

RESET_N and CS_N/PWRDN −0.5 VCC(I/O) + 0.5 V

on pins VBUS, FAULT and PSW_N −0.5 +5.5 V

on pin XTAL1 −0.5 +2.5 V

on pin ID −0.5 +4.6 V

on pins DP and DM [1] −0.5 +4.6 V

VESD electrostatic discharge

voltage ILI < 1 µA; Human Body Model

(JESD22-A114D) [2] −2000 +2000 V

ILI < 1 µA; Machine Model

(JESD22-A115-A) −200 +200 V

ILI < 1 µA; Charge Device Model

(JESD22-C101-C) −500 +500 V

Ilu latch-up current −0.5 × VCC < V < +1.5 × VCC - 100 mA

Tstg storage temperature −40 +125 °C

Tjjunction temperature −40 +125 °C

Table 45. Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

VCC supply voltage 3.0 3.6 4.5 V

VCC(I/O) input/output supply voltage [1] 1.65 1.8 3.6 V

VIinput voltage on pins CLOCK, STP, DATA[7:0],

RESET_N and CS_N/PWRDN 0- V

CC(I/O) V

on pins VBUS, FAULT and PSW_N 0 - 5.25 V

on pins DP, DM and ID 0 - 3.6 V

on pin XTAL1 0 - 1.95 V

Tamb ambient temperature −40 +25 +85 °C

Product data sheet Rev. 01 — 6 August 2007 57 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

13. Static characteristics

[1] A continuous stream of 1 kB packets with minimum inter-packet gap and all data bits set to logic 0 for continuous toggling.

Table 46. Static characteristics: supply pins

= 3.0 V to 4.5 V; V

CC(I/O)

= 1.65 V to 3.6 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Typical values are at V

= 3.6 V; V

CC(I/O)

= 1.8 V; T

amb

= +25

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

V(REG3V3) voltage on pin REG3V3 3.0 3.3 3.6 V

V(REG1V8) voltage on pin REG1V8 1.65 1.8 1.95 V

VPOR(trip) power-on reset trip voltage 1.0 - 1.5 V

ICC supply current power-down mode (pin CS_N/PWRDN =

HIGH or VCC(I/O) is not present) - 0.5 10 µA

low-power mode; VBUS valid detector

disabled; 1.5 kΩpull-up resistor on pin DP

disconnected

- 50 120 µA

low-power mode; VBUS valid detector

disabled; 1.5 kΩpull-up resistor on pin DP

connected

- 235 315 µA

full-speed idle; no USB activity - 11 - mA

high-speed idle; no USB activity - 19 - mA

full-speed continuous data transmit; 50 pF

load on pins DP and DM [1] -15- mA

full-speed continuous data receive [1] -11- mA

high-speed continuous data transmit; 45 Ω

load on pins DP and DM to ground [1] -48- mA

high-speed continuous data receive [1] -28- mA

ICC(I/O) supply current on

pin VCC(I/O)

static current; digital I/O pins are idle - - 10 µA

Table 47. Static characteristics: digital pins CLOCK, DIR, STP, NXT, DATA[7:0], RESET_N, CS_N/PWRDN

= 3.0 V to 4.5 V; V

CC(I/O)

= 1.65 V to 3.6 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Typical values are at V

= 3.6 V; V

CC(I/O)

= 1.8 V; T

amb

= +25

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Input levels

VIL LOW-level input voltage - - 0.3 × VCC(I/O) V

VIH HIGH-level input voltage 0.7 × VCC(I/O) -- V

ILI input leakage current −1 +0.1 +1 µA

Output levels

VOL LOW-level output voltage IOL =−2 mA - - 0.4 V

VOH HIGH-level output voltage IOH = +2 mA VCC(I/O) − 0.4 - - V

IOH HIGH-level output current VOH = VCC(I/O) − 0.4 V −4.8 - - mA

IOL LOW-level output current VOL = 0.4 V 4.2 - - mA

IOZ off-state output current 0 V < VO< VCC(I/O) --1µA

Impedance

ZLload impedance 45 - 65 Ω

Product data sheet Rev. 01 — 6 August 2007 58 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

[1] When VOH is less than 3.0 V, ICC may increase because of the cross current.

Pull-up and pull-down

Ipd pull-down current interface protect enabled;

DATA[7:0] pins only; VI=

VCC(I/O)

25 50 90 µA

Ipu pull-up current interface protect enabled;

STP pin only; VI= 0 V −30 −50 −80 µA

Capacitance

Cin input capacitance - - 3.5 pF

Table 47. Static characteristics: digital pins CLOCK, DIR, STP, NXT, DATA[7:0], RESET_N, CS_N/PWRDN

…continued

= 3.0 V to 4.5 V; V

CC(I/O)

= 1.65 V to 3.6 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Typical values are at V

= 3.6 V; V

CC(I/O)

= 1.8 V; T

amb

= +25

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Table 48. Static characteristics: digital pin FAULT

= 3.0 V to 4.5 V; V

CC(I/O)

= 1.65 V to 3.6 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Typical values are at V

= 3.6 V; V

CC(I/O)

= 1.8 V; T

amb

= +25

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Input levels

VIL LOW-level input voltage - - 0.8 V

VIH HIGH-level input voltage 2.0 - - V

IIL LOW-level input current VI= 0 V - - 1 µA

IIH HIGH-level input current VI= VCC(I/O) -- 1µA

Table 49. Static characteristics: digital pin PSW_N

= 3.0 V to 4.5 V; V

CC(I/O)

= 1.65 V to 3.6 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Typical values are at V

= 3.6 V; V

CC(I/O)

= 1.8 V; T

amb

= +25

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Output levels

VOH HIGH-level output voltage external pull-up resistor connected 3.0[1] - 5.25 V

VOL LOW-level output voltage IOL =−4 mA - - 0.4 V

IOH HIGH-level output current external pull-up resistor connected - - 1 µA

IOL LOW-level output current VO= 0.4 V 4.0 - - mA

Table 50. Static characteristics: analog I/O pins DP, DM

= 3.0 V to 4.5 V; V

CC(I/O)

= 1.65 V to 3.6 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Typical values are at V

= 3.6 V; V

CC(I/O)

= 1.8 V; T

amb

= +25

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Original USB transceiver (low-speed and full-speed)

Input levels (differential receiver)

VDI differential input sensitivity |VDP − VDM|0.2 - - V

VCM differential common mode voltage range includes VDI range 0.8 - 2.5 V

Input levels (single-ended receivers)

VIL LOW-level input voltage - - 0.8 V

VIH HIGH-level input voltage 2.0 - - V

Product data sheet Rev. 01 — 6 August 2007 59 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

[1] For high-speed USB and full-speed USB.

Output levels

VOL LOW-level output voltage pull-up on pin DP; RL=

1.5 kΩ to 3.6 V 0.0 0.18 0.3 V

VOH HIGH-level output voltage pull-down on pins DP and

DM; RL= 15 kΩ to GND 2.8 3.2 3.6 V

VCRS output signal crossover voltage excluding the ﬁrst

transition from the idle

state

1.3 - 2.0 V

Termination

VTERM termination voltage for upstream facing port

pull-up 3.0 - 3.6 V

Resistance

RUP(DP) pull-up resistance on pin DP 1425 1500 1575 Ω

High-speed USB transceiver (HS)

Input levels (differential receiver)

VHSSQ high-speed squelch detection threshold

voltage (differential signal amplitude) 100 - 150 mV

VHSDSC high-speed disconnect detection threshold

voltage (differential signal amplitude) 525 - 625 mV

VHSDI high-speed differential input sensitivity |VDP − VDM|300 - - mV

VHSCM high-speed data signaling common mode

voltage range includes VDI range −50 - +500 mV

Output levels

VHSOI high-speed idle level −10 - +10 mV

VHSOL high-speed data signaling LOW-level voltage −10 - +10 mV

VHSOH high-speed data signaling HIGH-level voltage 360 - 440 mV

VCHIRPJ Chirp J level (differential voltage) 700 - 1100 mV

VCHIRPK Chirp K level (differential voltage) −900 - −500 mV

Leakage current

ILZ off-state leakage current −1- +1µA

Capacitance

Cin input capacitance pin to GND - - 5 pF

Resistance

RDN(DP) pull-down resistance on pin DP 14.25 15 15.75 kΩ

RDN(DM) pull-down resistance on pin DM 14.25 15 15.75 kΩ

Termination

ZO(drv)(DP) driver output impedance on pin DP steady-state drive [1] 40.5 45 49.5 Ω

ZO(drv)(DM) driver output impedance on pin DM steady-state drive [1] 40.5 45 49.5 Ω

ZINP input impedance 1 - - MΩ

Table 50. Static characteristics: analog I/O pins DP, DM

…continued

= 3.0 V to 4.5 V; V

CC(I/O)

= 1.65 V to 3.6 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Typical values are at V

= 3.6 V; V

CC(I/O)

= 1.8 V; T

amb

= +25

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 01 — 6 August 2007 60 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

Table 51. Static characteristics: analog pin VBUS

= 3.0 V to 4.5 V; V

CC(I/O)

= 1.65 V to 3.6 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Typical values are at V

= 3.6 V; V

CC(I/O)

= 1.8 V; T

amb

= +25

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Comparators

VA_VBUS_VLD A-device VBUS valid voltage 4.4 - 4.75 V

VA_SESS_VLD A-device session valid voltage for A-device and B-device 0.8 1.6 2.0 V

Vhys(A_SESS_VLD) A-device session valid hysteresis

voltage for A-device and B-device 70 90 110 mV

VB_SESS_END B-device session end voltage 0.2 0.5 0.8 V

Resistance

RUP(VBUS) pull-up resistance on pin VBUS connect to pin REG3V3

when CHRG_VBUS is

logic 1

281 680 - Ω

RDN(VBUS) pull-down resistance on pin VBUS connect to GND when

DISCHRG_VBUS is logic 1 656 1200 - Ω

RI(idle)(VBUS) idle input resistance on pin VBUS 40 70 100 kΩ

Table 52. Static characteristics: ID detection circuit

= 3.0 V to 4.5 V; V

CC(I/O)

= 1.65 V to 3.6 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Typical values are at V

= 3.6 V; V

CC(I/O)

= 1.8 V; T

amb

= +25

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

tID ID detection time 50 - - ms

Vth(ID) ID detector threshold voltage 0.8 1.2 2.0 V

RUP(ID) ID pull-up resistance connect to pin REG3V3

ID_PULLUP is logic 1 40 50 60 kΩ

Table 53. Static characteristics: resistor reference

= 3.0 V to 4.5 V; V

CC(I/O)

= 1.65 V to 3.6 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Typical values are at V

= 3.6 V; V

CC(I/O)

= 1.8 V; T

amb

= +25

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

VO(RREF) output voltage on pin RREF SUSPENDM is logic 1 - 1.22 - V

Product data sheet Rev. 01 — 6 August 2007 61 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

14. Dynamic characteristics

[1] The internal PLL is triggered only on the positive edge from the crystal oscillator. Therefore, the duty cycle is not critical.

Table 54. Dynamic characteristics: reset and clock

= 3.0 V to 4.5 V; V

CC(I/O)

= 1.65 V to 3.6 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Typical values are at V

= 3.6 V; V

CC(I/O)

= 1.8 V; T

amb

= +25

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Reset

tW(POR) internal power-on reset pulse

width 0.2 - - µs

tw(REG1V8_H) REG1V8 HIGH pulse width 2 - - µs

tw(REG1V8_L) REG1V8 LOW pulse width 11 - - µs

tW(RESET_N) external RESET_N pulse width 200 - - ns

tstartup(PLL) PLL startup time - 650 - µs

tPWRUP regulator start-up time 4.7 µF±20 % capacitor each

on pins REG1V8 and

REG3V3

-- 1ms

tPWRDN regulator power-down time 4.7 µF±20 % capacitor each

on pins REG1V8 and

REG3V3

- - 100 ms

Crystal or clock applied to XTAL1

fi(XTAL1) input frequency on pin XTAL1 ISP1504A1ET - 19.2000 - MHz

ISP1504C1ET - 26.0000 - MHz

tjit(i)(XTAL1)RMS RMS input jitter on pin XTAL1 fi(XTAL1) = 19.2 MHz - - 200 ps

fi(XTAL1) = 26 MHz - - 300 ps

∆fi(XTAL1) input frequency tolerance on

pin XTAL1 - 50 200 ppm

δi(XTAL1) input duty cycle on pin XTAL1 [1] -50-%

tr(XTAL1) rise time on pin XTAL1 only for square wave input - - 5 ns

tf(XTAL1) fall time on pin XTAL1 only for square wave input - - 5 ns

V(XTAL1)(p-p) peak-to-peak voltage on

pin XTAL1 only for square wave input 0.566 - 1.95 V

Output CLOCK characteristics

fo(CLOCK) output frequency on pin CLOCK 59.97 60.00 60.03 MHz

tjit(o)(CLOCK)RMS RMS output jitter on pin CLOCK - - 500 ps

δo(CLOCK) output clock duty cycle on pin

CLOCK 45 50 55 %

Product data sheet Rev. 01 — 6 August 2007 62 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

Table 55. Dynamic characteristics: digital I/O pins

= 3.0 V to 4.5 V; V

CC(I/O)

= 1.65 V to 3.6 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Typical values are at V

= 3.6 V; V

CC(I/O)

= 1.8 V; T

amb

= +25

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

VCC(I/O) = 1.65 V to 1.95 V

tsu(DATA) DATA set-up time with respect to

the rising edge of pin CLOCK 20 pF total external load

per pin 5.7 - - ns

th(DATA) DATA hold time with respect to

the rising edge of pin CLOCK 20 pF total external load

per pin 0- - ns

td(DATA) DATA output delay with respect

to the rising edge of pin CLOCK 20 pF total external load

per pin - - 7.8 ns

tsu(STP) STP set-up time with respect to

the rising edge of pin CLOCK 20 pF total external load

per pin 4.5 - - ns

th(STP) STP hold time with respect to

the rising edge of pin CLOCK 20 pF total external load

per pin 0- - ns

td(DIR) DIR output delay with respect to

the rising edge of pin CLOCK 20 pF total external load

per pin - - 8.9 ns

td(NXT) NXT output delay with respect to

the rising edge of pin CLOCK 20 pF total external load

per pin - - 8.9 ns

VCC(I/O) = 3.0 V to 3.6 V

tsu(DATA) DATA set-up time with respect to

the rising edge of pin CLOCK 30 pF total external load

per pin 3.3 - - ns

th(DATA) DATA hold time with respect to

the rising edge of pin CLOCK 30 pF total external load

per pin 0.8 - - ns

td(DATA) DATA output delay with respect

to the rising edge of pin CLOCK 30 pF total external load

per pin - - 5.5 ns

tsu(STP) STP set-up time with respect to

the rising edge of pin CLOCK 30 pF total external load

per pin 3.4 - - ns

th(STP) STP hold time with respect to

the rising edge of pin CLOCK 30 pF total external load

per pin 0.8 - - ns

td(DIR) DIR output delay with respect to

the rising edge of pin CLOCK 30 pF total external load

per pin - - 6.6 ns

td(NXT) NXT output delay with respect to

the rising edge of pin CLOCK 30 pF total external load

per pin - - 6.6 ns

Table 56. Dynamic characteristics: other characteristics

= 3.0 V to 4.5 V; V

CC(I/O)

= 1.65 V to 3.6 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Typical values are at V

= 3.6 V; V

CC(I/O)

= 1.8 V; T

amb

= +25

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

td(busturn-DV) data valid after bus turnaround delay

time 30 pF load; see

Figure 28 1.9 - - ns

tO(THL) high-to-low output transition time line impedance 50 Ω1.2 - 3.1 µs

tO(TLH) low-to-high output transition time line impedance 50 Ω1.2 - 3.1 µs

Product data sheet Rev. 01 — 6 August 2007 63 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

Table 57. Dynamic characteristics: analog I/O pins DP and DM

= 3.0 V to 4.5 V; V

CC(I/O)

= 1.65 V to 3.6 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Typical values are at V

= 3.6 V; V

CC(I/O)

= 1.8 V; T

amb

= +25

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

High-speed driver

tHSR rise time (10 % to 90 %) drive 45 Ω to GND on pins

DP and DM 500 - - ps

tHSF fall time (10 % to 90 %) drive 45 Ω to GND on pins

DP and DM 500 - - ps

Full-speed driver

tFR rise time CL= 50 pF; 10 % to 90 % of

|VOH − VOL|4 - 20 ns

tFF fall time CL= 50 pF; 90 % to 10 % of

|VOH − VOL|4 - 20 ns

FRFM differential rise time/fall time

matching excluding the ﬁrst transition

from the idle state 90 - 111.1 %

USB low-speed driver characteristics

tLR transition time: rise time CL= 200 pF to 600 pF;

1.5 kΩ pull-up on pin DM

enabled; 10 % to 90 % of

|VOH − VOL|

75 - 300 ns

tLF transition time: fall time CL= 200 pF to 600 pF;

1.5 kΩ pull-up on pin DM

enabled; 90 % to 10 % of

|VOH − VOL|

75 - 300 ns

tLRFM rise and fall time matching tLR/tLF; excluding the ﬁrst

transition from the idle state 80 - 125 %

Driver timing (valid only for serial mode)

tPLH(drv) driver propagation delay (LOW

to HIGH) TX_DAT, TX_SE0 to DP, DM;

see Figure 24 --11ns

tPHL(drv) driver propagation delay (HIGH

to LOW) TX_DAT, TX_SE0 to DP, DM;

see Figure 24 --11ns

tPHZ driver disable delay from HIGH

level TX_ENABLE to DP, DM; see

Figure 25 --12ns

tPLZ driver disable delay from LOW

level TX_ENABLE to DP, DM; see

Figure 25 --12ns

tPZH driver enable delay to HIGH

level TX_ENABLE to DP, DM; see

Figure 25 --20ns

tPZL driver enable delay to LOW

level TX_ENABLE to DP, DM; see

Figure 25 --20ns

Receiver timing (valid only for serial mode)

Differential receiver

tPLH(rcv) receiver propagation delay

(LOW to HIGH) DP, DM to RX_RCV, RX_DP

and RX_DM; see Figure 26 --17ns

tPHL(rcv) receiver propagation delay

(HIGH to LOW) DP, DM to RX_RCV, RX_DP

and RX_DM; see Figure 26 --17ns

Product data sheet Rev. 01 — 6 August 2007 64 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

14.1 Timing characteristics

ULPI interface timing requirements are given in Figure 27. This timing apply to

synchronous mode only. All timing is measured with respect to the ISP1504x1 CLOCK

pin. All signals are clocked on the rising edge of CLOCK.

Single-ended receiver

tPLH(se) single-endedpropagation delay

(LOW to HIGH) DP, DM to RX_RCV, RX_DP

and RX_DM; see Figure 26 --17ns

tPHL(se) single-endedpropagation delay

(HIGH to LOW) DP, DM to RX_RCV, RX_DP

and RX_DM; see Figure 26 --17ns

Table 57. Dynamic characteristics: analog I/O pins DP and DM

…continued

= 3.0 V to 4.5 V; V

CC(I/O)

= 1.65 V to 3.6 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Typical values are at V

= 3.6 V; V

CC(I/O)

= 1.8 V; T

amb

= +25

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Fig 23. Rise time and fall time Fig 24. Timing of TX_DAT and TX_SE0 to DP and DM

Fig 25. Timing of TX_ENABLE to DP and DM Fig 26. Timing of DP and DM to RX_RCV, RX_DP and

RX_DM

004aaa861

VOL

tHSR, tFR, tLR tHSF, tFF, tLF

VOH 90 %

10 % 10 %

90 %

004aaa573

VOL

VOH

tPHL(drv)

tPLH(drv)

VCRS VCRS

0.9 V

1.8 V

0 V

logic input

differential

data lines

004aaa574

VOL

VOH

tPZH

tPZL tPHZ

tPLZ

VOH − 0.3 V

VOL + 0.3 V

VCRS

0.9 V

1.8 V

0 V

logic

input

differential

data lines

tPLH(se) tPHL(se)

004aaa575

VOL

VOH

tPHL(rcv)

tPLH(rcv)

VCRS VCRS

0.9 V

2.0 V

0.8 V

logic output

differential

data lines

Product data sheet Rev. 01 — 6 August 2007 65 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

Fig 27. ULPI timing interface

Fig 28. Bus turnaround timing

CLOCK

CONTROL IN

(STP)

DATA IN

(8-BIT)

tsu(STP) th(STP)

tsu(DATA) th(DATA)

CONTROL OUT

(DIR, NXT)

DATA OUT

(8-BIT)

004aaa722

td(DIR),

td(NXT)

td(DATA) td(DIR),

td(NXT)

004aaa794

CLOCK

DATA[7:0] DRIVE

td(busturn-DV)

3-STATE

link releases data bus

turnaround cycle

Product data sheet Rev. 01 — 6 August 2007 66 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

15. Application information

[1] Recommended crystal speciﬁcation: 500 µW (max) drive level, ESR 100 Ω (max) and shunt capacitance 7 pF (max).

Table 58. Recommended bill of materials

Designator Application Part type Comment

Cbypass highly recommended for all

applications 0.1 µF-

Cﬁlter highly recommended for all

applications 4.7 µF± 20 %; use a LOW

ESR capacitor (0.2 Ω to 2 Ω)

for best performance

CVBUS mandatory for peripherals 0.1 µF and 1 µF to 10 µF in

parallel -

mandatory for host 0.1 µF and 120 µF± 20 %

(min) in parallel -

mandatory for OTG 0.1 µF and 1 µF to 6.5 µF in

parallel -

DESD recommended for all

ESD-sensitive applications IP4359CX4/LF Wafer-Level Chip-Scale Package

(WLCSP); ESD IEC 61000-4-2 level 4;

±15 kV contact; ±15 kV air discharge

compliant protection

Rpullup recommended; for applications

with an external VBUS supply

controlled by PSW_N

4.7 kΩ (recommended) -

RRREF mandatory in all applications 12 kΩ± 1% -

RS(VBUS) strongly recommended for

peripheral or external 5 V

applications only

1kΩ± 5% -

RXTAL required only for applications

driving a square wave into the

XTAL1 pin

47 kΩ± 5 % used to avoid ﬂoating input on the XTAL1

XTAL crystal is used 19.2 MHz CL= 10 pF; RS< 220 Ω; CXTAL = 18 pF[1]

26 MHz CL= 10 pF; RS< 130 Ω; CXTAL = 18 pF[1]

C(XTAL)SQ required only for applications

driving a square wave into the

XTAL1 pin that has a DC offset

100 pF used to AC couple the input square wave to

the XTAL1 pin

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Product data sheet Rev. 01 — 6 August 2007 67 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

Fig 29. Using the ISP1504x1 with a standard USB Peripheral Controller; external crystal

ISP1504x1

DATA0

VCC(I/O)

RREF

FAULT

n.c.

VCC

PSW_N

DATA1

DATA2

VCC(I/O)

CS_N/PWRDN

DATA3

CLOCK

DATA4

DATA5

DATA6

DATA7

VCC(I/O)

NXT

004aaa945

VBUS

REG3V3

XTAL1

XTAL2

F4 STP

DIR

REG1V8

RESET_N C4

PERIPHERAL

CONTROLLER

USB

STANDARD-B

RECEPTACLE

SHIELD

VBUS

D−

D+

GND 4

1DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

CLOCK

NXT

STP

DIR

VCC(I/O)

VCC

CS_N/PWRDN

(optional)

GND (B4, C5, D2, E1, E4)

IP4359CX4/LF

A1 A2

Cbypass

RRREF

CVBUS

Cbypass Cfilter

CXTAL

XTAL

CXTAL Cbypass Cfilter

DESD

RS(VBUS)

Rpullup

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Product data sheet Rev. 01 — 6 August 2007 68 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

(1) Can be a square wave clock of 19.2 MHz or 26 MHz.

Fig 30. Using the ISP1504x1 with an OTG Controller; external 5 V source with built-in FAULT and external square wave input on pin XTAL1

ISP1504x1

DATA0

VCC(I/O)

RREF

FAULT

n.c.

VCC

PSW_N

DATA1

DATA2

VCC(I/O)

CS_N/PWRDN

DATA3

CLOCK

DATA4

DATA5

DATA6

DATA7

VCC(I/O)

NXT

004aaa946

VBUS

REG3V3

XTAL1

XTAL2

F4 STP

DIR

REG1V8

RESET_N C4

OTG

CONTROLLER

USB MICRO-AB

RECEPTACLE

SHIELD

VBUS

D−

D+

GND 5

1DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

CLOCK

NXT

STP

DIR RESET_N

(optional)

VCC(I/O)

VCC

GND (B4, C5, D2, E1, E4)

+5 V

IN FAULT

ON OUT

VBUS

SWITCH

CS_N/PWRDN

(optional)

RS(VBUS)

Cbypass Cbypass

RRREF

IP4359CX4/LF

A1 A2

DESD

CVBUS

Cbypass Cfilter

Rpullup

C(XTAL)SQ

fi(XTAL1)(1) RXTAL

B1 B2

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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Product data sheet Rev. 01 — 6 August 2007 69 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

Fig 31. Using the ISP1504x1 with a standard USB Host Controller; external 5 V source with built-in FAULT and external crystal

ISP1504x1

DATA0

VCC(I/O)

RREF

FAULT

n.c.

VCC

PSW_N

DATA1

DATA2

VCC(I/O)

CS_N/PWRDN

DATA3

CLOCK

DATA4

DATA5

DATA6

DATA7

VCC(I/O)

NXT

004aaa947

VBUS

REG3V3

XTAL1

XTAL2

F4 STP

DIR

REG1V8

RESET_N C4

HOST

CONTROLLER

USB

STANDARD-A

RECEPTACLE

SHIELD

VBUS

D−

D+

GND 4

1DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

CLOCK

NXT

STP

DIR RESET_N

(optional)

VCC(I/O)

VCC

GND (B4, C5, D2, E1, E4)

+5 V

IN FAULT

ON OUT

VBUS

SWITCH

CS_N/PWRDN

(optional)

RS(VBUS)

IP4359CX4/LF

A1 A2

DESD

Cbypass Cbypass

RRREF

Rpullup

CVBUS Cbypass Cfilter

CXTAL CXTAL Cbypass Cfilter

XTAL

B1 B2

Product data sheet Rev. 01 — 6 August 2007 70 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

16. Package outline

Fig 32. Package outline SOT912-1 (TFBGA36)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT912-1

05-08-09

05-09-01

UNIT A

max

mm 1.15 0.25

0.15 0.90

0.75 0.35

0.25 3.6

3.4 3.6

3.4

DIMENSIONS (mm are the original dimensions)

TFBGA36: plastic thin fine-pitch ball grid array package; 36 balls; body 3.5 x 3.5 x 0.8 mm

0 2.5 5 mm

scale

A2b D E e2

2.5

0.5

2.5

0.1

0.15

0.05

0.08

- - - - - -- - -

1/2 e

AC B

vMCw M

ball A1

index area

246135

ball A1

index area

B A

detail X

Product data sheet Rev. 01 — 6 August 2007 71 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

17. Soldering

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note

AN10365 “Surface mount reﬂow

soldering description”

17.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

17.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

•Board speciﬁcations, including the board ﬁnish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus PbSn soldering

17.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath speciﬁcations, including temperature and impurities

Product data sheet Rev. 01 — 6 August 2007 72 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

17.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

•Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 33) than a PbSn process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 59 and 60

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 33.

Table 59. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 60. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 01 — 6 August 2007 73 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

For further information on temperature proﬁles, refer to Application Note

AN10365

“Surface mount reﬂow soldering description”

18. Abbreviations

MSL: Moisture Sensitivity Level

Fig 33. Temperature proﬁles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Table 61. Abbreviations

Acronym Description

ASIC Application-Speciﬁc Integrated Circuit

ATX Analog USB Transceiver

EOP End-Of-Packet

ESR Effective Series Resistance

FS Full-Speed

HBM Human Body Model

HNP Host Negotiation Protocol

HS High-Speed

ID Identiﬁcation

LS Low-Speed

MM Machine Model

NRZI Non-Return-to-Zero Inverted

OTG On-The-Go

PHY Physical Layer[1]

PID Packet Identiﬁer

PLL Phase-Locked Loop

POR Power-On Reset

RXCMD Receive Command

SE0 Single-Ended Zero

Product data sheet Rev. 01 — 6 August 2007 74 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

[1] Physical layer containing the USB transceiver. The ISP1504x1 is a PHY.

19. References

[1] Universal Serial Bus Speciﬁcation Rev. 2.0

[2] On-The-Go Supplement to the USB 2.0 Speciﬁcation Rev. 1.2

[3] UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1

[4] UTMI+ Speciﬁcation Rev. 1.0

[5] USB 2.0 Transceiver Macrocell Interface (UTMI) Speciﬁcation Ver. 1.05

[6] Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM)

(JESD22-A114D)

[7] Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM)

(JESD22-A115-A)

[8] Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components

(JESD22-C101-C)

20. Revision history

SOF Start-Of-Frame

SRP Session Request Protocol

SYNC Synchronous

TTL Transistor-Transistor Logic

TXCMD Transmit Command

USB Universal Serial Bus

USB-IF USB Implementers Forum

ULPI UTMI+ Low Pin Interface

UTMI USB 2.0 Transceiver Macrocell Interface

UTMI+ USB 2.0 Transceiver Macrocell Interface Plus

Table 61. Abbreviations

…continued

Acronym Description

Table 62. Revision history

Document ID Release date Data sheet status Change notice Supersedes

ISP1504A1_ISP1504C1_1 20070806 Product data sheet - -

Product data sheet Rev. 01 — 6 August 2007 75 of 80

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

21. Legal information

21.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

21.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

21.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of a NXP Semiconductors product can reasonably be expected to

result in personal injury, death or severe property or environmental damage.

NXP Semiconductors accepts no liability for inclusion and/or use of NXP

Semiconductors products in such equipment or applications and therefore

such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

21.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

22. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

Product data sheet Rev. 01 — 6 August 2007 76 of 80

continued >>

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

23. Tables

Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table 3. Recommended VBUS capacitor value . . . . . . .12

Table 4. ULPI signal description . . . . . . . . . . . . . . . . . .14

Table 5. Signal mapping during low-power mode . . . . .16

Table 6. Signal mapping for 6-pin serial mode . . . . . . .16

Table 7. Signal mapping for 3-pin serial mode . . . . . . .17

Table 8. Operating states and corresponding resistor

settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 9. OTG Control register power control bits . . . . .25

Table 10. TXCMD byte format . . . . . . . . . . . . . . . . . . . . .26

Table 11. RXCMD byte format . . . . . . . . . . . . . . . . . . . . .27

Table 12. LINESTATE[1:0] encoding for upstream

facing ports: peripheral . . . . . . . . . . . . . . . . . .27

Table 13. LINESTATE[1:0] encoding for downstream

facing ports: host . . . . . . . . . . . . . . . . . . . . . . .28

Table 14. Encoded VBUS voltage state . . . . . . . . . . . . . .28

Table 15. VBUS indicators in RXCMD required for

typical applications . . . . . . . . . . . . . . . . . . . . . .29

Table 16. Encoded USB event signals . . . . . . . . . . . . . .30

Table 17. PHY pipeline delays . . . . . . . . . . . . . . . . . . . . .34

Table 18. Link decision times . . . . . . . . . . . . . . . . . . . . .35

Table 19. Immediate register set overview . . . . . . . . . . .47

Table 20. Extended register set overview . . . . . . . . . . . .47

Table 21. Vendor ID Low register (address R = 00h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 22. Vendor ID High register (address R = 01h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 23. Product ID Low register (address R = 02h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 24. Product ID High register (address R = 03h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 25. Function Control register (address R = 04h to

06h, W = 04h, S = 05h, C = 06h) bit allocation 48

Table 26. Function Control register (address

R = 04h to 06h, W = 04h, S = 05h, C = 06h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .49

Table 27. Interface Control register (address R = 07h to

09h, W = 07h, S = 08h, C = 09h) bit allocation 49

Table 28. Interface Control register (address R = 07h to

09h, W = 07h, S = 08h, C = 09h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Table 29. OTG Control register (address R = 0Ah to

0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Table 30. OTG Control register (address R = 0Ah to

0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Table 31. USB Interrupt Enable Rising Edge register

(address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh,

C = 0Fh) bit allocation . . . . . . . . . . . . . . . . . . .51

Table 32. USB Interrupt Enable Rising Edge register

(address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh,

C = 0Fh) bit description . . . . . . . . . . . . . . . . . .52

Table 33. USB Interrupt Enable Falling Edge register

(address R = 10h to 12h, W = 10h, S = 11h,

C = 12h) bit allocation . . . . . . . . . . . . . . . . . . .52

Table 34. USB Interrupt Enable Falling Edge register

(address R = 10h to 12h, W = 10h, S = 11h,

C = 12h) bit description . . . . . . . . . . . . . . . . . .52

Table 35. USB Interrupt Status register (address R =

13h) bit allocation . . . . . . . . . . . . . . . . . . . . . .53

Table 36. USB Interrupt Status register (address R =

13h) bit description . . . . . . . . . . . . . . . . . . . . .53

Table 37. USB Interrupt Latch register (address R =

14h) bit allocation . . . . . . . . . . . . . . . . . . . . . .53

Table 38. USB Interrupt Latch register (address R =

14h) bit description . . . . . . . . . . . . . . . . . . . . .53

Table 39. Debug register (address R = 15h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Table 40. Debug register (address R = 15h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Table 41. Scratch register (address R = 16h to 18h,

W = 16h, S = 17h, C = 18h) bit description . . .54

Table 42. Power Control register (address R = 3Dh to

3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Table 43. Power Control register (address R = 3Dh to

3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Table 44. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .56

Table 45. Recommended operating conditions . . . . . . . .56

Table 46. Static characteristics: supply pins . . . . . . . . . .57

Table 47. Static characteristics: digital pins CLOCK,

DIR, STP, NXT, DATA[7:0], RESET_N,

CS_N/PWRDN . . . . . . . . . . . . . . . . . . . . . . . .57

Table 48. Static characteristics: digital pin FAULT . . . . .58

Table 49. Static characteristics: digital pin PSW_N . . . .58

Table 50. Static characteristics: analog I/O pins DP,

DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Table 51. Static characteristics: analog pin VBUS . . . . . .60

Table 52. Static characteristics: ID detection circuit . . . .60

Table 53. Static characteristics: resistor reference . . . . .60

Table 54. Dynamic characteristics: reset and clock . . . .61

Table 55. Dynamic characteristics: digital I/O pins . . . . .62

Table 56. Dynamic characteristics: other characteristics 62

Product data sheet Rev. 01 — 6 August 2007 77 of 80

continued >>

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

Table 57. Dynamic characteristics: analog I/O pins DP

and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Table 58. Recommended bill of materials . . . . . . . . . . . .66

Table 59. SnPb eutectic process (from J-STD-020C) . . .72

Table 60. Lead-free process (from J-STD-020C) . . . . . .72

Table 61. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .73

Table 62. Revision history . . . . . . . . . . . . . . . . . . . . . . . .74

Product data sheet Rev. 01 — 6 August 2007 78 of 80

continued >>

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

24. Figures

Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Fig 2. Pin conﬁguration TFBGA36; top view . . . . . . . . . .5

Fig 3. Application circuit components . . . . . . . . . . . . . .12

Fig 4. Entering and exiting 3-state in normal mode . . . .18

Fig 5. Internal power-on reset timing . . . . . . . . . . . . . . .21

Fig 6. Power-up and reset sequence required before

the ULPI bus is ready for use. . . . . . . . . . . . . . . .23

Fig 7. Interface behavior with respect to RESET_N. . . .24

Fig 8. Interface behavior with respect to

CS_N/PWRDN. . . . . . . . . . . . . . . . . . . . . . . . . . .25

Fig 9. Single and back-to-back RXCMDs from the

ISP1504x1 to the link. . . . . . . . . . . . . . . . . . . . . .27

Fig 10. RXCMD A_VBUS_VLD indicator source. . . . . . .29

Fig 11. Example of register write, register read,

extended register write and extended register

read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Fig 12. USB reset and high-speed detection

handshake (chirp) sequence . . . . . . . . . . . . . . . .33

Fig 13. Example of using the ISP1504x1 to transmit and

receive USB data. . . . . . . . . . . . . . . . . . . . . . . . .34

Fig 14. High-speed transmit-to-transmit packet timing. . .35

Fig 15. High-speed receive-to-transmit packet timing . . .36

Fig 16. Preamble sequence. . . . . . . . . . . . . . . . . . . . . . .37

Fig 17. Full-speed suspend and resume . . . . . . . . . . . . .38

Fig 18. High-speed suspend and resume . . . . . . . . . . . .40

Fig 19. Remote wake-up from low-power mode . . . . . . .42

Fig 20. Transmitting USB packets without automatic

SYNC and EOP generation . . . . . . . . . . . . . . . . .43

Fig 21. Example of transmit followed by receive in

6-pin serial mode . . . . . . . . . . . . . . . . . . . . . . . . .45

Fig 22. Example of transmit followed by receive in

3-pin serial mode . . . . . . . . . . . . . . . . . . . . . . . . .45

Fig 23. Rise time and fall time . . . . . . . . . . . . . . . . . . . . .64

Fig 24. Timing of TX_DAT and TX_SE0 to DP and DM. .64

Fig 25. Timing of TX_ENABLE to DP and DM. . . . . . . . .64

Fig 26. Timing of DP and DM to RX_RCV, RX_DP and

RX_DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Fig 27. ULPI timing interface . . . . . . . . . . . . . . . . . . . . . .65

Fig 28. Bus turnaround timing . . . . . . . . . . . . . . . . . . . . .65

Fig 29. Using the ISP1504x1 with a standard USB

Peripheral Controller; external crystal . . . . . . . . .67

Fig 30. Using the ISP1504x1 with an OTG Controller;

external 5 V source with built-in FAULT and

external square wave input on pin XTAL1 . . . . . .68

Fig 31. Using the ISP1504x1 with a standard USB Host

Controller; external 5 V source with built-in

FAULT and external crystal . . . . . . . . . . . . . . . . .69

Fig 32. Package outline SOT912-1 (TFBGA36). . . . . . . .70

Fig 33. Temperature proﬁles for large and small

components. . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Product data sheet Rev. 01 — 6 August 2007 79 of 80

continued >>

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

25. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

7 Functional description . . . . . . . . . . . . . . . . . . . 7

7.1 ULPI interface controller. . . . . . . . . . . . . . . . . . 7

7.2 USB data serializer and deserializer. . . . . . . . . 7

7.3 Hi-Speed USB (USB 2.0) ATX . . . . . . . . . . . . . 7

7.4 Voltage regulator. . . . . . . . . . . . . . . . . . . . . . . . 8

7.5 Crystal oscillator and PLL. . . . . . . . . . . . . . . . . 8

7.6 OTG module . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

7.6.1 ID detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

7.6.2 VBUS comparators. . . . . . . . . . . . . . . . . . . . . . . 9

7.6.2.1 VBUS valid comparator . . . . . . . . . . . . . . . . . . . 9

7.6.2.2 Session valid comparator . . . . . . . . . . . . . . . . . 9

7.6.2.3 Session end comparator. . . . . . . . . . . . . . . . . . 9

7.6.3 SRP charge and discharge resistors . . . . . . . . 9

7.7 Band gap reference voltage . . . . . . . . . . . . . . 10

7.8 Power-On Reset (POR) . . . . . . . . . . . . . . . . . 10

7.9 Detailed description of pins . . . . . . . . . . . . . . 10

7.9.1 DATA[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

7.9.2 VCC(I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

7.9.3 RREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

7.9.4 DP and DM. . . . . . . . . . . . . . . . . . . . . . . . . . . 11

7.9.5 FAULT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

7.9.6 ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

7.9.7 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

7.9.8 PSW_N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

7.9.9 VBUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

7.9.10 REG3V3 and REG1V8 . . . . . . . . . . . . . . . . . . 12

7.9.11 XTAL1 and XTAL2. . . . . . . . . . . . . . . . . . . . . . 12

7.9.12 RESET_N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7.9.13 DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.9.14 STP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.9.15 NXT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.9.16 CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.9.17 CS_N/PWRDN . . . . . . . . . . . . . . . . . . . . . . . . 13

7.9.18 GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

8 Modes of operation . . . . . . . . . . . . . . . . . . . . . 14

8.1 ULPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . 14

8.1.1 Synchronous mode. . . . . . . . . . . . . . . . . . . . . 14

8.1.2 Low-power mode . . . . . . . . . . . . . . . . . . . . . . 15

8.1.3 6-pin full-speed or low-speed serial mode . . . 16

8.1.4 3-pin full-speed or low-speed serial mode . . . 16

8.1.5 Power-down mode . . . . . . . . . . . . . . . . . . . . . 17

8.2 USB state transitions . . . . . . . . . . . . . . . . . . . 18

9 Protocol description . . . . . . . . . . . . . . . . . . . . 21

9.1 ULPI references. . . . . . . . . . . . . . . . . . . . . . . 21

9.2 Power-On Reset (POR) . . . . . . . . . . . . . . . . . 21

9.3 Power-up, reset and bus idle sequence . . . . . 21

9.3.1 Interface protection. . . . . . . . . . . . . . . . . . . . . 24

9.3.2 Interface behavior with respect to

RESET_N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

9.3.3 Interface behavior with respect to

CS_N/PWRDN. . . . . . . . . . . . . . . . . . . . . . . . 24

9.4 VBUS power and overcurrent detection. . . . . . 25

9.4.1 Driving 5 V on VBUS . . . . . . . . . . . . . . . . . . . . 25

9.4.2 Fault detection . . . . . . . . . . . . . . . . . . . . . . . . 25

9.5 TXCMD and RXCMD. . . . . . . . . . . . . . . . . . . 25

9.5.1 TXCMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

9.5.2 RXCMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

9.5.2.1 Linestate encoding. . . . . . . . . . . . . . . . . . . . . 27

9.5.2.2 VBUS state encoding. . . . . . . . . . . . . . . . . . . . 28

9.5.2.3 Using and selecting the VBUS state encoding. 29

9.5.2.4 RxEvent encoding . . . . . . . . . . . . . . . . . . . . . 30

9.6 Register read and write operations . . . . . . . . 31

9.7 USB reset and high-speed detection

handshake (chirp) . . . . . . . . . . . . . . . . . . . . . 31

9.8 USB packet transmit and receive. . . . . . . . . . 34

9.8.1 USB packet timing . . . . . . . . . . . . . . . . . . . . . 34

9.8.1.1 ISP1504x1 pipeline delays. . . . . . . . . . . . . . . 34

9.8.1.2 Allowed link decision time . . . . . . . . . . . . . . . 34

9.9 Preamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

9.10 USB suspend and resume. . . . . . . . . . . . . . . 37

9.10.1 Full-speed or low-speed host-initiated

suspend and resume . . . . . . . . . . . . . . . . . . . 37

9.10.2 High-speed suspend and resume . . . . . . . . . 38

9.10.3 Remote wake-up . . . . . . . . . . . . . . . . . . . . . . 41

9.11 No automatic SYNC and EOP generation

(optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.12 On-The-Go operations. . . . . . . . . . . . . . . . . . 43

9.12.1 OTG comparators. . . . . . . . . . . . . . . . . . . . . . 44

9.12.2 Pull-up and pull-down resistors . . . . . . . . . . . 44

9.12.3 ID detection . . . . . . . . . . . . . . . . . . . . . . . . . . 44

9.12.4 VBUS charge and discharge resistors. . . . . . . 44

9.13 Serial modes . . . . . . . . . . . . . . . . . . . . . . . . . 44

9.14 Aborting transfers. . . . . . . . . . . . . . . . . . . . . . 46

9.15 Avoiding contention on the ULPI data bus. . . 46

10 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . 47

NXP Semiconductors ISP1504A1; ISP1504C1

ULPI HS USB OTG transceiver

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 6 August 2007

Document identifier: ISP1504A1_ISP1504C1_1

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

10.1 Immediate register set . . . . . . . . . . . . . . . . . . 48

10.1.1 Vendor ID and Product ID registers . . . . . . . . 48

10.1.1.1 Vendor ID Low register. . . . . . . . . . . . . . . . . . 48

10.1.1.2 Vendor ID High register . . . . . . . . . . . . . . . . . 48

10.1.1.3 Product ID Low register . . . . . . . . . . . . . . . . . 48

10.1.1.4 Product ID High register . . . . . . . . . . . . . . . . . 48

10.1.2 Function Control register . . . . . . . . . . . . . . . . 48

10.1.3 Interface Control register . . . . . . . . . . . . . . . . 49

10.1.4 OTG Control register . . . . . . . . . . . . . . . . . . . 50

10.1.5 USB Interrupt Enable Rising Edge register . . 51

10.1.6 USB Interrupt Enable Falling Edge register . . 52

10.1.7 USB Interrupt Status register . . . . . . . . . . . . . 52

10.1.8 USB Interrupt Latch register. . . . . . . . . . . . . . 53

10.1.9 Debug register . . . . . . . . . . . . . . . . . . . . . . . . 54

10.1.10 Scratch register. . . . . . . . . . . . . . . . . . . . . . . . 54

10.1.11 Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10.1.12 Access extended register set . . . . . . . . . . . . . 54

10.1.13 Vendor-speciﬁc registers . . . . . . . . . . . . . . . . 54

10.1.14 Power Control register . . . . . . . . . . . . . . . . . . 54

10.2 Extended register set . . . . . . . . . . . . . . . . . . . 55

11 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 56

12 Recommended operating conditions. . . . . . . 56

13 Static characteristics. . . . . . . . . . . . . . . . . . . . 57

14 Dynamic characteristics . . . . . . . . . . . . . . . . . 61

14.1 Timing characteristics. . . . . . . . . . . . . . . . . . . 64

15 Application information. . . . . . . . . . . . . . . . . . 66

16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 70

17 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

17.1 Introduction to soldering . . . . . . . . . . . . . . . . . 71

17.2 Wave and reﬂow soldering . . . . . . . . . . . . . . . 71

17.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 71

17.4 Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 72

18 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 73

19 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

20 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 74

21 Legal information. . . . . . . . . . . . . . . . . . . . . . . 75

21.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 75

21.2 Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

21.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 75

21.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 75

22 Contact information. . . . . . . . . . . . . . . . . . . . . 75

23 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

24 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

25 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79