Si8902EDB Vishay Siliconix Bi-Directional N-Channel 20-V (D-S) MOSFET FEATURES D D D D PRODUCT SUMMARY VS1S2 (V) 20 rS1S2(on) (W) IS1S2 (A) 0.045 @ VGS = 4.5 V 5.0 0.048 @ VGS = 3.7 V 4.8 0.057 @ VGS = 2.5 V 4.4 0.072 @ VGS = 1.8 V 3.9 TrenchFETr Power MOSFET Ultra-Low rSS(on) ESD Protected: 4000 V New MICRO FOOTr Chipscale Packaging Reduces Footprint Area, Profile (0.65 mm) and On-Resistance Per Footprint Area APPLICATIONS D Battery Protection Circuit - 1-2 Cell Li+/LiP Battery Pack for Portable Devices S1 MICRO FOOT Bump Side View S2 5 4 Backside View G1 S2 4 kW Pin 1 Identifier S1 6 1 3 2 8902E xxx G2 G1 4 kW Device Marking: G2 8902E = P/N Code xxx = Date/Lot Traceability Code Ordering Information: Si8902EDB-T2--E3 S1 N-Channel S2 ABSOLUTE MAXIMUM RATINGS (TA = 25_C UNLESS OTHERWISE NOTED) Parameter Symbol Source1--Source2 Voltage Gate-Source Voltage Continuous Source1--Source2 Current (TJ = 150_C)a TA = 25_C TA = 85_C Pulsed Source1--Source2 Current TA = 85_C Operating Junction and Storage Temperature Range Package Reflow Conditionsc Steady State VS1S2 20 VGS "12 IS1S2 PD Unit V 5.0 3.9 3.4 2.8 ISM TA = 25_C Maximum Power Dissipationa 5 secs A 40 1.7 1 0.8 0.5 TJ, Tstg W -55 to 150 VPR 215 IR/Convection 220 _C THERMAL RESISTANCE RATINGS Parameter M i Maximum JJunction-to-Ambient ti t A bi ta Maximum Junction-to-Footb Symbol t v 5 sec Steady State Steady State RthJA RthJF Typical Maximum 60 75 95 120 18 22 Unit _C/W C/W Notes a. Surface Mounted on 1" x 1" FR4 Board. b. The Foot is defined as the top surface of the package. c. Refer to IPC/JEDEC (J-STD-020A), no manual or hand soldering. Document Number: 71862 S-40861--Rev. F, 03-May-04 www.vishay.com 1 Si8902EDB Vishay Siliconix SPECIFICATIONS (TJ = 25_C UNLESS OTHERWISE NOTED) Parameter Symbol Test Condition Min VSS = VGS, ID = 980 mA 0.45 Typ Max Unit Static Gate Threshold Voltage VGS(th) Gate Body Leakage Gate-Body IGSS Zero Gate Voltage Source Current IS1S2 On-State Source Currenta IS(on) Source1 Source2 On-State Source1--Source2 On State Resistancea Forward V "4 mA VSS = 0 V, VGS = "12 V "10 mA VSS = 20 V, VGS = 0 V 1 VSS = 20 V, VGS = 0 V, TJ = 85_C 5 VSS = 5 V, VGS = 4.5 V rS1S2(on) Transconductancea 1.0 VSS = 0 V, VGS = "4.5 V gfs mA 5 A VGS = 4.5 V, ISS = 1 A 0.038 0.045 VGS = 3.7 V, ISS = 1 A 0.041 0.048 VGS = 2.5 V, ISS = 1 A 0.048 0.057 VGS = 1.8 V, ISS = 1 A 0.060 0.072 VSS = 10 V, ISS = 1 A 20 W S Dynamicb Turn-On Delay Time Rise Time Turn-Off Delay Time td(on) 1 1.5 tr 3 4.5 17 26 10 15 VSS = 10 V, RL = 10 W ISS ^ 1 A, VGEN = 4.5 V, RG = 6 W td(off) Fall Time tf ms Notes a. Pulse test; pulse width v 300 ms, duty cycle v 2%. b. Guaranteed by design, not subject to production testing. TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) Gate-Current vs. Gate-Source Voltage 20 Gate Current vs. Gate-Source Voltage 10,000 1,000 I GSS - Gate Current (mA) I GSS - Gate Current (mA) IGSS @ 25_C (mA) 16 12 8 4 TJ = 150_C 10 1 TJ = 25_C 0.1 0 0.01 0 3 6 9 12 VGS - Gate-to-Source Voltage (V) www.vishay.com 2 100 15 0 3 6 9 12 15 VGS - Gate-to-Source Voltage (V) Document Number: 71862 S-40861--Rev. F, 03-May-04 Si8902EDB Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) Output Characteristics Transfer Characteristics 10 10 VGS = 5 thru 1.5 V 8 I D - Drain Current (A) I D - Drain Current (A) 8 6 4 2 6 4 TC = 125_C 2 1V 25_C -55_C 0 0.0 0.5 1.0 1.5 2.0 2.5 0 0.0 3.0 0.2 VDS - Drain-to-Source Voltage (V) 1.0 1.2 1.4 On-Resistance vs. Junction Temperature 0.08 r DS(on) - On-Resistance (W) (Normalized) r DS(on) - On-Resistance ( W ) 0.8 1.6 VGS = 1.8 V 0.06 VGS = 2.5 V 0.04 VGS = 4.5 V VGS = 3.7 V 0.02 0.00 0 2 4 6 8 1.4 1.2 1.0 0.8 0.6 -50 10 VGS = 4.5 V IS1S2 = 1 A -25 On-Resistance vs. Gate-to-Source Voltage 0.10 0 25 50 75 100 125 150 125 150 TJ - Junction Temperature (_C) ID - Drain Current (A) Threshold Voltage 0.2 IS1S2 = 5 A 0.1 0.08 IS1S2 = 980 mA IS1S2 = 1 A V GS(th) Variance (V) r DS(on) - On-Resistance ( W ) 0.6 VGS - Gate-to-Source Voltage (V) On-Resistance vs. Drain Current 0.10 0.4 0.06 0.04 0.02 -0.0 -0.1 -0.2 -0.3 0.00 0 1 2 3 VGS - Gate-to-Source Voltage (V) Document Number: 71862 S-40861--Rev. F, 03-May-04 4 5 -0.4 -50 -25 0 25 50 75 100 TJ - Temperature (_C) www.vishay.com 3 Si8902EDB Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) Single Pulse Power, Junction-to-Ambient Safe Operating Area 100 30 25 IDM Limited Limited by rDS(on) 0.0001 s 10 I D - Drain Current (A) Power (W) 20 15 10 0.001 s 1 0.01 s ID(on) Limited 0.1 s 0.1 5 1s TA = 25_C Single Pulse 10 s dc 0.01 0 0.01 0.1 1 100 10 1000 0.1 Time (sec) 1 10 VDS - Drain-to-Source Voltage (V) 1 Duty Cycle = 0.5 0.2 Notes: 0.1 PDM 0.1 0.05 t1 t2 1. Duty Cycle, D = 0.02 2. 4. Surface Mounted 0.01 10-4 t1 t2 PER UNIT BASE = RTHJA = 95_C/W 3. TJM - TA = PDMZthJA(t) Single Pulse 10-3 10-2 10-1 1 Square Wave Pulse Duration (sec) 10 100 600 Normalized Thermal Transient Impedance, Junction-to-Foot 2 Normalized Effective Transient Thermal Impedance 100 Normalized Thermal Transient Impedance, Junction-to-Ambient 2 Normalized Effective Transient Thermal Impedance BVDSS Limited 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10-4 www.vishay.com 4 10-3 10-2 Square Wave Pulse Duration (sec) 10-1 1 Document Number: 71862 S-40861--Rev. F, 03-May-04 Si8902EDB Vishay Siliconix PACKAGE OUTLINE MICRO FOOT: 6-BUMP (2 X 3, 0.8-mm PITCH) 6 0.30 X 0.31 Note 3 Solder Mask -0.4 Note 2 A2 A A1 e b Diameter Bump Note 1 e e Recommended Land 8902E e XXX D s Mark on Backside of Die s e e E NOTES (Unless Otherwise Specified): 1. 6 solder bumps are Eutetic 63Sn/37Pb with diameter 0.37 - 0.41 mm 2. Backside surface is coated with a Ag/Ni/Ti layer 3. Non-solder mask defined copper landing pad. 4. Laser marks on the silicon die back MILLIMETERS* INCHES Dim Min Max Min Max A 0.600 0.650 0.0236 0.0256 A1 0.260 0.290 0.102 0.114 A2 0.340 0.360 0.0134 0.0142 b 0.370 0.410 0.0146 0.0161 D 1.520 1.600 0.0598 0.0630 E 2.320 2.400 0.0913 0.0945 e 0.750 0.850 0.0295 0.0335 s 0.380 0.400 0.0150 0.0157 * Use millimeters as the primary measurement. Document Number: 71862 S-40861--Rev. F, 03-May-04 www.vishay.com 5