Zero Drift, Digitally Programmable
Instrumentation Amplifier
AD8231
Rev. B
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FEATURES
Digitally/pin-programmable gain
G = 1, 2, 4, 8, 16, 32, 64, or 128
Specified from −40°C to +125°C
50 nV/°C maximum input offset drift
10 ppm/°C maximum gain drift
Excellent dc performance
80 dB minimum CMR, G = 1
15 µV maximum input offset voltage
500 pA maximum bias current
0.7 µV p-p noise (0.1 Hz to 10 Hz)
Good ac performance
2.7 MHz bandwidth, G = 1
1.1 V/s slew rate
Rail-to-rail output
Shutdown/multiplex
Extra op amp
Single-supply range: 3 V to 5 V
Dual-supply range: ±1.5 V to ±2.5 V
Qualified for automotive applications
APPLICATIONS
Pressure and strain transducers
Thermocouples and RTDs
Programmable instrumentation
Industrial controls
Weigh scales
Automotive controls
FUNCTIONAL BLOCK DIAGRAM
06586-001
IN-AMP
LOGIC
NC 1
–INA 2
+IN
A
3
NC 4
+V
S
12
–V
S
11
OUTA
10
REF
9
A2
16
A1
15
A0
14
CS
13
SDN 5
+INB 6
–INB 7
OUTB 8
OP
AMP
AD8231
Figure 1.
Table 1. Instrumentation and Difference Amplifiers by
Category
High
Performance
Low
Cost
High
Voltage
Mil
Grade
Low
Power
Digital
Gain
AD8221 AD6231 AD628 AD620 AD6271 AD82311
AD82201 AD85531 AD629 AD621 AD8250
AD8222 AD524 AD8251
AD82241 AD526 AD85551
AD624 AD85561
AD85571
1 Rail-to-rail output.
GENERAL DESCRIPTION
The AD8231 is a low drift, rail-to-rail, instrumentation amplifier
with software-programmable gains of 1, 2, 4, 8, 16, 32, 64, or 128.
The gains are programmed via digital logic or pin strapping.
The AD8231 is ideal for applications that require precision
performance over a wide temperature range, such as industrial
temperature sensing and data logging. Because the gain setting
resistors are internal, maximum gain drift is only 10 ppm/°C for
gains of 1 to 32. Because of the auto-zero input stage, maximum
input offset is 15 µV and maximum input offset drift is just
50 nV/°C. CMRR is 80 dB for G = 1, increasing to 110 dB at
higher gains.
The AD8231 also includes an uncommitted op amp that can be
used for additional gain, differential signal driving, or filtering.
Like the in-amp, the op amp has an auto-zero architecture, rail-
to-rail input, and rail-to-rail output.
The AD8231 includes a shutdown feature that reduces current
to a maximum of 1 µA. In shutdown, both amplifiers also have
a high output impedance, which allows easy multiplexing of
multiple amplifiers without additional switches.
The AD8231 is specified over the extended industrial tempera-
ture range of −40°C to +125°C. It is available in a 4 mm × 4 mm
16-lead LFCSP.
AD8231
Rev. B | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
Maximum Power Dissipation ..................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Instrumentation Amplifier Performance Curves..................... 9
Operational Amplifier Performance Curves .......................... 15
Performance Curves Valid for Both Amplifiers ..................... 17
Theory of Operation ...................................................................... 18
Amplifier Architecture .............................................................. 18
Gain Selection............................................................................. 18
Reference Terminal .................................................................... 18
Layout .......................................................................................... 19
Input Bias Current Return Path ............................................... 19
Input Protection ......................................................................... 19
RF Interference ........................................................................... 20
Common-Mode Input Voltage Range..................................... 20
Reducing Noise........................................................................... 20
Applications Information.............................................................. 21
Differential Output .................................................................... 21
Multiplexing................................................................................ 21
Using the AD8231 with Bipolar Supplies................................ 21
Sallen Key Filter.......................................................................... 22
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 23
Automotive Products................................................................. 23
REVISION HISTORY
4/11—Rev. A to Rev. B
Changes to Features Section and Applications Section............... 1
Added Exposed Pad Notation to Outline Dimensions ............. 23
Changes to Ordering Guide .......................................................... 23
Added Automotive Products Section .......................................... 23
9/07—Rev. 0 to Rev. A
Changes to Features and General Description ............................. 1
Changes to Table 2............................................................................ 3
Changes to Table 3............................................................................ 5
Changes to Typical Performance Characteristics Layout............ 9
Inserted Figure 3 to Figure 8; Renumbered Sequentially............ 9
Inserted Figure 9; Renumbered Sequentially.............................. 10
Inserted Figure 16, and Figure 18 to Figure 20; Renumbered
Sequentially ..................................................................................... 11
Inserted Figure 24; Renumbered Sequentially............................ 12
Deleted Figure 28 and Figure 29; Renumbered Sequentially ... 13
Inserted Figure 33 and Figure 34; Renumbered Sequentially... 14
Inserted Figure 41 to Figure 46; Renumbered Sequentially...... 16
Inserted Figure 48; Renumbered Sequentially............................ 17
Changes to Gain Selection Section and Figure 50 ..................... 18
Added Input Protection Section................................................... 19
Added Reducing Noise Section .................................................... 20
Changes to Multiplexing Section.................................................. 21
Added Using the AD8231 with Bipolar Supplies Section ......... 21
Added Sallen Key Filter Section ................................................... 22
Changes to Ordering Guide .......................................................... 23
5/07—Revision 0: Initial Version
AD8231
Rev. B | Page 3 of 24
SPECIFICATIONS
VS = 5 V, VREF = 2.5 V, G = 1, RL = 10 kΩ, TA = 25°C, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
INSTRUMENTATION AMPLIFIER
Offset Voltage VOS RTI = VOSI + VOSO/G
Input Offset, VOSI 4 15 μV
Average Temperature Drift TA = −40°C to +125°C 0.01 0.05 μV/°C
Output Offset, VOSO 15 30 μV
Average Temperature Drift TA = −40°C to +125°C 0.05 0.5 μV/°C
Input Currents
Input Bias Current 250 500 pA
T
A = −40°C to +125°C 5 nA
Input Offset Current 20 100 pA
T
A = −40°C to +125°C 0.5 nA
Gains 1, 2, 4, 8, 16, 32, 64, or 128
Gain Error
G = 1 0.05 %
G = 2 to 128 0.8 %
Gain Drift TA = −40°C to +125°C
G = 1 to 32 3 10 ppm/°C
G = 64 4 20 ppm/°C
G = 128 10 30 ppm/°C
Linearity 0.2 V to 4.8 V, 10 kΩ load 3 ppm
0.2 V to 4.8 V, 2 kΩ load 5 ppm
CMRR
G = 1 80 dB
G = 2 86 dB
G = 4 92 dB
G = 8 98 dB
G = 16 104 dB
G = 32 110 dB
G = 64 110 dB
G = 128 110 dB
Noise en = √(eni2 + (eno/G)2), VIN+, VIN− = 2.5 V
Input Voltage Noise, eni f = 1 kHz 32 nV/√Hz
f = 1 kHz, TA = −40°C 27 nV/√Hz
f = 1 kHz, TA = 125°C 39 nV/√Hz
f = 0.1 Hz to 10 Hz 0.7 μV p-p
Output Voltage Noise, eno f = 1 kHz 58 nV/√Hz
f = 1 kHz, TA = −40°C 50 nV/√Hz
f = 1 kHz, TA = 125°C 70 nV/√Hz
f = 0.1 Hz to 10 Hz 1.1 μV p-p
Current Noise f = 10 Hz 20 fA/√Hz
Other Input Characteristics
Common-Mode Input Impedance 10||5 GΩ||pF
Power Supply Rejection Ratio 100 115 dB
Input Operating Voltage Range 0.05 4.95 V
Reference Input
Input Impedance 28 kΩ
Voltage Range −0.2 +5.2 V
AD8231
Rev. B | Page 4 of 24
Parameter Conditions Min Typ Max Unit
Dynamic Performance
Bandwidth
G = 1 2.7 MHz
G = 2 2.5 MHz
Gain Bandwidth Product
G = 4 to 128 7 MHz
Slew Rate 1.1 V/μs
Output Characteristics
Output Voltage High RL = 100 kΩ to ground 4.9 4.94 V
R
L = 10 kΩ to ground 4.8 4.88 V
Output Voltage Low RL = 100 kΩ to 5 V 60 100 mV
R
L = 10 kΩ to 5 V 80 200 mV
Short-Circuit Current 70 mA
Digital Interface
Input Voltage Low TA = −40°C to +125°C 1.0 V
Input Voltage High TA = −40°C to +125°C 4.0 V
Setup Time to CS High TA = −40°C to +125°C 50 ns
Hold Time after CS High TA = −40°C to +125°C 20 ns
OPERATIONAL AMPLIFIER
Input Characteristics
Offset Voltage, VOS 5 15 μV
Temperature Drift TA = −40°C to +125°C 0.01 0.06 μV/°C
Input Bias Current 250 500 pA
T
A = −40°C to +125°C 5 nA
Input Offset Current 20 100 pA
T
A = −40°C to +125°C 0.5 nA
Input Voltage Range 0.05 4.95 V
Open-Loop Gain 100 120 V/mV
Common-Mode Rejection Ratio 100 120 dB
Power Supply Rejection Ratio 100 110 dB
Voltage Noise Density 20 nV/√Hz
Voltage Noise f = 0.1 Hz to 10 Hz 0.4 μV p-p
Dynamic Performance
Gain Bandwidth Product 1 MHz
Slew Rate 0.5 V/μs
Output Characteristics
Output Voltage High RL = 100 kΩ to ground 4.9 4.96 V
R
L = 10 kΩ to ground 4.8 4.92 V
Output Voltage Low RL = 100 kΩ to 5 V 60 100 mV
R
L = 10 kΩ to 5 V 80 200 mV
Short-Circuit Current 70 mA
BOTH AMPLIFIERS
Power Supply
Quiescent Current 4 5 mA
Quiescent Current (Shutdown) 0.01 1 μA
AD8231
Rev. B | Page 5 of 24
VS = 3.0 V, VREF = 1.5 V, TA = 25°C, G = 1, RL = 10 kΩ, unless otherwise noted.
Table 3.
Parameter Conditions Min Typ Max Unit
INSTRUMENTATION AMPLIFIER
Offset Voltage VOS RTI = VOSI + VOSO/G
Input Offset, VOSI 4 15 μV
Average Temperature Drift 0.01 0.05 μV/°C
Output Offset, VOSO 15 30 μV
Average Temperature Drift 0.05 0.5 μV/°C
Input Currents
Input Bias Current 250 500 pA
T
A = −40°C to +125°C 5 nA
Input Offset Current 20 100 pA
T
A = −40°C to +125°C 0.5 nA
Gains 1, 2, 4, 8, 16, 32, 64, or 128
Gain Error
G = 1 0.05 %
G = 2 to 128 0.8 %
Gain Drift TA = −40°C to +125°C
G = 1 to 32 3 10 ppm/°C
G = 64 4 20 ppm/°C
G = 128 10 30 ppm/°C
CMRR
G = 1 80 dB
G = 2 86 dB
G = 4 92 dB
G = 8 98 dB
G = 16 104 dB
G = 32 110 dB
G = 64 110 dB
G = 128 110 dB
Noise en = √(eni2 + (eno/G)2)
VIN+, VIN− = 2.5 V, TA = 25°C
Input Voltage Noise, eni f = 1 kHz 40 nV/√Hz
f = 1 kHz, TA = −40°C 35 nV/√Hz
f = 1 kHz, TA = 125°C 48 nV/√Hz
f = 0.1 Hz to 10 Hz 0.8 μV p-p
Output Voltage Noise, eno f = 1 kHz 72 nV/√Hz
f = 1 kHz, TA = −40°C 62 nV/√Hz
f = 1 kHz, TA = 125°C 83 nV/√Hz
f = 0.1 Hz to 10 Hz 1.4 μV p-p
Current Noise f = 10 Hz 20 fA/√Hz
Other Input Characteristics
Common-Mode Input Impedance 10||5 GΩ||pF
Power Supply Rejection Ratio 100 115 dB
Input Operating Voltage Range 0.05 2.95 V
Reference Input
Input Impedance 28 kΩ||pF
Voltage Range −0.2 +3.2 V
AD8231
Rev. B | Page 6 of 24
Parameter Conditions Min Typ Max Unit
Dynamic Performance
Bandwidth
G = 1 2.7 MHz
G = 2 2.5 MHz
Gain Bandwidth Product
G = 4 to 128 7 MHz
Slew Rate 1.1 V/μs
Output Characteristics
Output Voltage High RL = 100 kΩ to ground 2.9 2.94 V
R
L = 10 kΩ to ground 2.8 2.88 V
Output Voltage Low RL = 100 kΩ to 3 V 60 100 mV
R
L = 10 kΩ to 3 V 80 200 mV
Short-Circuit Current 40 mA
Digital Interface
Input Voltage Low TA = −40°C to +125°C 0.7 V
Input Voltage High TA = −40°C to +125°C 2.3 V
Setup Time to CS High TA = −40°C to +125°C 60 ns
Hold Time after CS High TA = −40°C to +125°C 20 ns
OPERATIONAL AMPLIFIERS
Input Characteristics
Offset Voltage, VOS 5 15 μV
Temperature Drift TA = −40°C to +125°C 0.01 0.06 μV/°C
Input Bias Current 250 500 pA
T
A = −40°C to +125°C 5 nA
Input Offset Current 20 100 pA
T
A = −40°C to +125°C 0.5 nA
Input Voltage Range 0.05 2.95 V
Open-Loop Gain 100 120 V/mV
Common-Mode Rejection Ratio 100 120 dB
Power Supply Rejection Ratio 100 110 dB
Voltage Noise Density 27 nV/√Hz
Voltage Noise f = 0.1 Hz to 10 Hz 0.6 μV p-p
Dynamic Performance
Gain Bandwidth Product 1 MHz
Slew Rate 0.5 V/μs
Output Characteristics
Output Voltage High RL = 100 kΩ to ground 2.9 2.96 V
R
L = 10 kΩ to ground 2.8 2.82 V
Output Voltage Low RL = 100 kΩ to 3 V 60 100 mV
R
L = 10 kΩ to 3 V 80 200 mV
Short-Circuit Current 40 mA
BOTH AMPLIFIERS
Power Supply
Quiescent Current 3.5 4.5 mA
Quiescent Current (Shutdown) 0.01 1 μA
AD8231
Rev. B | Page 7 of 24
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
Parameter Rating
Supply Voltage 6 V
Output Short-Circuit Current Indefinite1
Input Voltage (Common-Mode) −VS − 0.3 V to +VS + 0.3 V
Differential Input Voltage −VS − 0.3 V to +VS + 0.3 V
Storage Temperature Range –65°C to +150°C
Operational Temperature Range –40°C to +125°C
Package Glass Transition Temperature 130°C
ESD (Human Body Model) 1.5 kV
ESD (Charged Device Model) 1.5 kV
ESD (Machine Model) 0.2 kV
Table 5.
Thermal Pad θJA Unit
Soldered to Board 54 °C/W
Not Soldered to Board 96 °C/W
The θJA values in Table 5 assume a 4-layer JEDEC standard
board. If the thermal pad is soldered to the board, it is
also assumed it is connected to a plane. θJC at the exposed pad
is 6.3°C/W.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation for the AD8231 is limited
by the associated rise in junction temperature (TJ) on the die. At
approximately 130°C, which is the glass transition temperature,
the plastic changes its properties. Even temporarily exceeding
this temperature limit may change the stresses that the package
exerts on the die, permanently shifting the parametric perform-
ance of the amplifiers. Exceeding a temperature of 130°C for an
extended period can result in a loss of functionality.
1 For junction temperatures between 105°C and 130°C, short-circuit operation
beyond 1000 hours can impact part reliability.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD8231
Rev. B | Page 8 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1NC
2(IN-AMP –IN) –INA
3(IN-AMP +IN) +INA
4NC
11 –V
S
12 +V
S
10 OUTA (IN-AMP OUT)
9REF
5
SDN
6
+INB
7
–INB
8
(OP AMP OUT) OUTB
15 A1
16 A2
14 A0
13 CS
TOP VIEW
(Not to Scale)
AD8231
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD CAN BE CONNECTED TO THE NEGATIVE
SUPPLY (–V
S
) OR LEFT FLOATING.
06586-002
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin Number Mnemonic Description
1 NC No Connect.
2 −INA (IN-AMP −IN) Instrumentation Amplifier Negative Input.
3 +INA (IN-AMP +IN) Instrumentation Amplifier Positive Input.
4 NC No Connect.
5 SDN Shutdown.
6 +INB Operational Amplifier Positive Input.
7 −INB Operational Amplifier Negative Input.
8 OUTB (OP AMP OUT) Operational Amplifier Output.
9 REF Instrumentation Amplifier Reference Pin. It should be driven with a low impedance. Output is
referred to this pin.
10 OUTA (IN-AMP OUT) Instrumentation Amplifier Output.
11 −VS Negative Power Supply. Connect to ground in single-supply applications.
12 +VS Positive Power Supply.
13 CS Chip Select. Enables digital logic interface.
14 A0 Gain Setting Bit (LSB).
15 A1 Gain Setting Bit.
16 A2 Gain Setting Bit (MSB).
EPAD Exposed Pad. Can be connected to the negative supply (−VS) or left floating.
AD8231
Rev. B | Page 9 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
INSTRUMENTATION AMPLIFIER PERFORMANCE CURVES
1000
0
200
400
600
800
–100 –80 –60 –40 –20 0 20 40 60 80 100
HITS
CMRR (µV/V)
N: 5956
MEAN: 0.977167
SD: 11.8177
06586-100
Figure 3. Instrumentation Amplifier CMR Distribution, G = 1
800
700
600
500
400
300
200
100
0
–15 –10 –5 0 5 10 15
HITS
VOSI (µV)
N: 5956
MEAN: 2.06788
SD: 1.07546
06586-101
Figure 4. Instrumentation Amplifier Input Offset Voltage Distribution
800
700
600
500
400
300
200
100
0
–30 –20 –10 0 10 20 30
HITS
V
OSO
(µV)
N: 5956
MEAN: 10.3901
SD: 3.9553
06586-102
Figure 5. Instrumentation Amplifier Output Offset Voltage Distribution
1400
1200
1000
800
600
400
200
0
–500 –400 –300 –200 –100 0 100 200 300 400 500
HITS
GAIN ERROR (µV/V)
N: 5956
MEAN: –48.0779
SD: 21.0433
06586-103
Figure 6. Instrumentation Amplifier Gain Distribution, G = 1
9
8
7
6
5
4
3
2
1
0
–50 –40 –30 –20 –10 0 10 20 30 40 50
NUMBER OF AMPLIFIERS
INPUT OFFSET DRIFT (nV/°C)
06586-104
N: 40
MEAN: –8.31
SD: 6
Figure 7. Instrumentation Amplifier Input Offset Voltage Drift,
−40°C to +125°C
16
14
12
10
8
6
4
2
0
–0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5
NUMBER OF AMPLIFIERS
OUTPUT OFFSET DRIFT (µV/°C)
06586-105
N: 40
MEAN: –0.003
SD: 0.061
Figure 8. Instrumentation Amplifier Output Offset Drift, −40°C to +125°C
AD8231
Rev. B | Page 10 of 24
2000
1500
1000
500
0
–500
–40 –20 0 20
3V
5V
40 60 80 100 120
BIAS CURRENT (pA)
TEMPERATURE (°C)
V
REF
= MIDSUPPLY
V
CM
= MIDSUPPLY
06586-106
Figure 9. Instrumentation Amplifier Bias Current vs. Temperature
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5 2.52.01.51.00.50–0.5–1.0–1.5–2.0
BIAS CURRENT (nA)
V
CM
(V)
06586-006
+V
S
= +2.5V
–V
S
= –2.5V
V
REF
= 0V
Figure 10. Instrumentation Amplifier Bias Current vs.
Common-Mode Voltage, 5 V
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
–1.5 1.51.20.90.60.30–0.3–0.6–0.9–1.2
BIAS CURRENT (nA)
V
CM
(V)
+V
S
= +1.5V
–V
S
= –1.5V
V
REF
= 0V
06586-007
Figure 11. Instrumentation Amplifier Bias Current vs.
Common-Mode Voltage, 3 V
6
0V, 4.96V
0V, 2.96V
0V, 0.04V 2.92V, 1.5V
4.92V, 2.5V
5V SINGLE SUPPLY
3V SINGLE SUPPLY
5
4
3
2
1
0
0654321
INPUT COMMON-MODE VOLTAGE (V)
OUTPUT VOLTAGE (V)
06586-003
Figure 12. Instrumentation Amplifier Input Common-Mode Range vs.
Output Voltage, VREF = 0 V
6
5
4
3
2
1
0
054.54.03.53.02.52.01.51.00.5
INPUT COMMON-MODE VOLTAGE (V)
OUTPUT VOLTAGE (V)
.0
5V SINGLE SUPPLY
3V SINGLE SUPPLY
0.02V, 2.22V
0.02V, 0.78V
1.5V, 4.96V
0.02V, 4.22V
4.98V, 3.22V
4.98V, 1.78V
1.5V, 2.96V
2.98V, 2.22V
2.98V, 0.78V
1.5V, 0.04V
06586-004
Figure 13. Instrumentation Amplifier Input Common-Mode Range vs.
Output Voltage, VREF = 1.5 V
6
5
4
3
2
1
0
054.54.03.53.02.52.01.51.00.5
INPUT COMMON-MODE VOLTAGE (V)
OUTPUT VOLTAGE (V)
.0
5V SINGLE SUPPLY
3V SINGLE
SUPPLY
0.02V, 1.72V
2.5V, 4.96V
0.02V, 3.72V 4.98V, 3.72V
4.98V,1.28V
2.5V, 2.96V 2.98V, 2.72V
2.98V, 0.28V
2.5V, 0.04V
0.02V, 1.28V
06586-005
Figure 14. Instrumentation Amplifier Input Common-Mode Range vs.
Output Voltage, VREF = 2.5 V
AD8231
Rev. B | Page 11 of 24
50
40
30
20
10
0
–10
–20
–30
–40
100 10M1M100k10k1k
GAIN (dB)
FREQUENCY (Hz)
G = 128
G = 64
G = 32
G = 16
G = 8
G = 4
G = 2
G = 1
06586-009
Figure 15. Instrumentation Amplifier Gain vs. Frequency
1000
–1000
–800
–600
–400
–200
0
200
400
600
800
–40 –20 0 20 40 60 80 100 120
GAIN DRIFT (ppm)
TEMPERATURE (°C)
06586-116
G = 1
G = 2
G = 4
G = 8
G = 16
G = 32
G = 64
G = 128
Figure 16. Instrumentation Amplifier Gain Drift vs. Temperature
140
120
100
80
60
40
10 100 1k 10k 100k
CMRR (dB)
FREQUENCY (Hz)
G = 1
G = 8
G = 128
06586-010
Figure 17. Instrumentation Amplifier CMRR vs. Frequency
20
–20
–15
–10
–5
0
5
10
15
–40 –20 0 20 40 60 80 100 120
CMRR (µV/V)
TEMPERATURE (°C)
06586-118
G = 1
G = 1
G = 8
G = 8
G = 128
G = 128
REPRESENTATIVE SAMPLES
Figure 18. Instrumentation Amplifier CMRR vs. Temperature
140
120
100
80
60
40
20
0
1 100k10k1k10010
POSITIVE PSRR (dB)
FREQUENCY (Hz)
06586-146
G = 1
G = 8
G = 128
Figure 19. Instrumentation Amplifier Positive PSRR vs. Frequency
140
120
100
80
60
40
20
0
1 100k100k1k10010
NEGATIVE PSRR (dB)
FREQUENCY (Hz)
06586-147
G = 1
G = 8
G = 128
Figure 20. Instrumentation Amplifier Negative PSRR vs. Frequency
AD8231
Rev. B | Page 12 of 24
G = +1, 1µV/DIV
G = +128, 0.4µV/DIV
1s/DIV
06586-012
Figure 21. Instrumentation Amplifier 0.1 Hz to 10 Hz Noise
100
80
60
40
20
90
70
50
30
10
0
1 10 100 1k
NOISE (nV/ Hz)
FREQUENCY (Hz)
G = +1
G = +8
G = +128
06586-011
Figure 22. Instrumentation Amplifier Voltage Noise Spectral Density vs.
Frequency, 5 V, 1 Hz to 1000 Hz
1000
900
800
700
600
500
400
300
200
100
0
1 10 100 1k 10k 100k
NOISE (nV/ Hz)
FREQUENCY (Hz)
G = +1
G = +8
G = +128
06586-008
Figure 23. Instrumentation Amplifier Voltage Noise Spectral Density vs.
Frequency, 5 V, 1 Hz to 1 MHz
100
10
1
0.1
0.01
1110k1k10010
CURRENT NOISE (pA/ Hz)
FREQUENCY (Hz)
00k
06586-107
Figure 24. Instrumentation Amplifier Current Noise Spectral Density
5µs/DIV20mV/DIV
06586-013
Figure 25. Instrumentation Amplifier Small Signal Pulse Response, G = 1,
RL = 2 kΩ, CL = 500 pF
NO
LOAD
300pF 500pF 800pF
4µs/DIV20mV/DIV
06586-014
Figure 26. Instrumentation Amplifier Small Signal Pulse Response for Various
Capacitive Loads, G = 1
AD8231
Rev. B | Page 13 of 24
G = +8
G = +32
G = +128
10µs/DIV20mV/DIV
06586-015
Figure 27. Instrumentation Amplifier Small Signal Pulse Response, G = 4, 16,
and 128, RL = 2 kΩ, CL = 500 pF
10µs/DIV0.001%/DIV
2V/DIV
3.95µs TO 0.01%
4µs TO 0.001%
06586-016
Figure 28. Instrumentation Amplifier Large Signal Pulse Response,
G = 1, VS = 5 V
10µs/DIV0.001%/DIV
2V/DIV
3.75µs TO 0.01%
3.8µs TO 0.001%
06586-017
Figure 29. Instrumentation Amplifier Large Signal Pulse Response,
G = 8, VS = 5 V
100µs/DIV0.001%/DIV
2V/DIV
17.6µs TO 0.01%
21.4µs TO 0.001%
06586-018
Figure 30. Instrumentation Amplifier Large Signal Pulse Response,
G = 128, VS = 5 V
25
20
15
10
5
0
1110010
SETTLING TIME (µs)
GAIN (V/V)
k
0.001%
0.01%
06586-019
Figure 31. Instrumentation Amplifier Settling Time vs.
Gain for a 4 V p-p Step, VS = 5 V
25
20
15
10
5
0
1110010
SETTLING TIME (µs)
GAIN (V/V)
k
0.001%
0.01%
06586-020
Figure 32. Instrumentation Amplifier Settling Time vs.
Gain for a 2 V p-p Step, VS = 3 V
AD8231
Rev. B | Page 14 of 24
06586-133
+
V
S
–V
S
1.0
0.8
0.6
0.4
0.2
–1.0
–0.8
–0.6
–0.4
–0.2
0.1 100101
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
OUTPUT CURRENT (mA)
–40°C
+25°C
+85°C
+125°C
06586-134
+
V
S
–V
S
1.0
0.8
0.6
0.4
0.2
–1.0
–0.8
–0.6
–0.4
–0.2
0.1 100101
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
OUTPUT CURRENT (mA)
–40°C
+25°C
+85°C
+125°C
Figure 33. Instrumentation Amplifier Output Voltage Swing vs.
Output Current, VS = 3 V
Figure 34. Instrumentation Amplifier Output Voltage Swing vs.
Output Current, VS = 5 V
AD8231
Rev. B | Page 15 of 24
OPERATIONAL AMPLIFIER PERFORMANCE CURVES
100
80
60
40
20
0
–20
–
90
–100
–110
–120
–130
–140
–150
10 10M1M100k10k1k100
OPEN-LOOP GAIN (dB)
OPEN-LOOP PHASE SHIFT (Degrees)
FREQUENCY (Hz)
RL = 10kΩ
CL = 200pF
76° PHASE
MARGIN
06586-021
Figure 35. Operational Amplifier Open-Loop Gain and Phase vs.
Frequency, VS = 5 V
100
80
60
40
20
0
–20
–
90
–100
–110
–120
–130
–140
–150
10 10M1M100k10k1k100
OPEN-LOOP GAIN (dB)
OPEN-LOOP PHASE SHIFT (Degrees)
FREQUENCY (Hz)
RL = 10kΩ
CL = 200pF
72° PHASE
MARGIN
06586-022
Figure 36. Operational Amplifier Open-Loop Gain and Phase vs.
Frequency, VS = 3 V
NO
LOAD
800pF 1nF
1.5nF
2nF
5µs/DIV20mV/DIV
06586-023
Figure 37. Operational Amplifier Small Signal Response for
Various Capacitive Loads, VS = 5 V
NO
LOAD
300pF
800pF
1nF
1.5nF
5µs/DIV20mV/DIV
06586-024
Figure 38. Operational Amplifier Small Signal Response for
Various Capacitive Loads, VS = 3 V
NO
LOAD 1nF║2kΩ
1.5nF║2kΩ
TIME (5µs/DIV)
OUTPUT VOLTAGE (0.5V/DIV)
06586-025
Figure 39. Operational Amplifier Large Signal Transient Response, VS = 5 V
NO
LOAD
1nF║2kΩ
1.5nF║2kΩ
TIME (5µs/DIV)
OUTPUT VOLTAGE (0.5V/DIV)
06586-026
Figure 40. Operational Amplifier Large Signal Transient Response, VS = 3 V
AD8231
Rev. B | Page 16 of 24
1000
900
800
700
600
500
400
300
200
100
0
1 100k10k1k10010
SPECTRAL NOISE DENSITY (nV/ Hz)
FREQUENCY (Hz)
06586-141
Figure 41. Operational Amplifier Voltage Spectral Noise Density vs. Frequency
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
–40 1251109580655035205–10–25
BIAS CURRENT (nA)
TEMPERATURE (°C)
06586-108
5V
3V
Figure 42. Operational Amplifier Bias Current vs. Temperature
400
–400
–300
–200
–100
0
200
300
100
–3 3210–1–2
BIAS CURRENT (pA)
V
CM
(V)
V
S
= ±1.5V
V
S
= ±2.5V
06586-109
Figure 43. Operational Amplifier Bias Current vs. Common Mode
06586-144
+
V
S
–VS
1.0
0.8
0.6
0.4
0.2
–1.0
–0.8
–0.6
–0.4
–0.2
0.1 100101
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
OUTPUT CURRENT (mA)
–40°C
+25°C
+85°C
+125°C
Figure 44. Operational Amplifier Output Voltage Swing vs.
Output Current, VS = 3 V
06586-145
+
V
S
–VS
1.0
0.8
0.6
0.4
0.2
–1.0
–0.8
–0.6
–0.4
–0.2
0.1 100101
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
OUTPUT CURRENT (mA)
–40°C
+25°C
+85°C
+125°C
Figure 45. Operational Amplifier Output Voltage Swing vs.
Output Current, VS = 5 V
140
120
100
80
60
40
20
0
1 100k10k1k10010
PSRR (dB)
FREQUENCY (Hz)
06586-148
+PSRR
–PSRR
Figure 46. Operational Amplifier Power Supply Rejection Ratio
AD8231
Rev. B | Page 17 of 24
PERFORMANCE CURVES VALID FOR BOTH AMPLIFIERS
7
6
5
4
3
2
1
0
2.7 5.95.55.14.74.33.93.53.1
I
SUPPLY
(mA)
V
SUPPLY
(V)
+125°C
+85°C
+25°C
–40°C
06586-028
Figure 47. Supply Current vs. Supply Voltage
160
140
120
100
80
60
40
20
0
10 100k10k1k100
CHANNEL SEPARATION (dB)
FREQUENCY (Hz)
06586-149
G = 1
G = 8 G = 128
SOURCE CHANNEL: OP AMP AT G = 1
Figure 48. Channel Separation vs. Frequency
AD8231
Rev. B | Page 18 of 24
THEORY OF OPERATION
–INB
OUTB
+INB
OUTA
–INA
+INA
REF–V
S
+V
S
CS A0 A1 A2 SDN
AD8231
A1
A3
A4
14kΩ14kΩ
14kΩ14kΩ
A2
0
6586-031
Figure 49. Simplified Schematic
AMPLIFIER ARCHITECTURE
The AD8231 is based on the classic 3-op amp topology. This
topology has two stages: a preamplifier to provide amplification,
followed by a difference amplifier to remove the common-mode
voltage. Figure 49 shows a simplified schematic of the AD8231.
The preamp stage is composed of Amplifier A1, Amplifier A2,
and a digitally controlled resistor network. The second stage is a
gain of 1 difference amplifier composed of Amplifier A3 and
four 14 k resistors. A1, A2, and A3 are all zero drift, rail-to-
rail input, rail-to rail-output amplifiers.
The AD8231 design makes it extremely robust over temperature.
The AD8231 uses an internal thin film resistor to set the gain.
Because all of the resistors are on the same die, gain temperature
drift performance and CMRR drift performance are better than
can be achieved with topologies using external resistors. The
AD8231 also uses an auto-zero topology to null the offsets of all its
internal amplifiers. Because this topology continually corrects for
any offset errors, offset temperature drift is nearly nonexistent.
The AD8231 also includes a free operational amplifier. Like
the other amplifiers in the AD8231, it is a zero drift, rail-to-rail
input, rail-to-rail output architecture.
GAIN SELECTION
The gain of the AD8231 is set by voltages applied to the A0, A1,
and A2 pins. To change the gain, the CS pin must be driven
low. When the CS pin is driven high, the gain is latched, and
voltages at the A0 to A2 pins have no effect. Because the CS pin
is level sensitive rather than edge sensitive, it can also be tied
permanently low. shows the different gain settings. Table 7
The time required for a gain change is dominated by the settling
time of the amplifier. The AD8231 takes about 200 ns to switch
gains, after which the amplifier begins to settle. Refer to Figure 28
through Figure 32 to determine the settling time for different gains.
Table 7. Truth Table for AD8231 Gain Settings
CS A2 A1 A0 Gain
Low Low Low Low 1
Low Low Low High 2
Low Low High Low 4
Low Low High High 8
Low High Low Low 16
Low High Low High 32
Low High High Low 64
Low High High High 128
High X X X No change
REFERENCE TERMINAL
The output voltage of the AD8231 is developed with respect to
the potential on the reference terminal, which is useful when
the output signal needs to be offset to a midsupply level. For
example, a voltage source can be tied to the REF pin to level-
shift the output so that the AD8231 can drive a single-supply
ADC. The REF pin is protected with ESD diodes and should
not exceed either +VS or −VS by more than 0.3 V.
For best performance, source impedance to the REF terminal
should be kept below 1 Ω. As shown in Figure 49, the reference
terminal, REF, is at one end of a 14 k resistor. Additional
impedance at the REF terminal adds to this 14 k resistor
and results in amplification of the signal connected to the
positive input, causing a CMRR error.
INCORRECT
AD8231
IN-AMP
V
REF
CORRECT
AD8231
IN-AMP
V
REF
AD8231
OP AMP
+
–
+
–
+
–
06586-032
REFREF
Figure 50. Driving the Reference (REF)
AD8231
Rev. B | Page 19 of 24
LAYOUT
The AD8231 is a high precision device. To ensure optimum
performance at the PCB level, care must be taken in the design
of the board layout. The AD8231 pinout is arranged in a logical
manner to aid in this task.
Power Supplies
The AD8231 should be decoupled with a 0.1 µF bypass capacitor
between the two supplies. This capacitor should be placed as close
as possible to Pin 11 and Pin 12, either directly next to the pins or
beneath the pins on the backside of the board. The auto-zero
architecture of the AD8231 requires a low ac impedance between
the supplies. Long trace lengths to the bypass capacitor increase
this impedance, which results in a larger input offset voltage.
A stable dc voltage should be used to power the instrumentation
amplifier. Noise on the supply pins can adversely affect
performance.
Package Considerations
The AD8231 comes in a 4 mm × 4 mm LFCSP. Beware of
blindly copying the footprint from another 4 mm × 4 mm
LFCSP part; it cannot have the same thermal pad size and leads.
Refer to the Outline Dimensions section to verify that
the PCB symbol has the correct dimensions. Space between
the leads and thermal pad should be kept as wide as possible
for the best bias current performance.
Thermal Pad
The AD8231 4 mm × 4 mm LFCSP comes with a thermal pad.
This pad is connected internally to −VS. The pad can either be
left unconnected or connected to the negative supply rail. For
high vibration applications, a landing is recommended.
Because the AD8231 dissipates little power, heat dissipation
is rarely an issue. If improved heat dissipation is desired (for
example, when ambient temperatures are near 125°C or when
driving heavy loads), connect the thermal pad to the negative
supply rail. For the best heat dissipation performance, the
negative supply rail should be a plane in the board. See the
Thermal Resistance section for thermal coefficients with and
without the pad soldered.
INPUT BIAS CURRENT RETURN PATH
The input bias current of the AD8231 must have a return path
to common. When the source, such as a thermocouple, cannot
provide a return current path, one should be created, as shown
in Figure 51.
THERMOCOUPLE
+V
S
REF
–V
S
AD8231
CAPACITIVELY COUPLED
+V
S
REF
C
C
–V
S
AD8231
TRANSFORMER
+V
S
REF
–V
S
AD8231
INCORRECT
CAPACITIVELY COUPLED
+V
S
REF
C
R
R
C
–V
S
AD8231
1
fHIGH-PASS
= 2πRC
THERMOCOUPLE
+V
S
REF
–V
S
10MΩ
AD8231
TRANSFORMER
+V
S
REF
–V
S
AD8231
CORRECT
0
6586-033
Figure 51. Creating an IBIAS Path
INPUT PROTECTION
All terminals of the AD8231 are protected against ESD. In
addition, the input structure allows for dc overload conditions
a diode drop above the positive supply and a diode drop below
the negative supply. Voltages beyond these limits cause the ESD
diodes to conduct and current to flow. If overvoltage events are
anticipated, an external resistor should be used in series with
each of the inputs to limit the current to below 10 mA. Currents
up to 100 mA can be sustained for a few seconds.
Note that if either input is brought below the negative supply
to the point where the ESD diode turns on, the AD8231 output
can phase-reverse.
AD8231
Rev. B | Page 20 of 24
If more common-mode range is required, the simplest solution is
to apply less gain in the instrumentation amplifier. The extra op
amp can be used to provide another gain stage after the in-amp.
Because the AD8231 has good offset and noise performance at low
gains, applying less gain in the instrumentation amplifier generally
has a limited impact on the overall system performance.
RF INTERFERENCE
RF rectification is often a problem when amplifiers are used in
applications where there are strong RF signals. The disturbance
can appear as a small dc offset voltage. High frequency signals
can be filtered with a low-pass, RC network placed at the
input of the instrumentation amplifier, as shown in Figure 52.
The filter limits the input signal bandwidth according to the
following relationship
REDUCING NOISE
Because the AD8231 has no 1/f noise, reducing the bandwidth
corresponds directly to less noise. Table 8 shows the AD8231
performance at a gain of 1 at different bandwidths, assuming a
2-pole Butterworth filter roll off.
Table 8. AD8231 noise at various bandwidths
)(22
1
CD
Diff CCR
FilterFreq +π
=
C
CM RC
FilterFreq π
=
2
1
SNR
Single-Ended1
SNR Differential
Output2
where CD ≥ 10CC. Bandwidth
(Hz)
Noise
(µV rms)
R
R
AD8231
+
V
S
+INA
–INA
0.1µF 10µF
10µF
0.1µF
REF
V
OUT
–V
S
C
D
10nF
C
C
1nF
C
C
1nF
4.02kΩ
4.02kΩ
06586-034
dB Bits dB Bits
1 0.07 148.3 24.3 154.3 25.3
3.2 0.12 143.2 23.5 149.2 24.5
10 0.21 138.3 22.7 144.3 23.7
32 0.37 133.2 21.8 139.2 22.8
100 0.66 128.3 21.0 137.63 22.0
320 1.17 123.2 20.2 129.2 21.2
1 k 2.07 118.3 19.3 124.3 20.3
3.2 k 3.71 113.2 18.5 119.2 19.5
10 k 6.55 108.3 17.7 117.3 18.7
32 k 11.73 103.2 16.9 109.2 17.9
1 SNR for single-ended output configuration calculated with output signal of
4.8 V p-p, which corresponds to 1.697 V rms.
Figure 52. RFI Suppression 2 SNR for differential output configuration calculated with output signal of
9.6 V p-p, which corresponds to 3.397 V rms.
Figure 52 shows an example where the differential filter frequency
is approximately 2 kHz, and the common-mode filter frequency
is approximately 40 kHz.
The AD8231 has two clocks: an auto-zero clock at 3.4 kHz and
a commutating clock at 54 kHz. While the auto-zero clock has
negligible energy and can generally be ignored, the commutating
clock has enough energy to significantly affect the noise of the
part. Therefore, in applications where low noise is critical, limiting
the bandwidth of the system below 54 kHz is recommended.
Values of R and CC should be chosen to minimize RFI. Mismatch
between the R × CC at the positive input and the R × CC at the
negative input degrades the CMRR of the AD8231. By using a
value of CD that is ten times larger than the value of CC, the
effect of the mismatch is reduced and performance is improved.
COMMON-MODE INPUT VOLTAGE RANGE
The 3-op amp architecture of the AD8231 applies gain and then
removes the common-mode voltage. Therefore, internal nodes
in the AD8231 experience a combination of both the gained
signal and the common-mode signal. This combined signal can
be limited by the voltage supplies even when the individual input
and output signals are not. To determine whether the signal could
be limited, refer to Figure 12 through Figure 14 or use the
following formula
V04.0
2
V04.0 −+<
×
±<+− S
DIFF
CMS V
GainV
VV
AD8231
Rev. B | Page 21 of 24
APPLICATIONS INFORMATION
DIFFERENTIAL OUTPUT
Figure 53 shows how to create a differential output in-amp
using the AD8231 uncommitted op amp. Because this
configuration makes use of the reference terminal of the
in-amp, errors from the op amp and resistor mismatch result in
common-mode errors, rather than differential errors. Because
common-mode errors are typically rejected by the next device
in the signal chain, this circuit configuration adds almost no
extra error.
+IN
–IN
IN-AMP
V
REF
4.99kΩ
+
–
OP AMP
+OUT
–OUT
4.99kΩ
REF
9
10
76
8
3
2
06586-035
Figure 53. Differential Output Using Operational Amplifier
MULTIPLEXING
SDN0
SDN1
SDN2
SDN3
06586-036
Figure 54. Four AD8231s in Multiplexing Configuration
The outputs of both the AD8231 in-amp and op amp are high
impedance in the shutdown state. This feature allows several
AD8231s to be multiplexed together without any external
switches. Figure 54 shows an example of such a configuration.
All the outputs are connected together and only one amplifier is
turned on at a time. This feature is analogous to the high-Z
mode of the digital tristate logic.
The resistors in the AD8231 instrumentation amplifier create a
resistive path from the output to the reference pin of about
100 k. If a higher output impedance in shutdown mode is
desired, the reference pin can be driven with the op amp of
the AD8231. In this configuration, the output impedance in
shutdown is several GΩ, and many thousand AD8231s can
theoretically be multiplexed in such a way.
The AD8231 can enter and leave shutdown mode very quickly.
However, when the amplifier wakes up and reconnects its input
circuitry, the voltage at its internal input nodes changes dramati-
cally. It takes time for the output of the amplifier to settle. Refer
to Figure 28 through Figure 32 to determine the settling time
for different gains. This settling time limits how quickly the
AD8231 can be multiplexed with the SDN pin.
USING THE AD8231 WITH BIPOLAR SUPPLIES
The AD8231 can be used with bipolar supplies as long as the
maximum voltage drop between the supply rails is kept below
6 V and all input voltages are kept within the supply rails.
With bipolar supplies, the acceptable levels for the digital inputs
A0, A1, A2, CS, and SDN shift. shows acceptable values
for low and high signals for both single and dual supplies.
Table 9
Table 9. Digital Pin Thresholds
Low High
Supply Voltage (V) Min (V) Max (V) Min (V) Max (V)
0 to 5 0 +1 4 5
0 to 3 0 +0.8 2.2 3
−2.5 to +2.5 −2.5 −1.5 1.5 2.5
−1.5 to +1.5 −1.5 −0.7 0.7 1.5
AD8231
Rev. B | Page 22 of 24
When operating the AD8231 on dual supplies, a level-shift is
typically needed from standard single-supply control logic. One
easy way to accomplish the level-shift is through a single-pole,
double-throw switch, such as the ADG633. Figure 55 shows an
application schematic for ±2.5 V operation.
06586-055
+2.5V
–2.5V
+2.5V
–2.5V
+2.5V
–2.5V
A0
A1
A2
EN
V
DD
GND V
SS
–2.5V
GND
V
DD
DIGITAL
CONTROL
(FPGA,
MICROCONTROLLER,
ETC.)
V
DIGITAL
V
DIGITAL
ADG633
AD8231
A0 A1 A2
+V
S
–V
S
SDN
CS
+2.5V
V
DIGITAL
IS THE DIGITAL SUPPLY VOLTAGE. IT CAN BE
ANY VOLTAGE BETWEEN 2.5V AND 9.5V.
–2.5V
Figure 55. Converting Single-Supply Control Signals to Dual Supply.
SALLEN KEY FILTER
The extra op amp in the AD8231 can be used to create a 2-pole
Sallen Key filter. Such a filter can remove excess noise or
perform antialiasing before an analog-to-digital converter.
Figure 56 shows how to create a 2-pole low-pass Butterworth
filter. Components R1, R2, C1, and C2 set the frequency of the
filter. The ratio of R3 and R4 sets the peaking of the filter. If R4
equals 10 kΩ, R3 should equal 5.9 kΩ for an optimum 2-pole
response.
Depending on the circuitry before and after the AD8231,
a 3-pole filter can be possible. If the previous stage has a small
output impedance, an additional pole can be added before the
in amp (R6, R7, and C4). If the following stage has a high input
impedance, an additional pole can be added after the op amp
(R5 and C3). Peaking from the Sallen Key stage should be
higher to compensate for the extra attenuation of the third pole;
both R3 and R4 should be 10 kΩ for optimum response.
Note that in addition to setting the peaking of the filter, the
ratio R3/R4 also sets the dc gain: G = 1 + R3/R4. If lower dc
gain is required, replace R1 with a voltage divider, where the
output resistance of the divider is equal to the required value of R1.
Figure 56 shows a bias point connected to R4 and the in-amp
reference. The filter stage amplifies the signal around this bias
point. The bias point is Uypically midsupply and should be low
impedance.
Table 10. Recommended Component Values for Butterworth
Low-Pass Filter in Figure 56
Optional Poles
Sallen Key Before In-Amp After Op Amp
3 dB
Freq
R1, R2
(kΩ)
C1, C2
(nF)
R6, R7
(kΩ)
C4
(nF)
R5
(kΩ)
C3
(nF)
32 Hz 499 10 499 4.7 49.9 100
100 Hz 158 10 158 4.7 16 100
320 Hz 49.9 10 49.9 4.7 4.99 100
1 kHz 158 1 158 0.47 1.6 100
3.2 kHz 49.9 1 49.9 0.47 0.499 100
10 kHz 15.8 1 15.8 0.47 0.16 100
32 kHz 4.99 1 4.99 0.47 0.049 100
06586-056
IN-AMP
OP AMP
REF
BIAS
POINT
BIAS
POINT
R7
R1 R2
R6
R5
C4
SALLEN KEY
(TWO POLE)
OPTIONAL POLEOPTIONAL POLE
C3
R3
R4
C2
C1
Figure 56. Butterworth Low-Pass Filter (Dotted Sections Indicate Optional Poles)
AD8231
Rev. B | Page 23 of 24
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
2.25
2.10 SQ
1.95
16
5
13
8
9
12 1
4
1.95 BSC
PIN 1
INDICATOR TOP
VIEW
4.00
BSC SQ
3.75
BSC SQ
COPLANARITY
0.08
(BOTTOM VIEW )
12° MAX
1.00
0.85
0.80 SEATING
PLANE
0.35
0.30
0.25
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
0.20 REF
0.65 BSC
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
0.25 MIN
072808-A
0.75
0.60
0.50
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 57. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-16-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 , 2 Temperature Range Package Description Package Option
AD8231ACPZ-R7 −40°C to +125°C 16-Lead LFCSP_VQ, 7” Tape and Reel CP-16-4
AD8231ACPZ-RL −40°C to +125°C 16-Lead LFCSP_VQ, 13” Tape and Reel CP-16-4
AD8231ACPZ-WP −40°C to +125°C 16-Lead LFCSP_VQ, Waffle Pack CP-16-4
AD8231WACPZ-RL −40°C to +125°C 16-Lead LFCSP_VQ, 13” Tape and Reel CP-16-4
AD8231-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The AD8231W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices, Inc. account representative for specific product ordering information and
to obtain the specific Automotive Reliability reports for these models.
AD8231
Rev. B | Page 24 of 24
NOTES
©2007–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06586-0-4/11(B)
