DDR2 SDRAM UDIMM
MT4HTF1664AY – 128MB
MT4HTF3264AY – 256MB
MT4HTF6464AY – 512MB
Features
•240-pin, unbuffered dual in-line memory module
(UDIMM)
•Fast data transfer rates: PC2-3200, PC2-4200,
PC2-5300, or PC2-6400
•128MB (16 Meg x 64), 256MB (32 Meg x 64),
512MB (64 Meg x 64)
•VDD = VDDQ = 1.8V
•VDDSPD = 1.7–3.6V
•JEDEC-standard 1.8V I/O (SSTL_18-compatible)
•Differential data strobe (DQS, DQS#) option
•4n-bit prefetch architecture
•Multiple internal device banks for concurrent
operation
•Programmable CAS latency (CL)
•Posted CAS additive latency (AL)
•WRITE latency = READ latency - 1 tCK
•Programmable burst lengths (BL): 4 or 8
•Adjustable data-output drive strength
•64ms, 8192-cycle refresh
•On-die termination (ODT)
•Serial presence detect (SPD) with EEPROM
•Gold edge contacts
•Single rank
Figure 1: 240-Pin UDIMM (MO-237 R/C C)
Module height 30.0mm (1.18in)
Options Marking
•Operating temperature
–Commercial (0°C ≤ TA ≤ +70°C) None
–Industrial (–40°C ≤ TA ≤ +85°C)1I
•Package
–240-pin DIMM (lead-free) Y
•Frequency/CL2
–2.5ns @ CL = 5 (DDR2-800)4-80E
–2.5ns @ CL = 6 (DDR2-800)4-800
–3.0ns @ CL = 5 (DDR2-667) -667
–3.75ns @ CL = 4 (DDR2-533)3-53E
–5.0ns @ CL = 3 (DDR2-400)3-40E
Notes: 1. Contact Micron for industrial temperature
module offerings.
2. CL = CAS (READ) latency.
3. Contact Micron for product availability.
4. Not available in 128MB and 256MB.
Table 1: Key Timing Parameters
Speed
Grade
Industry
Nomenclature
Data Rate (MT/s) tRCD
(ns)
tRP
(ns)
tRC
(ns)CL = 6 CL = 5 CL = 4 CL = 3
-80E PC2-6400 800 800 533 400 12.5 12.5 55
-800 PC2-6400 800 667 533 400 15 15 55
-667 PC2-5300 –667 553 400 15 15 55
-53E PC2-4200 – – 553 400 15 15 55
-40E PC2-3200 – – 400 400 15 15 55
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Features
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Products and specifications discussed herein are subject to change by Micron without notice.
Table 2: Addressing
Parameter 128MB 256MB 512MB
Refresh count 8K 8K 8K
Row address 8K A[12:0] 8K A[12:0] 8K A[12:0]
Device bank address 4 BA[1:0] 4 BA[1:0] 8 BA[2:0]
Device configuration 256Mb (16 Meg x 16) 512Mb (32 Meg x 16) 1Gb (64 Meg x 16)
Column address 512 A[8:0] 1K A[9:0] 1K A[9:0]
Module rank address 1 S0# 1 S0# 1 S0#
Table 3: Part Numbers and Timing Parameters – 128MB Modules (End of Life)
Base device: MT47H16M16,1 256Mb DDR2 SDRAM
Part Number2
Module
Density Configuration
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
MT4HTF1664A(I)Y-667__ 128MB 16 Meg x 64 5.3 GB/s 3.0ns/667 MT/s 5-5-5
MT4HTF1664A(I)Y-53E__ 128MB 16 Meg x 64 4.3 GB/s 3.75ns/533 MT/s 4-4-4
MT4HTF1664A(I)Y-40E__ 128MB 16 Meg x 64 3.2 GB/s 5.0ns/400 MT/s 3-3-3
Table 4: Part Numbers and Timing Parameters – 256MB Modules
Base device: MT47H32M16,1 512Mb DDR2 SDRAM
Part Number2
Module
Density Configuration
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
MT4HTF3264A(I)Y-80E__ 256MB 32 Meg x 64 6.4 GB/s 2.5ns/800 MT/s 5-5-5
MT4HTF3264A(I)Y-800__ 256MB 32 Meg x 64 6.4 GB/s 2.5ns/800 MT/s 6-6-6
MT4HTF3264A(I)Y-667__ 256MB 32 Meg x 64 5.3 GB/s 3.0ns/667 MT/s 5-5-5
MT4HTF3264A(I)Y-53E__ 256MB 32 Meg x 64 4.3 GB/s 3.75ns/533 MT/s 4-4-4
MT4HTF3264A(I)Y-40E__ 256MB 32 Meg x 64 3.2 GB/s 5.0ns/400 MT/s 3-3-3
Table 5: Part Numbers and Timing Parameters – 512MB Modules
Base device: MT47H64M16,1 1Gb DDR2 SDRAM
Part Number2
Module
Density Configuration
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
MT4HTF6464A(I)Y-80E__ 512MB 64 Meg x 64 6.4 GB/s 2.5ns/800 MT/s 5-5-5
MT4HTF6464A(I)Y-800__ 512MB 64 Meg x 64 6.4 GB/s 2.5ns/800 MT/s 6-6-6
MT4HTF6464A(I)Y-667__ 512MB 64 Meg x 64 5.3 GB/s 3.0ns/667 MT/s 5-5-5
MT4HTF6464A(I)Y-53E__ 512MB 64 Meg x 64 4.3 GB/s 3.75ns/533 MT/s 4-4-4
MT4HTF6464A(I)Y-40E__ 512MB 64 Meg x 64 3.2 GB/s 5.0ns/400 MT/s 3-3-3
Notes: 1. The data sheet for the base device can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.
Consult factory for current revision codes. Example: MT4HTF3264AY-667E1.
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Features
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Pin Assignments
Table 6: Pin Assignments
240-Pin UDIMM Front 240-Pin UDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1 VREF 31 DQ19 61 A4 91 VSS 121 VSS 151 VSS 181 VDDQ 211 DM5
2 VSS 32 VSS 62 VDDQ 92 DQS5# 122 DQ4 152 DQ28 182 A3 212 NC
3 DQ0 33 DQ24 63 A2 93 DQS5 123 DQ5 153 DQ29 183 A1 213 VSS
4 DQ1 34 DQ25 64 VDD 94 VSS 124 VSS 154 VSS 184 VDD 214 DQ46
5 VSS 35 VSS 65 VSS 95 DQ42 125 DM0 155 DM3 185 CK0 215 DQ47
6 DQS0# 36 DQS3# 66 VSS 96 DQ43 126 NC 156 NC 186 CK0# 216 VSS
7 DQS0 37 DQS3 67 VDD 97 VSS 127 VSS 157 VSS 187 VDD 217 DQ52
8 VSS 38 VSS 68 NC 98 DQ48 128 DQ6 158 DQ30 188 A0 218 DQ53
9 DQ2 39 DQ26 69 VDD 99 DQ49 129 DQ7 159 DQ31 189 VDD 219 VSS
10 DQ3 40 DQ27 70 A10 100 VSS 130 VSS 160 VSS 190 BA1 220 CK2
11 VSS 41 VSS 71 BA0 101 SA2 131 DQ12 161 NC 191 VDDQ 221 CK2#
12 DQ8 42 NC 72 VDDQ 102 NC 132 DQ13 162 NC 192 RAS# 222 VSS
13 DQ9 43 NC 73 WE# 103 VSS 133 VSS 163 VSS 193 S0# 223 DM6
14 VSS 44 VSS 74 CAS# 104 DQS6# 134 DM1 164 NC 194 VDDQ 224 NC
15 DQS1# 45 NC 75 VDDQ 105 DQS6 135 NC 165 NC 195 ODT0 225 VSS
16 DQS1 46 NC 76 NC 106 VSS 136 VSS 166 VSS 196 NC 226 DQ54
17 VSS 47 VSS 77 NC 107 DQ50 137 CK1 167 NC 197 VDD 227 DQ55
18 NC 48 NC 78 VDDQ 108 DQ51 138 CK1# 168 NC 198 VSS 228 VSS
19 NC 49 NC 79 VSS 109 VSS 139 VSS 169 VSS 199 DQ36 229 DQ60
20 VSS 50 VSS 80 DQ32 110 DQ56 140 DQ14 170 VDDQ 200 DQ37 230 DQ61
21 DQ10 51 VDDQ 81 DQ33 111 DQ57 141 DQ15 171 NC 201 VSS 231 VSS
22 DQ11 52 CKE0 82 VSS 112 VSS 142 VSS 172 VDD 202 DM4 232 DM7
23 VSS 53 VDD 83 DQS4# 113 DQS7# 143 DQ20 173 NC 203 NC 233 NC
24 DQ16 54 NC/BA2184 DQS4 114 DQS7 144 DQ21 174 NC 204 VSS 234 VSS
25 DQ17 55 NC 85 VSS 115 VSS 145 VSS 175 VDDQ 205 DQ38 235 DQ62
26 VSS 56 VDDQ 86 DQ34 116 DQ58 146 DM2 176 A12 206 DQ39 236 DQ63
27 DQS2# 57 A11 87 DQ35 117 DQ59 147 NC 177 A9 207 VSS 237 VSS
28 DQS2 58 A7 88 VSS 118 VSS 148 VSS 178 VDD 208 DQ44 238 VDDSPD
29 VSS 59 VDD 89 DQ40 119 SDA 149 DQ22 179 A8 209 DQ45 239 SA0
30 DQ18 60 A5 90 DQ41 120 SCL 150 DQ23 180 A6 210 VSS 240 SA1
Note: 1. Pin 54 is NC for 128MB and 256MB or BA2 for 512MB.
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Pin Assignments
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Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for all DDR2
modules. All pins listed may not be supported on this module. See Pin Assignments for
information specific to this module.
Table 7: Pin Descriptions
Symbol Type Description
Ax Input Address inputs: Provide the row address for ACTIVE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command. See the Pin Assignments Table for density-specific
addressing information.
BAx Input Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA define which mode register (MR0, MR1,
MR2, and MR3) is loaded during the LOAD MODE command.
CKx,
CK#x
Input Clock: Differential clock inputs. All control, command, and address input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#.
CKEx Input Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circui-
try and clocks on the DDR2 SDRAM.
DMx, Input Data mask (x8 devices only): DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH, along with that input data, during a write ac-
cess. Although DM pins are input-only, DM loading is designed to match that of the
DQ and DQS pins.
ODTx Input On-die termination: Enables (registered HIGH) and disables (registered LOW) termi-
nation resistance internal to the DDR2 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
will be ignored if disabled via the LOAD MODE command.
Par_In Input Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.
RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
RESET# Input Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This
signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z.
S#x Input Chip select: Enables (registered LOW) and disables (registered HIGH) the command
decoder.
SAx Input Serial address inputs: Used to configure the SPD EEPROM address range on the I2C
bus.
SCL Input Serial clock for SPD EEPROM: Used to synchronize communication to and from the
SPD EEPROM on the I2C bus.
CBx I/O Check bits. Used for system error detection and correction.
DQx I/O Data input/output: Bidirectional data bus.
DQSx,
DQS#x
I/O Data strobe: Travels with the DQ and is used to capture DQ at the DRAM or the con-
troller. Output with read data; input with write data for source synchronous opera-
tion. DQS# is only used when differential data strobe mode is enabled via the LOAD
MODE command.
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Pin Descriptions
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© 2003 Micron Technology, Inc. All rights reserved.
Table 7: Pin Descriptions (Continued)
Symbol Type Description
SDA I/O Serial data: Used to transfer addresses and data into and out of the SPD EEPROM on
the I2C bus.
RDQSx,
RDQS#x
Output Redundant data strobe (x8 devices only): RDQS is enabled/disabled via the LOAD
MODE command to the extended mode register (EMR). When RDQS is enabled, RDQS
is output with read data only and is ignored during write data. When RDQS is disa-
bled, RDQS becomes data mask (see DMx). RDQS# is only used when RDQS is enabled
and differential data strobe mode is enabled.
Err_Out# Output
(open drain)
Parity error output: Parity error found on the command and address bus.
VDD/VDDQ Supply Power supply: 1.8V ±0.1V. The component VDD and VDDQ are connected to the mod-
ule VDD.
VDDSPD Supply SPD EEPROM power supply: 1.7–3.6V.
VREF Supply Reference voltage: VDD/2.
VSS Supply Ground.
NC –No connect: These pins are not connected on the module.
NF –No function: These pins are connected within the module, but provide no functionality.
NU –Not used: These pins are not used in specific module configurations/operations.
RFU –Reserved for future use.
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Pin Descriptions
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htf4c16_32_64x64ay – Rev. H 3/10 EN 5Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.
Functional Block Diagram
Figure 2: Functional Block Diagram
DQS#
DQ
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS#
DQ
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS0
DQS0#
DM0
DQS1
DQS1#
DM1
DQS2
DQS2#
DM2
DQS3
DQS3#
DM3
DQS4
DQS4#
DM4
DQS5
DQS5#
DM5
DQS6
DQS6#
DM6
DQS7
DQS7#
DM7
CS#
CS# CS#
CS#
U1
U2
U3
U4
S0#
DQS#
DQ
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS#
DQ
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS#
DQ
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS#
DQ
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS#
DQ
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS#
DQ
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
A0
SPD EEPROM
A1 A2
SA0
VSS SA1 SA2
SDA
SCL
WP
U5
BA[2/1:0]
A[12:0]
RAS#
CAS#
WE#
CKE0
ODT0
BA[2:0]: DDR2 SDRAM
A[12:0]: DDR2 SDRAM
RAS#: DDR2 SDRAM
CAS#: DDR2 SDRAM
WE#: DDR2 SDRAM
CKE0: DDR2 SDRAM
ODT0: DDR2 SDRAM
VDDSPD
VDD/VDDQ
VREF
VSS
DDR SDRAM x 2
CK1
CK1#
DDR SDRAM x 2
CK2
CK2#
CK0
CK0#
Vss
Vss
V
SS
SPD EEPROM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Functional Block Diagram
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htf4c16_32_64x64ay – Rev. H 3/10 EN 6Micron Technology, Inc. reserves the right to change products or specifications without notice.
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General Description
DDR2 SDRAM modules are high-speed, CMOS dynamic random access memory mod-
ules that use internally configured 4 or 8-bank DDR2 SDRAM devices. DDR2 SDRAM
modules use DDR architecture to achieve high-speed operation. DDR2 architecture is
essentially a 4n-prefetch architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM
module effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the
internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data trans-
fers at the I/O pins.
DDR2 modules use two sets of differential signals: DQS, DQS# to capture data and CK
and CK# to capture commands, addresses, and control signals. Differential clocks and
data strobes ensure exceptional noise immunity for these signals and provide precise
crossing points to capture input signals. A bidirectional data strobe (DQS, DQS#) is trans-
mitted externally, along with data, for use in data capture at the receiver. DQS is a
strobe transmitted by the DDR2 SDRAM device during READs and by the memory con-
troller during WRITEs. DQS is edge-aligned with data for READs and center-aligned
with data for WRITEs.
DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com-
mands (address and control signals) are registered at every positive edge of CK. Input
data is registered on both edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
Serial Presence-Detect EEPROM Operation
DDR2 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the mod-
ule type and various SDRAM organizations and timing parameters. The remaining 128
bytes of storage are available for use by the customer. System READ/WRITE operations
between the master (system logic) and the slave EEPROM device occur via a standard
I2C bus using the DIMM’s SCL (clock) SDA (data), and SA (address) pins. Write protect
(WP) is connected to VSS, permanently disabling hardware write protection.
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
General Description
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Electrical Specifications
Stresses greater than those listed may cause permanent damage to the module. This is a
stress rating only, and functional operation of the module at these or any other condi-
tions outside those indicated in the device data sheet are not implied. Exposure to
absolute maximum rating conditions for extended periods may adversely affect reliability.
Table 8: Absolute Maximum Ratings
Symbol Parameter Min Max Units
VDD/VDDQ VDD/VDDQ supply voltage relative to VSS –0.5 2.3 V
VIN, VOUT Voltage on any pin relative to VSS –0.5 2.3 V
IIInput leakage current; Any input 0V ≤ VIN ≤ VDD;
VREF input 0V ≤ VIN ≤ 0.95V; (All other pins not
under test = 0V)
Address inputs, RAS#,
CAS#, WE#, S#, CKE,
ODT, BA
–20 20 µA
CK, CK# –10 10
DM –5 5
IOZ Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQ
and ODT are disabled
DQ, DQS, DQS# –5 5 µA
IVREF VREF leakage current; VREF = valid VREF level –8 8 µA
TAModule ambient operating temperature Commercial 0 70 °C
Industrial –40 85 °C
TC1DDR2 SDRAM component operating tempera-
ture2
Commercial 0 85 °C
Industrial –40 95 °C
Notes: 1. The refresh rate is required to double when TC exceeds 85°C.
2. For further information, refer to technical note TN-00-08: "Thermal Applications," avail-
able on Micron’s Web site.
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Electrical Specifications
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DRAM Operating Conditions
Recommended AC operating conditions are given in the DDR2 component data sheets.
Component specifications are available on Micron's Web site. Module speed grades cor-
relate with component speed grades.
Table 9: Module and Component Speed Grades
DDR2 components may exceed the listed module speed grades; module may not be available in all listed speed grades
Module Speed Grade Component Speed Grade
-1GA -187E
-80E -25E
-800 -25
-667 -3
-53E -37E
-40E -5E
Design Considerations
Simulations
Micron memory modules are designed to optimize signal integrity through carefully de-
signed terminations, controlled board impedances, routing topologies, trace length
matching, and decoupling. However, good signal integrity starts at the system level. Mi-
cron encourages designers to simulate the signal characteristics of the system's memo-
ry bus to ensure adequate signal integrity of the entire memory system.
Power
Operating voltages are specified at the DRAM, not at the edge connector of the module.
Designers must account for any system voltage drops at anticipated power levels to en-
sure the required supply voltage is maintained.
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
DRAM Operating Conditions
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IDD Specifications
Table 10: DDR2 IDD Specifications and Conditions – 128MB
Values shown for MT47H16M16 DDR2 SDRAM only and are computed from values specified in the 256Mb (16 Meg x 16)
component data sheet
Parameter Symbol -667 -53E -40E Units
Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC
(IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid com-
mands; Address bus inputs are switching; Data bus inputs are switching
IDD0 360 320 300 mA
Operating one bank active-read-precharge current: IOUT = 0mA; BL =
4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD),
tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Ad-
dress bus inputs are switching; Data pattern is same as IDD4W
IDD1 400 360 340 mA
Precharge power-down current: All device banks idle; tCK = tCK (IDD);
CKE is LOW; Other control and address bus inputs are stable; Data bus in-
puts are floating
IDD2P 20 20 20 mA
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD);
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
IDD2Q 200 140 100 mA
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
bus inputs are switching
IDD2N 160 140 120 mA
Active power-down current: All device banks open; tCK =
tCK (IDD); CKE is LOW; Other control and address bus inputs
are stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0
IDD3P 120 100 80 mA
Slow PDN exit
MR[12] = 1
24 24 24
Active standby current: All device banks open; tCK = tCK (IDD), tRAS =
tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com-
mands; Other control and address bus inputs are switching; Data bus inputs
are switching
IDD3N 220 160 120 mA
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD),
tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are switching; Data bus inputs are switching
IDD4W 860 720 560 mA
Operating burst read current: All device banks open; Continuous burst
read, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
IDD4R 760 640 480 mA
Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC
(IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other con-
trol and address bus inputs are switching; Data bus inputs are switching
IDD5 720 680 660 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and ad-
dress bus inputs are floating; Data bus inputs are floating
IDD6 20 20 20 mA
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
IDD Specifications
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© 2003 Micron Technology, Inc. All rights reserved.
Table 10: DDR2 IDD Specifications and Conditions – 128MB (Continued)
Values shown for MT47H16M16 DDR2 SDRAM only and are computed from values specified in the 256Mb (16 Meg x 16)
component data sheet
Parameter Symbol -667 -53E -40E Units
Operating bank interleave read current: All device banks interleaving
reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK =
tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH,
S# is HIGH between valid commands; Address bus inputs are stable during
deselects; Data bus inputs are switching
IDD7 1000 960 920 mA
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
IDD Specifications
PDF: 09005aef80ed6fda
htf4c16_32_64x64ay – Rev. H 3/10 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.
Table 11: DDR2 IDD Specifications and Conditions – 256MB
Values shown for MT47H32M16 DDR2 SDRAM only and are computed from values specified in the 512Mb (32 Meg x 16)
component data sheet
Parameter Symbol
-80E/
-800 -667 -53E -40E Units
Operating one bank active-precharge current:tCK = tCK (IDD), tRC =
tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
IDD0 540 480 440 440 mA
Operating one bank active-read-precharge current: IOUT = 0mA; BL =
4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN
(IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data pattern is same as IDD4W
IDD1 660 600 540 520 mA
Precharge power-down current: All device banks idle; tCK = tCK (IDD);
CKE is LOW; Other control and address bus inputs are stable; Data bus in-
puts are floating
IDD2P 28 28 28 28 mA
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD);
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
IDD2Q 260 220 180 160 mA
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Da-
ta bus inputs are switching
IDD2N 280 240 200 180 mA
Active power-down current: All device banks open; tCK
= tCK (IDD); CKE is LOW; Other control and address bus in-
puts are stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0
IDD3P 160 140 120 100 mA
Slow PDN exit
MR[12] = 1
48 48 48 48
Active standby current: All device banks open; tCK = tCK (IDD), tRAS =
tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com-
mands; Other control and address bus inputs are switching; Data bus
inputs are switching
IDD3N 300 280 240 200 mA
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX
(IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
IDD4W 1180 1000 820 640 mA
Operating burst read current: All device banks open; Continuous burst
read, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com-
mands; Address bus inputs are switching; Data bus inputs are switching
IDD4R 1100 940 780 620 mA
Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC
(IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other con-
trol and address bus inputs are switching; Data bus inputs are switching
IDD5 920 740 700 680 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
IDD6 28 28 28 28 mA
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
IDD Specifications
PDF: 09005aef80ed6fda
htf4c16_32_64x64ay – Rev. H 3/10 EN 12 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.
Table 11: DDR2 IDD Specifications and Conditions – 256MB (Continued)
Values shown for MT47H32M16 DDR2 SDRAM only and are computed from values specified in the 512Mb (32 Meg x 16)
component data sheet
Parameter Symbol
-80E/
-800 -667 -53E -40E Units
Operating bank interleave read current: All device banks interleaving
reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK
= tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching
IDD7 1480 1400 1360 1360 mA
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
IDD Specifications
PDF: 09005aef80ed6fda
htf4c16_32_64x64ay – Rev. H 3/10 EN 13 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.
Table 12: DDR2 IDD Specifications and Conditions (Die Revision A) – 512MB
Values shown for MT47H64M16 DDR2 SDRAM only and are computed from values specified in the 1Gb (64 Meg x 16) com-
ponent data sheet
Parameter Symbol
-80E/
-800 -667 -53E -40E Units
Operating one bank active-precharge current:tCK = tCK (IDD), tRC =
tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
IDD0 600 540 440 440 mA
Operating one bank active-read-precharge current: IOUT = 0mA; BL =
4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN
(IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data pattern is same as IDD4W
IDD1 700 520 480 460 mA
Precharge power-down current: All device banks idle; tCK = tCK (IDD);
CKE is LOW; Other control and address bus inputs are stable; Data bus in-
puts are floating
IDD2P 28 28 28 28 mA
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD);
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
IDD2Q 300 260 180 160 mA
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Da-
ta bus inputs are switching
IDD2N 320 280 200 160 mA
Active power-down current: All device banks open; tCK
= tCK (IDD); CKE is LOW; Other control and address bus in-
puts are stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0
IDD3P 180 160 140 140 mA
Slow PDN exit
MR[12] = 1
56 56 56 56
Active standby current: All device banks open; tCK = tCK (IDD), tRAS =
tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com-
mands; Other control and address bus inputs are switching; Data bus
inputs are switching
IDD3N 340 300 240 220 mA
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX
(IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
IDD4W 1260 800 720 640 mA
Operating burst read current: All device banks open; Continuous burst
read, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com-
mands; Address bus inputs are switching; Data bus inputs are switching
IDD4R 1280 880 720 640 mA
Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC
(IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other con-
trol and address bus inputs are switching; Data bus inputs are switching
IDD5 1120 1080 1000 960 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
IDD6 28 28 28 28 mA
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
IDD Specifications
PDF: 09005aef80ed6fda
htf4c16_32_64x64ay – Rev. H 3/10 EN 14 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.
Table 12: DDR2 IDD Specifications and Conditions (Die Revision A) – 512MB (Continued)
Values shown for MT47H64M16 DDR2 SDRAM only and are computed from values specified in the 1Gb (64 Meg x 16) com-
ponent data sheet
Parameter Symbol
-80E/
-800 -667 -53E -40E Units
Operating bank interleave read current: All device banks interleaving
reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK
= tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching
IDD7 1760 1400 1360 1320 mA
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
IDD Specifications
PDF: 09005aef80ed6fda
htf4c16_32_64x64ay – Rev. H 3/10 EN 15 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.
Table 13: DDR2 IDD Specifications and Conditions (Die Revision E) – 512MB
Values shown for MT47H64M16 DDR2 SDRAM only and are computed from values specified in the 1Gb (32 Meg x 16) com-
ponent data sheet
Parameter Symbol
-80E/
-800 -667 -53E -40E Units
Operating one bank active-precharge current:tCK = tCK (IDD), tRC =
tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
IDD0 600 540 440 440 mA
Operating one bank active-read-precharge current: IOUT = 0mA; BL =
4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN
(IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data pattern is same as IDD4W
IDD1 700 520 480 460 mA
Precharge power-down current: All device banks idle; tCK = tCK (IDD);
CKE is LOW; Other control and address bus inputs are stable; Data bus
inputs are floating
IDD2P 28 28 28 28 mA
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD);
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
IDD2Q 300 260 180 160 mA
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Da-
ta bus inputs are switching
IDD2N 320 280 200 160 mA
Active power-down current: All device banks open; tCK
= tCK (IDD); CKE is LOW; Other control and address bus in-
puts are stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0
IDD3P 160 120 120 120 mA
Slow PDN ex-
it MR[12] = 1
40 40 40 40
Active standby current: All device banks open; tCK = tCK (IDD), tRAS =
tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com-
mands; Other control and address bus inputs are switching; Data bus
inputs are switching
IDD3N 340 300 240 220 mA
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX
(IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
IDD4W 1260 800 720 640 mA
Operating burst read current: All device banks open; Continuous burst
read, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com-
mands; Address bus inputs are switching; Data bus inputs are switching
IDD4R 1280 880 720 640 mA
Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC
(IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other con-
trol and address bus inputs are switching; Data bus inputs are switching
IDD5 1120 1080 1000 960 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
IDD6 28 28 28 28 mA
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
IDD Specifications
PDF: 09005aef80ed6fda
htf4c16_32_64x64ay – Rev. H 3/10 EN 16 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.
Table 13: DDR2 IDD Specifications and Conditions (Die Revision E) – 512MB (Continued)
Values shown for MT47H64M16 DDR2 SDRAM only and are computed from values specified in the 1Gb (32 Meg x 16) com-
ponent data sheet
Parameter Symbol
-80E/
-800 -667 -53E -40E Units
Operating bank interleave read current: All device banks interleaving
reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK
= tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching
IDD7 1760 1400 1320 1200 mA
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
IDD Specifications
PDF: 09005aef80ed6fda
htf4c16_32_64x64ay – Rev. H 3/10 EN 17 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.
Serial Presence-Detect
For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD.
Table 14: SPD EEPROM Operating Conditions
Parameter/Condition Symbol Min Max Units
Supply voltage VDDSPD 1.7 3.6 V
Input high voltage: logic 1; All inputs VIH VDDSPD × 0.7 VDDSPD + 0.5 V
Input low voltage: logic 0; All inputs VIL –0.6 VDDSPD × 0.3 V
Output low voltage: IOUT = 3mA VOL –0.4 V
Input leakage current: VIN = GND to VDD ILI 0.1 3 µA
Output leakage current: VOUT = GND to VDD ILO 0.05 3 µA
Standby current ISB 1.6 4 µA
Power supply current, READ: SCL clock frequency = 100 kHz ICCR 0.4 1 mA
Power supply current, WRITE: SCL clock frequency = 100 kHz ICCW 2 3 mA
Table 15: SPD EEPROM AC Operating Conditions
Parameter/Condition Symbol Min Max Units Notes
SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1
Time bus must be free before a new transition can start tBUF 1.3 –µs
Data-out hold time tDH 200 –ns
SDA and SCL fall time tF–300 ns 2
SDA and SCL rise time tR–300 ns 2
Data-in hold time tHD:DAT 0 –µs
Start condition hold time tHD:STA 0.6 –µs
Clock HIGH period tHIGH 0.6 –µs
Noise suppression time constant at SCL, SDA inputs tI–50 µs
Clock LOW period tLOW 1.3 –µs
SCL clock frequency tSCL –400 kHz
Data-in setup time tSU:DAT 100 –ns
Start condition setup time tSU:STA 0.6 –µs 3
Stop condition setup time tSU:STO 0.6 –µs
WRITE cycle time tWRC –10 ms 4
Notes: 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1
and the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a
write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the
WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-
up resistance, and the EEPROM does not respond to its slave address.
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Serial Presence-Detect
PDF: 09005aef80ed6fda
htf4c16_32_64x64ay – Rev. H 3/10 EN 18 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.
Module Dimensions
Figure 3: 240-Pin DDR2 UDIMM
No components this side of module
U1 U2 U3 U4
U5
30.50 (1.20)
29.85 (1.175)
Pin 1
17.78 (0.70)
TYP
2.50 (0.098) D
(2X)
2.30 (0.091) TYP
5.0 (0.197) TYP
123.0 (4.840)
TYP
1.0 (0.039)
TYP
0.80 (0.031)
TYP
2.00 (0.079) R
(4X)
0.76 (0.030) R
Pin 120
Front view
133.50 (5.256)
133.20 (5.244)
63.0 (2.48)
TYP
55.0 (2.165)
TYP
10.0 (0.394)
TYP
Back view
Pin 240 Pin 121
1.37 (0.054)
1.17 (0.046)
2.70 (0.106)
MAX
2.20 (0.087) TYP
1.0 (0.039) TYP
3.05 (0.12) TYP
70.68 (2.78)
TYP
Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for
additional design dimensions.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Module Dimensions
PDF: 09005aef80ed6fda
htf4c16_32_64x64ay – Rev. H 3/10 EN 19 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.
